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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree for the ARM Integrator/AP platform
4 */
5
6/dts-v1/;
7#include "integrator.dtsi"
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10
11/ {
12 model = "ARM Integrator/AP";
13 compatible = "arm,integrator-ap";
14
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 device_type = "cpu";
21 /*
22 * Since the board has pluggable CPU modules, we
23 * cannot define a proper compatible here. Let the
24 * boot loader fill in the apropriate compatible
25 * string if necessary.
26 */
27 /* compatible = "arm,arm926ej-s"; */
28 reg = <0>;
29 /*
30 * The documentation in ARM DUI 0138E page 3-12 states
31 * that the maximum frequency for this clock is 200 MHz
32 * but painful trial-and-error has proved to me that it
33 * is actually just hanging the system above 71 MHz.
34 * Sad but true.
35 */
36 /* kHz uV */
37 operating-points = <71000 0
38 66000 0
39 60000 0
40 48000 0
41 36000 0
42 24000 0
43 12000 0>;
44 clocks = <&cmosc>;
45 clock-names = "cpu";
46 clock-latency = <1000000>; /* 1 ms */
47 };
48 };
49
50 aliases {
51 arm,timer-primary = &timer2;
52 arm,timer-secondary = &timer1;
53 };
54
55 chosen {
56 bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
57 };
58
59 /* 24 MHz chrystal on the Integrator/AP development board */
60 xtal24mhz: xtal24mhz@24M {
61 #clock-cells = <0>;
62 compatible = "fixed-clock";
63 clock-frequency = <24000000>;
64 };
65
66 pclk: pclk@0 {
67 #clock-cells = <0>;
68 compatible = "fixed-factor-clock";
69 clock-div = <1>;
70 clock-mult = <1>;
71 clocks = <&xtal24mhz>;
72 };
73
74 /* The UART clock is 14.74 MHz divided by an ICS525 */
75 uartclk: uartclk@14.74M {
76 #clock-cells = <0>;
77 compatible = "fixed-clock";
78 clock-frequency = <14745600>;
79 clocks = <&xtal24mhz>;
80 };
81
82 core-module@10000000 {
83 /* 24 MHz chrystal on the core module */
84 cm24mhz: cm24mhz@24M {
85 #clock-cells = <0>;
86 compatible = "fixed-clock";
87 clock-frequency = <24000000>;
88 };
89
90 /* Oscillator on the core module, clocks the CPU core */
91 cmosc: clock-controller@8 {
92 compatible = "arm,syscon-icst525-integratorap-cm";
93 reg = <0x08 0x04>;
94 #clock-cells = <0>;
95 lock-offset = <0x14>;
96 vco-offset = <0x08>;
97 clocks = <&cm24mhz>;
98 };
99
100 /* Auxilary oscillator on the core module, 32.369MHz at boot */
101 auxosc: clock-controller@1c {
102 compatible = "arm,syscon-icst525";
103 reg = <0x1c 0x04>;
104 #clock-cells = <0>;
105 lock-offset = <0x14>;
106 vco-offset = <0x1c>;
107 clocks = <&cm24mhz>;
108 };
109 };
110
111 syscon {
112 compatible = "arm,integrator-ap-syscon", "syscon";
113 reg = <0x11000000 0x100>;
114 ranges = <0x0 0x11000000 0x100>;
115 #size-cells = <1>;
116 #address-cells = <1>;
117
118 /*
119 * SYSCLK clocks PCIv3 bridge, system controller and the
120 * logic modules.
121 */
122 sysclk: clock-controller@4 {
123 compatible = "arm,syscon-icst525-integratorap-sys";
124 reg = <0x04 0x04>;
125 #clock-cells = <0>;
126 lock-offset = <0x1c>;
127 vco-offset = <0x04>;
128 clocks = <&xtal24mhz>;
129 };
130
131 /* One-bit control for the PCI bus clock (33 or 25 MHz) */
132 pciclk: clock-controller@4,8 {
133 compatible = "arm,syscon-icst525-integratorap-pci";
134 reg = <0x04 0x04>;
135 #clock-cells = <0>;
136 lock-offset = <0x1c>;
137 vco-offset = <0x04>;
138 clocks = <&xtal24mhz>;
139 };
140 };
141
142 timer0: timer@13000000 {
143 compatible = "arm,integrator-timer";
144 clocks = <&xtal24mhz>;
145 };
146
147 timer1: timer@13000100 {
148 compatible = "arm,integrator-timer";
149 clocks = <&xtal24mhz>;
150 };
151
152 timer2: timer@13000200 {
153 compatible = "arm,integrator-timer";
154 clocks = <&xtal24mhz>;
155 };
156
157 pic: pic@14000000 {
158 valid-mask = <0x003fffff>;
159 };
160
161 pci: pciv3@62000000 {
162 compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
163 device_type = "pci";
164 #interrupt-cells = <1>;
165 #size-cells = <2>;
166 #address-cells = <3>;
167 /* Bridge registers and config access space */
168 reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
169 interrupt-parent = <&pic>;
170 interrupts = <17>; /* Bus error IRQ */
171 clocks = <&pciclk>;
172 bus-range = <0x00 0xff>;
173 ranges = <0x01000000 0 0x0000000 /* I/O space @00000000 */
174 0x60000000 0 0x00010000 /* 64 KB @ LB 60000000 */
175 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
176 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
177 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
178 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
179 dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
180 0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */
181 0x02000000 0 0x80000000 /* Core module alias memory */
182 0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */
183 interrupt-map-mask = <0xf800 0 0 0x7>;
184 interrupt-map = <
185 /* IDSEL 9 */
186 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
187 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
188 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
189 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
190 /* IDSEL 10 */
191 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
192 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
193 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
194 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
195 /* IDSEL 11 */
196 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
197 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
198 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
199 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
200 /* IDSEL 12 */
201 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
202 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
203 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
204 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
205 >;
206 };
207
208 fpga {
209 /*
210 * The Integator/AP predates the idea to have magic numbers
211 * identifying the PrimeCell in hardware, thus we have to
212 * supply these from the device tree.
213 */
214 rtc: rtc@15000000 {
215 compatible = "arm,pl030", "arm,primecell";
216 arm,primecell-periphid = <0x00041030>;
217 clocks = <&pclk>;
218 clock-names = "apb_pclk";
219 };
220
221 uart0: uart@16000000 {
222 compatible = "arm,pl010", "arm,primecell";
223 arm,primecell-periphid = <0x00041010>;
224 clocks = <&uartclk>, <&pclk>;
225 clock-names = "uartclk", "apb_pclk";
226 };
227
228 uart1: uart@17000000 {
229 compatible = "arm,pl010", "arm,primecell";
230 arm,primecell-periphid = <0x00041010>;
231 clocks = <&uartclk>, <&pclk>;
232 clock-names = "uartclk", "apb_pclk";
233 };
234
235 kmi0: kmi@18000000 {
236 compatible = "arm,pl050", "arm,primecell";
237 arm,primecell-periphid = <0x00041050>;
238 clocks = <&xtal24mhz>, <&pclk>;
239 clock-names = "KMIREFCLK", "apb_pclk";
240 };
241
242 kmi1: kmi@19000000 {
243 compatible = "arm,pl050", "arm,primecell";
244 arm,primecell-periphid = <0x00041050>;
245 clocks = <&xtal24mhz>, <&pclk>;
246 clock-names = "KMIREFCLK", "apb_pclk";
247 };
248 };
249
250 /*
251 * Logic module bus, we support up to 4 logical modules
252 * They appear at 0xc0000000, 0xd0000000, 0xe0000000 and 0xf0000000
253 * and use interrupts 9, 10, 11 and 12 respectively.
254 */
255 bus@c0000000 {
256 compatible = "arm,integrator-ap-lm";
257 #address-cells = <1>;
258 #size-cells = <1>;
259 ranges = <0xc0000000 0xc0000000 0x40000000>;
260 dma-ranges;
261
262 lm0: bus@c0000000 {
263 compatible = "simple-bus";
264 ranges = <0x00000000 0xc0000000 0x10000000>;
265 dma-ranges = <0x00000000 0xc0000000 0x10000000>;
266 reg = <0xc0000000 0x10000000>;
267 #address-cells = <1>;
268 #size-cells = <1>;
269 };
270 lm1: bus@d0000000 {
271 compatible = "simple-bus";
272 ranges = <0x00000000 0xd0000000 0x10000000>;
273 dma-ranges = <0x00000000 0xd0000000 0x10000000>;
274 reg = <0xd0000000 0x10000000>;
275 #address-cells = <1>;
276 #size-cells = <1>;
277 };
278 lm2: bus@e0000000 {
279 compatible = "simple-bus";
280 ranges = <0x00000000 0xe0000000 0x10000000>;
281 dma-ranges = <0x00000000 0xe0000000 0x10000000>;
282 reg = <0xe0000000 0x10000000>;
283 #address-cells = <1>;
284 #size-cells = <1>;
285 };
286 lm3: bus@f0000000 {
287 compatible = "simple-bus";
288 ranges = <0x00000000 0xf0000000 0x10000000>;
289 dma-ranges = <0x00000000 0xf0000000 0x10000000>;
290 reg = <0xf0000000 0x10000000>;
291 #address-cells = <1>;
292 #size-cells = <1>;
293 };
294 };
295};
1/*
2 * Device Tree for the ARM Integrator/AP platform
3 */
4
5/dts-v1/;
6/include/ "integrator.dtsi"
7
8/ {
9 model = "ARM Integrator/AP";
10 compatible = "arm,integrator-ap";
11
12 aliases {
13 arm,timer-primary = &timer2;
14 arm,timer-secondary = &timer1;
15 };
16
17 chosen {
18 bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
19 };
20
21 /* 24 MHz chrystal on the core module */
22 xtal24mhz: xtal24mhz@24M {
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <24000000>;
26 };
27
28 pclk: pclk@0 {
29 #clock-cells = <0>;
30 compatible = "fixed-factor-clock";
31 clock-div = <1>;
32 clock-mult = <1>;
33 clocks = <&xtal24mhz>;
34 };
35
36 /* The UART clock is 14.74 MHz divided by an ICS525 */
37 uartclk: uartclk@14.74M {
38 #clock-cells = <0>;
39 compatible = "fixed-clock";
40 clock-frequency = <14745600>;
41 };
42
43 syscon {
44 compatible = "arm,integrator-ap-syscon";
45 reg = <0x11000000 0x100>;
46 interrupt-parent = <&pic>;
47 /* These are the logical module IRQs */
48 interrupts = <9>, <10>, <11>, <12>;
49 };
50
51 timer0: timer@13000000 {
52 compatible = "arm,integrator-timer";
53 clocks = <&xtal24mhz>;
54 };
55
56 timer1: timer@13000100 {
57 compatible = "arm,integrator-timer";
58 clocks = <&xtal24mhz>;
59 };
60
61 timer2: timer@13000200 {
62 compatible = "arm,integrator-timer";
63 clocks = <&xtal24mhz>;
64 };
65
66 pic: pic@14000000 {
67 valid-mask = <0x003fffff>;
68 };
69
70 pci: pciv3@62000000 {
71 compatible = "v3,v360epc-pci";
72 #interrupt-cells = <1>;
73 #size-cells = <2>;
74 #address-cells = <3>;
75 reg = <0x62000000 0x10000>;
76 interrupt-parent = <&pic>;
77 interrupts = <17>; /* Bus error IRQ */
78 ranges = <0x00000000 0 0x61000000 /* config space */
79 0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */
80 0x01000000 0 0x0 /* I/O space */
81 0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */
82 0x02000000 0 0x00000000 /* non-prefectable memory */
83 0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */
84 0x42000000 0 0x10000000 /* prefetchable memory */
85 0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */
86 interrupt-map-mask = <0xf800 0 0 0x7>;
87 interrupt-map = <
88 /* IDSEL 9 */
89 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
90 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
91 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
92 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
93 /* IDSEL 10 */
94 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
95 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
96 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
97 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
98 /* IDSEL 11 */
99 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
100 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
101 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
102 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
103 /* IDSEL 12 */
104 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
105 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
106 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
107 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
108 >;
109 };
110
111 fpga {
112 /*
113 * The Integator/AP predates the idea to have magic numbers
114 * identifying the PrimeCell in hardware, thus we have to
115 * supply these from the device tree.
116 */
117 rtc: rtc@15000000 {
118 compatible = "arm,pl030", "arm,primecell";
119 arm,primecell-periphid = <0x00041030>;
120 clocks = <&pclk>;
121 clock-names = "apb_pclk";
122 };
123
124 uart0: uart@16000000 {
125 compatible = "arm,pl010", "arm,primecell";
126 arm,primecell-periphid = <0x00041010>;
127 clocks = <&uartclk>, <&pclk>;
128 clock-names = "uartclk", "apb_pclk";
129 };
130
131 uart1: uart@17000000 {
132 compatible = "arm,pl010", "arm,primecell";
133 arm,primecell-periphid = <0x00041010>;
134 clocks = <&uartclk>, <&pclk>;
135 clock-names = "uartclk", "apb_pclk";
136 };
137
138 kmi0: kmi@18000000 {
139 compatible = "arm,pl050", "arm,primecell";
140 arm,primecell-periphid = <0x00041050>;
141 clocks = <&xtal24mhz>, <&pclk>;
142 clock-names = "KMIREFCLK", "apb_pclk";
143 };
144
145 kmi1: kmi@19000000 {
146 compatible = "arm,pl050", "arm,primecell";
147 arm,primecell-periphid = <0x00041050>;
148 clocks = <&xtal24mhz>, <&pclk>;
149 clock-names = "KMIREFCLK", "apb_pclk";
150 };
151 };
152};