1/*
  2 * Device tree for Energy Micro EFM32 Giant Gecko SoC.
  3 *
  4 * Documentation available from
  5 * http://www.silabs.com/Support%20Documents/TechnicalDocs/EFM32GG-RM.pdf
  6 */
  7#include "armv7-m.dtsi"
  8#include "dt-bindings/clock/efm32-cmu.h"
  9
 10/ {
 11	aliases {
 12		i2c0 = &i2c0;
 13		i2c1 = &i2c1;
 14		serial0 = &uart0;
 15		serial1 = &uart1;
 16		serial2 = &uart2;
 17		serial3 = &uart3;
 18		serial4 = &uart4;
 19		spi0 = &spi0;
 20		spi1 = &spi1;
 21		spi2 = &spi2;
 22	};
 23
 24	soc {
 25		adc: adc@40002000 {
 26			compatible = "efm32,adc";
 27			reg = <0x40002000 0x400>;
 28			interrupts = <7>;
 29			clocks = <&cmu clk_HFPERCLKADC0>;
 30			status = "disabled";
 31		};
 32
 33		gpio: gpio@40006000 {
 34			compatible = "efm32,gpio";
 35			reg = <0x40006000 0x1000>;
 36			interrupts = <1 11>;
 37			gpio-controller;
 38			#gpio-cells = <2>;
 39			interrupt-controller;
 40			#interrupt-cells = <1>;
 41			clocks = <&cmu clk_HFPERCLKGPIO>;
 42			status = "ok";
 43		};
 44
 45		i2c0: i2c@4000a000 {
 46			#address-cells = <1>;
 47			#size-cells = <0>;
 48			compatible = "efm32,i2c";
 49			reg = <0x4000a000 0x400>;
 50			interrupts = <9>;
 51			clocks = <&cmu clk_HFPERCLKI2C0>;
 52			clock-frequency = <100000>;
 53			status = "disabled";
 54		};
 55
 56		i2c1: i2c@4000a400 {
 57			#address-cells = <1>;
 58			#size-cells = <0>;
 59			compatible = "efm32,i2c";
 60			reg = <0x4000a400 0x400>;
 61			interrupts = <10>;
 62			clocks = <&cmu clk_HFPERCLKI2C1>;
 63			clock-frequency = <100000>;
 64			status = "disabled";
 65		};
 66
 67		spi0: spi@4000c000 { /* USART0 */
 68			#address-cells = <1>;
 69			#size-cells = <0>;
 70			compatible = "efm32,spi";
 71			reg = <0x4000c000 0x400>;
 72			interrupts = <3 4>;
 73			clocks = <&cmu clk_HFPERCLKUSART0>;
 74			status = "disabled";
 75		};
 76
 77		spi1: spi@4000c400 { /* USART1 */
 78			#address-cells = <1>;
 79			#size-cells = <0>;
 80			compatible = "efm32,spi";
 81			reg = <0x4000c400 0x400>;
 82			interrupts = <15 16>;
 83			clocks = <&cmu clk_HFPERCLKUSART1>;
 84			status = "disabled";
 85		};
 86
 87		spi2: spi@4000c800 { /* USART2 */
 88			#address-cells = <1>;
 89			#size-cells = <0>;
 90			compatible = "efm32,spi";
 91			reg = <0x4000c800 0x400>;
 92			interrupts = <18 19>;
 93			clocks = <&cmu clk_HFPERCLKUSART2>;
 94			status = "disabled";
 95		};
 96
 97		uart0: uart@4000c000 { /* USART0 */
 98			compatible = "efm32,uart";
 99			reg = <0x4000c000 0x400>;
100			interrupts = <3 4>;
101			clocks = <&cmu clk_HFPERCLKUSART0>;
102			status = "disabled";
103		};
104
105		uart1: uart@4000c400 { /* USART1 */
106			compatible = "efm32,uart";
107			reg = <0x4000c400 0x400>;
108			interrupts = <15 16>;
109			clocks = <&cmu clk_HFPERCLKUSART1>;
110			status = "disabled";
111		};
112
113		uart2: uart@4000c800 { /* USART2 */
114			compatible = "efm32,uart";
115			reg = <0x4000c800 0x400>;
116			interrupts = <18 19>;
117			clocks = <&cmu clk_HFPERCLKUSART2>;
118			status = "disabled";
119		};
120
121		uart3: uart@4000e000 { /* UART0 */
122			compatible = "efm32,uart";
123			reg = <0x4000e000 0x400>;
124			interrupts = <20 21>;
125			clocks = <&cmu clk_HFPERCLKUART0>;
126			status = "disabled";
127		};
128
129		uart4: uart@4000e400 { /* UART1 */
130			compatible = "efm32,uart";
131			reg = <0x4000e400 0x400>;
132			interrupts = <22 23>;
133			clocks = <&cmu clk_HFPERCLKUART1>;
134			status = "disabled";
135		};
136
137		timer0: timer@40010000 {
138			compatible = "efm32,timer";
139			reg = <0x40010000 0x400>;
140			interrupts = <2>;
141			clocks = <&cmu clk_HFPERCLKTIMER0>;
142		};
143
144		timer1: timer@40010400 {
145			compatible = "efm32,timer";
146			reg = <0x40010400 0x400>;
147			interrupts = <12>;
148			clocks = <&cmu clk_HFPERCLKTIMER1>;
149		};
150
151		timer2: timer@40010800 {
152			compatible = "efm32,timer";
153			reg = <0x40010800 0x400>;
154			interrupts = <13>;
155			clocks = <&cmu clk_HFPERCLKTIMER2>;
156		};
157
158		timer3: timer@40010c00 {
159			compatible = "efm32,timer";
160			reg = <0x40010c00 0x400>;
161			interrupts = <14>;
162			clocks = <&cmu clk_HFPERCLKTIMER3>;
163		};
164
165		cmu: cmu@400c8000 {
166			compatible = "efm32gg,cmu";
167			reg = <0x400c8000 0x400>;
168			interrupts = <32>;
169			#clock-cells = <1>;
170		};
171	};
172};