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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Library implementing the most common irq chip callback functions
4 *
5 * Copyright (C) 2011, Thomas Gleixner
6 */
7#include <linux/io.h>
8#include <linux/irq.h>
9#include <linux/slab.h>
10#include <linux/export.h>
11#include <linux/irqdomain.h>
12#include <linux/interrupt.h>
13#include <linux/kernel_stat.h>
14#include <linux/syscore_ops.h>
15
16#include "internals.h"
17
18static LIST_HEAD(gc_list);
19static DEFINE_RAW_SPINLOCK(gc_lock);
20
21/**
22 * irq_gc_noop - NOOP function
23 * @d: irq_data
24 */
25void irq_gc_noop(struct irq_data *d)
26{
27}
28EXPORT_SYMBOL_GPL(irq_gc_noop);
29
30/**
31 * irq_gc_mask_disable_reg - Mask chip via disable register
32 * @d: irq_data
33 *
34 * Chip has separate enable/disable registers instead of a single mask
35 * register.
36 */
37void irq_gc_mask_disable_reg(struct irq_data *d)
38{
39 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
40 struct irq_chip_type *ct = irq_data_get_chip_type(d);
41 u32 mask = d->mask;
42
43 irq_gc_lock(gc);
44 irq_reg_writel(gc, mask, ct->regs.disable);
45 *ct->mask_cache &= ~mask;
46 irq_gc_unlock(gc);
47}
48EXPORT_SYMBOL_GPL(irq_gc_mask_disable_reg);
49
50/**
51 * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
52 * @d: irq_data
53 *
54 * Chip has a single mask register. Values of this register are cached
55 * and protected by gc->lock
56 */
57void irq_gc_mask_set_bit(struct irq_data *d)
58{
59 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
60 struct irq_chip_type *ct = irq_data_get_chip_type(d);
61 u32 mask = d->mask;
62
63 irq_gc_lock(gc);
64 *ct->mask_cache |= mask;
65 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
66 irq_gc_unlock(gc);
67}
68EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);
69
70/**
71 * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
72 * @d: irq_data
73 *
74 * Chip has a single mask register. Values of this register are cached
75 * and protected by gc->lock
76 */
77void irq_gc_mask_clr_bit(struct irq_data *d)
78{
79 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
80 struct irq_chip_type *ct = irq_data_get_chip_type(d);
81 u32 mask = d->mask;
82
83 irq_gc_lock(gc);
84 *ct->mask_cache &= ~mask;
85 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
86 irq_gc_unlock(gc);
87}
88EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit);
89
90/**
91 * irq_gc_unmask_enable_reg - Unmask chip via enable register
92 * @d: irq_data
93 *
94 * Chip has separate enable/disable registers instead of a single mask
95 * register.
96 */
97void irq_gc_unmask_enable_reg(struct irq_data *d)
98{
99 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
100 struct irq_chip_type *ct = irq_data_get_chip_type(d);
101 u32 mask = d->mask;
102
103 irq_gc_lock(gc);
104 irq_reg_writel(gc, mask, ct->regs.enable);
105 *ct->mask_cache |= mask;
106 irq_gc_unlock(gc);
107}
108EXPORT_SYMBOL_GPL(irq_gc_unmask_enable_reg);
109
110/**
111 * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
112 * @d: irq_data
113 */
114void irq_gc_ack_set_bit(struct irq_data *d)
115{
116 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
117 struct irq_chip_type *ct = irq_data_get_chip_type(d);
118 u32 mask = d->mask;
119
120 irq_gc_lock(gc);
121 irq_reg_writel(gc, mask, ct->regs.ack);
122 irq_gc_unlock(gc);
123}
124EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit);
125
126/**
127 * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
128 * @d: irq_data
129 */
130void irq_gc_ack_clr_bit(struct irq_data *d)
131{
132 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
133 struct irq_chip_type *ct = irq_data_get_chip_type(d);
134 u32 mask = ~d->mask;
135
136 irq_gc_lock(gc);
137 irq_reg_writel(gc, mask, ct->regs.ack);
138 irq_gc_unlock(gc);
139}
140
141/**
142 * irq_gc_mask_disable_and_ack_set - Mask and ack pending interrupt
143 * @d: irq_data
144 *
145 * This generic implementation of the irq_mask_ack method is for chips
146 * with separate enable/disable registers instead of a single mask
147 * register and where a pending interrupt is acknowledged by setting a
148 * bit.
149 *
150 * Note: This is the only permutation currently used. Similar generic
151 * functions should be added here if other permutations are required.
152 */
153void irq_gc_mask_disable_and_ack_set(struct irq_data *d)
154{
155 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
156 struct irq_chip_type *ct = irq_data_get_chip_type(d);
157 u32 mask = d->mask;
158
159 irq_gc_lock(gc);
160 irq_reg_writel(gc, mask, ct->regs.disable);
161 *ct->mask_cache &= ~mask;
162 irq_reg_writel(gc, mask, ct->regs.ack);
163 irq_gc_unlock(gc);
164}
165
166/**
167 * irq_gc_eoi - EOI interrupt
168 * @d: irq_data
169 */
170void irq_gc_eoi(struct irq_data *d)
171{
172 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
173 struct irq_chip_type *ct = irq_data_get_chip_type(d);
174 u32 mask = d->mask;
175
176 irq_gc_lock(gc);
177 irq_reg_writel(gc, mask, ct->regs.eoi);
178 irq_gc_unlock(gc);
179}
180
181/**
182 * irq_gc_set_wake - Set/clr wake bit for an interrupt
183 * @d: irq_data
184 * @on: Indicates whether the wake bit should be set or cleared
185 *
186 * For chips where the wake from suspend functionality is not
187 * configured in a separate register and the wakeup active state is
188 * just stored in a bitmask.
189 */
190int irq_gc_set_wake(struct irq_data *d, unsigned int on)
191{
192 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
193 u32 mask = d->mask;
194
195 if (!(mask & gc->wake_enabled))
196 return -EINVAL;
197
198 irq_gc_lock(gc);
199 if (on)
200 gc->wake_active |= mask;
201 else
202 gc->wake_active &= ~mask;
203 irq_gc_unlock(gc);
204 return 0;
205}
206EXPORT_SYMBOL_GPL(irq_gc_set_wake);
207
208static u32 irq_readl_be(void __iomem *addr)
209{
210 return ioread32be(addr);
211}
212
213static void irq_writel_be(u32 val, void __iomem *addr)
214{
215 iowrite32be(val, addr);
216}
217
218void irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
219 int num_ct, unsigned int irq_base,
220 void __iomem *reg_base, irq_flow_handler_t handler)
221{
222 raw_spin_lock_init(&gc->lock);
223 gc->num_ct = num_ct;
224 gc->irq_base = irq_base;
225 gc->reg_base = reg_base;
226 gc->chip_types->chip.name = name;
227 gc->chip_types->handler = handler;
228}
229
230/**
231 * irq_alloc_generic_chip - Allocate a generic chip and initialize it
232 * @name: Name of the irq chip
233 * @num_ct: Number of irq_chip_type instances associated with this
234 * @irq_base: Interrupt base nr for this chip
235 * @reg_base: Register base address (virtual)
236 * @handler: Default flow handler associated with this chip
237 *
238 * Returns an initialized irq_chip_generic structure. The chip defaults
239 * to the primary (index 0) irq_chip_type and @handler
240 */
241struct irq_chip_generic *
242irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
243 void __iomem *reg_base, irq_flow_handler_t handler)
244{
245 struct irq_chip_generic *gc;
246
247 gc = kzalloc(struct_size(gc, chip_types, num_ct), GFP_KERNEL);
248 if (gc) {
249 irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base,
250 handler);
251 }
252 return gc;
253}
254EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);
255
256static void
257irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags)
258{
259 struct irq_chip_type *ct = gc->chip_types;
260 u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
261 int i;
262
263 for (i = 0; i < gc->num_ct; i++) {
264 if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
265 mskptr = &ct[i].mask_cache_priv;
266 mskreg = ct[i].regs.mask;
267 }
268 ct[i].mask_cache = mskptr;
269 if (flags & IRQ_GC_INIT_MASK_CACHE)
270 *mskptr = irq_reg_readl(gc, mskreg);
271 }
272}
273
274/**
275 * __irq_alloc_domain_generic_chips - Allocate generic chips for an irq domain
276 * @d: irq domain for which to allocate chips
277 * @irqs_per_chip: Number of interrupts each chip handles (max 32)
278 * @num_ct: Number of irq_chip_type instances associated with this
279 * @name: Name of the irq chip
280 * @handler: Default flow handler associated with these chips
281 * @clr: IRQ_* bits to clear in the mapping function
282 * @set: IRQ_* bits to set in the mapping function
283 * @gcflags: Generic chip specific setup flags
284 */
285int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
286 int num_ct, const char *name,
287 irq_flow_handler_t handler,
288 unsigned int clr, unsigned int set,
289 enum irq_gc_flags gcflags)
290{
291 struct irq_domain_chip_generic *dgc;
292 struct irq_chip_generic *gc;
293 unsigned long flags;
294 int numchips, i;
295 size_t dgc_sz;
296 size_t gc_sz;
297 size_t sz;
298 void *tmp;
299
300 if (d->gc)
301 return -EBUSY;
302
303 numchips = DIV_ROUND_UP(d->revmap_size, irqs_per_chip);
304 if (!numchips)
305 return -EINVAL;
306
307 /* Allocate a pointer, generic chip and chiptypes for each chip */
308 gc_sz = struct_size(gc, chip_types, num_ct);
309 dgc_sz = struct_size(dgc, gc, numchips);
310 sz = dgc_sz + numchips * gc_sz;
311
312 tmp = dgc = kzalloc(sz, GFP_KERNEL);
313 if (!dgc)
314 return -ENOMEM;
315 dgc->irqs_per_chip = irqs_per_chip;
316 dgc->num_chips = numchips;
317 dgc->irq_flags_to_set = set;
318 dgc->irq_flags_to_clear = clr;
319 dgc->gc_flags = gcflags;
320 d->gc = dgc;
321
322 /* Calc pointer to the first generic chip */
323 tmp += dgc_sz;
324 for (i = 0; i < numchips; i++) {
325 /* Store the pointer to the generic chip */
326 dgc->gc[i] = gc = tmp;
327 irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
328 NULL, handler);
329
330 gc->domain = d;
331 if (gcflags & IRQ_GC_BE_IO) {
332 gc->reg_readl = &irq_readl_be;
333 gc->reg_writel = &irq_writel_be;
334 }
335
336 raw_spin_lock_irqsave(&gc_lock, flags);
337 list_add_tail(&gc->list, &gc_list);
338 raw_spin_unlock_irqrestore(&gc_lock, flags);
339 /* Calc pointer to the next generic chip */
340 tmp += gc_sz;
341 }
342 return 0;
343}
344EXPORT_SYMBOL_GPL(__irq_alloc_domain_generic_chips);
345
346static struct irq_chip_generic *
347__irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
348{
349 struct irq_domain_chip_generic *dgc = d->gc;
350 int idx;
351
352 if (!dgc)
353 return ERR_PTR(-ENODEV);
354 idx = hw_irq / dgc->irqs_per_chip;
355 if (idx >= dgc->num_chips)
356 return ERR_PTR(-EINVAL);
357 return dgc->gc[idx];
358}
359
360/**
361 * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
362 * @d: irq domain pointer
363 * @hw_irq: Hardware interrupt number
364 */
365struct irq_chip_generic *
366irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
367{
368 struct irq_chip_generic *gc = __irq_get_domain_generic_chip(d, hw_irq);
369
370 return !IS_ERR(gc) ? gc : NULL;
371}
372EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);
373
374/*
375 * Separate lockdep classes for interrupt chip which can nest irq_desc
376 * lock and request mutex.
377 */
378static struct lock_class_key irq_nested_lock_class;
379static struct lock_class_key irq_nested_request_class;
380
381/*
382 * irq_map_generic_chip - Map a generic chip for an irq domain
383 */
384int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
385 irq_hw_number_t hw_irq)
386{
387 struct irq_data *data = irq_domain_get_irq_data(d, virq);
388 struct irq_domain_chip_generic *dgc = d->gc;
389 struct irq_chip_generic *gc;
390 struct irq_chip_type *ct;
391 struct irq_chip *chip;
392 unsigned long flags;
393 int idx;
394
395 gc = __irq_get_domain_generic_chip(d, hw_irq);
396 if (IS_ERR(gc))
397 return PTR_ERR(gc);
398
399 idx = hw_irq % dgc->irqs_per_chip;
400
401 if (test_bit(idx, &gc->unused))
402 return -ENOTSUPP;
403
404 if (test_bit(idx, &gc->installed))
405 return -EBUSY;
406
407 ct = gc->chip_types;
408 chip = &ct->chip;
409
410 /* We only init the cache for the first mapping of a generic chip */
411 if (!gc->installed) {
412 raw_spin_lock_irqsave(&gc->lock, flags);
413 irq_gc_init_mask_cache(gc, dgc->gc_flags);
414 raw_spin_unlock_irqrestore(&gc->lock, flags);
415 }
416
417 /* Mark the interrupt as installed */
418 set_bit(idx, &gc->installed);
419
420 if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK)
421 irq_set_lockdep_class(virq, &irq_nested_lock_class,
422 &irq_nested_request_class);
423
424 if (chip->irq_calc_mask)
425 chip->irq_calc_mask(data);
426 else
427 data->mask = 1 << idx;
428
429 irq_domain_set_info(d, virq, hw_irq, chip, gc, ct->handler, NULL, NULL);
430 irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
431 return 0;
432}
433
434void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
435{
436 struct irq_data *data = irq_domain_get_irq_data(d, virq);
437 struct irq_domain_chip_generic *dgc = d->gc;
438 unsigned int hw_irq = data->hwirq;
439 struct irq_chip_generic *gc;
440 int irq_idx;
441
442 gc = irq_get_domain_generic_chip(d, hw_irq);
443 if (!gc)
444 return;
445
446 irq_idx = hw_irq % dgc->irqs_per_chip;
447
448 clear_bit(irq_idx, &gc->installed);
449 irq_domain_set_info(d, virq, hw_irq, &no_irq_chip, NULL, NULL, NULL,
450 NULL);
451
452}
453
454const struct irq_domain_ops irq_generic_chip_ops = {
455 .map = irq_map_generic_chip,
456 .unmap = irq_unmap_generic_chip,
457 .xlate = irq_domain_xlate_onetwocell,
458};
459EXPORT_SYMBOL_GPL(irq_generic_chip_ops);
460
461/**
462 * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
463 * @gc: Generic irq chip holding all data
464 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
465 * @flags: Flags for initialization
466 * @clr: IRQ_* bits to clear
467 * @set: IRQ_* bits to set
468 *
469 * Set up max. 32 interrupts starting from gc->irq_base. Note, this
470 * initializes all interrupts to the primary irq_chip_type and its
471 * associated handler.
472 */
473void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
474 enum irq_gc_flags flags, unsigned int clr,
475 unsigned int set)
476{
477 struct irq_chip_type *ct = gc->chip_types;
478 struct irq_chip *chip = &ct->chip;
479 unsigned int i;
480
481 raw_spin_lock(&gc_lock);
482 list_add_tail(&gc->list, &gc_list);
483 raw_spin_unlock(&gc_lock);
484
485 irq_gc_init_mask_cache(gc, flags);
486
487 for (i = gc->irq_base; msk; msk >>= 1, i++) {
488 if (!(msk & 0x01))
489 continue;
490
491 if (flags & IRQ_GC_INIT_NESTED_LOCK)
492 irq_set_lockdep_class(i, &irq_nested_lock_class,
493 &irq_nested_request_class);
494
495 if (!(flags & IRQ_GC_NO_MASK)) {
496 struct irq_data *d = irq_get_irq_data(i);
497
498 if (chip->irq_calc_mask)
499 chip->irq_calc_mask(d);
500 else
501 d->mask = 1 << (i - gc->irq_base);
502 }
503 irq_set_chip_and_handler(i, chip, ct->handler);
504 irq_set_chip_data(i, gc);
505 irq_modify_status(i, clr, set);
506 }
507 gc->irq_cnt = i - gc->irq_base;
508}
509EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
510
511/**
512 * irq_setup_alt_chip - Switch to alternative chip
513 * @d: irq_data for this interrupt
514 * @type: Flow type to be initialized
515 *
516 * Only to be called from chip->irq_set_type() callbacks.
517 */
518int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
519{
520 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
521 struct irq_chip_type *ct = gc->chip_types;
522 unsigned int i;
523
524 for (i = 0; i < gc->num_ct; i++, ct++) {
525 if (ct->type & type) {
526 d->chip = &ct->chip;
527 irq_data_to_desc(d)->handle_irq = ct->handler;
528 return 0;
529 }
530 }
531 return -EINVAL;
532}
533EXPORT_SYMBOL_GPL(irq_setup_alt_chip);
534
535/**
536 * irq_remove_generic_chip - Remove a chip
537 * @gc: Generic irq chip holding all data
538 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
539 * @clr: IRQ_* bits to clear
540 * @set: IRQ_* bits to set
541 *
542 * Remove up to 32 interrupts starting from gc->irq_base.
543 */
544void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
545 unsigned int clr, unsigned int set)
546{
547 unsigned int i = gc->irq_base;
548
549 raw_spin_lock(&gc_lock);
550 list_del(&gc->list);
551 raw_spin_unlock(&gc_lock);
552
553 for (; msk; msk >>= 1, i++) {
554 if (!(msk & 0x01))
555 continue;
556
557 /* Remove handler first. That will mask the irq line */
558 irq_set_handler(i, NULL);
559 irq_set_chip(i, &no_irq_chip);
560 irq_set_chip_data(i, NULL);
561 irq_modify_status(i, clr, set);
562 }
563}
564EXPORT_SYMBOL_GPL(irq_remove_generic_chip);
565
566static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc)
567{
568 unsigned int virq;
569
570 if (!gc->domain)
571 return irq_get_irq_data(gc->irq_base);
572
573 /*
574 * We don't know which of the irqs has been actually
575 * installed. Use the first one.
576 */
577 if (!gc->installed)
578 return NULL;
579
580 virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed));
581 return virq ? irq_get_irq_data(virq) : NULL;
582}
583
584#ifdef CONFIG_PM
585static int irq_gc_suspend(void)
586{
587 struct irq_chip_generic *gc;
588
589 list_for_each_entry(gc, &gc_list, list) {
590 struct irq_chip_type *ct = gc->chip_types;
591
592 if (ct->chip.irq_suspend) {
593 struct irq_data *data = irq_gc_get_irq_data(gc);
594
595 if (data)
596 ct->chip.irq_suspend(data);
597 }
598
599 if (gc->suspend)
600 gc->suspend(gc);
601 }
602 return 0;
603}
604
605static void irq_gc_resume(void)
606{
607 struct irq_chip_generic *gc;
608
609 list_for_each_entry(gc, &gc_list, list) {
610 struct irq_chip_type *ct = gc->chip_types;
611
612 if (gc->resume)
613 gc->resume(gc);
614
615 if (ct->chip.irq_resume) {
616 struct irq_data *data = irq_gc_get_irq_data(gc);
617
618 if (data)
619 ct->chip.irq_resume(data);
620 }
621 }
622}
623#else
624#define irq_gc_suspend NULL
625#define irq_gc_resume NULL
626#endif
627
628static void irq_gc_shutdown(void)
629{
630 struct irq_chip_generic *gc;
631
632 list_for_each_entry(gc, &gc_list, list) {
633 struct irq_chip_type *ct = gc->chip_types;
634
635 if (ct->chip.irq_pm_shutdown) {
636 struct irq_data *data = irq_gc_get_irq_data(gc);
637
638 if (data)
639 ct->chip.irq_pm_shutdown(data);
640 }
641 }
642}
643
644static struct syscore_ops irq_gc_syscore_ops = {
645 .suspend = irq_gc_suspend,
646 .resume = irq_gc_resume,
647 .shutdown = irq_gc_shutdown,
648};
649
650static int __init irq_gc_init_ops(void)
651{
652 register_syscore_ops(&irq_gc_syscore_ops);
653 return 0;
654}
655device_initcall(irq_gc_init_ops);
1/*
2 * Library implementing the most common irq chip callback functions
3 *
4 * Copyright (C) 2011, Thomas Gleixner
5 */
6#include <linux/io.h>
7#include <linux/irq.h>
8#include <linux/slab.h>
9#include <linux/interrupt.h>
10#include <linux/kernel_stat.h>
11#include <linux/syscore_ops.h>
12
13#include "internals.h"
14
15static LIST_HEAD(gc_list);
16static DEFINE_RAW_SPINLOCK(gc_lock);
17
18static inline struct irq_chip_regs *cur_regs(struct irq_data *d)
19{
20 return &container_of(d->chip, struct irq_chip_type, chip)->regs;
21}
22
23/**
24 * irq_gc_noop - NOOP function
25 * @d: irq_data
26 */
27void irq_gc_noop(struct irq_data *d)
28{
29}
30
31/**
32 * irq_gc_mask_disable_reg - Mask chip via disable register
33 * @d: irq_data
34 *
35 * Chip has separate enable/disable registers instead of a single mask
36 * register.
37 */
38void irq_gc_mask_disable_reg(struct irq_data *d)
39{
40 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
41 u32 mask = 1 << (d->irq - gc->irq_base);
42
43 irq_gc_lock(gc);
44 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->disable);
45 gc->mask_cache &= ~mask;
46 irq_gc_unlock(gc);
47}
48
49/**
50 * irq_gc_mask_set_mask_bit - Mask chip via setting bit in mask register
51 * @d: irq_data
52 *
53 * Chip has a single mask register. Values of this register are cached
54 * and protected by gc->lock
55 */
56void irq_gc_mask_set_bit(struct irq_data *d)
57{
58 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
59 u32 mask = 1 << (d->irq - gc->irq_base);
60
61 irq_gc_lock(gc);
62 gc->mask_cache |= mask;
63 irq_reg_writel(gc->mask_cache, gc->reg_base + cur_regs(d)->mask);
64 irq_gc_unlock(gc);
65}
66
67/**
68 * irq_gc_mask_set_mask_bit - Mask chip via clearing bit in mask register
69 * @d: irq_data
70 *
71 * Chip has a single mask register. Values of this register are cached
72 * and protected by gc->lock
73 */
74void irq_gc_mask_clr_bit(struct irq_data *d)
75{
76 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
77 u32 mask = 1 << (d->irq - gc->irq_base);
78
79 irq_gc_lock(gc);
80 gc->mask_cache &= ~mask;
81 irq_reg_writel(gc->mask_cache, gc->reg_base + cur_regs(d)->mask);
82 irq_gc_unlock(gc);
83}
84
85/**
86 * irq_gc_unmask_enable_reg - Unmask chip via enable register
87 * @d: irq_data
88 *
89 * Chip has separate enable/disable registers instead of a single mask
90 * register.
91 */
92void irq_gc_unmask_enable_reg(struct irq_data *d)
93{
94 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
95 u32 mask = 1 << (d->irq - gc->irq_base);
96
97 irq_gc_lock(gc);
98 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->enable);
99 gc->mask_cache |= mask;
100 irq_gc_unlock(gc);
101}
102
103/**
104 * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
105 * @d: irq_data
106 */
107void irq_gc_ack_set_bit(struct irq_data *d)
108{
109 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
110 u32 mask = 1 << (d->irq - gc->irq_base);
111
112 irq_gc_lock(gc);
113 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
114 irq_gc_unlock(gc);
115}
116
117/**
118 * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
119 * @d: irq_data
120 */
121void irq_gc_ack_clr_bit(struct irq_data *d)
122{
123 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
124 u32 mask = ~(1 << (d->irq - gc->irq_base));
125
126 irq_gc_lock(gc);
127 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
128 irq_gc_unlock(gc);
129}
130
131/**
132 * irq_gc_mask_disable_reg_and_ack- Mask and ack pending interrupt
133 * @d: irq_data
134 */
135void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
136{
137 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
138 u32 mask = 1 << (d->irq - gc->irq_base);
139
140 irq_gc_lock(gc);
141 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->mask);
142 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
143 irq_gc_unlock(gc);
144}
145
146/**
147 * irq_gc_eoi - EOI interrupt
148 * @d: irq_data
149 */
150void irq_gc_eoi(struct irq_data *d)
151{
152 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
153 u32 mask = 1 << (d->irq - gc->irq_base);
154
155 irq_gc_lock(gc);
156 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->eoi);
157 irq_gc_unlock(gc);
158}
159
160/**
161 * irq_gc_set_wake - Set/clr wake bit for an interrupt
162 * @d: irq_data
163 *
164 * For chips where the wake from suspend functionality is not
165 * configured in a separate register and the wakeup active state is
166 * just stored in a bitmask.
167 */
168int irq_gc_set_wake(struct irq_data *d, unsigned int on)
169{
170 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
171 u32 mask = 1 << (d->irq - gc->irq_base);
172
173 if (!(mask & gc->wake_enabled))
174 return -EINVAL;
175
176 irq_gc_lock(gc);
177 if (on)
178 gc->wake_active |= mask;
179 else
180 gc->wake_active &= ~mask;
181 irq_gc_unlock(gc);
182 return 0;
183}
184
185/**
186 * irq_alloc_generic_chip - Allocate a generic chip and initialize it
187 * @name: Name of the irq chip
188 * @num_ct: Number of irq_chip_type instances associated with this
189 * @irq_base: Interrupt base nr for this chip
190 * @reg_base: Register base address (virtual)
191 * @handler: Default flow handler associated with this chip
192 *
193 * Returns an initialized irq_chip_generic structure. The chip defaults
194 * to the primary (index 0) irq_chip_type and @handler
195 */
196struct irq_chip_generic *
197irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
198 void __iomem *reg_base, irq_flow_handler_t handler)
199{
200 struct irq_chip_generic *gc;
201 unsigned long sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
202
203 gc = kzalloc(sz, GFP_KERNEL);
204 if (gc) {
205 raw_spin_lock_init(&gc->lock);
206 gc->num_ct = num_ct;
207 gc->irq_base = irq_base;
208 gc->reg_base = reg_base;
209 gc->chip_types->chip.name = name;
210 gc->chip_types->handler = handler;
211 }
212 return gc;
213}
214
215/*
216 * Separate lockdep class for interrupt chip which can nest irq_desc
217 * lock.
218 */
219static struct lock_class_key irq_nested_lock_class;
220
221/**
222 * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
223 * @gc: Generic irq chip holding all data
224 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
225 * @flags: Flags for initialization
226 * @clr: IRQ_* bits to clear
227 * @set: IRQ_* bits to set
228 *
229 * Set up max. 32 interrupts starting from gc->irq_base. Note, this
230 * initializes all interrupts to the primary irq_chip_type and its
231 * associated handler.
232 */
233void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
234 enum irq_gc_flags flags, unsigned int clr,
235 unsigned int set)
236{
237 struct irq_chip_type *ct = gc->chip_types;
238 unsigned int i;
239
240 raw_spin_lock(&gc_lock);
241 list_add_tail(&gc->list, &gc_list);
242 raw_spin_unlock(&gc_lock);
243
244 /* Init mask cache ? */
245 if (flags & IRQ_GC_INIT_MASK_CACHE)
246 gc->mask_cache = irq_reg_readl(gc->reg_base + ct->regs.mask);
247
248 for (i = gc->irq_base; msk; msk >>= 1, i++) {
249 if (!(msk & 0x01))
250 continue;
251
252 if (flags & IRQ_GC_INIT_NESTED_LOCK)
253 irq_set_lockdep_class(i, &irq_nested_lock_class);
254
255 irq_set_chip_and_handler(i, &ct->chip, ct->handler);
256 irq_set_chip_data(i, gc);
257 irq_modify_status(i, clr, set);
258 }
259 gc->irq_cnt = i - gc->irq_base;
260}
261
262/**
263 * irq_setup_alt_chip - Switch to alternative chip
264 * @d: irq_data for this interrupt
265 * @type Flow type to be initialized
266 *
267 * Only to be called from chip->irq_set_type() callbacks.
268 */
269int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
270{
271 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
272 struct irq_chip_type *ct = gc->chip_types;
273 unsigned int i;
274
275 for (i = 0; i < gc->num_ct; i++, ct++) {
276 if (ct->type & type) {
277 d->chip = &ct->chip;
278 irq_data_to_desc(d)->handle_irq = ct->handler;
279 return 0;
280 }
281 }
282 return -EINVAL;
283}
284
285/**
286 * irq_remove_generic_chip - Remove a chip
287 * @gc: Generic irq chip holding all data
288 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
289 * @clr: IRQ_* bits to clear
290 * @set: IRQ_* bits to set
291 *
292 * Remove up to 32 interrupts starting from gc->irq_base.
293 */
294void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
295 unsigned int clr, unsigned int set)
296{
297 unsigned int i = gc->irq_base;
298
299 raw_spin_lock(&gc_lock);
300 list_del(&gc->list);
301 raw_spin_unlock(&gc_lock);
302
303 for (; msk; msk >>= 1, i++) {
304 if (!(msk & 0x01))
305 continue;
306
307 /* Remove handler first. That will mask the irq line */
308 irq_set_handler(i, NULL);
309 irq_set_chip(i, &no_irq_chip);
310 irq_set_chip_data(i, NULL);
311 irq_modify_status(i, clr, set);
312 }
313}
314
315#ifdef CONFIG_PM
316static int irq_gc_suspend(void)
317{
318 struct irq_chip_generic *gc;
319
320 list_for_each_entry(gc, &gc_list, list) {
321 struct irq_chip_type *ct = gc->chip_types;
322
323 if (ct->chip.irq_suspend)
324 ct->chip.irq_suspend(irq_get_irq_data(gc->irq_base));
325 }
326 return 0;
327}
328
329static void irq_gc_resume(void)
330{
331 struct irq_chip_generic *gc;
332
333 list_for_each_entry(gc, &gc_list, list) {
334 struct irq_chip_type *ct = gc->chip_types;
335
336 if (ct->chip.irq_resume)
337 ct->chip.irq_resume(irq_get_irq_data(gc->irq_base));
338 }
339}
340#else
341#define irq_gc_suspend NULL
342#define irq_gc_resume NULL
343#endif
344
345static void irq_gc_shutdown(void)
346{
347 struct irq_chip_generic *gc;
348
349 list_for_each_entry(gc, &gc_list, list) {
350 struct irq_chip_type *ct = gc->chip_types;
351
352 if (ct->chip.irq_pm_shutdown)
353 ct->chip.irq_pm_shutdown(irq_get_irq_data(gc->irq_base));
354 }
355}
356
357static struct syscore_ops irq_gc_syscore_ops = {
358 .suspend = irq_gc_suspend,
359 .resume = irq_gc_resume,
360 .shutdown = irq_gc_shutdown,
361};
362
363static int __init irq_gc_init_ops(void)
364{
365 register_syscore_ops(&irq_gc_syscore_ops);
366 return 0;
367}
368device_initcall(irq_gc_init_ops);