1/* SPDX-License-Identifier: GPL-2.0 */
  2#ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H
  3#define DT_BINDINGS_MEMORY_TEGRA30_MC_H
  4
  5#define TEGRA_SWGROUP_PTC	0
  6#define TEGRA_SWGROUP_DC	1
  7#define TEGRA_SWGROUP_DCB	2
  8#define TEGRA_SWGROUP_EPP	3
  9#define TEGRA_SWGROUP_G2	4
 10#define TEGRA_SWGROUP_MPE	5
 11#define TEGRA_SWGROUP_VI	6
 12#define TEGRA_SWGROUP_AFI	7
 13#define TEGRA_SWGROUP_AVPC	8
 14#define TEGRA_SWGROUP_NV	9
 15#define TEGRA_SWGROUP_NV2	10
 16#define TEGRA_SWGROUP_HDA	11
 17#define TEGRA_SWGROUP_HC	12
 18#define TEGRA_SWGROUP_PPCS	13
 19#define TEGRA_SWGROUP_SATA	14
 20#define TEGRA_SWGROUP_VDE	15
 21#define TEGRA_SWGROUP_MPCORELP	16
 22#define TEGRA_SWGROUP_MPCORE	17
 23#define TEGRA_SWGROUP_ISP	18
 24
 25#define TEGRA30_MC_RESET_AFI		0
 26#define TEGRA30_MC_RESET_AVPC		1
 27#define TEGRA30_MC_RESET_DC		2
 28#define TEGRA30_MC_RESET_DCB		3
 29#define TEGRA30_MC_RESET_EPP		4
 30#define TEGRA30_MC_RESET_2D		5
 31#define TEGRA30_MC_RESET_HC		6
 32#define TEGRA30_MC_RESET_HDA		7
 33#define TEGRA30_MC_RESET_ISP		8
 34#define TEGRA30_MC_RESET_MPCORE		9
 35#define TEGRA30_MC_RESET_MPCORELP	10
 36#define TEGRA30_MC_RESET_MPE		11
 37#define TEGRA30_MC_RESET_3D		12
 38#define TEGRA30_MC_RESET_3D2		13
 39#define TEGRA30_MC_RESET_PPCS		14
 40#define TEGRA30_MC_RESET_SATA		15
 41#define TEGRA30_MC_RESET_VDE		16
 42#define TEGRA30_MC_RESET_VI		17
 43
 44#define TEGRA30_MC_PTCR			0
 45#define TEGRA30_MC_DISPLAY0A		1
 46#define TEGRA30_MC_DISPLAY0AB		2
 47#define TEGRA30_MC_DISPLAY0B		3
 48#define TEGRA30_MC_DISPLAY0BB		4
 49#define TEGRA30_MC_DISPLAY0C		5
 50#define TEGRA30_MC_DISPLAY0CB		6
 51#define TEGRA30_MC_DISPLAY1B		7
 52#define TEGRA30_MC_DISPLAY1BB		8
 53#define TEGRA30_MC_EPPUP		9
 54#define TEGRA30_MC_G2PR			10
 55#define TEGRA30_MC_G2SR			11
 56#define TEGRA30_MC_MPEUNIFBR		12
 57#define TEGRA30_MC_VIRUV		13
 58#define TEGRA30_MC_AFIR			14
 59#define TEGRA30_MC_AVPCARM7R		15
 60#define TEGRA30_MC_DISPLAYHC		16
 61#define TEGRA30_MC_DISPLAYHCB		17
 62#define TEGRA30_MC_FDCDRD		18
 63#define TEGRA30_MC_FDCDRD2		19
 64#define TEGRA30_MC_G2DR			20
 65#define TEGRA30_MC_HDAR			21
 66#define TEGRA30_MC_HOST1XDMAR		22
 67#define TEGRA30_MC_HOST1XR		23
 68#define TEGRA30_MC_IDXSRD		24
 69#define TEGRA30_MC_IDXSRD2		25
 70#define TEGRA30_MC_MPE_IPRED		26
 71#define TEGRA30_MC_MPEAMEMRD		27
 72#define TEGRA30_MC_MPECSRD		28
 73#define TEGRA30_MC_PPCSAHBDMAR		29
 74#define TEGRA30_MC_PPCSAHBSLVR		30
 75#define TEGRA30_MC_SATAR		31
 76#define TEGRA30_MC_TEXSRD		32
 77#define TEGRA30_MC_TEXSRD2		33
 78#define TEGRA30_MC_VDEBSEVR		34
 79#define TEGRA30_MC_VDEMBER		35
 80#define TEGRA30_MC_VDEMCER		36
 81#define TEGRA30_MC_VDETPER		37
 82#define TEGRA30_MC_MPCORELPR		38
 83#define TEGRA30_MC_MPCORER		39
 84#define TEGRA30_MC_EPPU			40
 85#define TEGRA30_MC_EPPV			41
 86#define TEGRA30_MC_EPPY			42
 87#define TEGRA30_MC_MPEUNIFBW		43
 88#define TEGRA30_MC_VIWSB		44
 89#define TEGRA30_MC_VIWU			45
 90#define TEGRA30_MC_VIWV			46
 91#define TEGRA30_MC_VIWY			47
 92#define TEGRA30_MC_G2DW			48
 93#define TEGRA30_MC_AFIW			49
 94#define TEGRA30_MC_AVPCARM7W		50
 95#define TEGRA30_MC_FDCDWR		51
 96#define TEGRA30_MC_FDCDWR2		52
 97#define TEGRA30_MC_HDAW			53
 98#define TEGRA30_MC_HOST1XW		54
 99#define TEGRA30_MC_ISPW			55
100#define TEGRA30_MC_MPCORELPW		56
101#define TEGRA30_MC_MPCOREW		57
102#define TEGRA30_MC_MPECSWR		58
103#define TEGRA30_MC_PPCSAHBDMAW		59
104#define TEGRA30_MC_PPCSAHBSLVW		60
105#define TEGRA30_MC_SATAW		61
106#define TEGRA30_MC_VDEBSEVW		62
107#define TEGRA30_MC_VDEDBGW		63
108#define TEGRA30_MC_VDEMBEW		64
109#define TEGRA30_MC_VDETPMW		65
110
111#endif