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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2017 MediaTek Inc.
4 * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
5 */
6
7#ifndef _DT_BINDINGS_CLK_MT6797_H
8#define _DT_BINDINGS_CLK_MT6797_H
9
10/* TOPCKGEN */
11#define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE 1
12#define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX 2
13#define CLK_TOP_MUX_AXI 3
14#define CLK_TOP_MUX_MEM 4
15#define CLK_TOP_MUX_DDRPHYCFG 5
16#define CLK_TOP_MUX_MM 6
17#define CLK_TOP_MUX_PWM 7
18#define CLK_TOP_MUX_VDEC 8
19#define CLK_TOP_MUX_VENC 9
20#define CLK_TOP_MUX_MFG 10
21#define CLK_TOP_MUX_CAMTG 11
22#define CLK_TOP_MUX_UART 12
23#define CLK_TOP_MUX_SPI 13
24#define CLK_TOP_MUX_ULPOSC_SPI_CK_MUX 14
25#define CLK_TOP_MUX_USB20 15
26#define CLK_TOP_MUX_MSDC50_0_HCLK 16
27#define CLK_TOP_MUX_MSDC50_0 17
28#define CLK_TOP_MUX_MSDC30_1 18
29#define CLK_TOP_MUX_MSDC30_2 19
30#define CLK_TOP_MUX_AUDIO 20
31#define CLK_TOP_MUX_AUD_INTBUS 21
32#define CLK_TOP_MUX_PMICSPI 22
33#define CLK_TOP_MUX_SCP 23
34#define CLK_TOP_MUX_ATB 24
35#define CLK_TOP_MUX_MJC 25
36#define CLK_TOP_MUX_DPI0 26
37#define CLK_TOP_MUX_AUD_1 27
38#define CLK_TOP_MUX_AUD_2 28
39#define CLK_TOP_MUX_SSUSB_TOP_SYS 29
40#define CLK_TOP_MUX_SPM 30
41#define CLK_TOP_MUX_BSI_SPI 31
42#define CLK_TOP_MUX_AUDIO_H 32
43#define CLK_TOP_MUX_ANC_MD32 33
44#define CLK_TOP_MUX_MFG_52M 34
45#define CLK_TOP_SYSPLL_CK 35
46#define CLK_TOP_SYSPLL_D2 36
47#define CLK_TOP_SYSPLL1_D2 37
48#define CLK_TOP_SYSPLL1_D4 38
49#define CLK_TOP_SYSPLL1_D8 39
50#define CLK_TOP_SYSPLL1_D16 40
51#define CLK_TOP_SYSPLL_D3 41
52#define CLK_TOP_SYSPLL_D3_D3 42
53#define CLK_TOP_SYSPLL2_D2 43
54#define CLK_TOP_SYSPLL2_D4 44
55#define CLK_TOP_SYSPLL2_D8 45
56#define CLK_TOP_SYSPLL_D5 46
57#define CLK_TOP_SYSPLL3_D2 47
58#define CLK_TOP_SYSPLL3_D4 48
59#define CLK_TOP_SYSPLL_D7 49
60#define CLK_TOP_SYSPLL4_D2 50
61#define CLK_TOP_SYSPLL4_D4 51
62#define CLK_TOP_UNIVPLL_CK 52
63#define CLK_TOP_UNIVPLL_D7 53
64#define CLK_TOP_UNIVPLL_D26 54
65#define CLK_TOP_SSUSB_PHY_48M_CK 55
66#define CLK_TOP_USB_PHY48M_CK 56
67#define CLK_TOP_UNIVPLL_D2 57
68#define CLK_TOP_UNIVPLL1_D2 58
69#define CLK_TOP_UNIVPLL1_D4 59
70#define CLK_TOP_UNIVPLL1_D8 60
71#define CLK_TOP_UNIVPLL_D3 61
72#define CLK_TOP_UNIVPLL2_D2 62
73#define CLK_TOP_UNIVPLL2_D4 63
74#define CLK_TOP_UNIVPLL2_D8 64
75#define CLK_TOP_UNIVPLL_D5 65
76#define CLK_TOP_UNIVPLL3_D2 66
77#define CLK_TOP_UNIVPLL3_D4 67
78#define CLK_TOP_UNIVPLL3_D8 68
79#define CLK_TOP_ULPOSC_CK_ORG 69
80#define CLK_TOP_ULPOSC_CK 70
81#define CLK_TOP_ULPOSC_D2 71
82#define CLK_TOP_ULPOSC_D3 72
83#define CLK_TOP_ULPOSC_D4 73
84#define CLK_TOP_ULPOSC_D8 74
85#define CLK_TOP_ULPOSC_D10 75
86#define CLK_TOP_APLL1_CK 76
87#define CLK_TOP_APLL2_CK 77
88#define CLK_TOP_MFGPLL_CK 78
89#define CLK_TOP_MFGPLL_D2 79
90#define CLK_TOP_IMGPLL_CK 80
91#define CLK_TOP_IMGPLL_D2 81
92#define CLK_TOP_IMGPLL_D4 82
93#define CLK_TOP_CODECPLL_CK 83
94#define CLK_TOP_CODECPLL_D2 84
95#define CLK_TOP_VDECPLL_CK 85
96#define CLK_TOP_TVDPLL_CK 86
97#define CLK_TOP_TVDPLL_D2 87
98#define CLK_TOP_TVDPLL_D4 88
99#define CLK_TOP_TVDPLL_D8 89
100#define CLK_TOP_TVDPLL_D16 90
101#define CLK_TOP_MSDCPLL_CK 91
102#define CLK_TOP_MSDCPLL_D2 92
103#define CLK_TOP_MSDCPLL_D4 93
104#define CLK_TOP_MSDCPLL_D8 94
105#define CLK_TOP_NR 95
106
107/* APMIXED_SYS */
108#define CLK_APMIXED_MAINPLL 1
109#define CLK_APMIXED_UNIVPLL 2
110#define CLK_APMIXED_MFGPLL 3
111#define CLK_APMIXED_MSDCPLL 4
112#define CLK_APMIXED_IMGPLL 5
113#define CLK_APMIXED_TVDPLL 6
114#define CLK_APMIXED_CODECPLL 7
115#define CLK_APMIXED_VDECPLL 8
116#define CLK_APMIXED_APLL1 9
117#define CLK_APMIXED_APLL2 10
118#define CLK_APMIXED_NR 11
119
120/* INFRA_SYS */
121#define CLK_INFRA_PMIC_TMR 1
122#define CLK_INFRA_PMIC_AP 2
123#define CLK_INFRA_PMIC_MD 3
124#define CLK_INFRA_PMIC_CONN 4
125#define CLK_INFRA_SCP 5
126#define CLK_INFRA_SEJ 6
127#define CLK_INFRA_APXGPT 7
128#define CLK_INFRA_SEJ_13M 8
129#define CLK_INFRA_ICUSB 9
130#define CLK_INFRA_GCE 10
131#define CLK_INFRA_THERM 11
132#define CLK_INFRA_I2C0 12
133#define CLK_INFRA_I2C1 13
134#define CLK_INFRA_I2C2 14
135#define CLK_INFRA_I2C3 15
136#define CLK_INFRA_PWM_HCLK 16
137#define CLK_INFRA_PWM1 17
138#define CLK_INFRA_PWM2 18
139#define CLK_INFRA_PWM3 19
140#define CLK_INFRA_PWM4 20
141#define CLK_INFRA_PWM 21
142#define CLK_INFRA_UART0 22
143#define CLK_INFRA_UART1 23
144#define CLK_INFRA_UART2 24
145#define CLK_INFRA_UART3 25
146#define CLK_INFRA_MD2MD_CCIF_0 26
147#define CLK_INFRA_MD2MD_CCIF_1 27
148#define CLK_INFRA_MD2MD_CCIF_2 28
149#define CLK_INFRA_FHCTL 29
150#define CLK_INFRA_BTIF 30
151#define CLK_INFRA_MD2MD_CCIF_3 31
152#define CLK_INFRA_SPI 32
153#define CLK_INFRA_MSDC0 33
154#define CLK_INFRA_MD2MD_CCIF_4 34
155#define CLK_INFRA_MSDC1 35
156#define CLK_INFRA_MSDC2 36
157#define CLK_INFRA_MD2MD_CCIF_5 37
158#define CLK_INFRA_GCPU 38
159#define CLK_INFRA_TRNG 39
160#define CLK_INFRA_AUXADC 40
161#define CLK_INFRA_CPUM 41
162#define CLK_INFRA_AP_C2K_CCIF_0 42
163#define CLK_INFRA_AP_C2K_CCIF_1 43
164#define CLK_INFRA_CLDMA 44
165#define CLK_INFRA_DISP_PWM 45
166#define CLK_INFRA_AP_DMA 46
167#define CLK_INFRA_DEVICE_APC 47
168#define CLK_INFRA_L2C_SRAM 48
169#define CLK_INFRA_CCIF_AP 49
170#define CLK_INFRA_AUDIO 50
171#define CLK_INFRA_CCIF_MD 51
172#define CLK_INFRA_DRAMC_F26M 52
173#define CLK_INFRA_I2C4 53
174#define CLK_INFRA_I2C_APPM 54
175#define CLK_INFRA_I2C_GPUPM 55
176#define CLK_INFRA_I2C2_IMM 56
177#define CLK_INFRA_I2C2_ARB 57
178#define CLK_INFRA_I2C3_IMM 58
179#define CLK_INFRA_I2C3_ARB 59
180#define CLK_INFRA_I2C5 60
181#define CLK_INFRA_SYS_CIRQ 61
182#define CLK_INFRA_SPI1 62
183#define CLK_INFRA_DRAMC_B_F26M 63
184#define CLK_INFRA_ANC_MD32 64
185#define CLK_INFRA_ANC_MD32_32K 65
186#define CLK_INFRA_DVFS_SPM1 66
187#define CLK_INFRA_AES_TOP0 67
188#define CLK_INFRA_AES_TOP1 68
189#define CLK_INFRA_SSUSB_BUS 69
190#define CLK_INFRA_SPI2 70
191#define CLK_INFRA_SPI3 71
192#define CLK_INFRA_SPI4 72
193#define CLK_INFRA_SPI5 73
194#define CLK_INFRA_IRTX 74
195#define CLK_INFRA_SSUSB_SYS 75
196#define CLK_INFRA_SSUSB_REF 76
197#define CLK_INFRA_AUDIO_26M 77
198#define CLK_INFRA_AUDIO_26M_PAD_TOP 78
199#define CLK_INFRA_MODEM_TEMP_SHARE 79
200#define CLK_INFRA_VAD_WRAP_SOC 80
201#define CLK_INFRA_DRAMC_CONF 81
202#define CLK_INFRA_DRAMC_B_CONF 82
203#define CLK_INFRA_MFG_VCG 83
204#define CLK_INFRA_13M 84
205#define CLK_INFRA_NR 85
206
207/* IMG_SYS */
208#define CLK_IMG_FDVT 1
209#define CLK_IMG_DPE 2
210#define CLK_IMG_DIP 3
211#define CLK_IMG_LARB6 4
212#define CLK_IMG_NR 5
213
214/* MM_SYS */
215#define CLK_MM_SMI_COMMON 1
216#define CLK_MM_SMI_LARB0 2
217#define CLK_MM_SMI_LARB5 3
218#define CLK_MM_CAM_MDP 4
219#define CLK_MM_MDP_RDMA0 5
220#define CLK_MM_MDP_RDMA1 6
221#define CLK_MM_MDP_RSZ0 7
222#define CLK_MM_MDP_RSZ1 8
223#define CLK_MM_MDP_RSZ2 9
224#define CLK_MM_MDP_TDSHP 10
225#define CLK_MM_MDP_COLOR 11
226#define CLK_MM_MDP_WDMA 12
227#define CLK_MM_MDP_WROT0 13
228#define CLK_MM_MDP_WROT1 14
229#define CLK_MM_FAKE_ENG 15
230#define CLK_MM_DISP_OVL0 16
231#define CLK_MM_DISP_OVL1 17
232#define CLK_MM_DISP_OVL0_2L 18
233#define CLK_MM_DISP_OVL1_2L 19
234#define CLK_MM_DISP_RDMA0 20
235#define CLK_MM_DISP_RDMA1 21
236#define CLK_MM_DISP_WDMA0 22
237#define CLK_MM_DISP_WDMA1 23
238#define CLK_MM_DISP_COLOR 24
239#define CLK_MM_DISP_CCORR 25
240#define CLK_MM_DISP_AAL 26
241#define CLK_MM_DISP_GAMMA 27
242#define CLK_MM_DISP_OD 28
243#define CLK_MM_DISP_DITHER 29
244#define CLK_MM_DISP_UFOE 30
245#define CLK_MM_DISP_DSC 31
246#define CLK_MM_DISP_SPLIT 32
247#define CLK_MM_DSI0_MM_CLOCK 33
248#define CLK_MM_DSI1_MM_CLOCK 34
249#define CLK_MM_DPI_MM_CLOCK 35
250#define CLK_MM_DPI_INTERFACE_CLOCK 36
251#define CLK_MM_LARB4_AXI_ASIF_MM_CLOCK 37
252#define CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK 38
253#define CLK_MM_DISP_OVL0_MOUT_CLOCK 39
254#define CLK_MM_FAKE_ENG2 40
255#define CLK_MM_DSI0_INTERFACE_CLOCK 41
256#define CLK_MM_DSI1_INTERFACE_CLOCK 42
257#define CLK_MM_NR 43
258
259/* VDEC_SYS */
260#define CLK_VDEC_CKEN_ENG 1
261#define CLK_VDEC_ACTIVE 2
262#define CLK_VDEC_CKEN 3
263#define CLK_VDEC_LARB1_CKEN 4
264#define CLK_VDEC_NR 5
265
266/* VENC_SYS */
267#define CLK_VENC_0 1
268#define CLK_VENC_1 2
269#define CLK_VENC_2 3
270#define CLK_VENC_3 4
271#define CLK_VENC_NR 5
272
273#endif /* _DT_BINDINGS_CLK_MT6797_H */