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1/*
2 * R8A66597 UDC
3 *
4 * Copyright (C) 2007-2009 Renesas Solutions Corp.
5 *
6 * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 *
21 */
22
23#ifndef __R8A66597_H__
24#define __R8A66597_H__
25
26#ifdef CONFIG_HAVE_CLK
27#include <linux/clk.h>
28#endif
29
30#include <linux/usb/r8a66597.h>
31
32#define R8A66597_MAX_SAMPLING 10
33
34#define R8A66597_MAX_NUM_PIPE 8
35#define R8A66597_MAX_NUM_BULK 3
36#define R8A66597_MAX_NUM_ISOC 2
37#define R8A66597_MAX_NUM_INT 2
38
39#define R8A66597_BASE_PIPENUM_BULK 3
40#define R8A66597_BASE_PIPENUM_ISOC 1
41#define R8A66597_BASE_PIPENUM_INT 6
42
43#define R8A66597_BASE_BUFNUM 6
44#define R8A66597_MAX_BUFNUM 0x4F
45
46#define is_bulk_pipe(pipenum) \
47 ((pipenum >= R8A66597_BASE_PIPENUM_BULK) && \
48 (pipenum < (R8A66597_BASE_PIPENUM_BULK + R8A66597_MAX_NUM_BULK)))
49#define is_interrupt_pipe(pipenum) \
50 ((pipenum >= R8A66597_BASE_PIPENUM_INT) && \
51 (pipenum < (R8A66597_BASE_PIPENUM_INT + R8A66597_MAX_NUM_INT)))
52#define is_isoc_pipe(pipenum) \
53 ((pipenum >= R8A66597_BASE_PIPENUM_ISOC) && \
54 (pipenum < (R8A66597_BASE_PIPENUM_ISOC + R8A66597_MAX_NUM_ISOC)))
55
56struct r8a66597_pipe_info {
57 u16 pipe;
58 u16 epnum;
59 u16 maxpacket;
60 u16 type;
61 u16 interval;
62 u16 dir_in;
63};
64
65struct r8a66597_request {
66 struct usb_request req;
67 struct list_head queue;
68};
69
70struct r8a66597_ep {
71 struct usb_ep ep;
72 struct r8a66597 *r8a66597;
73
74 struct list_head queue;
75 unsigned busy:1;
76 unsigned wedge:1;
77 unsigned internal_ccpl:1; /* use only control */
78
79 /* this member can able to after r8a66597_enable */
80 unsigned use_dma:1;
81 u16 pipenum;
82 u16 type;
83 const struct usb_endpoint_descriptor *desc;
84 /* register address */
85 unsigned char fifoaddr;
86 unsigned char fifosel;
87 unsigned char fifoctr;
88 unsigned char fifotrn;
89 unsigned char pipectr;
90};
91
92struct r8a66597 {
93 spinlock_t lock;
94 void __iomem *reg;
95
96#ifdef CONFIG_HAVE_CLK
97 struct clk *clk;
98#endif
99 struct r8a66597_platdata *pdata;
100
101 struct usb_gadget gadget;
102 struct usb_gadget_driver *driver;
103
104 struct r8a66597_ep ep[R8A66597_MAX_NUM_PIPE];
105 struct r8a66597_ep *pipenum2ep[R8A66597_MAX_NUM_PIPE];
106 struct r8a66597_ep *epaddr2ep[16];
107
108 struct timer_list timer;
109 struct usb_request *ep0_req; /* for internal request */
110 u16 ep0_data; /* for internal request */
111 u16 old_vbus;
112 u16 scount;
113 u16 old_dvsq;
114
115 /* pipe config */
116 unsigned char bulk;
117 unsigned char interrupt;
118 unsigned char isochronous;
119 unsigned char num_dma;
120
121 unsigned irq_sense_low:1;
122};
123
124#define gadget_to_r8a66597(_gadget) \
125 container_of(_gadget, struct r8a66597, gadget)
126#define r8a66597_to_gadget(r8a66597) (&r8a66597->gadget)
127
128static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
129{
130 return ioread16(r8a66597->reg + offset);
131}
132
133static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
134 unsigned long offset,
135 unsigned char *buf,
136 int len)
137{
138 void __iomem *fifoaddr = r8a66597->reg + offset;
139 unsigned int data = 0;
140 int i;
141
142 if (r8a66597->pdata->on_chip) {
143 /* 32-bit accesses for on_chip controllers */
144
145 /* aligned buf case */
146 if (len >= 4 && !((unsigned long)buf & 0x03)) {
147 ioread32_rep(fifoaddr, buf, len / 4);
148 buf += len & ~0x03;
149 len &= 0x03;
150 }
151
152 /* unaligned buf case */
153 for (i = 0; i < len; i++) {
154 if (!(i & 0x03))
155 data = ioread32(fifoaddr);
156
157 buf[i] = (data >> ((i & 0x03) * 8)) & 0xff;
158 }
159 } else {
160 /* 16-bit accesses for external controllers */
161
162 /* aligned buf case */
163 if (len >= 2 && !((unsigned long)buf & 0x01)) {
164 ioread16_rep(fifoaddr, buf, len / 2);
165 buf += len & ~0x01;
166 len &= 0x01;
167 }
168
169 /* unaligned buf case */
170 for (i = 0; i < len; i++) {
171 if (!(i & 0x01))
172 data = ioread16(fifoaddr);
173
174 buf[i] = (data >> ((i & 0x01) * 8)) & 0xff;
175 }
176 }
177}
178
179static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
180 unsigned long offset)
181{
182 iowrite16(val, r8a66597->reg + offset);
183}
184
185static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
186 unsigned long offset,
187 unsigned char *buf,
188 int len)
189{
190 void __iomem *fifoaddr = r8a66597->reg + offset;
191 int adj = 0;
192 int i;
193
194 if (r8a66597->pdata->on_chip) {
195 /* 32-bit access only if buf is 32-bit aligned */
196 if (len >= 4 && !((unsigned long)buf & 0x03)) {
197 iowrite32_rep(fifoaddr, buf, len / 4);
198 buf += len & ~0x03;
199 len &= 0x03;
200 }
201 } else {
202 /* 16-bit access only if buf is 16-bit aligned */
203 if (len >= 2 && !((unsigned long)buf & 0x01)) {
204 iowrite16_rep(fifoaddr, buf, len / 2);
205 buf += len & ~0x01;
206 len &= 0x01;
207 }
208 }
209
210 /* adjust fifo address in the little endian case */
211 if (!(r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)) {
212 if (r8a66597->pdata->on_chip)
213 adj = 0x03; /* 32-bit wide */
214 else
215 adj = 0x01; /* 16-bit wide */
216 }
217
218 for (i = 0; i < len; i++)
219 iowrite8(buf[i], fifoaddr + adj - (i & adj));
220}
221
222static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
223 u16 val, u16 pat, unsigned long offset)
224{
225 u16 tmp;
226 tmp = r8a66597_read(r8a66597, offset);
227 tmp = tmp & (~pat);
228 tmp = tmp | val;
229 r8a66597_write(r8a66597, tmp, offset);
230}
231
232static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
233{
234 u16 clock = 0;
235
236 switch (pdata->xtal) {
237 case R8A66597_PLATDATA_XTAL_12MHZ:
238 clock = XTAL12;
239 break;
240 case R8A66597_PLATDATA_XTAL_24MHZ:
241 clock = XTAL24;
242 break;
243 case R8A66597_PLATDATA_XTAL_48MHZ:
244 clock = XTAL48;
245 break;
246 default:
247 printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
248 break;
249 }
250
251 return clock;
252}
253
254#define r8a66597_bclr(r8a66597, val, offset) \
255 r8a66597_mdfy(r8a66597, 0, val, offset)
256#define r8a66597_bset(r8a66597, val, offset) \
257 r8a66597_mdfy(r8a66597, val, 0, offset)
258
259#define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
260
261#define enable_irq_ready(r8a66597, pipenum) \
262 enable_pipe_irq(r8a66597, pipenum, BRDYENB)
263#define disable_irq_ready(r8a66597, pipenum) \
264 disable_pipe_irq(r8a66597, pipenum, BRDYENB)
265#define enable_irq_empty(r8a66597, pipenum) \
266 enable_pipe_irq(r8a66597, pipenum, BEMPENB)
267#define disable_irq_empty(r8a66597, pipenum) \
268 disable_pipe_irq(r8a66597, pipenum, BEMPENB)
269#define enable_irq_nrdy(r8a66597, pipenum) \
270 enable_pipe_irq(r8a66597, pipenum, NRDYENB)
271#define disable_irq_nrdy(r8a66597, pipenum) \
272 disable_pipe_irq(r8a66597, pipenum, NRDYENB)
273
274#endif /* __R8A66597_H__ */
275