1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
  4 */
  5
  6#ifndef QCOM_PHY_QMP_H_
  7#define QCOM_PHY_QMP_H_
  8
  9#include "phy-qcom-qmp-qserdes-com.h"
 10#include "phy-qcom-qmp-qserdes-txrx.h"
 11
 12#include "phy-qcom-qmp-qserdes-com-v3.h"
 13#include "phy-qcom-qmp-qserdes-txrx-v3.h"
 14
 15#include "phy-qcom-qmp-qserdes-com-v4.h"
 16#include "phy-qcom-qmp-qserdes-txrx-v4.h"
 17#include "phy-qcom-qmp-qserdes-txrx-v4_20.h"
 18
 19#include "phy-qcom-qmp-qserdes-com-v5.h"
 20#include "phy-qcom-qmp-qserdes-txrx-v5.h"
 21#include "phy-qcom-qmp-qserdes-txrx-v5_20.h"
 22#include "phy-qcom-qmp-qserdes-txrx-v5_5nm.h"
 23
 24#include "phy-qcom-qmp-qserdes-pll.h"
 25
 26#include "phy-qcom-qmp-pcs-v2.h"
 27
 28#include "phy-qcom-qmp-pcs-v3.h"
 29#include "phy-qcom-qmp-pcs-misc-v3.h"
 30#include "phy-qcom-qmp-pcs-ufs-v3.h"
 31
 32#include "phy-qcom-qmp-pcs-v4.h"
 33#include "phy-qcom-qmp-pcs-pcie-v4.h"
 34#include "phy-qcom-qmp-pcs-usb-v4.h"
 35#include "phy-qcom-qmp-pcs-ufs-v4.h"
 36
 37#include "phy-qcom-qmp-pcs-v4_20.h"
 38#include "phy-qcom-qmp-pcs-pcie-v4_20.h"
 39
 40#include "phy-qcom-qmp-pcs-v5.h"
 41#include "phy-qcom-qmp-pcs-v5_20.h"
 42#include "phy-qcom-qmp-pcs-pcie-v5.h"
 43#include "phy-qcom-qmp-pcs-usb-v5.h"
 44#include "phy-qcom-qmp-pcs-ufs-v5.h"
 45
 46#include "phy-qcom-qmp-pcs-pcie-v5_20.h"
 47
 48#include "phy-qcom-qmp-pcie-qhp.h"
 49
 50/* Only for QMP V3 & V4 PHY - DP COM registers */
 51#define QPHY_V3_DP_COM_PHY_MODE_CTRL			0x00
 52#define QPHY_V3_DP_COM_SW_RESET				0x04
 53#define QPHY_V3_DP_COM_POWER_DOWN_CTRL			0x08
 54#define QPHY_V3_DP_COM_SWI_CTRL				0x0c
 55#define QPHY_V3_DP_COM_TYPEC_CTRL			0x10
 56#define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL			0x14
 57#define QPHY_V3_DP_COM_RESET_OVRD_CTRL			0x1c
 58
 59/* QSERDES V3 COM bits */
 60# define QSERDES_V3_COM_BIAS_EN				0x0001
 61# define QSERDES_V3_COM_BIAS_EN_MUX			0x0002
 62# define QSERDES_V3_COM_CLKBUF_R_EN			0x0004
 63# define QSERDES_V3_COM_CLKBUF_L_EN			0x0008
 64# define QSERDES_V3_COM_EN_SYSCLK_TX_SEL		0x0010
 65# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L		0x0020
 66# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R		0x0040
 67
 68/* QSERDES V3 TX bits */
 69# define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK		0x001f
 70# define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN		0x0020
 71# define DP_PHY_TXn_TX_DRV_LVL_MASK			0x001f
 72# define DP_PHY_TXn_TX_DRV_LVL_MUX_EN			0x0020
 73
 74/* QMP PHY - DP PHY registers */
 75#define QSERDES_DP_PHY_REVISION_ID0			0x000
 76#define QSERDES_DP_PHY_REVISION_ID1			0x004
 77#define QSERDES_DP_PHY_REVISION_ID2			0x008
 78#define QSERDES_DP_PHY_REVISION_ID3			0x00c
 79#define QSERDES_DP_PHY_CFG				0x010
 80#define QSERDES_DP_PHY_PD_CTL				0x018
 81# define DP_PHY_PD_CTL_PWRDN				0x001
 82# define DP_PHY_PD_CTL_PSR_PWRDN			0x002
 83# define DP_PHY_PD_CTL_AUX_PWRDN			0x004
 84# define DP_PHY_PD_CTL_LANE_0_1_PWRDN			0x008
 85# define DP_PHY_PD_CTL_LANE_2_3_PWRDN			0x010
 86# define DP_PHY_PD_CTL_PLL_PWRDN			0x020
 87# define DP_PHY_PD_CTL_DP_CLAMP_EN			0x040
 88#define QSERDES_DP_PHY_MODE				0x01c
 89#define QSERDES_DP_PHY_AUX_CFG0				0x020
 90#define QSERDES_DP_PHY_AUX_CFG1				0x024
 91#define QSERDES_DP_PHY_AUX_CFG2				0x028
 92#define QSERDES_DP_PHY_AUX_CFG3				0x02c
 93#define QSERDES_DP_PHY_AUX_CFG4				0x030
 94#define QSERDES_DP_PHY_AUX_CFG5				0x034
 95#define QSERDES_DP_PHY_AUX_CFG6				0x038
 96#define QSERDES_DP_PHY_AUX_CFG7				0x03c
 97#define QSERDES_DP_PHY_AUX_CFG8				0x040
 98#define QSERDES_DP_PHY_AUX_CFG9				0x044
 99
100/* Only for QMP V3 PHY - DP PHY registers */
101#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK		0x048
102# define PHY_AUX_STOP_ERR_MASK				0x01
103# define PHY_AUX_DEC_ERR_MASK				0x02
104# define PHY_AUX_SYNC_ERR_MASK				0x04
105# define PHY_AUX_ALIGN_ERR_MASK				0x08
106# define PHY_AUX_REQ_ERR_MASK				0x10
107
108#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR		0x04c
109#define QSERDES_V3_DP_PHY_AUX_BIST_CFG			0x050
110
111#define QSERDES_V3_DP_PHY_VCO_DIV			0x064
112#define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL		0x06c
113#define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL		0x088
114
115#define QSERDES_V3_DP_PHY_SPARE0			0x0ac
116#define DP_PHY_SPARE0_MASK				0x0f
117#define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT		0x04(0x0004)
118
119#define QSERDES_V3_DP_PHY_STATUS			0x0c0
120
121/* Only for QMP V4 PHY - DP PHY registers */
122#define QSERDES_V4_DP_PHY_CFG_1				0x014
123#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK		0x054
124#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR		0x058
125#define QSERDES_V4_DP_PHY_VCO_DIV			0x070
126#define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL		0x078
127#define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL		0x09c
128#define QSERDES_V4_DP_PHY_SPARE0			0x0c8
129#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS		0x0d8
130#define QSERDES_V4_DP_PHY_STATUS			0x0dc
131
132/* Only for QMP V4 PHY - PCS_MISC registers */
133#define QPHY_V4_PCS_MISC_TYPEC_CTRL			0x00
134#define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL		0x04
135#define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1		0x08
136#define QPHY_V4_PCS_MISC_CLAMP_ENABLE			0x0c
137#define QPHY_V4_PCS_MISC_TYPEC_STATUS			0x10
138#define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS		0x14
139
140#endif