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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/delay.h>
9#include <linux/err.h>
10#include <linux/io.h>
11#include <linux/iopoll.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/of_device.h>
16#include <linux/of_address.h>
17#include <linux/phy/phy.h>
18#include <linux/platform_device.h>
19#include <linux/regulator/consumer.h>
20#include <linux/reset.h>
21#include <linux/slab.h>
22
23#include "phy-qcom-qmp.h"
24
25/* QPHY_SW_RESET bit */
26#define SW_RESET BIT(0)
27/* QPHY_POWER_DOWN_CONTROL */
28#define SW_PWRDN BIT(0)
29/* QPHY_START_CONTROL bits */
30#define SERDES_START BIT(0)
31#define PCS_START BIT(1)
32/* QPHY_PCS_STATUS bit */
33#define PHYSTATUS BIT(6)
34
35/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
36/* DP PHY soft reset */
37#define SW_DPPHY_RESET BIT(0)
38/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
39#define SW_DPPHY_RESET_MUX BIT(1)
40/* USB3 PHY soft reset */
41#define SW_USB3PHY_RESET BIT(2)
42/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
43#define SW_USB3PHY_RESET_MUX BIT(3)
44
45/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
46#define USB3_MODE BIT(0) /* enables USB3 mode */
47#define DP_MODE BIT(1) /* enables DP mode */
48
49/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
50#define ARCVR_DTCT_EN BIT(0)
51#define ALFPS_DTCT_EN BIT(1)
52#define ARCVR_DTCT_EVENT_SEL BIT(4)
53
54/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
55#define IRQ_CLEAR BIT(0)
56
57/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
58#define RCVR_DETECT BIT(0)
59
60/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
61#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
62
63#define PHY_INIT_COMPLETE_TIMEOUT 10000
64
65struct qmp_phy_init_tbl {
66 unsigned int offset;
67 unsigned int val;
68 /*
69 * mask of lanes for which this register is written
70 * for cases when second lane needs different values
71 */
72 u8 lane_mask;
73};
74
75#define QMP_PHY_INIT_CFG(o, v) \
76 { \
77 .offset = o, \
78 .val = v, \
79 .lane_mask = 0xff, \
80 }
81
82#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
83 { \
84 .offset = o, \
85 .val = v, \
86 .lane_mask = l, \
87 }
88
89/* set of registers with offsets different per-PHY */
90enum qphy_reg_layout {
91 /* PCS registers */
92 QPHY_SW_RESET,
93 QPHY_START_CTRL,
94 QPHY_PCS_STATUS,
95 QPHY_PCS_AUTONOMOUS_MODE_CTRL,
96 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
97 QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
98 QPHY_PCS_POWER_DOWN_CONTROL,
99 /* PCS_MISC registers */
100 QPHY_PCS_MISC_TYPEC_CTRL,
101 /* Keep last to ensure regs_layout arrays are properly initialized */
102 QPHY_LAYOUT_SIZE
103};
104
105static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
106 [QPHY_SW_RESET] = 0x00,
107 [QPHY_START_CTRL] = 0x08,
108 [QPHY_PCS_STATUS] = 0x17c,
109 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
110 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
111 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
112 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
113};
114
115static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
116 [QPHY_SW_RESET] = 0x00,
117 [QPHY_START_CTRL] = 0x08,
118 [QPHY_PCS_STATUS] = 0x174,
119 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
120 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
121 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
122 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
123};
124
125static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
126 [QPHY_SW_RESET] = 0x00,
127 [QPHY_START_CTRL] = 0x44,
128 [QPHY_PCS_STATUS] = 0x14,
129 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
130
131 /* In PCS_USB */
132 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x008,
133 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x014,
134};
135
136static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
137 [QPHY_SW_RESET] = 0x00,
138 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
139 [QPHY_START_CTRL] = 0x08,
140 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
141 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
142 [QPHY_PCS_STATUS] = 0x174,
143 [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
144};
145
146static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
147 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
148 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
149 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
150 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
151 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
152 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
153 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
154 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
155 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
156 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
157 /* PLL and Loop filter settings */
158 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
159 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
160 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
161 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
162 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
163 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
164 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
165 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
166 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
167 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
168 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
169 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
170 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
171 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
172 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
173 /* SSC settings */
174 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
175 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
176 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
177 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
178 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
179 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
180 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
181};
182
183static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
184 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
185 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
186 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
187 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
188 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
189 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
190 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
191 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
192 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
193};
194
195static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
196 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
197 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
198 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
199 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
200 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
201 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
202 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
203 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
204 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
205 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
206 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
207 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
208 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
209 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
210 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
211 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
212 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
213 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
214 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
215 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
216 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
217 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
218 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
219};
220
221static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
222 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
223 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
224 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
225 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
226 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
227 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
228 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
229 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
230 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
231 /* PLL and Loop filter settings */
232 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
233 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
234 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
235 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
236 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
237 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
238 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
239 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
240 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
241 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
242 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
243 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
244 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
245 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
246 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
247 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
248 /* SSC settings */
249 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
250 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
251 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
252 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
253 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
254 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
255 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
256};
257
258static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
259 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
260 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
261 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
262};
263
264static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
265 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
266 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
267 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
268 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
269 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
270 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
271 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
272 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
273 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
274 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
275};
276
277static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
278 /* FLL settings */
279 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL2, 0x03),
280 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL1, 0x02),
281 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_L, 0x09),
282 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_H_TOL, 0x42),
283 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_MAN_CODE, 0x85),
284
285 /* Lock Det settings */
286 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1),
287 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG2, 0x1f),
288 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG3, 0x47),
289 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG2, 0x08),
290};
291
292static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
293 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
294 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
295 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
296 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
297 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
298 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
299 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
300 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
301 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
302 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
303 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
304 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
305 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
306 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
307 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
308 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
309 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
310 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
311 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
312 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
313 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
314 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
315 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
316 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
317 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
318 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
319 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
320 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
321 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
322 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
323 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
324 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
325 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
326 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
327 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
328 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
329};
330
331static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
332 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
333 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
334 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
335 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
336 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
337};
338
339static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
340 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
341 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
342 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
343 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
344 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
345 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
346 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
347 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
348 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
349};
350
351static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
352 /* FLL settings */
353 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
354 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
355 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
356 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
357 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
358
359 /* Lock Det settings */
360 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
361 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
362 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
363 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
364
365 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
366 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
367 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
368 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
369 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
370 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
371 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
372 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
373 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
374 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
375 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
376 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
377 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
378 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
379 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
380 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
381 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
382 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
383 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
384
385 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
386 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
387 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
388 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
389 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
390 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
391 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
392 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
393 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
394 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
395 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
396};
397
398static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
399 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
400 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
401 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
402 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
403 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
404 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
405 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
406 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
407 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
408 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
409 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
410 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
411 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
412 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
413 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
414 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
415 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
416 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
417 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
418 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
419 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
420 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
421 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
422 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
423 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
424 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
425 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
426 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
427 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
428 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
429 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
430 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
431 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
432 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
433 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
434 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
435};
436
437static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
438 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
439 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
440 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
441 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
442 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
443};
444
445static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
446 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
447 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
448 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
449 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
450 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
451 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
452 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
453 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
454 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
455 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
456 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
457};
458
459static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
460 /* FLL settings */
461 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
462 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
463 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
464 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
465 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
466
467 /* Lock Det settings */
468 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
469 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
470 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
471 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
472
473 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
474 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
475 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
476 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
477 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
478 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
479 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
480 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
481 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
482 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
483 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
484 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
485 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
486 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
487 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
488 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
489 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
490 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
491 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
492
493 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
494 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
495 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
496 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
497 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
498 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
499 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
500 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
501 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
502 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
503 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
504
505 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
506 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
507};
508
509static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
510 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
511 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
512 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
513 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
514 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
515 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
516 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
517 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
518 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
519 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
520 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
521 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
522 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
523 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
524 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
534 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
535 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
536 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
537 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
538 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
539 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
540 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
541 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
542 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
543 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
544 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
545 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
546 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
547 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
548};
549
550static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
551 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
552 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
553 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
554 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
555};
556
557static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
558 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
559 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
560 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
561 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
562 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
563 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
564 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
565 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
566 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
567 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
568 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
569 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
570 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
571 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
572 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
573 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
574 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
575};
576
577static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
578 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
579 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
580 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
581 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
582 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
583 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
584 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
585 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
586 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
587 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
588 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
589 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
590 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
591 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
592 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
593 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
594 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
595 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
596 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
597 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
598 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
599 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
600 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
601 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
602 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
603 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
604 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
605 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
606 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
607 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
608 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
609 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
610 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
611 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
612 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
613 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
614 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
615 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
616};
617
618static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
619 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
620 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
621 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
622 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
623 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
624 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
625 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
626 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
627 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
628 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
629 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
630 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
631 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
632 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
633 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
634 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
635 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
636 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
637 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
638 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
639 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
640 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
641 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
642 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
643 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
644 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
645 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
646 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
647 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
648 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
649 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
650 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
651 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
652 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
653 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
654 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
655 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
656 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
657 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
658 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
659};
660
661static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
662 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
663 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
664 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
665 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
666 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
667};
668
669static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
670 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
671 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
672 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
673 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
674 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
675 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
676 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
677 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
678 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
679 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
680 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
681 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
682 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
683 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
684 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
685 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
686 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
687 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
688 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
689 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
690 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
691 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
692 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
693 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
694 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
695 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
696 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
697 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
698 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
699 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
700 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
701 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
702 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
703 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
704 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
705 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
706};
707
708static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
709 /* Lock Det settings */
710 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
711 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
712 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
713
714 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
715 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
716 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
717 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
718 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
719 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
720 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
721 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
722};
723
724static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = {
725 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
726 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
727};
728
729static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
730 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
731 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
732 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
733 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
734 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
735 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
736 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
737 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
738 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
739 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
740 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
741 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
742 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
743 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
744 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
745 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
746 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
747 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
748 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
749 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
750 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
751 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
752 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
753 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
754 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
755 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
756 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
757 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
758 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
759 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
760 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
761 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
762 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
763 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
764 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
765 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
766 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
767 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
768 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
769 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
770};
771
772static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
773 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
774 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
775 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
776 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
777};
778
779static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
780 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
781 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
782 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
783 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
784 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
785 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
786 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
787 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
788 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
789 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
790 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
791 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
792 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
793 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
794 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
795 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
796 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
797 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
798 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
799 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
800 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
801 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
802 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
803 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
804 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
805 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
806 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
807 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
808 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
809 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
810 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
811 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
812 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
813 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
814 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
815 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
816};
817
818static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
819 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
820 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
821 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
822 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
823 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
824 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
825 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
826 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
827 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
828 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
829 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
830 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
831 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
832 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
833};
834
835static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_usb_tbl[] = {
836 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
837 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
838};
839
840static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
841 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
842 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
843 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
844 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
845 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
846 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
847 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
848 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
849};
850
851static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
852 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
853 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
854 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
855 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
856 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
857 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
858 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
859 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
860 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
861 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
862 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
863 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
864 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
865 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
866 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
867 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
868 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
869 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
870 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
871 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
872 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
873 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
874 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
875 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
876 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
877 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
878 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
879 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
880 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
881 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
882 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
883 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
884 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
885 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
886 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
887 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
888 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
889 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
890};
891
892static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
893 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
894 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
895 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
896 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
897 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
898 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
899 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
900 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
901 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
902 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
903 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
904 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
905};
906
907static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = {
908 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
909 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
910};
911
912static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
913 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
914 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
915 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
916 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
917 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
918 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
919};
920
921static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
922 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
923 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
924 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
925 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
926 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
927 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
928 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
929 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
930 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
931 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
932 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
933 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
934 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
935 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
936 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
937 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
938 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
939 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
940 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
941 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
942 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
943 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
944 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
945 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
946 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
947 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
948 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
949 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
950 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
951 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
952 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
953 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
954 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
955 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
956 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
957 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
958};
959
960static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
961 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
962 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
963 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
964 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
965 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
966 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
967 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
968 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
969 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
970 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
971 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
972 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
973 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
974 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
975};
976
977static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_usb_tbl[] = {
978 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
979 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
980};
981
982static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
983 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
984 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
985 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
986 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
987 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
988};
989
990static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
991 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
992 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
993 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
994 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
995 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
996 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
997 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
998 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
999 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1000 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1001 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1002 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
1003 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1004 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
1005 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
1006 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1007 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1008 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1009 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1010 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
1011 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1012 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1013 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1014 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1015 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1016 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1017 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1018 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1019 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1020 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1021 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1022 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1023 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1024 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
1025 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1026 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1027};
1028
1029static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
1030 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
1031 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
1032 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
1033 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1034 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
1035 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
1036 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
1037};
1038
1039static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
1040 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
1041 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
1042 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
1043 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
1044 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
1045 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
1046 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
1047 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
1048 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
1049 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
1050 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
1051 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1052 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1053 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
1054 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
1055 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1056 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1057 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1058 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
1059 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
1060 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1061 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1062 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1063 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1064 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1065 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
1066 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1067 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1068 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1069 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1070 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
1071};
1072
1073static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
1074 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
1075 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
1076 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
1077 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
1078 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
1079 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
1080 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
1081 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
1082 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
1083 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
1084};
1085
1086static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
1087 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
1088 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1089 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1090 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1091 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1092 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1093 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
1094 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1095 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1096 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
1097 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
1098 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
1099 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1100 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1101 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1102 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1103 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1104 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1105 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1106 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
1107 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1108 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
1109 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
1110 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
1111 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
1112 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
1113 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
1114 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
1115 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
1116 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
1117 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
1118 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
1119 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
1120 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1121 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1122 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
1123 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1124 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
1125};
1126
1127static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
1128 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1129 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1130 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1131 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1132 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1133 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1134 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1135 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1136 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1137 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1138 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1139 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1140 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1141 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1142};
1143
1144static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = {
1145 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
1146 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
1147 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1148 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1149};
1150
1151static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
1152 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
1153 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
1154 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
1155 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1156 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
1157 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
1158 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
1159};
1160
1161static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
1162 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
1163 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
1164 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
1165 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
1166 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
1167 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
1168 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
1169 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
1170 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
1171 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
1172 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
1173 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1174 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1175 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
1176 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
1177 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1178 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1179 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1180 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
1181 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
1182 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1183 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1184 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1185 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1186 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1187 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
1188 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1189 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1190 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1191 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1192 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
1193};
1194
1195static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
1196 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1197 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1198 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1199 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1200 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1201 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1202 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1203 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1204 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1205 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1206 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1207 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1208 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1209 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1210};
1211
1212static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_usb_tbl[] = {
1213 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1214 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1215};
1216
1217static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
1218 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
1219 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
1220 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
1221 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
1222 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
1223 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
1224 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
1225 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
1226 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
1227 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
1228 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
1229 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
1230 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
1231 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
1232 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
1233 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
1234 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
1235 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1236 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
1237 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
1238 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
1239 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
1240 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
1241 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
1242 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
1243 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
1244 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
1245 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
1246 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
1247 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
1248 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
1249 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
1250 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
1251 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
1252 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
1253 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
1254 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
1255 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
1256};
1257
1258static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
1259 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1260 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1261 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
1262 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
1263 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
1264};
1265
1266static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
1267 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1268 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
1269 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
1270 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
1271 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
1272 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
1273 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1274 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
1275 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1276 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1277 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1278 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1279 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
1280 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
1281 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
1282 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
1283 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
1284};
1285
1286static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
1287 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1288 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
1289 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
1290 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1291 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1292 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1293 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1294 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
1295 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1296 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1297 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1298 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1299 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1300 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1301 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1302 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1303 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1304 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1305 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1306 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1307 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
1308};
1309
1310static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_serdes_tbl[] = {
1311 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a),
1312 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1313 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
1314 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
1315 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0xab),
1316 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xea),
1317 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x02),
1318 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1319 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1320 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
1321 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1322 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1323 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
1324 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34),
1325 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14),
1326 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04),
1327 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a),
1328 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x02),
1329 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0x24),
1330 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
1331 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x82),
1332 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
1333 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xea),
1334 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
1335 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82),
1336 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34),
1337 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
1338 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1339 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1340 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1341 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1342 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
1343 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1344 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1345 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1346 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1347 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1348 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1349 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1350};
1351
1352static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_tx_tbl[] = {
1353 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
1354 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
1355 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
1356 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1357 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
1358 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
1359 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
1360};
1361
1362static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_rx_tbl[] = {
1363 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
1364 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
1365 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
1366 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
1367 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
1368 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
1369 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
1370 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
1371 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
1372 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
1373 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
1374 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1375 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1376 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
1377 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
1378 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1379 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1380 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1381 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x0a),
1382 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
1383 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1384 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1385 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1386 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1387 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1388 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
1389 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1390 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1391 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1392 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1393 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
1394};
1395
1396static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_tbl[] = {
1397 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1398 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07),
1399 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1400 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1401 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1402 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1403 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1404 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1405 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1406 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1407 QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a),
1408 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1409 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1410 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1411 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1412 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1413};
1414
1415struct qmp_usb_offsets {
1416 u16 serdes;
1417 u16 pcs;
1418 u16 pcs_usb;
1419 u16 tx;
1420 u16 rx;
1421};
1422
1423/* struct qmp_phy_cfg - per-PHY initialization config */
1424struct qmp_phy_cfg {
1425 int lanes;
1426
1427 const struct qmp_usb_offsets *offsets;
1428
1429 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1430 const struct qmp_phy_init_tbl *serdes_tbl;
1431 int serdes_tbl_num;
1432 const struct qmp_phy_init_tbl *tx_tbl;
1433 int tx_tbl_num;
1434 const struct qmp_phy_init_tbl *rx_tbl;
1435 int rx_tbl_num;
1436 const struct qmp_phy_init_tbl *pcs_tbl;
1437 int pcs_tbl_num;
1438 const struct qmp_phy_init_tbl *pcs_usb_tbl;
1439 int pcs_usb_tbl_num;
1440
1441 /* clock ids to be requested */
1442 const char * const *clk_list;
1443 int num_clks;
1444 /* resets to be requested */
1445 const char * const *reset_list;
1446 int num_resets;
1447 /* regulators to be requested */
1448 const char * const *vreg_list;
1449 int num_vregs;
1450
1451 /* array of registers with different offsets */
1452 const unsigned int *regs;
1453
1454 /* true, if PHY needs delay after POWER_DOWN */
1455 bool has_pwrdn_delay;
1456
1457 /* true, if PHY has a separate DP_COM control block */
1458 bool has_phy_dp_com_ctrl;
1459
1460 /* Offset from PCS to PCS_USB region */
1461 unsigned int pcs_usb_offset;
1462};
1463
1464struct qmp_usb {
1465 struct device *dev;
1466
1467 const struct qmp_phy_cfg *cfg;
1468
1469 void __iomem *serdes;
1470 void __iomem *pcs;
1471 void __iomem *pcs_misc;
1472 void __iomem *pcs_usb;
1473 void __iomem *tx;
1474 void __iomem *rx;
1475 void __iomem *tx2;
1476 void __iomem *rx2;
1477
1478 void __iomem *dp_com;
1479
1480 struct clk *pipe_clk;
1481 struct clk_bulk_data *clks;
1482 struct reset_control_bulk_data *resets;
1483 struct regulator_bulk_data *vregs;
1484
1485 enum phy_mode mode;
1486
1487 struct phy *phy;
1488
1489 struct clk_fixed_rate pipe_clk_fixed;
1490};
1491
1492static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1493{
1494 u32 reg;
1495
1496 reg = readl(base + offset);
1497 reg |= val;
1498 writel(reg, base + offset);
1499
1500 /* ensure that above write is through */
1501 readl(base + offset);
1502}
1503
1504static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1505{
1506 u32 reg;
1507
1508 reg = readl(base + offset);
1509 reg &= ~val;
1510 writel(reg, base + offset);
1511
1512 /* ensure that above write is through */
1513 readl(base + offset);
1514}
1515
1516/* list of clocks required by phy */
1517static const char * const msm8996_phy_clk_l[] = {
1518 "aux", "cfg_ahb", "ref",
1519};
1520
1521static const char * const qmp_v3_phy_clk_l[] = {
1522 "aux", "cfg_ahb", "ref", "com_aux",
1523};
1524
1525static const char * const qmp_v4_phy_clk_l[] = {
1526 "aux", "ref", "com_aux",
1527};
1528
1529static const char * const qmp_v4_ref_phy_clk_l[] = {
1530 "aux", "ref_clk_src", "ref", "com_aux",
1531};
1532
1533/* the primary usb3 phy on sm8250 doesn't have a ref clock */
1534static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
1535 "aux", "ref_clk_src", "com_aux"
1536};
1537
1538/* usb3 phy on sdx55 doesn't have com_aux clock */
1539static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
1540 "aux", "cfg_ahb", "ref"
1541};
1542
1543static const char * const qcm2290_usb3phy_clk_l[] = {
1544 "cfg_ahb", "ref", "com_aux",
1545};
1546
1547/* list of resets */
1548static const char * const msm8996_usb3phy_reset_l[] = {
1549 "phy", "common",
1550};
1551
1552static const char * const sc7180_usb3phy_reset_l[] = {
1553 "phy",
1554};
1555
1556static const char * const qcm2290_usb3phy_reset_l[] = {
1557 "phy_phy", "phy",
1558};
1559
1560/* list of regulators */
1561static const char * const qmp_phy_vreg_l[] = {
1562 "vdda-phy", "vdda-pll",
1563};
1564
1565static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
1566 .serdes = 0,
1567 .pcs = 0x0200,
1568 .pcs_usb = 0x1200,
1569 .tx = 0x0e00,
1570 .rx = 0x1000,
1571};
1572
1573static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
1574 .lanes = 1,
1575
1576 .serdes_tbl = ipq8074_usb3_serdes_tbl,
1577 .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
1578 .tx_tbl = msm8996_usb3_tx_tbl,
1579 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1580 .rx_tbl = ipq8074_usb3_rx_tbl,
1581 .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
1582 .pcs_tbl = ipq8074_usb3_pcs_tbl,
1583 .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
1584 .clk_list = msm8996_phy_clk_l,
1585 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
1586 .reset_list = msm8996_usb3phy_reset_l,
1587 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1588 .vreg_list = qmp_phy_vreg_l,
1589 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1590 .regs = qmp_v3_usb3phy_regs_layout,
1591};
1592
1593static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
1594 .lanes = 1,
1595
1596 .serdes_tbl = msm8996_usb3_serdes_tbl,
1597 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
1598 .tx_tbl = msm8996_usb3_tx_tbl,
1599 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1600 .rx_tbl = msm8996_usb3_rx_tbl,
1601 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
1602 .pcs_tbl = msm8996_usb3_pcs_tbl,
1603 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
1604 .clk_list = msm8996_phy_clk_l,
1605 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
1606 .reset_list = msm8996_usb3phy_reset_l,
1607 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1608 .vreg_list = qmp_phy_vreg_l,
1609 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1610 .regs = usb3phy_regs_layout,
1611};
1612
1613static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
1614 .lanes = 2,
1615
1616 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
1617 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1618 .tx_tbl = qmp_v3_usb3_tx_tbl,
1619 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1620 .rx_tbl = qmp_v3_usb3_rx_tbl,
1621 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1622 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
1623 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1624 .clk_list = qmp_v3_phy_clk_l,
1625 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
1626 .reset_list = msm8996_usb3phy_reset_l,
1627 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1628 .vreg_list = qmp_phy_vreg_l,
1629 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1630 .regs = qmp_v3_usb3phy_regs_layout,
1631
1632 .has_pwrdn_delay = true,
1633 .has_phy_dp_com_ctrl = true,
1634};
1635
1636static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
1637 .lanes = 2,
1638
1639 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
1640 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1641 .tx_tbl = qmp_v3_usb3_tx_tbl,
1642 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1643 .rx_tbl = qmp_v3_usb3_rx_tbl,
1644 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1645 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
1646 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1647 .clk_list = qmp_v3_phy_clk_l,
1648 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
1649 .reset_list = sc7180_usb3phy_reset_l,
1650 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
1651 .vreg_list = qmp_phy_vreg_l,
1652 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1653 .regs = qmp_v3_usb3phy_regs_layout,
1654
1655 .has_pwrdn_delay = true,
1656 .has_phy_dp_com_ctrl = true,
1657};
1658
1659static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = {
1660 .lanes = 1,
1661
1662 .offsets = &qmp_usb_offsets_v5,
1663
1664 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl,
1665 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),
1666 .tx_tbl = sc8280xp_usb3_uniphy_tx_tbl,
1667 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl),
1668 .rx_tbl = sc8280xp_usb3_uniphy_rx_tbl,
1669 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl),
1670 .pcs_tbl = sc8280xp_usb3_uniphy_pcs_tbl,
1671 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_tbl),
1672 .clk_list = qmp_v4_phy_clk_l,
1673 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
1674 .reset_list = qcm2290_usb3phy_reset_l,
1675 .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
1676 .vreg_list = qmp_phy_vreg_l,
1677 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1678 .regs = qmp_v4_usb3phy_regs_layout,
1679};
1680
1681static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
1682 .lanes = 1,
1683
1684 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
1685 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
1686 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
1687 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
1688 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
1689 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
1690 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
1691 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
1692 .clk_list = qmp_v3_phy_clk_l,
1693 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
1694 .reset_list = msm8996_usb3phy_reset_l,
1695 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1696 .vreg_list = qmp_phy_vreg_l,
1697 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1698 .regs = qmp_v3_usb3phy_regs_layout,
1699
1700 .has_pwrdn_delay = true,
1701};
1702
1703static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
1704 .lanes = 2,
1705
1706 .serdes_tbl = msm8998_usb3_serdes_tbl,
1707 .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
1708 .tx_tbl = msm8998_usb3_tx_tbl,
1709 .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
1710 .rx_tbl = msm8998_usb3_rx_tbl,
1711 .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
1712 .pcs_tbl = msm8998_usb3_pcs_tbl,
1713 .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
1714 .clk_list = msm8996_phy_clk_l,
1715 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
1716 .reset_list = msm8996_usb3phy_reset_l,
1717 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1718 .vreg_list = qmp_phy_vreg_l,
1719 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1720 .regs = qmp_v3_usb3phy_regs_layout,
1721};
1722
1723static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
1724 .lanes = 2,
1725
1726 .serdes_tbl = sm8150_usb3_serdes_tbl,
1727 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1728 .tx_tbl = sm8150_usb3_tx_tbl,
1729 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
1730 .rx_tbl = sm8150_usb3_rx_tbl,
1731 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
1732 .pcs_tbl = sm8150_usb3_pcs_tbl,
1733 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
1734 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl,
1735 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl),
1736 .clk_list = qmp_v4_ref_phy_clk_l,
1737 .num_clks = ARRAY_SIZE(qmp_v4_ref_phy_clk_l),
1738 .reset_list = msm8996_usb3phy_reset_l,
1739 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1740 .vreg_list = qmp_phy_vreg_l,
1741 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1742 .regs = qmp_v4_usb3phy_regs_layout,
1743 .pcs_usb_offset = 0x300,
1744
1745 .has_pwrdn_delay = true,
1746 .has_phy_dp_com_ctrl = true,
1747};
1748
1749static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
1750 .lanes = 1,
1751
1752 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1753 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1754 .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
1755 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
1756 .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
1757 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
1758 .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
1759 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
1760 .pcs_usb_tbl = sm8150_usb3_uniphy_pcs_usb_tbl,
1761 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_usb_tbl),
1762 .clk_list = qmp_v4_ref_phy_clk_l,
1763 .num_clks = ARRAY_SIZE(qmp_v4_ref_phy_clk_l),
1764 .reset_list = msm8996_usb3phy_reset_l,
1765 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1766 .vreg_list = qmp_phy_vreg_l,
1767 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1768 .regs = qmp_v4_usb3phy_regs_layout,
1769 .pcs_usb_offset = 0x600,
1770
1771 .has_pwrdn_delay = true,
1772};
1773
1774static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
1775 .lanes = 2,
1776
1777 .serdes_tbl = sm8150_usb3_serdes_tbl,
1778 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1779 .tx_tbl = sm8250_usb3_tx_tbl,
1780 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
1781 .rx_tbl = sm8250_usb3_rx_tbl,
1782 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
1783 .pcs_tbl = sm8250_usb3_pcs_tbl,
1784 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
1785 .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl,
1786 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl),
1787 .clk_list = qmp_v4_sm8250_usbphy_clk_l,
1788 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
1789 .reset_list = msm8996_usb3phy_reset_l,
1790 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1791 .vreg_list = qmp_phy_vreg_l,
1792 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1793 .regs = qmp_v4_usb3phy_regs_layout,
1794 .pcs_usb_offset = 0x300,
1795
1796 .has_pwrdn_delay = true,
1797 .has_phy_dp_com_ctrl = true,
1798};
1799
1800static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
1801 .lanes = 1,
1802
1803 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1804 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1805 .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
1806 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
1807 .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
1808 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
1809 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
1810 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
1811 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl,
1812 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
1813 .clk_list = qmp_v4_ref_phy_clk_l,
1814 .num_clks = ARRAY_SIZE(qmp_v4_ref_phy_clk_l),
1815 .reset_list = msm8996_usb3phy_reset_l,
1816 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1817 .vreg_list = qmp_phy_vreg_l,
1818 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1819 .regs = qmp_v4_usb3phy_regs_layout,
1820 .pcs_usb_offset = 0x600,
1821
1822 .has_pwrdn_delay = true,
1823};
1824
1825static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
1826 .lanes = 1,
1827
1828 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1829 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1830 .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
1831 .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
1832 .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
1833 .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
1834 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
1835 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
1836 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl,
1837 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
1838 .clk_list = qmp_v4_sdx55_usbphy_clk_l,
1839 .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
1840 .reset_list = msm8996_usb3phy_reset_l,
1841 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1842 .vreg_list = qmp_phy_vreg_l,
1843 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1844 .regs = qmp_v4_usb3phy_regs_layout,
1845 .pcs_usb_offset = 0x600,
1846
1847 .has_pwrdn_delay = true,
1848};
1849
1850static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
1851 .lanes = 1,
1852
1853 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1854 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1855 .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
1856 .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
1857 .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
1858 .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
1859 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
1860 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
1861 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl,
1862 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
1863 .clk_list = qmp_v4_sdx55_usbphy_clk_l,
1864 .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
1865 .reset_list = msm8996_usb3phy_reset_l,
1866 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1867 .vreg_list = qmp_phy_vreg_l,
1868 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1869 .regs = qmp_v4_usb3phy_regs_layout,
1870 .pcs_usb_offset = 0x1000,
1871
1872 .has_pwrdn_delay = true,
1873};
1874
1875static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
1876 .lanes = 2,
1877
1878 .serdes_tbl = sm8150_usb3_serdes_tbl,
1879 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1880 .tx_tbl = sm8350_usb3_tx_tbl,
1881 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
1882 .rx_tbl = sm8350_usb3_rx_tbl,
1883 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
1884 .pcs_tbl = sm8350_usb3_pcs_tbl,
1885 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
1886 .pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl,
1887 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl),
1888 .clk_list = qmp_v4_sm8250_usbphy_clk_l,
1889 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
1890 .reset_list = msm8996_usb3phy_reset_l,
1891 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1892 .vreg_list = qmp_phy_vreg_l,
1893 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1894 .regs = qmp_v4_usb3phy_regs_layout,
1895 .pcs_usb_offset = 0x300,
1896
1897 .has_pwrdn_delay = true,
1898 .has_phy_dp_com_ctrl = true,
1899};
1900
1901static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
1902 .lanes = 1,
1903
1904 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1905 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1906 .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
1907 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
1908 .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
1909 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
1910 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
1911 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
1912 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl,
1913 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
1914 .clk_list = qmp_v4_ref_phy_clk_l,
1915 .num_clks = ARRAY_SIZE(qmp_v4_ref_phy_clk_l),
1916 .reset_list = msm8996_usb3phy_reset_l,
1917 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1918 .vreg_list = qmp_phy_vreg_l,
1919 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1920 .regs = qmp_v4_usb3phy_regs_layout,
1921 .pcs_usb_offset = 0x1000,
1922
1923 .has_pwrdn_delay = true,
1924};
1925
1926static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
1927 .lanes = 2,
1928
1929 .serdes_tbl = qcm2290_usb3_serdes_tbl,
1930 .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
1931 .tx_tbl = qcm2290_usb3_tx_tbl,
1932 .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
1933 .rx_tbl = qcm2290_usb3_rx_tbl,
1934 .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
1935 .pcs_tbl = qcm2290_usb3_pcs_tbl,
1936 .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
1937 .clk_list = qcm2290_usb3phy_clk_l,
1938 .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
1939 .reset_list = qcm2290_usb3phy_reset_l,
1940 .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
1941 .vreg_list = qmp_phy_vreg_l,
1942 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1943 .regs = qcm2290_usb3phy_regs_layout,
1944};
1945
1946static void qmp_usb_configure_lane(void __iomem *base,
1947 const struct qmp_phy_init_tbl tbl[],
1948 int num,
1949 u8 lane_mask)
1950{
1951 int i;
1952 const struct qmp_phy_init_tbl *t = tbl;
1953
1954 if (!t)
1955 return;
1956
1957 for (i = 0; i < num; i++, t++) {
1958 if (!(t->lane_mask & lane_mask))
1959 continue;
1960
1961 writel(t->val, base + t->offset);
1962 }
1963}
1964
1965static void qmp_usb_configure(void __iomem *base,
1966 const struct qmp_phy_init_tbl tbl[],
1967 int num)
1968{
1969 qmp_usb_configure_lane(base, tbl, num, 0xff);
1970}
1971
1972static int qmp_usb_serdes_init(struct qmp_usb *qmp)
1973{
1974 const struct qmp_phy_cfg *cfg = qmp->cfg;
1975 void __iomem *serdes = qmp->serdes;
1976 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
1977 int serdes_tbl_num = cfg->serdes_tbl_num;
1978
1979 qmp_usb_configure(serdes, serdes_tbl, serdes_tbl_num);
1980
1981 return 0;
1982}
1983
1984static int qmp_usb_init(struct phy *phy)
1985{
1986 struct qmp_usb *qmp = phy_get_drvdata(phy);
1987 const struct qmp_phy_cfg *cfg = qmp->cfg;
1988 void __iomem *pcs = qmp->pcs;
1989 void __iomem *dp_com = qmp->dp_com;
1990 int ret;
1991
1992 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
1993 if (ret) {
1994 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
1995 return ret;
1996 }
1997
1998 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
1999 if (ret) {
2000 dev_err(qmp->dev, "reset assert failed\n");
2001 goto err_disable_regulators;
2002 }
2003
2004 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
2005 if (ret) {
2006 dev_err(qmp->dev, "reset deassert failed\n");
2007 goto err_disable_regulators;
2008 }
2009
2010 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
2011 if (ret)
2012 goto err_assert_reset;
2013
2014 if (cfg->has_phy_dp_com_ctrl) {
2015 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
2016 SW_PWRDN);
2017 /* override hardware control for reset of qmp phy */
2018 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
2019 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
2020 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
2021
2022 /* Default type-c orientation, i.e CC1 */
2023 qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
2024
2025 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
2026 USB3_MODE | DP_MODE);
2027
2028 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
2029 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
2030 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
2031 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
2032
2033 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
2034 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
2035 }
2036
2037 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
2038
2039 return 0;
2040
2041err_assert_reset:
2042 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2043err_disable_regulators:
2044 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2045
2046 return ret;
2047}
2048
2049static int qmp_usb_exit(struct phy *phy)
2050{
2051 struct qmp_usb *qmp = phy_get_drvdata(phy);
2052 const struct qmp_phy_cfg *cfg = qmp->cfg;
2053
2054 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2055
2056 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2057
2058 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2059
2060 return 0;
2061}
2062
2063static int qmp_usb_power_on(struct phy *phy)
2064{
2065 struct qmp_usb *qmp = phy_get_drvdata(phy);
2066 const struct qmp_phy_cfg *cfg = qmp->cfg;
2067 void __iomem *tx = qmp->tx;
2068 void __iomem *rx = qmp->rx;
2069 void __iomem *pcs = qmp->pcs;
2070 void __iomem *status;
2071 unsigned int val;
2072 int ret;
2073
2074 qmp_usb_serdes_init(qmp);
2075
2076 ret = clk_prepare_enable(qmp->pipe_clk);
2077 if (ret) {
2078 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
2079 return ret;
2080 }
2081
2082 /* Tx, Rx, and PCS configurations */
2083 qmp_usb_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
2084 qmp_usb_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
2085
2086 if (cfg->lanes >= 2) {
2087 qmp_usb_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
2088 qmp_usb_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
2089 }
2090
2091 qmp_usb_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
2092
2093 if (cfg->has_pwrdn_delay)
2094 usleep_range(10, 20);
2095
2096 /* Pull PHY out of reset state */
2097 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2098
2099 /* start SerDes and Phy-Coding-Sublayer */
2100 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
2101
2102 status = pcs + cfg->regs[QPHY_PCS_STATUS];
2103 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200,
2104 PHY_INIT_COMPLETE_TIMEOUT);
2105 if (ret) {
2106 dev_err(qmp->dev, "phy initialization timed-out\n");
2107 goto err_disable_pipe_clk;
2108 }
2109
2110 return 0;
2111
2112err_disable_pipe_clk:
2113 clk_disable_unprepare(qmp->pipe_clk);
2114
2115 return ret;
2116}
2117
2118static int qmp_usb_power_off(struct phy *phy)
2119{
2120 struct qmp_usb *qmp = phy_get_drvdata(phy);
2121 const struct qmp_phy_cfg *cfg = qmp->cfg;
2122
2123 clk_disable_unprepare(qmp->pipe_clk);
2124
2125 /* PHY reset */
2126 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2127
2128 /* stop SerDes and Phy-Coding-Sublayer */
2129 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
2130 SERDES_START | PCS_START);
2131
2132 /* Put PHY into POWER DOWN state: active low */
2133 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
2134 SW_PWRDN);
2135
2136 return 0;
2137}
2138
2139static int qmp_usb_enable(struct phy *phy)
2140{
2141 int ret;
2142
2143 ret = qmp_usb_init(phy);
2144 if (ret)
2145 return ret;
2146
2147 ret = qmp_usb_power_on(phy);
2148 if (ret)
2149 qmp_usb_exit(phy);
2150
2151 return ret;
2152}
2153
2154static int qmp_usb_disable(struct phy *phy)
2155{
2156 int ret;
2157
2158 ret = qmp_usb_power_off(phy);
2159 if (ret)
2160 return ret;
2161 return qmp_usb_exit(phy);
2162}
2163
2164static int qmp_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode)
2165{
2166 struct qmp_usb *qmp = phy_get_drvdata(phy);
2167
2168 qmp->mode = mode;
2169
2170 return 0;
2171}
2172
2173static const struct phy_ops qmp_usb_phy_ops = {
2174 .init = qmp_usb_enable,
2175 .exit = qmp_usb_disable,
2176 .set_mode = qmp_usb_set_mode,
2177 .owner = THIS_MODULE,
2178};
2179
2180static void qmp_usb_enable_autonomous_mode(struct qmp_usb *qmp)
2181{
2182 const struct qmp_phy_cfg *cfg = qmp->cfg;
2183 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
2184 void __iomem *pcs_misc = qmp->pcs_misc;
2185 u32 intr_mask;
2186
2187 if (qmp->mode == PHY_MODE_USB_HOST_SS ||
2188 qmp->mode == PHY_MODE_USB_DEVICE_SS)
2189 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
2190 else
2191 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
2192
2193 /* Clear any pending interrupts status */
2194 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2195 /* Writing 1 followed by 0 clears the interrupt */
2196 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2197
2198 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
2199 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
2200
2201 /* Enable required PHY autonomous mode interrupts */
2202 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
2203
2204 /* Enable i/o clamp_n for autonomous mode */
2205 if (pcs_misc)
2206 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
2207}
2208
2209static void qmp_usb_disable_autonomous_mode(struct qmp_usb *qmp)
2210{
2211 const struct qmp_phy_cfg *cfg = qmp->cfg;
2212 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
2213 void __iomem *pcs_misc = qmp->pcs_misc;
2214
2215 /* Disable i/o clamp_n on resume for normal mode */
2216 if (pcs_misc)
2217 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
2218
2219 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
2220 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
2221
2222 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2223 /* Writing 1 followed by 0 clears the interrupt */
2224 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2225}
2226
2227static int __maybe_unused qmp_usb_runtime_suspend(struct device *dev)
2228{
2229 struct qmp_usb *qmp = dev_get_drvdata(dev);
2230 const struct qmp_phy_cfg *cfg = qmp->cfg;
2231
2232 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
2233
2234 if (!qmp->phy->init_count) {
2235 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2236 return 0;
2237 }
2238
2239 qmp_usb_enable_autonomous_mode(qmp);
2240
2241 clk_disable_unprepare(qmp->pipe_clk);
2242 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2243
2244 return 0;
2245}
2246
2247static int __maybe_unused qmp_usb_runtime_resume(struct device *dev)
2248{
2249 struct qmp_usb *qmp = dev_get_drvdata(dev);
2250 const struct qmp_phy_cfg *cfg = qmp->cfg;
2251 int ret = 0;
2252
2253 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
2254
2255 if (!qmp->phy->init_count) {
2256 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2257 return 0;
2258 }
2259
2260 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
2261 if (ret)
2262 return ret;
2263
2264 ret = clk_prepare_enable(qmp->pipe_clk);
2265 if (ret) {
2266 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
2267 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2268 return ret;
2269 }
2270
2271 qmp_usb_disable_autonomous_mode(qmp);
2272
2273 return 0;
2274}
2275
2276static const struct dev_pm_ops qmp_usb_pm_ops = {
2277 SET_RUNTIME_PM_OPS(qmp_usb_runtime_suspend,
2278 qmp_usb_runtime_resume, NULL)
2279};
2280
2281static int qmp_usb_vreg_init(struct qmp_usb *qmp)
2282{
2283 const struct qmp_phy_cfg *cfg = qmp->cfg;
2284 struct device *dev = qmp->dev;
2285 int num = cfg->num_vregs;
2286 int i;
2287
2288 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
2289 if (!qmp->vregs)
2290 return -ENOMEM;
2291
2292 for (i = 0; i < num; i++)
2293 qmp->vregs[i].supply = cfg->vreg_list[i];
2294
2295 return devm_regulator_bulk_get(dev, num, qmp->vregs);
2296}
2297
2298static int qmp_usb_reset_init(struct qmp_usb *qmp)
2299{
2300 const struct qmp_phy_cfg *cfg = qmp->cfg;
2301 struct device *dev = qmp->dev;
2302 int i;
2303 int ret;
2304
2305 qmp->resets = devm_kcalloc(dev, cfg->num_resets,
2306 sizeof(*qmp->resets), GFP_KERNEL);
2307 if (!qmp->resets)
2308 return -ENOMEM;
2309
2310 for (i = 0; i < cfg->num_resets; i++)
2311 qmp->resets[i].id = cfg->reset_list[i];
2312
2313 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);
2314 if (ret)
2315 return dev_err_probe(dev, ret, "failed to get resets\n");
2316
2317 return 0;
2318}
2319
2320static int qmp_usb_clk_init(struct qmp_usb *qmp)
2321{
2322 const struct qmp_phy_cfg *cfg = qmp->cfg;
2323 struct device *dev = qmp->dev;
2324 int num = cfg->num_clks;
2325 int i;
2326
2327 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
2328 if (!qmp->clks)
2329 return -ENOMEM;
2330
2331 for (i = 0; i < num; i++)
2332 qmp->clks[i].id = cfg->clk_list[i];
2333
2334 return devm_clk_bulk_get(dev, num, qmp->clks);
2335}
2336
2337static void phy_clk_release_provider(void *res)
2338{
2339 of_clk_del_provider(res);
2340}
2341
2342/*
2343 * Register a fixed rate pipe clock.
2344 *
2345 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
2346 * controls it. The <s>_pipe_clk coming out of the GCC is requested
2347 * by the PHY driver for its operations.
2348 * We register the <s>_pipe_clksrc here. The gcc driver takes care
2349 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
2350 * Below picture shows this relationship.
2351 *
2352 * +---------------+
2353 * | PHY block |<<---------------------------------------+
2354 * | | |
2355 * | +-------+ | +-----+ |
2356 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
2357 * clk | +-------+ | +-----+
2358 * +---------------+
2359 */
2360static int phy_pipe_clk_register(struct qmp_usb *qmp, struct device_node *np)
2361{
2362 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
2363 struct clk_init_data init = { };
2364 int ret;
2365
2366 ret = of_property_read_string(np, "clock-output-names", &init.name);
2367 if (ret) {
2368 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
2369 return ret;
2370 }
2371
2372 init.ops = &clk_fixed_rate_ops;
2373
2374 /* controllers using QMP phys use 125MHz pipe clock interface */
2375 fixed->fixed_rate = 125000000;
2376 fixed->hw.init = &init;
2377
2378 ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
2379 if (ret)
2380 return ret;
2381
2382 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
2383 if (ret)
2384 return ret;
2385
2386 /*
2387 * Roll a devm action because the clock provider is the child node, but
2388 * the child node is not actually a device.
2389 */
2390 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
2391}
2392
2393static void __iomem *qmp_usb_iomap(struct device *dev, struct device_node *np,
2394 int index, bool exclusive)
2395{
2396 struct resource res;
2397
2398 if (!exclusive) {
2399 if (of_address_to_resource(np, index, &res))
2400 return IOMEM_ERR_PTR(-EINVAL);
2401
2402 return devm_ioremap(dev, res.start, resource_size(&res));
2403 }
2404
2405 return devm_of_iomap(dev, np, index, NULL);
2406}
2407
2408static int qmp_usb_parse_dt_legacy(struct qmp_usb *qmp, struct device_node *np)
2409{
2410 struct platform_device *pdev = to_platform_device(qmp->dev);
2411 const struct qmp_phy_cfg *cfg = qmp->cfg;
2412 struct device *dev = qmp->dev;
2413 bool exclusive = true;
2414
2415 qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
2416 if (IS_ERR(qmp->serdes))
2417 return PTR_ERR(qmp->serdes);
2418
2419 if (cfg->has_phy_dp_com_ctrl) {
2420 qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
2421 if (IS_ERR(qmp->dp_com))
2422 return PTR_ERR(qmp->dp_com);
2423 }
2424
2425 /*
2426 * FIXME: These bindings should be fixed to not rely on overlapping
2427 * mappings for PCS.
2428 */
2429 if (of_device_is_compatible(dev->of_node, "qcom,sdx65-qmp-usb3-uni-phy"))
2430 exclusive = false;
2431 if (of_device_is_compatible(dev->of_node, "qcom,sm8350-qmp-usb3-uni-phy"))
2432 exclusive = false;
2433
2434 /*
2435 * Get memory resources for the PHY:
2436 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
2437 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
2438 * For single lane PHYs: pcs_misc (optional) -> 3.
2439 */
2440 qmp->tx = devm_of_iomap(dev, np, 0, NULL);
2441 if (IS_ERR(qmp->tx))
2442 return PTR_ERR(qmp->tx);
2443
2444 qmp->rx = devm_of_iomap(dev, np, 1, NULL);
2445 if (IS_ERR(qmp->rx))
2446 return PTR_ERR(qmp->rx);
2447
2448 qmp->pcs = qmp_usb_iomap(dev, np, 2, exclusive);
2449 if (IS_ERR(qmp->pcs))
2450 return PTR_ERR(qmp->pcs);
2451
2452 if (cfg->pcs_usb_offset)
2453 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset;
2454
2455 if (cfg->lanes >= 2) {
2456 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
2457 if (IS_ERR(qmp->tx2))
2458 return PTR_ERR(qmp->tx2);
2459
2460 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
2461 if (IS_ERR(qmp->rx2))
2462 return PTR_ERR(qmp->rx2);
2463
2464 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
2465 } else {
2466 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
2467 }
2468
2469 if (IS_ERR(qmp->pcs_misc)) {
2470 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
2471 qmp->pcs_misc = NULL;
2472 }
2473
2474 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
2475 if (IS_ERR(qmp->pipe_clk)) {
2476 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
2477 "failed to get pipe clock\n");
2478 }
2479
2480 return 0;
2481}
2482
2483static int qmp_usb_parse_dt(struct qmp_usb *qmp)
2484{
2485 struct platform_device *pdev = to_platform_device(qmp->dev);
2486 const struct qmp_phy_cfg *cfg = qmp->cfg;
2487 const struct qmp_usb_offsets *offs = cfg->offsets;
2488 struct device *dev = qmp->dev;
2489 void __iomem *base;
2490
2491 if (!offs)
2492 return -EINVAL;
2493
2494 base = devm_platform_ioremap_resource(pdev, 0);
2495 if (IS_ERR(base))
2496 return PTR_ERR(base);
2497
2498 qmp->serdes = base + offs->serdes;
2499 qmp->pcs = base + offs->pcs;
2500 qmp->pcs_usb = base + offs->pcs_usb;
2501 qmp->tx = base + offs->tx;
2502 qmp->rx = base + offs->rx;
2503
2504 qmp->pipe_clk = devm_clk_get(dev, "pipe");
2505 if (IS_ERR(qmp->pipe_clk)) {
2506 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
2507 "failed to get pipe clock\n");
2508 }
2509
2510 return 0;
2511}
2512
2513static int qmp_usb_probe(struct platform_device *pdev)
2514{
2515 struct device *dev = &pdev->dev;
2516 struct phy_provider *phy_provider;
2517 struct device_node *np;
2518 struct qmp_usb *qmp;
2519 int ret;
2520
2521 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
2522 if (!qmp)
2523 return -ENOMEM;
2524
2525 qmp->dev = dev;
2526
2527 qmp->cfg = of_device_get_match_data(dev);
2528 if (!qmp->cfg)
2529 return -EINVAL;
2530
2531 ret = qmp_usb_clk_init(qmp);
2532 if (ret)
2533 return ret;
2534
2535 ret = qmp_usb_reset_init(qmp);
2536 if (ret)
2537 return ret;
2538
2539 ret = qmp_usb_vreg_init(qmp);
2540 if (ret)
2541 return ret;
2542
2543 /* Check for legacy binding with child node. */
2544 np = of_get_next_available_child(dev->of_node, NULL);
2545 if (np) {
2546 ret = qmp_usb_parse_dt_legacy(qmp, np);
2547 } else {
2548 np = of_node_get(dev->of_node);
2549 ret = qmp_usb_parse_dt(qmp);
2550 }
2551 if (ret)
2552 goto err_node_put;
2553
2554 pm_runtime_set_active(dev);
2555 ret = devm_pm_runtime_enable(dev);
2556 if (ret)
2557 goto err_node_put;
2558 /*
2559 * Prevent runtime pm from being ON by default. Users can enable
2560 * it using power/control in sysfs.
2561 */
2562 pm_runtime_forbid(dev);
2563
2564 ret = phy_pipe_clk_register(qmp, np);
2565 if (ret)
2566 goto err_node_put;
2567
2568 qmp->phy = devm_phy_create(dev, np, &qmp_usb_phy_ops);
2569 if (IS_ERR(qmp->phy)) {
2570 ret = PTR_ERR(qmp->phy);
2571 dev_err(dev, "failed to create PHY: %d\n", ret);
2572 goto err_node_put;
2573 }
2574
2575 phy_set_drvdata(qmp->phy, qmp);
2576
2577 of_node_put(np);
2578
2579 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2580
2581 return PTR_ERR_OR_ZERO(phy_provider);
2582
2583err_node_put:
2584 of_node_put(np);
2585 return ret;
2586}
2587
2588static const struct of_device_id qmp_usb_of_match_table[] = {
2589 {
2590 .compatible = "qcom,ipq6018-qmp-usb3-phy",
2591 .data = &ipq8074_usb3phy_cfg,
2592 }, {
2593 .compatible = "qcom,ipq8074-qmp-usb3-phy",
2594 .data = &ipq8074_usb3phy_cfg,
2595 }, {
2596 .compatible = "qcom,msm8996-qmp-usb3-phy",
2597 .data = &msm8996_usb3phy_cfg,
2598 }, {
2599 .compatible = "qcom,msm8998-qmp-usb3-phy",
2600 .data = &msm8998_usb3phy_cfg,
2601 }, {
2602 .compatible = "qcom,qcm2290-qmp-usb3-phy",
2603 .data = &qcm2290_usb3phy_cfg,
2604 }, {
2605 .compatible = "qcom,sc7180-qmp-usb3-phy",
2606 .data = &sc7180_usb3phy_cfg,
2607 }, {
2608 .compatible = "qcom,sc8180x-qmp-usb3-phy",
2609 .data = &sm8150_usb3phy_cfg,
2610 }, {
2611 .compatible = "qcom,sc8280xp-qmp-usb3-uni-phy",
2612 .data = &sc8280xp_usb3_uniphy_cfg,
2613 }, {
2614 .compatible = "qcom,sdm845-qmp-usb3-phy",
2615 .data = &qmp_v3_usb3phy_cfg,
2616 }, {
2617 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
2618 .data = &qmp_v3_usb3_uniphy_cfg,
2619 }, {
2620 .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
2621 .data = &sdx55_usb3_uniphy_cfg,
2622 }, {
2623 .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
2624 .data = &sdx65_usb3_uniphy_cfg,
2625 }, {
2626 .compatible = "qcom,sm8150-qmp-usb3-phy",
2627 .data = &sm8150_usb3phy_cfg,
2628 }, {
2629 .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
2630 .data = &sm8150_usb3_uniphy_cfg,
2631 }, {
2632 .compatible = "qcom,sm8250-qmp-usb3-phy",
2633 .data = &sm8250_usb3phy_cfg,
2634 }, {
2635 .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
2636 .data = &sm8250_usb3_uniphy_cfg,
2637 }, {
2638 .compatible = "qcom,sm8350-qmp-usb3-phy",
2639 .data = &sm8350_usb3phy_cfg,
2640 }, {
2641 .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
2642 .data = &sm8350_usb3_uniphy_cfg,
2643 }, {
2644 .compatible = "qcom,sm8450-qmp-usb3-phy",
2645 .data = &sm8350_usb3phy_cfg,
2646 },
2647 { },
2648};
2649MODULE_DEVICE_TABLE(of, qmp_usb_of_match_table);
2650
2651static struct platform_driver qmp_usb_driver = {
2652 .probe = qmp_usb_probe,
2653 .driver = {
2654 .name = "qcom-qmp-usb-phy",
2655 .pm = &qmp_usb_pm_ops,
2656 .of_match_table = qmp_usb_of_match_table,
2657 },
2658};
2659
2660module_platform_driver(qmp_usb_driver);
2661
2662MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
2663MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver");
2664MODULE_LICENSE("GPL v2");