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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Keyboard class input driver for the NVIDIA Tegra SoC internal matrix
4 * keyboard controller
5 *
6 * Copyright (c) 2009-2011, NVIDIA Corporation.
7 */
8
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/input.h>
12#include <linux/platform_device.h>
13#include <linux/delay.h>
14#include <linux/io.h>
15#include <linux/interrupt.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18#include <linux/clk.h>
19#include <linux/slab.h>
20#include <linux/input/matrix_keypad.h>
21#include <linux/reset.h>
22#include <linux/err.h>
23
24#define KBC_MAX_KPENT 8
25
26/* Maximum row/column supported by Tegra KBC yet is 16x8 */
27#define KBC_MAX_GPIO 24
28/* Maximum keys supported by Tegra KBC yet is 16 x 8*/
29#define KBC_MAX_KEY (16 * 8)
30
31#define KBC_MAX_DEBOUNCE_CNT 0x3ffu
32
33/* KBC row scan time and delay for beginning the row scan. */
34#define KBC_ROW_SCAN_TIME 16
35#define KBC_ROW_SCAN_DLY 5
36
37/* KBC uses a 32KHz clock so a cycle = 1/32Khz */
38#define KBC_CYCLE_MS 32
39
40/* KBC Registers */
41
42/* KBC Control Register */
43#define KBC_CONTROL_0 0x0
44#define KBC_FIFO_TH_CNT_SHIFT(cnt) (cnt << 14)
45#define KBC_DEBOUNCE_CNT_SHIFT(cnt) (cnt << 4)
46#define KBC_CONTROL_FIFO_CNT_INT_EN (1 << 3)
47#define KBC_CONTROL_KEYPRESS_INT_EN (1 << 1)
48#define KBC_CONTROL_KBC_EN (1 << 0)
49
50/* KBC Interrupt Register */
51#define KBC_INT_0 0x4
52#define KBC_INT_FIFO_CNT_INT_STATUS (1 << 2)
53#define KBC_INT_KEYPRESS_INT_STATUS (1 << 0)
54
55#define KBC_ROW_CFG0_0 0x8
56#define KBC_COL_CFG0_0 0x18
57#define KBC_TO_CNT_0 0x24
58#define KBC_INIT_DLY_0 0x28
59#define KBC_RPT_DLY_0 0x2c
60#define KBC_KP_ENT0_0 0x30
61#define KBC_KP_ENT1_0 0x34
62#define KBC_ROW0_MASK_0 0x38
63
64#define KBC_ROW_SHIFT 3
65
66enum tegra_pin_type {
67 PIN_CFG_IGNORE,
68 PIN_CFG_COL,
69 PIN_CFG_ROW,
70};
71
72/* Tegra KBC hw support */
73struct tegra_kbc_hw_support {
74 int max_rows;
75 int max_columns;
76};
77
78struct tegra_kbc_pin_cfg {
79 enum tegra_pin_type type;
80 unsigned char num;
81};
82
83struct tegra_kbc {
84 struct device *dev;
85 unsigned int debounce_cnt;
86 unsigned int repeat_cnt;
87 struct tegra_kbc_pin_cfg pin_cfg[KBC_MAX_GPIO];
88 const struct matrix_keymap_data *keymap_data;
89 bool wakeup;
90 void __iomem *mmio;
91 struct input_dev *idev;
92 int irq;
93 spinlock_t lock;
94 unsigned int repoll_dly;
95 unsigned long cp_dly_jiffies;
96 unsigned int cp_to_wkup_dly;
97 bool use_fn_map;
98 bool use_ghost_filter;
99 bool keypress_caused_wake;
100 unsigned short keycode[KBC_MAX_KEY * 2];
101 unsigned short current_keys[KBC_MAX_KPENT];
102 unsigned int num_pressed_keys;
103 u32 wakeup_key;
104 struct timer_list timer;
105 struct clk *clk;
106 struct reset_control *rst;
107 const struct tegra_kbc_hw_support *hw_support;
108 int max_keys;
109 int num_rows_and_columns;
110};
111
112static void tegra_kbc_report_released_keys(struct input_dev *input,
113 unsigned short old_keycodes[],
114 unsigned int old_num_keys,
115 unsigned short new_keycodes[],
116 unsigned int new_num_keys)
117{
118 unsigned int i, j;
119
120 for (i = 0; i < old_num_keys; i++) {
121 for (j = 0; j < new_num_keys; j++)
122 if (old_keycodes[i] == new_keycodes[j])
123 break;
124
125 if (j == new_num_keys)
126 input_report_key(input, old_keycodes[i], 0);
127 }
128}
129
130static void tegra_kbc_report_pressed_keys(struct input_dev *input,
131 unsigned char scancodes[],
132 unsigned short keycodes[],
133 unsigned int num_pressed_keys)
134{
135 unsigned int i;
136
137 for (i = 0; i < num_pressed_keys; i++) {
138 input_event(input, EV_MSC, MSC_SCAN, scancodes[i]);
139 input_report_key(input, keycodes[i], 1);
140 }
141}
142
143static void tegra_kbc_report_keys(struct tegra_kbc *kbc)
144{
145 unsigned char scancodes[KBC_MAX_KPENT];
146 unsigned short keycodes[KBC_MAX_KPENT];
147 u32 val = 0;
148 unsigned int i;
149 unsigned int num_down = 0;
150 bool fn_keypress = false;
151 bool key_in_same_row = false;
152 bool key_in_same_col = false;
153
154 for (i = 0; i < KBC_MAX_KPENT; i++) {
155 if ((i % 4) == 0)
156 val = readl(kbc->mmio + KBC_KP_ENT0_0 + i);
157
158 if (val & 0x80) {
159 unsigned int col = val & 0x07;
160 unsigned int row = (val >> 3) & 0x0f;
161 unsigned char scancode =
162 MATRIX_SCAN_CODE(row, col, KBC_ROW_SHIFT);
163
164 scancodes[num_down] = scancode;
165 keycodes[num_down] = kbc->keycode[scancode];
166 /* If driver uses Fn map, do not report the Fn key. */
167 if ((keycodes[num_down] == KEY_FN) && kbc->use_fn_map)
168 fn_keypress = true;
169 else
170 num_down++;
171 }
172
173 val >>= 8;
174 }
175
176 /*
177 * Matrix keyboard designs are prone to keyboard ghosting.
178 * Ghosting occurs if there are 3 keys such that -
179 * any 2 of the 3 keys share a row, and any 2 of them share a column.
180 * If so ignore the key presses for this iteration.
181 */
182 if (kbc->use_ghost_filter && num_down >= 3) {
183 for (i = 0; i < num_down; i++) {
184 unsigned int j;
185 u8 curr_col = scancodes[i] & 0x07;
186 u8 curr_row = scancodes[i] >> KBC_ROW_SHIFT;
187
188 /*
189 * Find 2 keys such that one key is in the same row
190 * and the other is in the same column as the i-th key.
191 */
192 for (j = i + 1; j < num_down; j++) {
193 u8 col = scancodes[j] & 0x07;
194 u8 row = scancodes[j] >> KBC_ROW_SHIFT;
195
196 if (col == curr_col)
197 key_in_same_col = true;
198 if (row == curr_row)
199 key_in_same_row = true;
200 }
201 }
202 }
203
204 /*
205 * If the platform uses Fn keymaps, translate keys on a Fn keypress.
206 * Function keycodes are max_keys apart from the plain keycodes.
207 */
208 if (fn_keypress) {
209 for (i = 0; i < num_down; i++) {
210 scancodes[i] += kbc->max_keys;
211 keycodes[i] = kbc->keycode[scancodes[i]];
212 }
213 }
214
215 /* Ignore the key presses for this iteration? */
216 if (key_in_same_col && key_in_same_row)
217 return;
218
219 tegra_kbc_report_released_keys(kbc->idev,
220 kbc->current_keys, kbc->num_pressed_keys,
221 keycodes, num_down);
222 tegra_kbc_report_pressed_keys(kbc->idev, scancodes, keycodes, num_down);
223 input_sync(kbc->idev);
224
225 memcpy(kbc->current_keys, keycodes, sizeof(kbc->current_keys));
226 kbc->num_pressed_keys = num_down;
227}
228
229static void tegra_kbc_set_fifo_interrupt(struct tegra_kbc *kbc, bool enable)
230{
231 u32 val;
232
233 val = readl(kbc->mmio + KBC_CONTROL_0);
234 if (enable)
235 val |= KBC_CONTROL_FIFO_CNT_INT_EN;
236 else
237 val &= ~KBC_CONTROL_FIFO_CNT_INT_EN;
238 writel(val, kbc->mmio + KBC_CONTROL_0);
239}
240
241static void tegra_kbc_keypress_timer(struct timer_list *t)
242{
243 struct tegra_kbc *kbc = from_timer(kbc, t, timer);
244 unsigned long flags;
245 u32 val;
246 unsigned int i;
247
248 spin_lock_irqsave(&kbc->lock, flags);
249
250 val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf;
251 if (val) {
252 unsigned long dly;
253
254 tegra_kbc_report_keys(kbc);
255
256 /*
257 * If more than one keys are pressed we need not wait
258 * for the repoll delay.
259 */
260 dly = (val == 1) ? kbc->repoll_dly : 1;
261 mod_timer(&kbc->timer, jiffies + msecs_to_jiffies(dly));
262 } else {
263 /* Release any pressed keys and exit the polling loop */
264 for (i = 0; i < kbc->num_pressed_keys; i++)
265 input_report_key(kbc->idev, kbc->current_keys[i], 0);
266 input_sync(kbc->idev);
267
268 kbc->num_pressed_keys = 0;
269
270 /* All keys are released so enable the keypress interrupt */
271 tegra_kbc_set_fifo_interrupt(kbc, true);
272 }
273
274 spin_unlock_irqrestore(&kbc->lock, flags);
275}
276
277static irqreturn_t tegra_kbc_isr(int irq, void *args)
278{
279 struct tegra_kbc *kbc = args;
280 unsigned long flags;
281 u32 val;
282
283 spin_lock_irqsave(&kbc->lock, flags);
284
285 /*
286 * Quickly bail out & reenable interrupts if the fifo threshold
287 * count interrupt wasn't the interrupt source
288 */
289 val = readl(kbc->mmio + KBC_INT_0);
290 writel(val, kbc->mmio + KBC_INT_0);
291
292 if (val & KBC_INT_FIFO_CNT_INT_STATUS) {
293 /*
294 * Until all keys are released, defer further processing to
295 * the polling loop in tegra_kbc_keypress_timer.
296 */
297 tegra_kbc_set_fifo_interrupt(kbc, false);
298 mod_timer(&kbc->timer, jiffies + kbc->cp_dly_jiffies);
299 } else if (val & KBC_INT_KEYPRESS_INT_STATUS) {
300 /* We can be here only through system resume path */
301 kbc->keypress_caused_wake = true;
302 }
303
304 spin_unlock_irqrestore(&kbc->lock, flags);
305
306 return IRQ_HANDLED;
307}
308
309static void tegra_kbc_setup_wakekeys(struct tegra_kbc *kbc, bool filter)
310{
311 int i;
312 unsigned int rst_val;
313
314 /* Either mask all keys or none. */
315 rst_val = (filter && !kbc->wakeup) ? ~0 : 0;
316
317 for (i = 0; i < kbc->hw_support->max_rows; i++)
318 writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4);
319}
320
321static void tegra_kbc_config_pins(struct tegra_kbc *kbc)
322{
323 int i;
324
325 for (i = 0; i < KBC_MAX_GPIO; i++) {
326 u32 r_shft = 5 * (i % 6);
327 u32 c_shft = 4 * (i % 8);
328 u32 r_mask = 0x1f << r_shft;
329 u32 c_mask = 0x0f << c_shft;
330 u32 r_offs = (i / 6) * 4 + KBC_ROW_CFG0_0;
331 u32 c_offs = (i / 8) * 4 + KBC_COL_CFG0_0;
332 u32 row_cfg = readl(kbc->mmio + r_offs);
333 u32 col_cfg = readl(kbc->mmio + c_offs);
334
335 row_cfg &= ~r_mask;
336 col_cfg &= ~c_mask;
337
338 switch (kbc->pin_cfg[i].type) {
339 case PIN_CFG_ROW:
340 row_cfg |= ((kbc->pin_cfg[i].num << 1) | 1) << r_shft;
341 break;
342
343 case PIN_CFG_COL:
344 col_cfg |= ((kbc->pin_cfg[i].num << 1) | 1) << c_shft;
345 break;
346
347 case PIN_CFG_IGNORE:
348 break;
349 }
350
351 writel(row_cfg, kbc->mmio + r_offs);
352 writel(col_cfg, kbc->mmio + c_offs);
353 }
354}
355
356static int tegra_kbc_start(struct tegra_kbc *kbc)
357{
358 unsigned int debounce_cnt;
359 u32 val = 0;
360 int ret;
361
362 ret = clk_prepare_enable(kbc->clk);
363 if (ret)
364 return ret;
365
366 /* Reset the KBC controller to clear all previous status.*/
367 reset_control_assert(kbc->rst);
368 udelay(100);
369 reset_control_deassert(kbc->rst);
370 udelay(100);
371
372 tegra_kbc_config_pins(kbc);
373 tegra_kbc_setup_wakekeys(kbc, false);
374
375 writel(kbc->repeat_cnt, kbc->mmio + KBC_RPT_DLY_0);
376
377 /* Keyboard debounce count is maximum of 12 bits. */
378 debounce_cnt = min(kbc->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
379 val = KBC_DEBOUNCE_CNT_SHIFT(debounce_cnt);
380 val |= KBC_FIFO_TH_CNT_SHIFT(1); /* set fifo interrupt threshold to 1 */
381 val |= KBC_CONTROL_FIFO_CNT_INT_EN; /* interrupt on FIFO threshold */
382 val |= KBC_CONTROL_KBC_EN; /* enable */
383 writel(val, kbc->mmio + KBC_CONTROL_0);
384
385 /*
386 * Compute the delay(ns) from interrupt mode to continuous polling
387 * mode so the timer routine is scheduled appropriately.
388 */
389 val = readl(kbc->mmio + KBC_INIT_DLY_0);
390 kbc->cp_dly_jiffies = usecs_to_jiffies((val & 0xfffff) * 32);
391
392 kbc->num_pressed_keys = 0;
393
394 /*
395 * Atomically clear out any remaining entries in the key FIFO
396 * and enable keyboard interrupts.
397 */
398 while (1) {
399 val = readl(kbc->mmio + KBC_INT_0);
400 val >>= 4;
401 if (!val)
402 break;
403
404 val = readl(kbc->mmio + KBC_KP_ENT0_0);
405 val = readl(kbc->mmio + KBC_KP_ENT1_0);
406 }
407 writel(0x7, kbc->mmio + KBC_INT_0);
408
409 enable_irq(kbc->irq);
410
411 return 0;
412}
413
414static void tegra_kbc_stop(struct tegra_kbc *kbc)
415{
416 unsigned long flags;
417 u32 val;
418
419 spin_lock_irqsave(&kbc->lock, flags);
420 val = readl(kbc->mmio + KBC_CONTROL_0);
421 val &= ~1;
422 writel(val, kbc->mmio + KBC_CONTROL_0);
423 spin_unlock_irqrestore(&kbc->lock, flags);
424
425 disable_irq(kbc->irq);
426 del_timer_sync(&kbc->timer);
427
428 clk_disable_unprepare(kbc->clk);
429}
430
431static int tegra_kbc_open(struct input_dev *dev)
432{
433 struct tegra_kbc *kbc = input_get_drvdata(dev);
434
435 return tegra_kbc_start(kbc);
436}
437
438static void tegra_kbc_close(struct input_dev *dev)
439{
440 struct tegra_kbc *kbc = input_get_drvdata(dev);
441
442 return tegra_kbc_stop(kbc);
443}
444
445static bool tegra_kbc_check_pin_cfg(const struct tegra_kbc *kbc,
446 unsigned int *num_rows)
447{
448 int i;
449
450 *num_rows = 0;
451
452 for (i = 0; i < KBC_MAX_GPIO; i++) {
453 const struct tegra_kbc_pin_cfg *pin_cfg = &kbc->pin_cfg[i];
454
455 switch (pin_cfg->type) {
456 case PIN_CFG_ROW:
457 if (pin_cfg->num >= kbc->hw_support->max_rows) {
458 dev_err(kbc->dev,
459 "pin_cfg[%d]: invalid row number %d\n",
460 i, pin_cfg->num);
461 return false;
462 }
463 (*num_rows)++;
464 break;
465
466 case PIN_CFG_COL:
467 if (pin_cfg->num >= kbc->hw_support->max_columns) {
468 dev_err(kbc->dev,
469 "pin_cfg[%d]: invalid column number %d\n",
470 i, pin_cfg->num);
471 return false;
472 }
473 break;
474
475 case PIN_CFG_IGNORE:
476 break;
477
478 default:
479 dev_err(kbc->dev,
480 "pin_cfg[%d]: invalid entry type %d\n",
481 pin_cfg->type, pin_cfg->num);
482 return false;
483 }
484 }
485
486 return true;
487}
488
489static int tegra_kbc_parse_dt(struct tegra_kbc *kbc)
490{
491 struct device_node *np = kbc->dev->of_node;
492 u32 prop;
493 int i;
494 u32 num_rows = 0;
495 u32 num_cols = 0;
496 u32 cols_cfg[KBC_MAX_GPIO];
497 u32 rows_cfg[KBC_MAX_GPIO];
498 int proplen;
499 int ret;
500
501 if (!of_property_read_u32(np, "nvidia,debounce-delay-ms", &prop))
502 kbc->debounce_cnt = prop;
503
504 if (!of_property_read_u32(np, "nvidia,repeat-delay-ms", &prop))
505 kbc->repeat_cnt = prop;
506
507 if (of_find_property(np, "nvidia,needs-ghost-filter", NULL))
508 kbc->use_ghost_filter = true;
509
510 if (of_property_read_bool(np, "wakeup-source") ||
511 of_property_read_bool(np, "nvidia,wakeup-source")) /* legacy */
512 kbc->wakeup = true;
513
514 if (!of_get_property(np, "nvidia,kbc-row-pins", &proplen)) {
515 dev_err(kbc->dev, "property nvidia,kbc-row-pins not found\n");
516 return -ENOENT;
517 }
518 num_rows = proplen / sizeof(u32);
519
520 if (!of_get_property(np, "nvidia,kbc-col-pins", &proplen)) {
521 dev_err(kbc->dev, "property nvidia,kbc-col-pins not found\n");
522 return -ENOENT;
523 }
524 num_cols = proplen / sizeof(u32);
525
526 if (num_rows > kbc->hw_support->max_rows) {
527 dev_err(kbc->dev,
528 "Number of rows is more than supported by hardware\n");
529 return -EINVAL;
530 }
531
532 if (num_cols > kbc->hw_support->max_columns) {
533 dev_err(kbc->dev,
534 "Number of cols is more than supported by hardware\n");
535 return -EINVAL;
536 }
537
538 if (!of_get_property(np, "linux,keymap", &proplen)) {
539 dev_err(kbc->dev, "property linux,keymap not found\n");
540 return -ENOENT;
541 }
542
543 if (!num_rows || !num_cols || ((num_rows + num_cols) > KBC_MAX_GPIO)) {
544 dev_err(kbc->dev,
545 "keypad rows/columns not properly specified\n");
546 return -EINVAL;
547 }
548
549 /* Set all pins as non-configured */
550 for (i = 0; i < kbc->num_rows_and_columns; i++)
551 kbc->pin_cfg[i].type = PIN_CFG_IGNORE;
552
553 ret = of_property_read_u32_array(np, "nvidia,kbc-row-pins",
554 rows_cfg, num_rows);
555 if (ret < 0) {
556 dev_err(kbc->dev, "Rows configurations are not proper\n");
557 return -EINVAL;
558 }
559
560 ret = of_property_read_u32_array(np, "nvidia,kbc-col-pins",
561 cols_cfg, num_cols);
562 if (ret < 0) {
563 dev_err(kbc->dev, "Cols configurations are not proper\n");
564 return -EINVAL;
565 }
566
567 for (i = 0; i < num_rows; i++) {
568 kbc->pin_cfg[rows_cfg[i]].type = PIN_CFG_ROW;
569 kbc->pin_cfg[rows_cfg[i]].num = i;
570 }
571
572 for (i = 0; i < num_cols; i++) {
573 kbc->pin_cfg[cols_cfg[i]].type = PIN_CFG_COL;
574 kbc->pin_cfg[cols_cfg[i]].num = i;
575 }
576
577 return 0;
578}
579
580static const struct tegra_kbc_hw_support tegra20_kbc_hw_support = {
581 .max_rows = 16,
582 .max_columns = 8,
583};
584
585static const struct tegra_kbc_hw_support tegra11_kbc_hw_support = {
586 .max_rows = 11,
587 .max_columns = 8,
588};
589
590static const struct of_device_id tegra_kbc_of_match[] = {
591 { .compatible = "nvidia,tegra114-kbc", .data = &tegra11_kbc_hw_support},
592 { .compatible = "nvidia,tegra30-kbc", .data = &tegra20_kbc_hw_support},
593 { .compatible = "nvidia,tegra20-kbc", .data = &tegra20_kbc_hw_support},
594 { },
595};
596MODULE_DEVICE_TABLE(of, tegra_kbc_of_match);
597
598static int tegra_kbc_probe(struct platform_device *pdev)
599{
600 struct tegra_kbc *kbc;
601 struct resource *res;
602 int err;
603 int num_rows = 0;
604 unsigned int debounce_cnt;
605 unsigned int scan_time_rows;
606 unsigned int keymap_rows;
607 const struct of_device_id *match;
608
609 match = of_match_device(tegra_kbc_of_match, &pdev->dev);
610
611 kbc = devm_kzalloc(&pdev->dev, sizeof(*kbc), GFP_KERNEL);
612 if (!kbc) {
613 dev_err(&pdev->dev, "failed to alloc memory for kbc\n");
614 return -ENOMEM;
615 }
616
617 kbc->dev = &pdev->dev;
618 kbc->hw_support = match->data;
619 kbc->max_keys = kbc->hw_support->max_rows *
620 kbc->hw_support->max_columns;
621 kbc->num_rows_and_columns = kbc->hw_support->max_rows +
622 kbc->hw_support->max_columns;
623 keymap_rows = kbc->max_keys;
624 spin_lock_init(&kbc->lock);
625
626 err = tegra_kbc_parse_dt(kbc);
627 if (err)
628 return err;
629
630 if (!tegra_kbc_check_pin_cfg(kbc, &num_rows))
631 return -EINVAL;
632
633 kbc->irq = platform_get_irq(pdev, 0);
634 if (kbc->irq < 0)
635 return -ENXIO;
636
637 kbc->idev = devm_input_allocate_device(&pdev->dev);
638 if (!kbc->idev) {
639 dev_err(&pdev->dev, "failed to allocate input device\n");
640 return -ENOMEM;
641 }
642
643 timer_setup(&kbc->timer, tegra_kbc_keypress_timer, 0);
644
645 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
646 kbc->mmio = devm_ioremap_resource(&pdev->dev, res);
647 if (IS_ERR(kbc->mmio))
648 return PTR_ERR(kbc->mmio);
649
650 kbc->clk = devm_clk_get(&pdev->dev, NULL);
651 if (IS_ERR(kbc->clk)) {
652 dev_err(&pdev->dev, "failed to get keyboard clock\n");
653 return PTR_ERR(kbc->clk);
654 }
655
656 kbc->rst = devm_reset_control_get(&pdev->dev, "kbc");
657 if (IS_ERR(kbc->rst)) {
658 dev_err(&pdev->dev, "failed to get keyboard reset\n");
659 return PTR_ERR(kbc->rst);
660 }
661
662 /*
663 * The time delay between two consecutive reads of the FIFO is
664 * the sum of the repeat time and the time taken for scanning
665 * the rows. There is an additional delay before the row scanning
666 * starts. The repoll delay is computed in milliseconds.
667 */
668 debounce_cnt = min(kbc->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
669 scan_time_rows = (KBC_ROW_SCAN_TIME + debounce_cnt) * num_rows;
670 kbc->repoll_dly = KBC_ROW_SCAN_DLY + scan_time_rows + kbc->repeat_cnt;
671 kbc->repoll_dly = DIV_ROUND_UP(kbc->repoll_dly, KBC_CYCLE_MS);
672
673 kbc->idev->name = pdev->name;
674 kbc->idev->id.bustype = BUS_HOST;
675 kbc->idev->dev.parent = &pdev->dev;
676 kbc->idev->open = tegra_kbc_open;
677 kbc->idev->close = tegra_kbc_close;
678
679 if (kbc->keymap_data && kbc->use_fn_map)
680 keymap_rows *= 2;
681
682 err = matrix_keypad_build_keymap(kbc->keymap_data, NULL,
683 keymap_rows,
684 kbc->hw_support->max_columns,
685 kbc->keycode, kbc->idev);
686 if (err) {
687 dev_err(&pdev->dev, "failed to setup keymap\n");
688 return err;
689 }
690
691 __set_bit(EV_REP, kbc->idev->evbit);
692 input_set_capability(kbc->idev, EV_MSC, MSC_SCAN);
693
694 input_set_drvdata(kbc->idev, kbc);
695
696 err = devm_request_irq(&pdev->dev, kbc->irq, tegra_kbc_isr,
697 IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN,
698 pdev->name, kbc);
699 if (err) {
700 dev_err(&pdev->dev, "failed to request keyboard IRQ\n");
701 return err;
702 }
703
704 err = input_register_device(kbc->idev);
705 if (err) {
706 dev_err(&pdev->dev, "failed to register input device\n");
707 return err;
708 }
709
710 platform_set_drvdata(pdev, kbc);
711 device_init_wakeup(&pdev->dev, kbc->wakeup);
712
713 return 0;
714}
715
716static void tegra_kbc_set_keypress_interrupt(struct tegra_kbc *kbc, bool enable)
717{
718 u32 val;
719
720 val = readl(kbc->mmio + KBC_CONTROL_0);
721 if (enable)
722 val |= KBC_CONTROL_KEYPRESS_INT_EN;
723 else
724 val &= ~KBC_CONTROL_KEYPRESS_INT_EN;
725 writel(val, kbc->mmio + KBC_CONTROL_0);
726}
727
728static int tegra_kbc_suspend(struct device *dev)
729{
730 struct platform_device *pdev = to_platform_device(dev);
731 struct tegra_kbc *kbc = platform_get_drvdata(pdev);
732
733 mutex_lock(&kbc->idev->mutex);
734 if (device_may_wakeup(&pdev->dev)) {
735 disable_irq(kbc->irq);
736 del_timer_sync(&kbc->timer);
737 tegra_kbc_set_fifo_interrupt(kbc, false);
738
739 /* Forcefully clear the interrupt status */
740 writel(0x7, kbc->mmio + KBC_INT_0);
741 /*
742 * Store the previous resident time of continuous polling mode.
743 * Force the keyboard into interrupt mode.
744 */
745 kbc->cp_to_wkup_dly = readl(kbc->mmio + KBC_TO_CNT_0);
746 writel(0, kbc->mmio + KBC_TO_CNT_0);
747
748 tegra_kbc_setup_wakekeys(kbc, true);
749 msleep(30);
750
751 kbc->keypress_caused_wake = false;
752 /* Enable keypress interrupt before going into suspend. */
753 tegra_kbc_set_keypress_interrupt(kbc, true);
754 enable_irq(kbc->irq);
755 enable_irq_wake(kbc->irq);
756 } else {
757 if (input_device_enabled(kbc->idev))
758 tegra_kbc_stop(kbc);
759 }
760 mutex_unlock(&kbc->idev->mutex);
761
762 return 0;
763}
764
765static int tegra_kbc_resume(struct device *dev)
766{
767 struct platform_device *pdev = to_platform_device(dev);
768 struct tegra_kbc *kbc = platform_get_drvdata(pdev);
769 int err = 0;
770
771 mutex_lock(&kbc->idev->mutex);
772 if (device_may_wakeup(&pdev->dev)) {
773 disable_irq_wake(kbc->irq);
774 tegra_kbc_setup_wakekeys(kbc, false);
775 /* We will use fifo interrupts for key detection. */
776 tegra_kbc_set_keypress_interrupt(kbc, false);
777
778 /* Restore the resident time of continuous polling mode. */
779 writel(kbc->cp_to_wkup_dly, kbc->mmio + KBC_TO_CNT_0);
780
781 tegra_kbc_set_fifo_interrupt(kbc, true);
782
783 if (kbc->keypress_caused_wake && kbc->wakeup_key) {
784 /*
785 * We can't report events directly from the ISR
786 * because timekeeping is stopped when processing
787 * wakeup request and we get a nasty warning when
788 * we try to call do_gettimeofday() in evdev
789 * handler.
790 */
791 input_report_key(kbc->idev, kbc->wakeup_key, 1);
792 input_sync(kbc->idev);
793 input_report_key(kbc->idev, kbc->wakeup_key, 0);
794 input_sync(kbc->idev);
795 }
796 } else {
797 if (input_device_enabled(kbc->idev))
798 err = tegra_kbc_start(kbc);
799 }
800 mutex_unlock(&kbc->idev->mutex);
801
802 return err;
803}
804
805static DEFINE_SIMPLE_DEV_PM_OPS(tegra_kbc_pm_ops,
806 tegra_kbc_suspend, tegra_kbc_resume);
807
808static struct platform_driver tegra_kbc_driver = {
809 .probe = tegra_kbc_probe,
810 .driver = {
811 .name = "tegra-kbc",
812 .pm = pm_sleep_ptr(&tegra_kbc_pm_ops),
813 .of_match_table = tegra_kbc_of_match,
814 },
815};
816module_platform_driver(tegra_kbc_driver);
817
818MODULE_LICENSE("GPL");
819MODULE_AUTHOR("Rakesh Iyer <riyer@nvidia.com>");
820MODULE_DESCRIPTION("Tegra matrix keyboard controller driver");
821MODULE_ALIAS("platform:tegra-kbc");
1/*
2 * Keyboard class input driver for the NVIDIA Tegra SoC internal matrix
3 * keyboard controller
4 *
5 * Copyright (c) 2009-2011, NVIDIA Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/input.h>
25#include <linux/platform_device.h>
26#include <linux/delay.h>
27#include <linux/io.h>
28#include <linux/interrupt.h>
29#include <linux/clk.h>
30#include <linux/slab.h>
31#include <mach/clk.h>
32#include <mach/kbc.h>
33
34#define KBC_MAX_DEBOUNCE_CNT 0x3ffu
35
36/* KBC row scan time and delay for beginning the row scan. */
37#define KBC_ROW_SCAN_TIME 16
38#define KBC_ROW_SCAN_DLY 5
39
40/* KBC uses a 32KHz clock so a cycle = 1/32Khz */
41#define KBC_CYCLE_MS 32
42
43/* KBC Registers */
44
45/* KBC Control Register */
46#define KBC_CONTROL_0 0x0
47#define KBC_FIFO_TH_CNT_SHIFT(cnt) (cnt << 14)
48#define KBC_DEBOUNCE_CNT_SHIFT(cnt) (cnt << 4)
49#define KBC_CONTROL_FIFO_CNT_INT_EN (1 << 3)
50#define KBC_CONTROL_KBC_EN (1 << 0)
51
52/* KBC Interrupt Register */
53#define KBC_INT_0 0x4
54#define KBC_INT_FIFO_CNT_INT_STATUS (1 << 2)
55
56#define KBC_ROW_CFG0_0 0x8
57#define KBC_COL_CFG0_0 0x18
58#define KBC_INIT_DLY_0 0x28
59#define KBC_RPT_DLY_0 0x2c
60#define KBC_KP_ENT0_0 0x30
61#define KBC_KP_ENT1_0 0x34
62#define KBC_ROW0_MASK_0 0x38
63
64#define KBC_ROW_SHIFT 3
65
66struct tegra_kbc {
67 void __iomem *mmio;
68 struct input_dev *idev;
69 unsigned int irq;
70 spinlock_t lock;
71 unsigned int repoll_dly;
72 unsigned long cp_dly_jiffies;
73 bool use_fn_map;
74 bool use_ghost_filter;
75 const struct tegra_kbc_platform_data *pdata;
76 unsigned short keycode[KBC_MAX_KEY * 2];
77 unsigned short current_keys[KBC_MAX_KPENT];
78 unsigned int num_pressed_keys;
79 struct timer_list timer;
80 struct clk *clk;
81};
82
83static const u32 tegra_kbc_default_keymap[] = {
84 KEY(0, 2, KEY_W),
85 KEY(0, 3, KEY_S),
86 KEY(0, 4, KEY_A),
87 KEY(0, 5, KEY_Z),
88 KEY(0, 7, KEY_FN),
89
90 KEY(1, 7, KEY_LEFTMETA),
91
92 KEY(2, 6, KEY_RIGHTALT),
93 KEY(2, 7, KEY_LEFTALT),
94
95 KEY(3, 0, KEY_5),
96 KEY(3, 1, KEY_4),
97 KEY(3, 2, KEY_R),
98 KEY(3, 3, KEY_E),
99 KEY(3, 4, KEY_F),
100 KEY(3, 5, KEY_D),
101 KEY(3, 6, KEY_X),
102
103 KEY(4, 0, KEY_7),
104 KEY(4, 1, KEY_6),
105 KEY(4, 2, KEY_T),
106 KEY(4, 3, KEY_H),
107 KEY(4, 4, KEY_G),
108 KEY(4, 5, KEY_V),
109 KEY(4, 6, KEY_C),
110 KEY(4, 7, KEY_SPACE),
111
112 KEY(5, 0, KEY_9),
113 KEY(5, 1, KEY_8),
114 KEY(5, 2, KEY_U),
115 KEY(5, 3, KEY_Y),
116 KEY(5, 4, KEY_J),
117 KEY(5, 5, KEY_N),
118 KEY(5, 6, KEY_B),
119 KEY(5, 7, KEY_BACKSLASH),
120
121 KEY(6, 0, KEY_MINUS),
122 KEY(6, 1, KEY_0),
123 KEY(6, 2, KEY_O),
124 KEY(6, 3, KEY_I),
125 KEY(6, 4, KEY_L),
126 KEY(6, 5, KEY_K),
127 KEY(6, 6, KEY_COMMA),
128 KEY(6, 7, KEY_M),
129
130 KEY(7, 1, KEY_EQUAL),
131 KEY(7, 2, KEY_RIGHTBRACE),
132 KEY(7, 3, KEY_ENTER),
133 KEY(7, 7, KEY_MENU),
134
135 KEY(8, 4, KEY_RIGHTSHIFT),
136 KEY(8, 5, KEY_LEFTSHIFT),
137
138 KEY(9, 5, KEY_RIGHTCTRL),
139 KEY(9, 7, KEY_LEFTCTRL),
140
141 KEY(11, 0, KEY_LEFTBRACE),
142 KEY(11, 1, KEY_P),
143 KEY(11, 2, KEY_APOSTROPHE),
144 KEY(11, 3, KEY_SEMICOLON),
145 KEY(11, 4, KEY_SLASH),
146 KEY(11, 5, KEY_DOT),
147
148 KEY(12, 0, KEY_F10),
149 KEY(12, 1, KEY_F9),
150 KEY(12, 2, KEY_BACKSPACE),
151 KEY(12, 3, KEY_3),
152 KEY(12, 4, KEY_2),
153 KEY(12, 5, KEY_UP),
154 KEY(12, 6, KEY_PRINT),
155 KEY(12, 7, KEY_PAUSE),
156
157 KEY(13, 0, KEY_INSERT),
158 KEY(13, 1, KEY_DELETE),
159 KEY(13, 3, KEY_PAGEUP),
160 KEY(13, 4, KEY_PAGEDOWN),
161 KEY(13, 5, KEY_RIGHT),
162 KEY(13, 6, KEY_DOWN),
163 KEY(13, 7, KEY_LEFT),
164
165 KEY(14, 0, KEY_F11),
166 KEY(14, 1, KEY_F12),
167 KEY(14, 2, KEY_F8),
168 KEY(14, 3, KEY_Q),
169 KEY(14, 4, KEY_F4),
170 KEY(14, 5, KEY_F3),
171 KEY(14, 6, KEY_1),
172 KEY(14, 7, KEY_F7),
173
174 KEY(15, 0, KEY_ESC),
175 KEY(15, 1, KEY_GRAVE),
176 KEY(15, 2, KEY_F5),
177 KEY(15, 3, KEY_TAB),
178 KEY(15, 4, KEY_F1),
179 KEY(15, 5, KEY_F2),
180 KEY(15, 6, KEY_CAPSLOCK),
181 KEY(15, 7, KEY_F6),
182
183 /* Software Handled Function Keys */
184 KEY(20, 0, KEY_KP7),
185
186 KEY(21, 0, KEY_KP9),
187 KEY(21, 1, KEY_KP8),
188 KEY(21, 2, KEY_KP4),
189 KEY(21, 4, KEY_KP1),
190
191 KEY(22, 1, KEY_KPSLASH),
192 KEY(22, 2, KEY_KP6),
193 KEY(22, 3, KEY_KP5),
194 KEY(22, 4, KEY_KP3),
195 KEY(22, 5, KEY_KP2),
196 KEY(22, 7, KEY_KP0),
197
198 KEY(27, 1, KEY_KPASTERISK),
199 KEY(27, 3, KEY_KPMINUS),
200 KEY(27, 4, KEY_KPPLUS),
201 KEY(27, 5, KEY_KPDOT),
202
203 KEY(28, 5, KEY_VOLUMEUP),
204
205 KEY(29, 3, KEY_HOME),
206 KEY(29, 4, KEY_END),
207 KEY(29, 5, KEY_BRIGHTNESSDOWN),
208 KEY(29, 6, KEY_VOLUMEDOWN),
209 KEY(29, 7, KEY_BRIGHTNESSUP),
210
211 KEY(30, 0, KEY_NUMLOCK),
212 KEY(30, 1, KEY_SCROLLLOCK),
213 KEY(30, 2, KEY_MUTE),
214
215 KEY(31, 4, KEY_HELP),
216};
217
218static const struct matrix_keymap_data tegra_kbc_default_keymap_data = {
219 .keymap = tegra_kbc_default_keymap,
220 .keymap_size = ARRAY_SIZE(tegra_kbc_default_keymap),
221};
222
223static void tegra_kbc_report_released_keys(struct input_dev *input,
224 unsigned short old_keycodes[],
225 unsigned int old_num_keys,
226 unsigned short new_keycodes[],
227 unsigned int new_num_keys)
228{
229 unsigned int i, j;
230
231 for (i = 0; i < old_num_keys; i++) {
232 for (j = 0; j < new_num_keys; j++)
233 if (old_keycodes[i] == new_keycodes[j])
234 break;
235
236 if (j == new_num_keys)
237 input_report_key(input, old_keycodes[i], 0);
238 }
239}
240
241static void tegra_kbc_report_pressed_keys(struct input_dev *input,
242 unsigned char scancodes[],
243 unsigned short keycodes[],
244 unsigned int num_pressed_keys)
245{
246 unsigned int i;
247
248 for (i = 0; i < num_pressed_keys; i++) {
249 input_event(input, EV_MSC, MSC_SCAN, scancodes[i]);
250 input_report_key(input, keycodes[i], 1);
251 }
252}
253
254static void tegra_kbc_report_keys(struct tegra_kbc *kbc)
255{
256 unsigned char scancodes[KBC_MAX_KPENT];
257 unsigned short keycodes[KBC_MAX_KPENT];
258 u32 val = 0;
259 unsigned int i;
260 unsigned int num_down = 0;
261 unsigned long flags;
262 bool fn_keypress = false;
263 bool key_in_same_row = false;
264 bool key_in_same_col = false;
265
266 spin_lock_irqsave(&kbc->lock, flags);
267 for (i = 0; i < KBC_MAX_KPENT; i++) {
268 if ((i % 4) == 0)
269 val = readl(kbc->mmio + KBC_KP_ENT0_0 + i);
270
271 if (val & 0x80) {
272 unsigned int col = val & 0x07;
273 unsigned int row = (val >> 3) & 0x0f;
274 unsigned char scancode =
275 MATRIX_SCAN_CODE(row, col, KBC_ROW_SHIFT);
276
277 scancodes[num_down] = scancode;
278 keycodes[num_down] = kbc->keycode[scancode];
279 /* If driver uses Fn map, do not report the Fn key. */
280 if ((keycodes[num_down] == KEY_FN) && kbc->use_fn_map)
281 fn_keypress = true;
282 else
283 num_down++;
284 }
285
286 val >>= 8;
287 }
288
289 /*
290 * Matrix keyboard designs are prone to keyboard ghosting.
291 * Ghosting occurs if there are 3 keys such that -
292 * any 2 of the 3 keys share a row, and any 2 of them share a column.
293 * If so ignore the key presses for this iteration.
294 */
295 if ((kbc->use_ghost_filter) && (num_down >= 3)) {
296 for (i = 0; i < num_down; i++) {
297 unsigned int j;
298 u8 curr_col = scancodes[i] & 0x07;
299 u8 curr_row = scancodes[i] >> KBC_ROW_SHIFT;
300
301 /*
302 * Find 2 keys such that one key is in the same row
303 * and the other is in the same column as the i-th key.
304 */
305 for (j = i + 1; j < num_down; j++) {
306 u8 col = scancodes[j] & 0x07;
307 u8 row = scancodes[j] >> KBC_ROW_SHIFT;
308
309 if (col == curr_col)
310 key_in_same_col = true;
311 if (row == curr_row)
312 key_in_same_row = true;
313 }
314 }
315 }
316
317 /*
318 * If the platform uses Fn keymaps, translate keys on a Fn keypress.
319 * Function keycodes are KBC_MAX_KEY apart from the plain keycodes.
320 */
321 if (fn_keypress) {
322 for (i = 0; i < num_down; i++) {
323 scancodes[i] += KBC_MAX_KEY;
324 keycodes[i] = kbc->keycode[scancodes[i]];
325 }
326 }
327
328 spin_unlock_irqrestore(&kbc->lock, flags);
329
330 /* Ignore the key presses for this iteration? */
331 if (key_in_same_col && key_in_same_row)
332 return;
333
334 tegra_kbc_report_released_keys(kbc->idev,
335 kbc->current_keys, kbc->num_pressed_keys,
336 keycodes, num_down);
337 tegra_kbc_report_pressed_keys(kbc->idev, scancodes, keycodes, num_down);
338 input_sync(kbc->idev);
339
340 memcpy(kbc->current_keys, keycodes, sizeof(kbc->current_keys));
341 kbc->num_pressed_keys = num_down;
342}
343
344static void tegra_kbc_keypress_timer(unsigned long data)
345{
346 struct tegra_kbc *kbc = (struct tegra_kbc *)data;
347 unsigned long flags;
348 u32 val;
349 unsigned int i;
350
351 val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf;
352 if (val) {
353 unsigned long dly;
354
355 tegra_kbc_report_keys(kbc);
356
357 /*
358 * If more than one keys are pressed we need not wait
359 * for the repoll delay.
360 */
361 dly = (val == 1) ? kbc->repoll_dly : 1;
362 mod_timer(&kbc->timer, jiffies + msecs_to_jiffies(dly));
363 } else {
364 /* Release any pressed keys and exit the polling loop */
365 for (i = 0; i < kbc->num_pressed_keys; i++)
366 input_report_key(kbc->idev, kbc->current_keys[i], 0);
367 input_sync(kbc->idev);
368
369 kbc->num_pressed_keys = 0;
370
371 /* All keys are released so enable the keypress interrupt */
372 spin_lock_irqsave(&kbc->lock, flags);
373 val = readl(kbc->mmio + KBC_CONTROL_0);
374 val |= KBC_CONTROL_FIFO_CNT_INT_EN;
375 writel(val, kbc->mmio + KBC_CONTROL_0);
376 spin_unlock_irqrestore(&kbc->lock, flags);
377 }
378}
379
380static irqreturn_t tegra_kbc_isr(int irq, void *args)
381{
382 struct tegra_kbc *kbc = args;
383 u32 val, ctl;
384
385 /*
386 * Until all keys are released, defer further processing to
387 * the polling loop in tegra_kbc_keypress_timer
388 */
389 ctl = readl(kbc->mmio + KBC_CONTROL_0);
390 ctl &= ~KBC_CONTROL_FIFO_CNT_INT_EN;
391 writel(ctl, kbc->mmio + KBC_CONTROL_0);
392
393 /*
394 * Quickly bail out & reenable interrupts if the fifo threshold
395 * count interrupt wasn't the interrupt source
396 */
397 val = readl(kbc->mmio + KBC_INT_0);
398 writel(val, kbc->mmio + KBC_INT_0);
399
400 if (val & KBC_INT_FIFO_CNT_INT_STATUS) {
401 /*
402 * Schedule timer to run when hardware is in continuous
403 * polling mode.
404 */
405 mod_timer(&kbc->timer, jiffies + kbc->cp_dly_jiffies);
406 } else {
407 ctl |= KBC_CONTROL_FIFO_CNT_INT_EN;
408 writel(ctl, kbc->mmio + KBC_CONTROL_0);
409 }
410
411 return IRQ_HANDLED;
412}
413
414static void tegra_kbc_setup_wakekeys(struct tegra_kbc *kbc, bool filter)
415{
416 const struct tegra_kbc_platform_data *pdata = kbc->pdata;
417 int i;
418 unsigned int rst_val;
419
420 /* Either mask all keys or none. */
421 rst_val = (filter && !pdata->wakeup) ? ~0 : 0;
422
423 for (i = 0; i < KBC_MAX_ROW; i++)
424 writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4);
425}
426
427static void tegra_kbc_config_pins(struct tegra_kbc *kbc)
428{
429 const struct tegra_kbc_platform_data *pdata = kbc->pdata;
430 int i;
431
432 for (i = 0; i < KBC_MAX_GPIO; i++) {
433 u32 r_shft = 5 * (i % 6);
434 u32 c_shft = 4 * (i % 8);
435 u32 r_mask = 0x1f << r_shft;
436 u32 c_mask = 0x0f << c_shft;
437 u32 r_offs = (i / 6) * 4 + KBC_ROW_CFG0_0;
438 u32 c_offs = (i / 8) * 4 + KBC_COL_CFG0_0;
439 u32 row_cfg = readl(kbc->mmio + r_offs);
440 u32 col_cfg = readl(kbc->mmio + c_offs);
441
442 row_cfg &= ~r_mask;
443 col_cfg &= ~c_mask;
444
445 if (pdata->pin_cfg[i].is_row)
446 row_cfg |= ((pdata->pin_cfg[i].num << 1) | 1) << r_shft;
447 else
448 col_cfg |= ((pdata->pin_cfg[i].num << 1) | 1) << c_shft;
449
450 writel(row_cfg, kbc->mmio + r_offs);
451 writel(col_cfg, kbc->mmio + c_offs);
452 }
453}
454
455static int tegra_kbc_start(struct tegra_kbc *kbc)
456{
457 const struct tegra_kbc_platform_data *pdata = kbc->pdata;
458 unsigned long flags;
459 unsigned int debounce_cnt;
460 u32 val = 0;
461
462 clk_enable(kbc->clk);
463
464 /* Reset the KBC controller to clear all previous status.*/
465 tegra_periph_reset_assert(kbc->clk);
466 udelay(100);
467 tegra_periph_reset_deassert(kbc->clk);
468 udelay(100);
469
470 tegra_kbc_config_pins(kbc);
471 tegra_kbc_setup_wakekeys(kbc, false);
472
473 writel(pdata->repeat_cnt, kbc->mmio + KBC_RPT_DLY_0);
474
475 /* Keyboard debounce count is maximum of 12 bits. */
476 debounce_cnt = min(pdata->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
477 val = KBC_DEBOUNCE_CNT_SHIFT(debounce_cnt);
478 val |= KBC_FIFO_TH_CNT_SHIFT(1); /* set fifo interrupt threshold to 1 */
479 val |= KBC_CONTROL_FIFO_CNT_INT_EN; /* interrupt on FIFO threshold */
480 val |= KBC_CONTROL_KBC_EN; /* enable */
481 writel(val, kbc->mmio + KBC_CONTROL_0);
482
483 /*
484 * Compute the delay(ns) from interrupt mode to continuous polling
485 * mode so the timer routine is scheduled appropriately.
486 */
487 val = readl(kbc->mmio + KBC_INIT_DLY_0);
488 kbc->cp_dly_jiffies = usecs_to_jiffies((val & 0xfffff) * 32);
489
490 kbc->num_pressed_keys = 0;
491
492 /*
493 * Atomically clear out any remaining entries in the key FIFO
494 * and enable keyboard interrupts.
495 */
496 spin_lock_irqsave(&kbc->lock, flags);
497 while (1) {
498 val = readl(kbc->mmio + KBC_INT_0);
499 val >>= 4;
500 if (!val)
501 break;
502
503 val = readl(kbc->mmio + KBC_KP_ENT0_0);
504 val = readl(kbc->mmio + KBC_KP_ENT1_0);
505 }
506 writel(0x7, kbc->mmio + KBC_INT_0);
507 spin_unlock_irqrestore(&kbc->lock, flags);
508
509 enable_irq(kbc->irq);
510
511 return 0;
512}
513
514static void tegra_kbc_stop(struct tegra_kbc *kbc)
515{
516 unsigned long flags;
517 u32 val;
518
519 spin_lock_irqsave(&kbc->lock, flags);
520 val = readl(kbc->mmio + KBC_CONTROL_0);
521 val &= ~1;
522 writel(val, kbc->mmio + KBC_CONTROL_0);
523 spin_unlock_irqrestore(&kbc->lock, flags);
524
525 disable_irq(kbc->irq);
526 del_timer_sync(&kbc->timer);
527
528 clk_disable(kbc->clk);
529}
530
531static int tegra_kbc_open(struct input_dev *dev)
532{
533 struct tegra_kbc *kbc = input_get_drvdata(dev);
534
535 return tegra_kbc_start(kbc);
536}
537
538static void tegra_kbc_close(struct input_dev *dev)
539{
540 struct tegra_kbc *kbc = input_get_drvdata(dev);
541
542 return tegra_kbc_stop(kbc);
543}
544
545static bool __devinit
546tegra_kbc_check_pin_cfg(const struct tegra_kbc_platform_data *pdata,
547 struct device *dev, unsigned int *num_rows)
548{
549 int i;
550
551 *num_rows = 0;
552
553 for (i = 0; i < KBC_MAX_GPIO; i++) {
554 const struct tegra_kbc_pin_cfg *pin_cfg = &pdata->pin_cfg[i];
555
556 if (pin_cfg->is_row) {
557 if (pin_cfg->num >= KBC_MAX_ROW) {
558 dev_err(dev,
559 "pin_cfg[%d]: invalid row number %d\n",
560 i, pin_cfg->num);
561 return false;
562 }
563 (*num_rows)++;
564 } else {
565 if (pin_cfg->num >= KBC_MAX_COL) {
566 dev_err(dev,
567 "pin_cfg[%d]: invalid column number %d\n",
568 i, pin_cfg->num);
569 return false;
570 }
571 }
572 }
573
574 return true;
575}
576
577static int __devinit tegra_kbc_probe(struct platform_device *pdev)
578{
579 const struct tegra_kbc_platform_data *pdata = pdev->dev.platform_data;
580 const struct matrix_keymap_data *keymap_data;
581 struct tegra_kbc *kbc;
582 struct input_dev *input_dev;
583 struct resource *res;
584 int irq;
585 int err;
586 int num_rows = 0;
587 unsigned int debounce_cnt;
588 unsigned int scan_time_rows;
589
590 if (!pdata)
591 return -EINVAL;
592
593 if (!tegra_kbc_check_pin_cfg(pdata, &pdev->dev, &num_rows))
594 return -EINVAL;
595
596 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
597 if (!res) {
598 dev_err(&pdev->dev, "failed to get I/O memory\n");
599 return -ENXIO;
600 }
601
602 irq = platform_get_irq(pdev, 0);
603 if (irq < 0) {
604 dev_err(&pdev->dev, "failed to get keyboard IRQ\n");
605 return -ENXIO;
606 }
607
608 kbc = kzalloc(sizeof(*kbc), GFP_KERNEL);
609 input_dev = input_allocate_device();
610 if (!kbc || !input_dev) {
611 err = -ENOMEM;
612 goto err_free_mem;
613 }
614
615 kbc->pdata = pdata;
616 kbc->idev = input_dev;
617 kbc->irq = irq;
618 spin_lock_init(&kbc->lock);
619 setup_timer(&kbc->timer, tegra_kbc_keypress_timer, (unsigned long)kbc);
620
621 res = request_mem_region(res->start, resource_size(res), pdev->name);
622 if (!res) {
623 dev_err(&pdev->dev, "failed to request I/O memory\n");
624 err = -EBUSY;
625 goto err_free_mem;
626 }
627
628 kbc->mmio = ioremap(res->start, resource_size(res));
629 if (!kbc->mmio) {
630 dev_err(&pdev->dev, "failed to remap I/O memory\n");
631 err = -ENXIO;
632 goto err_free_mem_region;
633 }
634
635 kbc->clk = clk_get(&pdev->dev, NULL);
636 if (IS_ERR(kbc->clk)) {
637 dev_err(&pdev->dev, "failed to get keyboard clock\n");
638 err = PTR_ERR(kbc->clk);
639 goto err_iounmap;
640 }
641
642 /*
643 * The time delay between two consecutive reads of the FIFO is
644 * the sum of the repeat time and the time taken for scanning
645 * the rows. There is an additional delay before the row scanning
646 * starts. The repoll delay is computed in milliseconds.
647 */
648 debounce_cnt = min(pdata->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
649 scan_time_rows = (KBC_ROW_SCAN_TIME + debounce_cnt) * num_rows;
650 kbc->repoll_dly = KBC_ROW_SCAN_DLY + scan_time_rows + pdata->repeat_cnt;
651 kbc->repoll_dly = DIV_ROUND_UP(kbc->repoll_dly, KBC_CYCLE_MS);
652
653 input_dev->name = pdev->name;
654 input_dev->id.bustype = BUS_HOST;
655 input_dev->dev.parent = &pdev->dev;
656 input_dev->open = tegra_kbc_open;
657 input_dev->close = tegra_kbc_close;
658
659 input_set_drvdata(input_dev, kbc);
660
661 input_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_REP);
662 input_set_capability(input_dev, EV_MSC, MSC_SCAN);
663
664 input_dev->keycode = kbc->keycode;
665 input_dev->keycodesize = sizeof(kbc->keycode[0]);
666 input_dev->keycodemax = KBC_MAX_KEY;
667 if (pdata->use_fn_map)
668 input_dev->keycodemax *= 2;
669
670 kbc->use_fn_map = pdata->use_fn_map;
671 kbc->use_ghost_filter = pdata->use_ghost_filter;
672 keymap_data = pdata->keymap_data ?: &tegra_kbc_default_keymap_data;
673 matrix_keypad_build_keymap(keymap_data, KBC_ROW_SHIFT,
674 input_dev->keycode, input_dev->keybit);
675
676 err = request_irq(kbc->irq, tegra_kbc_isr, IRQF_TRIGGER_HIGH,
677 pdev->name, kbc);
678 if (err) {
679 dev_err(&pdev->dev, "failed to request keyboard IRQ\n");
680 goto err_put_clk;
681 }
682
683 disable_irq(kbc->irq);
684
685 err = input_register_device(kbc->idev);
686 if (err) {
687 dev_err(&pdev->dev, "failed to register input device\n");
688 goto err_free_irq;
689 }
690
691 platform_set_drvdata(pdev, kbc);
692 device_init_wakeup(&pdev->dev, pdata->wakeup);
693
694 return 0;
695
696err_free_irq:
697 free_irq(kbc->irq, pdev);
698err_put_clk:
699 clk_put(kbc->clk);
700err_iounmap:
701 iounmap(kbc->mmio);
702err_free_mem_region:
703 release_mem_region(res->start, resource_size(res));
704err_free_mem:
705 input_free_device(input_dev);
706 kfree(kbc);
707
708 return err;
709}
710
711static int __devexit tegra_kbc_remove(struct platform_device *pdev)
712{
713 struct tegra_kbc *kbc = platform_get_drvdata(pdev);
714 struct resource *res;
715
716 free_irq(kbc->irq, pdev);
717 clk_put(kbc->clk);
718
719 input_unregister_device(kbc->idev);
720 iounmap(kbc->mmio);
721 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
722 release_mem_region(res->start, resource_size(res));
723
724 kfree(kbc);
725
726 platform_set_drvdata(pdev, NULL);
727
728 return 0;
729}
730
731#ifdef CONFIG_PM_SLEEP
732static int tegra_kbc_suspend(struct device *dev)
733{
734 struct platform_device *pdev = to_platform_device(dev);
735 struct tegra_kbc *kbc = platform_get_drvdata(pdev);
736
737 if (device_may_wakeup(&pdev->dev)) {
738 tegra_kbc_setup_wakekeys(kbc, true);
739 enable_irq_wake(kbc->irq);
740 /* Forcefully clear the interrupt status */
741 writel(0x7, kbc->mmio + KBC_INT_0);
742 msleep(30);
743 } else {
744 mutex_lock(&kbc->idev->mutex);
745 if (kbc->idev->users)
746 tegra_kbc_stop(kbc);
747 mutex_unlock(&kbc->idev->mutex);
748 }
749
750 return 0;
751}
752
753static int tegra_kbc_resume(struct device *dev)
754{
755 struct platform_device *pdev = to_platform_device(dev);
756 struct tegra_kbc *kbc = platform_get_drvdata(pdev);
757 int err = 0;
758
759 if (device_may_wakeup(&pdev->dev)) {
760 disable_irq_wake(kbc->irq);
761 tegra_kbc_setup_wakekeys(kbc, false);
762 } else {
763 mutex_lock(&kbc->idev->mutex);
764 if (kbc->idev->users)
765 err = tegra_kbc_start(kbc);
766 mutex_unlock(&kbc->idev->mutex);
767 }
768
769 return err;
770}
771#endif
772
773static SIMPLE_DEV_PM_OPS(tegra_kbc_pm_ops, tegra_kbc_suspend, tegra_kbc_resume);
774
775static struct platform_driver tegra_kbc_driver = {
776 .probe = tegra_kbc_probe,
777 .remove = __devexit_p(tegra_kbc_remove),
778 .driver = {
779 .name = "tegra-kbc",
780 .owner = THIS_MODULE,
781 .pm = &tegra_kbc_pm_ops,
782 },
783};
784
785static void __exit tegra_kbc_exit(void)
786{
787 platform_driver_unregister(&tegra_kbc_driver);
788}
789module_exit(tegra_kbc_exit);
790
791static int __init tegra_kbc_init(void)
792{
793 return platform_driver_register(&tegra_kbc_driver);
794}
795module_init(tegra_kbc_init);
796
797MODULE_LICENSE("GPL");
798MODULE_AUTHOR("Rakesh Iyer <riyer@nvidia.com>");
799MODULE_DESCRIPTION("Tegra matrix keyboard controller driver");
800MODULE_ALIAS("platform:tegra-kbc");