1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Intel MID platform setup code
  4 *
  5 * (C) Copyright 2008, 2012, 2021 Intel Corporation
  6 * Author: Jacob Pan (jacob.jun.pan@intel.com)
  7 * Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>
  8 */
  9
 10#define pr_fmt(fmt) "intel_mid: " fmt
 11
 12#include <linux/init.h>
 13#include <linux/kernel.h>
 14#include <linux/interrupt.h>
 15#include <linux/regulator/machine.h>
 16#include <linux/scatterlist.h>
 17#include <linux/irq.h>
 18#include <linux/export.h>
 19#include <linux/notifier.h>
 20
 21#include <asm/setup.h>
 22#include <asm/mpspec_def.h>
 23#include <asm/hw_irq.h>
 24#include <asm/apic.h>
 25#include <asm/io_apic.h>
 26#include <asm/intel-mid.h>
 27#include <asm/io.h>
 28#include <asm/i8259.h>
 29#include <asm/intel_scu_ipc.h>
 30#include <asm/reboot.h>
 31
 32#define IPCMSG_COLD_OFF		0x80	/* Only for Tangier */
 33#define IPCMSG_COLD_RESET	0xF1
 34
 35static void intel_mid_power_off(void)
 36{
 37	/* Shut down South Complex via PWRMU */
 38	intel_mid_pwr_power_off();
 39
 40	/* Only for Tangier, the rest will ignore this command */
 41	intel_scu_ipc_dev_simple_command(NULL, IPCMSG_COLD_OFF, 1);
 42};
 43
 44static void intel_mid_reboot(void)
 45{
 46	intel_scu_ipc_dev_simple_command(NULL, IPCMSG_COLD_RESET, 0);
 47}
 48
 49static void __init intel_mid_time_init(void)
 50{
 51	/* Lapic only, no apbt */
 52	x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
 53	x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
 54}
 55
 56static void intel_mid_arch_setup(void)
 57{
 58	switch (boot_cpu_data.x86_model) {
 59	case 0x3C:
 60	case 0x4A:
 61		x86_platform.legacy.rtc = 1;
 62		break;
 63	default:
 64		break;
 65	}
 66
 67	/*
 68	 * Intel MID platforms are using explicitly defined regulators.
 69	 *
 70	 * Let the regulator core know that we do not have any additional
 71	 * regulators left. This lets it substitute unprovided regulators with
 72	 * dummy ones:
 73	 */
 74	regulator_has_full_constraints();
 75}
 76
 77/*
 78 * Moorestown does not have external NMI source nor port 0x61 to report
 79 * NMI status. The possible NMI sources are from pmu as a result of NMI
 80 * watchdog or lock debug. Reading io port 0x61 results in 0xff which
 81 * misled NMI handler.
 82 */
 83static unsigned char intel_mid_get_nmi_reason(void)
 84{
 85	return 0;
 86}
 87
 88/*
 89 * Moorestown specific x86_init function overrides and early setup
 90 * calls.
 91 */
 92void __init x86_intel_mid_early_setup(void)
 93{
 94	x86_init.resources.probe_roms = x86_init_noop;
 95	x86_init.resources.reserve_resources = x86_init_noop;
 96
 97	x86_init.timers.timer_init = intel_mid_time_init;
 98	x86_init.timers.setup_percpu_clockev = x86_init_noop;
 99
100	x86_init.irqs.pre_vector_init = x86_init_noop;
101
102	x86_init.oem.arch_setup = intel_mid_arch_setup;
103
104	x86_platform.get_nmi_reason = intel_mid_get_nmi_reason;
105
106	x86_init.pci.arch_init = intel_mid_pci_init;
107	x86_init.pci.fixup_irqs = x86_init_noop;
108
109	legacy_pic = &null_legacy_pic;
110
111	/*
112	 * Do nothing for now as everything needed done in
113	 * x86_intel_mid_early_setup() below.
114	 */
115	x86_init.acpi.reduced_hw_early_init = x86_init_noop;
116
117	pm_power_off = intel_mid_power_off;
118	machine_ops.emergency_restart  = intel_mid_reboot;
119
120	/* Avoid searching for BIOS MP tables */
121	x86_init.mpparse.find_smp_config = x86_init_noop;
122	x86_init.mpparse.get_smp_config = x86_init_uint_noop;
123	set_bit(MP_BUS_ISA, mp_bus_not_pci);
124}