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1/*
2 * Copyright (C) 2001 MandrakeSoft S.A.
3 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
4 *
5 * MandrakeSoft S.A.
6 * 43, rue d'Aboukir
7 * 75002 Paris - France
8 * http://www.linux-mandrake.com/
9 * http://www.mandrakesoft.com/
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with this library; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * Yunhong Jiang <yunhong.jiang@intel.com>
26 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
27 * Based on Xen 3.1 code.
28 */
29
30#include <linux/kvm_host.h>
31#include <linux/kvm.h>
32#include <linux/mm.h>
33#include <linux/highmem.h>
34#include <linux/smp.h>
35#include <linux/hrtimer.h>
36#include <linux/io.h>
37#include <linux/slab.h>
38#include <linux/export.h>
39#include <linux/nospec.h>
40#include <asm/processor.h>
41#include <asm/page.h>
42#include <asm/current.h>
43#include <trace/events/kvm.h>
44
45#include "ioapic.h"
46#include "lapic.h"
47#include "irq.h"
48
49static int ioapic_service(struct kvm_ioapic *vioapic, int irq,
50 bool line_status);
51
52static void kvm_ioapic_update_eoi_one(struct kvm_vcpu *vcpu,
53 struct kvm_ioapic *ioapic,
54 int trigger_mode,
55 int pin);
56
57static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic)
58{
59 unsigned long result = 0;
60
61 switch (ioapic->ioregsel) {
62 case IOAPIC_REG_VERSION:
63 result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
64 | (IOAPIC_VERSION_ID & 0xff));
65 break;
66
67 case IOAPIC_REG_APIC_ID:
68 case IOAPIC_REG_ARB_ID:
69 result = ((ioapic->id & 0xf) << 24);
70 break;
71
72 default:
73 {
74 u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
75 u64 redir_content = ~0ULL;
76
77 if (redir_index < IOAPIC_NUM_PINS) {
78 u32 index = array_index_nospec(
79 redir_index, IOAPIC_NUM_PINS);
80
81 redir_content = ioapic->redirtbl[index].bits;
82 }
83
84 result = (ioapic->ioregsel & 0x1) ?
85 (redir_content >> 32) & 0xffffffff :
86 redir_content & 0xffffffff;
87 break;
88 }
89 }
90
91 return result;
92}
93
94static void rtc_irq_eoi_tracking_reset(struct kvm_ioapic *ioapic)
95{
96 ioapic->rtc_status.pending_eoi = 0;
97 bitmap_zero(ioapic->rtc_status.dest_map.map, KVM_MAX_VCPU_IDS);
98}
99
100static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic);
101
102static void rtc_status_pending_eoi_check_valid(struct kvm_ioapic *ioapic)
103{
104 if (WARN_ON(ioapic->rtc_status.pending_eoi < 0))
105 kvm_rtc_eoi_tracking_restore_all(ioapic);
106}
107
108static void __rtc_irq_eoi_tracking_restore_one(struct kvm_vcpu *vcpu)
109{
110 bool new_val, old_val;
111 struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
112 struct dest_map *dest_map = &ioapic->rtc_status.dest_map;
113 union kvm_ioapic_redirect_entry *e;
114
115 e = &ioapic->redirtbl[RTC_GSI];
116 if (!kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT,
117 e->fields.dest_id,
118 kvm_lapic_irq_dest_mode(!!e->fields.dest_mode)))
119 return;
120
121 new_val = kvm_apic_pending_eoi(vcpu, e->fields.vector);
122 old_val = test_bit(vcpu->vcpu_id, dest_map->map);
123
124 if (new_val == old_val)
125 return;
126
127 if (new_val) {
128 __set_bit(vcpu->vcpu_id, dest_map->map);
129 dest_map->vectors[vcpu->vcpu_id] = e->fields.vector;
130 ioapic->rtc_status.pending_eoi++;
131 } else {
132 __clear_bit(vcpu->vcpu_id, dest_map->map);
133 ioapic->rtc_status.pending_eoi--;
134 rtc_status_pending_eoi_check_valid(ioapic);
135 }
136}
137
138void kvm_rtc_eoi_tracking_restore_one(struct kvm_vcpu *vcpu)
139{
140 struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
141
142 spin_lock(&ioapic->lock);
143 __rtc_irq_eoi_tracking_restore_one(vcpu);
144 spin_unlock(&ioapic->lock);
145}
146
147static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic)
148{
149 struct kvm_vcpu *vcpu;
150 unsigned long i;
151
152 if (RTC_GSI >= IOAPIC_NUM_PINS)
153 return;
154
155 rtc_irq_eoi_tracking_reset(ioapic);
156 kvm_for_each_vcpu(i, vcpu, ioapic->kvm)
157 __rtc_irq_eoi_tracking_restore_one(vcpu);
158}
159
160static void rtc_irq_eoi(struct kvm_ioapic *ioapic, struct kvm_vcpu *vcpu,
161 int vector)
162{
163 struct dest_map *dest_map = &ioapic->rtc_status.dest_map;
164
165 /* RTC special handling */
166 if (test_bit(vcpu->vcpu_id, dest_map->map) &&
167 (vector == dest_map->vectors[vcpu->vcpu_id]) &&
168 (test_and_clear_bit(vcpu->vcpu_id,
169 ioapic->rtc_status.dest_map.map))) {
170 --ioapic->rtc_status.pending_eoi;
171 rtc_status_pending_eoi_check_valid(ioapic);
172 }
173}
174
175static bool rtc_irq_check_coalesced(struct kvm_ioapic *ioapic)
176{
177 if (ioapic->rtc_status.pending_eoi > 0)
178 return true; /* coalesced */
179
180 return false;
181}
182
183static void ioapic_lazy_update_eoi(struct kvm_ioapic *ioapic, int irq)
184{
185 unsigned long i;
186 struct kvm_vcpu *vcpu;
187 union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
188
189 kvm_for_each_vcpu(i, vcpu, ioapic->kvm) {
190 if (!kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT,
191 entry->fields.dest_id,
192 entry->fields.dest_mode) ||
193 kvm_apic_pending_eoi(vcpu, entry->fields.vector))
194 continue;
195
196 /*
197 * If no longer has pending EOI in LAPICs, update
198 * EOI for this vector.
199 */
200 rtc_irq_eoi(ioapic, vcpu, entry->fields.vector);
201 break;
202 }
203}
204
205static int ioapic_set_irq(struct kvm_ioapic *ioapic, unsigned int irq,
206 int irq_level, bool line_status)
207{
208 union kvm_ioapic_redirect_entry entry;
209 u32 mask = 1 << irq;
210 u32 old_irr;
211 int edge, ret;
212
213 entry = ioapic->redirtbl[irq];
214 edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
215
216 if (!irq_level) {
217 ioapic->irr &= ~mask;
218 ret = 1;
219 goto out;
220 }
221
222 /*
223 * AMD SVM AVIC accelerate EOI write iff the interrupt is edge
224 * triggered, in which case the in-kernel IOAPIC will not be able
225 * to receive the EOI. In this case, we do a lazy update of the
226 * pending EOI when trying to set IOAPIC irq.
227 */
228 if (edge && kvm_apicv_activated(ioapic->kvm))
229 ioapic_lazy_update_eoi(ioapic, irq);
230
231 /*
232 * Return 0 for coalesced interrupts; for edge-triggered interrupts,
233 * this only happens if a previous edge has not been delivered due
234 * to masking. For level interrupts, the remote_irr field tells
235 * us if the interrupt is waiting for an EOI.
236 *
237 * RTC is special: it is edge-triggered, but userspace likes to know
238 * if it has been already ack-ed via EOI because coalesced RTC
239 * interrupts lead to time drift in Windows guests. So we track
240 * EOI manually for the RTC interrupt.
241 */
242 if (irq == RTC_GSI && line_status &&
243 rtc_irq_check_coalesced(ioapic)) {
244 ret = 0;
245 goto out;
246 }
247
248 old_irr = ioapic->irr;
249 ioapic->irr |= mask;
250 if (edge) {
251 ioapic->irr_delivered &= ~mask;
252 if (old_irr == ioapic->irr) {
253 ret = 0;
254 goto out;
255 }
256 }
257
258 ret = ioapic_service(ioapic, irq, line_status);
259
260out:
261 trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
262 return ret;
263}
264
265static void kvm_ioapic_inject_all(struct kvm_ioapic *ioapic, unsigned long irr)
266{
267 u32 idx;
268
269 rtc_irq_eoi_tracking_reset(ioapic);
270 for_each_set_bit(idx, &irr, IOAPIC_NUM_PINS)
271 ioapic_set_irq(ioapic, idx, 1, true);
272
273 kvm_rtc_eoi_tracking_restore_all(ioapic);
274}
275
276
277void kvm_ioapic_scan_entry(struct kvm_vcpu *vcpu, ulong *ioapic_handled_vectors)
278{
279 struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
280 struct dest_map *dest_map = &ioapic->rtc_status.dest_map;
281 union kvm_ioapic_redirect_entry *e;
282 int index;
283
284 spin_lock(&ioapic->lock);
285
286 /* Make sure we see any missing RTC EOI */
287 if (test_bit(vcpu->vcpu_id, dest_map->map))
288 __set_bit(dest_map->vectors[vcpu->vcpu_id],
289 ioapic_handled_vectors);
290
291 for (index = 0; index < IOAPIC_NUM_PINS; index++) {
292 e = &ioapic->redirtbl[index];
293 if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG ||
294 kvm_irq_has_notifier(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index) ||
295 index == RTC_GSI) {
296 u16 dm = kvm_lapic_irq_dest_mode(!!e->fields.dest_mode);
297
298 if (kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT,
299 e->fields.dest_id, dm) ||
300 kvm_apic_pending_eoi(vcpu, e->fields.vector))
301 __set_bit(e->fields.vector,
302 ioapic_handled_vectors);
303 }
304 }
305 spin_unlock(&ioapic->lock);
306}
307
308void kvm_arch_post_irq_ack_notifier_list_update(struct kvm *kvm)
309{
310 if (!ioapic_in_kernel(kvm))
311 return;
312 kvm_make_scan_ioapic_request(kvm);
313}
314
315static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
316{
317 unsigned index;
318 bool mask_before, mask_after;
319 union kvm_ioapic_redirect_entry *e;
320 int old_remote_irr, old_delivery_status, old_dest_id, old_dest_mode;
321 DECLARE_BITMAP(vcpu_bitmap, KVM_MAX_VCPUS);
322
323 switch (ioapic->ioregsel) {
324 case IOAPIC_REG_VERSION:
325 /* Writes are ignored. */
326 break;
327
328 case IOAPIC_REG_APIC_ID:
329 ioapic->id = (val >> 24) & 0xf;
330 break;
331
332 case IOAPIC_REG_ARB_ID:
333 break;
334
335 default:
336 index = (ioapic->ioregsel - 0x10) >> 1;
337
338 if (index >= IOAPIC_NUM_PINS)
339 return;
340 index = array_index_nospec(index, IOAPIC_NUM_PINS);
341 e = &ioapic->redirtbl[index];
342 mask_before = e->fields.mask;
343 /* Preserve read-only fields */
344 old_remote_irr = e->fields.remote_irr;
345 old_delivery_status = e->fields.delivery_status;
346 old_dest_id = e->fields.dest_id;
347 old_dest_mode = e->fields.dest_mode;
348 if (ioapic->ioregsel & 1) {
349 e->bits &= 0xffffffff;
350 e->bits |= (u64) val << 32;
351 } else {
352 e->bits &= ~0xffffffffULL;
353 e->bits |= (u32) val;
354 }
355 e->fields.remote_irr = old_remote_irr;
356 e->fields.delivery_status = old_delivery_status;
357
358 /*
359 * Some OSes (Linux, Xen) assume that Remote IRR bit will
360 * be cleared by IOAPIC hardware when the entry is configured
361 * as edge-triggered. This behavior is used to simulate an
362 * explicit EOI on IOAPICs that don't have the EOI register.
363 */
364 if (e->fields.trig_mode == IOAPIC_EDGE_TRIG)
365 e->fields.remote_irr = 0;
366
367 mask_after = e->fields.mask;
368 if (mask_before != mask_after)
369 kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after);
370 if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
371 && ioapic->irr & (1 << index))
372 ioapic_service(ioapic, index, false);
373 if (e->fields.delivery_mode == APIC_DM_FIXED) {
374 struct kvm_lapic_irq irq;
375
376 irq.vector = e->fields.vector;
377 irq.delivery_mode = e->fields.delivery_mode << 8;
378 irq.dest_mode =
379 kvm_lapic_irq_dest_mode(!!e->fields.dest_mode);
380 irq.level = false;
381 irq.trig_mode = e->fields.trig_mode;
382 irq.shorthand = APIC_DEST_NOSHORT;
383 irq.dest_id = e->fields.dest_id;
384 irq.msi_redir_hint = false;
385 bitmap_zero(vcpu_bitmap, KVM_MAX_VCPUS);
386 kvm_bitmap_or_dest_vcpus(ioapic->kvm, &irq,
387 vcpu_bitmap);
388 if (old_dest_mode != e->fields.dest_mode ||
389 old_dest_id != e->fields.dest_id) {
390 /*
391 * Update vcpu_bitmap with vcpus specified in
392 * the previous request as well. This is done to
393 * keep ioapic_handled_vectors synchronized.
394 */
395 irq.dest_id = old_dest_id;
396 irq.dest_mode =
397 kvm_lapic_irq_dest_mode(
398 !!e->fields.dest_mode);
399 kvm_bitmap_or_dest_vcpus(ioapic->kvm, &irq,
400 vcpu_bitmap);
401 }
402 kvm_make_scan_ioapic_request_mask(ioapic->kvm,
403 vcpu_bitmap);
404 } else {
405 kvm_make_scan_ioapic_request(ioapic->kvm);
406 }
407 break;
408 }
409}
410
411static int ioapic_service(struct kvm_ioapic *ioapic, int irq, bool line_status)
412{
413 union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
414 struct kvm_lapic_irq irqe;
415 int ret;
416
417 if (entry->fields.mask ||
418 (entry->fields.trig_mode == IOAPIC_LEVEL_TRIG &&
419 entry->fields.remote_irr))
420 return -1;
421
422 irqe.dest_id = entry->fields.dest_id;
423 irqe.vector = entry->fields.vector;
424 irqe.dest_mode = kvm_lapic_irq_dest_mode(!!entry->fields.dest_mode);
425 irqe.trig_mode = entry->fields.trig_mode;
426 irqe.delivery_mode = entry->fields.delivery_mode << 8;
427 irqe.level = 1;
428 irqe.shorthand = APIC_DEST_NOSHORT;
429 irqe.msi_redir_hint = false;
430
431 if (irqe.trig_mode == IOAPIC_EDGE_TRIG)
432 ioapic->irr_delivered |= 1 << irq;
433
434 if (irq == RTC_GSI && line_status) {
435 /*
436 * pending_eoi cannot ever become negative (see
437 * rtc_status_pending_eoi_check_valid) and the caller
438 * ensures that it is only called if it is >= zero, namely
439 * if rtc_irq_check_coalesced returns false).
440 */
441 BUG_ON(ioapic->rtc_status.pending_eoi != 0);
442 ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe,
443 &ioapic->rtc_status.dest_map);
444 ioapic->rtc_status.pending_eoi = (ret < 0 ? 0 : ret);
445 } else
446 ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe, NULL);
447
448 if (ret && irqe.trig_mode == IOAPIC_LEVEL_TRIG)
449 entry->fields.remote_irr = 1;
450
451 return ret;
452}
453
454int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id,
455 int level, bool line_status)
456{
457 int ret, irq_level;
458
459 BUG_ON(irq < 0 || irq >= IOAPIC_NUM_PINS);
460
461 spin_lock(&ioapic->lock);
462 irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq],
463 irq_source_id, level);
464 ret = ioapic_set_irq(ioapic, irq, irq_level, line_status);
465
466 spin_unlock(&ioapic->lock);
467
468 return ret;
469}
470
471void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id)
472{
473 int i;
474
475 spin_lock(&ioapic->lock);
476 for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++)
477 __clear_bit(irq_source_id, &ioapic->irq_states[i]);
478 spin_unlock(&ioapic->lock);
479}
480
481static void kvm_ioapic_eoi_inject_work(struct work_struct *work)
482{
483 int i;
484 struct kvm_ioapic *ioapic = container_of(work, struct kvm_ioapic,
485 eoi_inject.work);
486 spin_lock(&ioapic->lock);
487 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
488 union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
489
490 if (ent->fields.trig_mode != IOAPIC_LEVEL_TRIG)
491 continue;
492
493 if (ioapic->irr & (1 << i) && !ent->fields.remote_irr)
494 ioapic_service(ioapic, i, false);
495 }
496 spin_unlock(&ioapic->lock);
497}
498
499#define IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT 10000
500static void kvm_ioapic_update_eoi_one(struct kvm_vcpu *vcpu,
501 struct kvm_ioapic *ioapic,
502 int trigger_mode,
503 int pin)
504{
505 struct kvm_lapic *apic = vcpu->arch.apic;
506 union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[pin];
507
508 /*
509 * We are dropping lock while calling ack notifiers because ack
510 * notifier callbacks for assigned devices call into IOAPIC
511 * recursively. Since remote_irr is cleared only after call
512 * to notifiers if the same vector will be delivered while lock
513 * is dropped it will be put into irr and will be delivered
514 * after ack notifier returns.
515 */
516 spin_unlock(&ioapic->lock);
517 kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin);
518 spin_lock(&ioapic->lock);
519
520 if (trigger_mode != IOAPIC_LEVEL_TRIG ||
521 kvm_lapic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI)
522 return;
523
524 ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
525 ent->fields.remote_irr = 0;
526 if (!ent->fields.mask && (ioapic->irr & (1 << pin))) {
527 ++ioapic->irq_eoi[pin];
528 if (ioapic->irq_eoi[pin] == IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT) {
529 /*
530 * Real hardware does not deliver the interrupt
531 * immediately during eoi broadcast, and this
532 * lets a buggy guest make slow progress
533 * even if it does not correctly handle a
534 * level-triggered interrupt. Emulate this
535 * behavior if we detect an interrupt storm.
536 */
537 schedule_delayed_work(&ioapic->eoi_inject, HZ / 100);
538 ioapic->irq_eoi[pin] = 0;
539 trace_kvm_ioapic_delayed_eoi_inj(ent->bits);
540 } else {
541 ioapic_service(ioapic, pin, false);
542 }
543 } else {
544 ioapic->irq_eoi[pin] = 0;
545 }
546}
547
548void kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu, int vector, int trigger_mode)
549{
550 int i;
551 struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
552
553 spin_lock(&ioapic->lock);
554 rtc_irq_eoi(ioapic, vcpu, vector);
555 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
556 union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
557
558 if (ent->fields.vector != vector)
559 continue;
560 kvm_ioapic_update_eoi_one(vcpu, ioapic, trigger_mode, i);
561 }
562 spin_unlock(&ioapic->lock);
563}
564
565static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev)
566{
567 return container_of(dev, struct kvm_ioapic, dev);
568}
569
570static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
571{
572 return ((addr >= ioapic->base_address &&
573 (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
574}
575
576static int ioapic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
577 gpa_t addr, int len, void *val)
578{
579 struct kvm_ioapic *ioapic = to_ioapic(this);
580 u32 result;
581 if (!ioapic_in_range(ioapic, addr))
582 return -EOPNOTSUPP;
583
584 ASSERT(!(addr & 0xf)); /* check alignment */
585
586 addr &= 0xff;
587 spin_lock(&ioapic->lock);
588 switch (addr) {
589 case IOAPIC_REG_SELECT:
590 result = ioapic->ioregsel;
591 break;
592
593 case IOAPIC_REG_WINDOW:
594 result = ioapic_read_indirect(ioapic);
595 break;
596
597 default:
598 result = 0;
599 break;
600 }
601 spin_unlock(&ioapic->lock);
602
603 switch (len) {
604 case 8:
605 *(u64 *) val = result;
606 break;
607 case 1:
608 case 2:
609 case 4:
610 memcpy(val, (char *)&result, len);
611 break;
612 default:
613 printk(KERN_WARNING "ioapic: wrong length %d\n", len);
614 }
615 return 0;
616}
617
618static int ioapic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
619 gpa_t addr, int len, const void *val)
620{
621 struct kvm_ioapic *ioapic = to_ioapic(this);
622 u32 data;
623 if (!ioapic_in_range(ioapic, addr))
624 return -EOPNOTSUPP;
625
626 ASSERT(!(addr & 0xf)); /* check alignment */
627
628 switch (len) {
629 case 8:
630 case 4:
631 data = *(u32 *) val;
632 break;
633 case 2:
634 data = *(u16 *) val;
635 break;
636 case 1:
637 data = *(u8 *) val;
638 break;
639 default:
640 printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
641 return 0;
642 }
643
644 addr &= 0xff;
645 spin_lock(&ioapic->lock);
646 switch (addr) {
647 case IOAPIC_REG_SELECT:
648 ioapic->ioregsel = data & 0xFF; /* 8-bit register */
649 break;
650
651 case IOAPIC_REG_WINDOW:
652 ioapic_write_indirect(ioapic, data);
653 break;
654
655 default:
656 break;
657 }
658 spin_unlock(&ioapic->lock);
659 return 0;
660}
661
662static void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
663{
664 int i;
665
666 cancel_delayed_work_sync(&ioapic->eoi_inject);
667 for (i = 0; i < IOAPIC_NUM_PINS; i++)
668 ioapic->redirtbl[i].fields.mask = 1;
669 ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
670 ioapic->ioregsel = 0;
671 ioapic->irr = 0;
672 ioapic->irr_delivered = 0;
673 ioapic->id = 0;
674 memset(ioapic->irq_eoi, 0x00, sizeof(ioapic->irq_eoi));
675 rtc_irq_eoi_tracking_reset(ioapic);
676}
677
678static const struct kvm_io_device_ops ioapic_mmio_ops = {
679 .read = ioapic_mmio_read,
680 .write = ioapic_mmio_write,
681};
682
683int kvm_ioapic_init(struct kvm *kvm)
684{
685 struct kvm_ioapic *ioapic;
686 int ret;
687
688 ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL_ACCOUNT);
689 if (!ioapic)
690 return -ENOMEM;
691 spin_lock_init(&ioapic->lock);
692 INIT_DELAYED_WORK(&ioapic->eoi_inject, kvm_ioapic_eoi_inject_work);
693 kvm->arch.vioapic = ioapic;
694 kvm_ioapic_reset(ioapic);
695 kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
696 ioapic->kvm = kvm;
697 mutex_lock(&kvm->slots_lock);
698 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address,
699 IOAPIC_MEM_LENGTH, &ioapic->dev);
700 mutex_unlock(&kvm->slots_lock);
701 if (ret < 0) {
702 kvm->arch.vioapic = NULL;
703 kfree(ioapic);
704 }
705
706 return ret;
707}
708
709void kvm_ioapic_destroy(struct kvm *kvm)
710{
711 struct kvm_ioapic *ioapic = kvm->arch.vioapic;
712
713 if (!ioapic)
714 return;
715
716 cancel_delayed_work_sync(&ioapic->eoi_inject);
717 mutex_lock(&kvm->slots_lock);
718 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
719 mutex_unlock(&kvm->slots_lock);
720 kvm->arch.vioapic = NULL;
721 kfree(ioapic);
722}
723
724void kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
725{
726 struct kvm_ioapic *ioapic = kvm->arch.vioapic;
727
728 spin_lock(&ioapic->lock);
729 memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
730 state->irr &= ~ioapic->irr_delivered;
731 spin_unlock(&ioapic->lock);
732}
733
734void kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
735{
736 struct kvm_ioapic *ioapic = kvm->arch.vioapic;
737
738 spin_lock(&ioapic->lock);
739 memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
740 ioapic->irr = 0;
741 ioapic->irr_delivered = 0;
742 kvm_make_scan_ioapic_request(kvm);
743 kvm_ioapic_inject_all(ioapic, state->irr);
744 spin_unlock(&ioapic->lock);
745}