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1/*
2 * 8259 interrupt controller emulation
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2007 Intel Corporation
6 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 * Authors:
26 * Yaozu (Eddie) Dong <Eddie.dong@intel.com>
27 * Port from Qemu.
28 */
29#include <linux/mm.h>
30#include <linux/slab.h>
31#include <linux/bitops.h>
32#include "irq.h"
33
34#include <linux/kvm_host.h>
35#include "trace.h"
36
37#define pr_pic_unimpl(fmt, ...) \
38 pr_err_ratelimited("kvm: pic: " fmt, ## __VA_ARGS__)
39
40static void pic_irq_request(struct kvm *kvm, int level);
41
42static void pic_lock(struct kvm_pic *s)
43 __acquires(&s->lock)
44{
45 spin_lock(&s->lock);
46}
47
48static void pic_unlock(struct kvm_pic *s)
49 __releases(&s->lock)
50{
51 bool wakeup = s->wakeup_needed;
52 struct kvm_vcpu *vcpu;
53 unsigned long i;
54
55 s->wakeup_needed = false;
56
57 spin_unlock(&s->lock);
58
59 if (wakeup) {
60 kvm_for_each_vcpu(i, vcpu, s->kvm) {
61 if (kvm_apic_accept_pic_intr(vcpu)) {
62 kvm_make_request(KVM_REQ_EVENT, vcpu);
63 kvm_vcpu_kick(vcpu);
64 return;
65 }
66 }
67 }
68}
69
70static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
71{
72 s->isr &= ~(1 << irq);
73 if (s != &s->pics_state->pics[0])
74 irq += 8;
75 /*
76 * We are dropping lock while calling ack notifiers since ack
77 * notifier callbacks for assigned devices call into PIC recursively.
78 * Other interrupt may be delivered to PIC while lock is dropped but
79 * it should be safe since PIC state is already updated at this stage.
80 */
81 pic_unlock(s->pics_state);
82 kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);
83 pic_lock(s->pics_state);
84}
85
86/*
87 * set irq level. If an edge is detected, then the IRR is set to 1
88 */
89static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
90{
91 int mask, ret = 1;
92 mask = 1 << irq;
93 if (s->elcr & mask) /* level triggered */
94 if (level) {
95 ret = !(s->irr & mask);
96 s->irr |= mask;
97 s->last_irr |= mask;
98 } else {
99 s->irr &= ~mask;
100 s->last_irr &= ~mask;
101 }
102 else /* edge triggered */
103 if (level) {
104 if ((s->last_irr & mask) == 0) {
105 ret = !(s->irr & mask);
106 s->irr |= mask;
107 }
108 s->last_irr |= mask;
109 } else
110 s->last_irr &= ~mask;
111
112 return (s->imr & mask) ? -1 : ret;
113}
114
115/*
116 * return the highest priority found in mask (highest = smallest
117 * number). Return 8 if no irq
118 */
119static inline int get_priority(struct kvm_kpic_state *s, int mask)
120{
121 int priority;
122 if (mask == 0)
123 return 8;
124 priority = 0;
125 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
126 priority++;
127 return priority;
128}
129
130/*
131 * return the pic wanted interrupt. return -1 if none
132 */
133static int pic_get_irq(struct kvm_kpic_state *s)
134{
135 int mask, cur_priority, priority;
136
137 mask = s->irr & ~s->imr;
138 priority = get_priority(s, mask);
139 if (priority == 8)
140 return -1;
141 /*
142 * compute current priority. If special fully nested mode on the
143 * master, the IRQ coming from the slave is not taken into account
144 * for the priority computation.
145 */
146 mask = s->isr;
147 if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
148 mask &= ~(1 << 2);
149 cur_priority = get_priority(s, mask);
150 if (priority < cur_priority)
151 /*
152 * higher priority found: an irq should be generated
153 */
154 return (priority + s->priority_add) & 7;
155 else
156 return -1;
157}
158
159/*
160 * raise irq to CPU if necessary. must be called every time the active
161 * irq may change
162 */
163static void pic_update_irq(struct kvm_pic *s)
164{
165 int irq2, irq;
166
167 irq2 = pic_get_irq(&s->pics[1]);
168 if (irq2 >= 0) {
169 /*
170 * if irq request by slave pic, signal master PIC
171 */
172 pic_set_irq1(&s->pics[0], 2, 1);
173 pic_set_irq1(&s->pics[0], 2, 0);
174 }
175 irq = pic_get_irq(&s->pics[0]);
176 pic_irq_request(s->kvm, irq >= 0);
177}
178
179void kvm_pic_update_irq(struct kvm_pic *s)
180{
181 pic_lock(s);
182 pic_update_irq(s);
183 pic_unlock(s);
184}
185
186int kvm_pic_set_irq(struct kvm_pic *s, int irq, int irq_source_id, int level)
187{
188 int ret, irq_level;
189
190 BUG_ON(irq < 0 || irq >= PIC_NUM_PINS);
191
192 pic_lock(s);
193 irq_level = __kvm_irq_line_state(&s->irq_states[irq],
194 irq_source_id, level);
195 ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, irq_level);
196 pic_update_irq(s);
197 trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
198 s->pics[irq >> 3].imr, ret == 0);
199 pic_unlock(s);
200
201 return ret;
202}
203
204void kvm_pic_clear_all(struct kvm_pic *s, int irq_source_id)
205{
206 int i;
207
208 pic_lock(s);
209 for (i = 0; i < PIC_NUM_PINS; i++)
210 __clear_bit(irq_source_id, &s->irq_states[i]);
211 pic_unlock(s);
212}
213
214/*
215 * acknowledge interrupt 'irq'
216 */
217static inline void pic_intack(struct kvm_kpic_state *s, int irq)
218{
219 s->isr |= 1 << irq;
220 /*
221 * We don't clear a level sensitive interrupt here
222 */
223 if (!(s->elcr & (1 << irq)))
224 s->irr &= ~(1 << irq);
225
226 if (s->auto_eoi) {
227 if (s->rotate_on_auto_eoi)
228 s->priority_add = (irq + 1) & 7;
229 pic_clear_isr(s, irq);
230 }
231
232}
233
234int kvm_pic_read_irq(struct kvm *kvm)
235{
236 int irq, irq2, intno;
237 struct kvm_pic *s = kvm->arch.vpic;
238
239 s->output = 0;
240
241 pic_lock(s);
242 irq = pic_get_irq(&s->pics[0]);
243 if (irq >= 0) {
244 pic_intack(&s->pics[0], irq);
245 if (irq == 2) {
246 irq2 = pic_get_irq(&s->pics[1]);
247 if (irq2 >= 0)
248 pic_intack(&s->pics[1], irq2);
249 else
250 /*
251 * spurious IRQ on slave controller
252 */
253 irq2 = 7;
254 intno = s->pics[1].irq_base + irq2;
255 } else
256 intno = s->pics[0].irq_base + irq;
257 } else {
258 /*
259 * spurious IRQ on host controller
260 */
261 irq = 7;
262 intno = s->pics[0].irq_base + irq;
263 }
264 pic_update_irq(s);
265 pic_unlock(s);
266
267 return intno;
268}
269
270static void kvm_pic_reset(struct kvm_kpic_state *s)
271{
272 int irq;
273 unsigned long i;
274 struct kvm_vcpu *vcpu;
275 u8 edge_irr = s->irr & ~s->elcr;
276 bool found = false;
277
278 s->last_irr = 0;
279 s->irr &= s->elcr;
280 s->imr = 0;
281 s->priority_add = 0;
282 s->special_mask = 0;
283 s->read_reg_select = 0;
284 if (!s->init4) {
285 s->special_fully_nested_mode = 0;
286 s->auto_eoi = 0;
287 }
288 s->init_state = 1;
289
290 kvm_for_each_vcpu(i, vcpu, s->pics_state->kvm)
291 if (kvm_apic_accept_pic_intr(vcpu)) {
292 found = true;
293 break;
294 }
295
296
297 if (!found)
298 return;
299
300 for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
301 if (edge_irr & (1 << irq))
302 pic_clear_isr(s, irq);
303}
304
305static void pic_ioport_write(void *opaque, u32 addr, u32 val)
306{
307 struct kvm_kpic_state *s = opaque;
308 int priority, cmd, irq;
309
310 addr &= 1;
311 if (addr == 0) {
312 if (val & 0x10) {
313 s->init4 = val & 1;
314 if (val & 0x02)
315 pr_pic_unimpl("single mode not supported");
316 if (val & 0x08)
317 pr_pic_unimpl(
318 "level sensitive irq not supported");
319 kvm_pic_reset(s);
320 } else if (val & 0x08) {
321 if (val & 0x04)
322 s->poll = 1;
323 if (val & 0x02)
324 s->read_reg_select = val & 1;
325 if (val & 0x40)
326 s->special_mask = (val >> 5) & 1;
327 } else {
328 cmd = val >> 5;
329 switch (cmd) {
330 case 0:
331 case 4:
332 s->rotate_on_auto_eoi = cmd >> 2;
333 break;
334 case 1: /* end of interrupt */
335 case 5:
336 priority = get_priority(s, s->isr);
337 if (priority != 8) {
338 irq = (priority + s->priority_add) & 7;
339 if (cmd == 5)
340 s->priority_add = (irq + 1) & 7;
341 pic_clear_isr(s, irq);
342 pic_update_irq(s->pics_state);
343 }
344 break;
345 case 3:
346 irq = val & 7;
347 pic_clear_isr(s, irq);
348 pic_update_irq(s->pics_state);
349 break;
350 case 6:
351 s->priority_add = (val + 1) & 7;
352 pic_update_irq(s->pics_state);
353 break;
354 case 7:
355 irq = val & 7;
356 s->priority_add = (irq + 1) & 7;
357 pic_clear_isr(s, irq);
358 pic_update_irq(s->pics_state);
359 break;
360 default:
361 break; /* no operation */
362 }
363 }
364 } else
365 switch (s->init_state) {
366 case 0: { /* normal mode */
367 u8 imr_diff = s->imr ^ val,
368 off = (s == &s->pics_state->pics[0]) ? 0 : 8;
369 s->imr = val;
370 for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
371 if (imr_diff & (1 << irq))
372 kvm_fire_mask_notifiers(
373 s->pics_state->kvm,
374 SELECT_PIC(irq + off),
375 irq + off,
376 !!(s->imr & (1 << irq)));
377 pic_update_irq(s->pics_state);
378 break;
379 }
380 case 1:
381 s->irq_base = val & 0xf8;
382 s->init_state = 2;
383 break;
384 case 2:
385 if (s->init4)
386 s->init_state = 3;
387 else
388 s->init_state = 0;
389 break;
390 case 3:
391 s->special_fully_nested_mode = (val >> 4) & 1;
392 s->auto_eoi = (val >> 1) & 1;
393 s->init_state = 0;
394 break;
395 }
396}
397
398static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
399{
400 int ret;
401
402 ret = pic_get_irq(s);
403 if (ret >= 0) {
404 if (addr1 >> 7) {
405 s->pics_state->pics[0].isr &= ~(1 << 2);
406 s->pics_state->pics[0].irr &= ~(1 << 2);
407 }
408 s->irr &= ~(1 << ret);
409 pic_clear_isr(s, ret);
410 if (addr1 >> 7 || ret != 2)
411 pic_update_irq(s->pics_state);
412 } else {
413 ret = 0x07;
414 pic_update_irq(s->pics_state);
415 }
416
417 return ret;
418}
419
420static u32 pic_ioport_read(void *opaque, u32 addr)
421{
422 struct kvm_kpic_state *s = opaque;
423 int ret;
424
425 if (s->poll) {
426 ret = pic_poll_read(s, addr);
427 s->poll = 0;
428 } else
429 if ((addr & 1) == 0)
430 if (s->read_reg_select)
431 ret = s->isr;
432 else
433 ret = s->irr;
434 else
435 ret = s->imr;
436 return ret;
437}
438
439static void elcr_ioport_write(void *opaque, u32 val)
440{
441 struct kvm_kpic_state *s = opaque;
442 s->elcr = val & s->elcr_mask;
443}
444
445static u32 elcr_ioport_read(void *opaque)
446{
447 struct kvm_kpic_state *s = opaque;
448 return s->elcr;
449}
450
451static int picdev_write(struct kvm_pic *s,
452 gpa_t addr, int len, const void *val)
453{
454 unsigned char data = *(unsigned char *)val;
455
456 if (len != 1) {
457 pr_pic_unimpl("non byte write\n");
458 return 0;
459 }
460 switch (addr) {
461 case 0x20:
462 case 0x21:
463 pic_lock(s);
464 pic_ioport_write(&s->pics[0], addr, data);
465 pic_unlock(s);
466 break;
467 case 0xa0:
468 case 0xa1:
469 pic_lock(s);
470 pic_ioport_write(&s->pics[1], addr, data);
471 pic_unlock(s);
472 break;
473 case 0x4d0:
474 case 0x4d1:
475 pic_lock(s);
476 elcr_ioport_write(&s->pics[addr & 1], data);
477 pic_unlock(s);
478 break;
479 default:
480 return -EOPNOTSUPP;
481 }
482 return 0;
483}
484
485static int picdev_read(struct kvm_pic *s,
486 gpa_t addr, int len, void *val)
487{
488 unsigned char *data = (unsigned char *)val;
489
490 if (len != 1) {
491 memset(val, 0, len);
492 pr_pic_unimpl("non byte read\n");
493 return 0;
494 }
495 switch (addr) {
496 case 0x20:
497 case 0x21:
498 case 0xa0:
499 case 0xa1:
500 pic_lock(s);
501 *data = pic_ioport_read(&s->pics[addr >> 7], addr);
502 pic_unlock(s);
503 break;
504 case 0x4d0:
505 case 0x4d1:
506 pic_lock(s);
507 *data = elcr_ioport_read(&s->pics[addr & 1]);
508 pic_unlock(s);
509 break;
510 default:
511 return -EOPNOTSUPP;
512 }
513 return 0;
514}
515
516static int picdev_master_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
517 gpa_t addr, int len, const void *val)
518{
519 return picdev_write(container_of(dev, struct kvm_pic, dev_master),
520 addr, len, val);
521}
522
523static int picdev_master_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
524 gpa_t addr, int len, void *val)
525{
526 return picdev_read(container_of(dev, struct kvm_pic, dev_master),
527 addr, len, val);
528}
529
530static int picdev_slave_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
531 gpa_t addr, int len, const void *val)
532{
533 return picdev_write(container_of(dev, struct kvm_pic, dev_slave),
534 addr, len, val);
535}
536
537static int picdev_slave_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
538 gpa_t addr, int len, void *val)
539{
540 return picdev_read(container_of(dev, struct kvm_pic, dev_slave),
541 addr, len, val);
542}
543
544static int picdev_elcr_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
545 gpa_t addr, int len, const void *val)
546{
547 return picdev_write(container_of(dev, struct kvm_pic, dev_elcr),
548 addr, len, val);
549}
550
551static int picdev_elcr_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
552 gpa_t addr, int len, void *val)
553{
554 return picdev_read(container_of(dev, struct kvm_pic, dev_elcr),
555 addr, len, val);
556}
557
558/*
559 * callback when PIC0 irq status changed
560 */
561static void pic_irq_request(struct kvm *kvm, int level)
562{
563 struct kvm_pic *s = kvm->arch.vpic;
564
565 if (!s->output)
566 s->wakeup_needed = true;
567 s->output = level;
568}
569
570static const struct kvm_io_device_ops picdev_master_ops = {
571 .read = picdev_master_read,
572 .write = picdev_master_write,
573};
574
575static const struct kvm_io_device_ops picdev_slave_ops = {
576 .read = picdev_slave_read,
577 .write = picdev_slave_write,
578};
579
580static const struct kvm_io_device_ops picdev_elcr_ops = {
581 .read = picdev_elcr_read,
582 .write = picdev_elcr_write,
583};
584
585int kvm_pic_init(struct kvm *kvm)
586{
587 struct kvm_pic *s;
588 int ret;
589
590 s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL_ACCOUNT);
591 if (!s)
592 return -ENOMEM;
593 spin_lock_init(&s->lock);
594 s->kvm = kvm;
595 s->pics[0].elcr_mask = 0xf8;
596 s->pics[1].elcr_mask = 0xde;
597 s->pics[0].pics_state = s;
598 s->pics[1].pics_state = s;
599
600 /*
601 * Initialize PIO device
602 */
603 kvm_iodevice_init(&s->dev_master, &picdev_master_ops);
604 kvm_iodevice_init(&s->dev_slave, &picdev_slave_ops);
605 kvm_iodevice_init(&s->dev_elcr, &picdev_elcr_ops);
606 mutex_lock(&kvm->slots_lock);
607 ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0x20, 2,
608 &s->dev_master);
609 if (ret < 0)
610 goto fail_unlock;
611
612 ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0xa0, 2, &s->dev_slave);
613 if (ret < 0)
614 goto fail_unreg_2;
615
616 ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0x4d0, 2, &s->dev_elcr);
617 if (ret < 0)
618 goto fail_unreg_1;
619
620 mutex_unlock(&kvm->slots_lock);
621
622 kvm->arch.vpic = s;
623
624 return 0;
625
626fail_unreg_1:
627 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &s->dev_slave);
628
629fail_unreg_2:
630 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &s->dev_master);
631
632fail_unlock:
633 mutex_unlock(&kvm->slots_lock);
634
635 kfree(s);
636
637 return ret;
638}
639
640void kvm_pic_destroy(struct kvm *kvm)
641{
642 struct kvm_pic *vpic = kvm->arch.vpic;
643
644 if (!vpic)
645 return;
646
647 mutex_lock(&kvm->slots_lock);
648 kvm_io_bus_unregister_dev(vpic->kvm, KVM_PIO_BUS, &vpic->dev_master);
649 kvm_io_bus_unregister_dev(vpic->kvm, KVM_PIO_BUS, &vpic->dev_slave);
650 kvm_io_bus_unregister_dev(vpic->kvm, KVM_PIO_BUS, &vpic->dev_elcr);
651 mutex_unlock(&kvm->slots_lock);
652
653 kvm->arch.vpic = NULL;
654 kfree(vpic);
655}
1/*
2 * 8259 interrupt controller emulation
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2007 Intel Corporation
6 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 * Authors:
26 * Yaozu (Eddie) Dong <Eddie.dong@intel.com>
27 * Port from Qemu.
28 */
29#include <linux/mm.h>
30#include <linux/slab.h>
31#include <linux/bitops.h>
32#include "irq.h"
33
34#include <linux/kvm_host.h>
35#include "trace.h"
36
37static void pic_irq_request(struct kvm *kvm, int level);
38
39static void pic_lock(struct kvm_pic *s)
40 __acquires(&s->lock)
41{
42 spin_lock(&s->lock);
43}
44
45static void pic_unlock(struct kvm_pic *s)
46 __releases(&s->lock)
47{
48 bool wakeup = s->wakeup_needed;
49 struct kvm_vcpu *vcpu, *found = NULL;
50 int i;
51
52 s->wakeup_needed = false;
53
54 spin_unlock(&s->lock);
55
56 if (wakeup) {
57 kvm_for_each_vcpu(i, vcpu, s->kvm) {
58 if (kvm_apic_accept_pic_intr(vcpu)) {
59 found = vcpu;
60 break;
61 }
62 }
63
64 if (!found)
65 return;
66
67 kvm_make_request(KVM_REQ_EVENT, found);
68 kvm_vcpu_kick(found);
69 }
70}
71
72static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
73{
74 s->isr &= ~(1 << irq);
75 if (s != &s->pics_state->pics[0])
76 irq += 8;
77 /*
78 * We are dropping lock while calling ack notifiers since ack
79 * notifier callbacks for assigned devices call into PIC recursively.
80 * Other interrupt may be delivered to PIC while lock is dropped but
81 * it should be safe since PIC state is already updated at this stage.
82 */
83 pic_unlock(s->pics_state);
84 kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);
85 pic_lock(s->pics_state);
86}
87
88/*
89 * set irq level. If an edge is detected, then the IRR is set to 1
90 */
91static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
92{
93 int mask, ret = 1;
94 mask = 1 << irq;
95 if (s->elcr & mask) /* level triggered */
96 if (level) {
97 ret = !(s->irr & mask);
98 s->irr |= mask;
99 s->last_irr |= mask;
100 } else {
101 s->irr &= ~mask;
102 s->last_irr &= ~mask;
103 }
104 else /* edge triggered */
105 if (level) {
106 if ((s->last_irr & mask) == 0) {
107 ret = !(s->irr & mask);
108 s->irr |= mask;
109 }
110 s->last_irr |= mask;
111 } else
112 s->last_irr &= ~mask;
113
114 return (s->imr & mask) ? -1 : ret;
115}
116
117/*
118 * return the highest priority found in mask (highest = smallest
119 * number). Return 8 if no irq
120 */
121static inline int get_priority(struct kvm_kpic_state *s, int mask)
122{
123 int priority;
124 if (mask == 0)
125 return 8;
126 priority = 0;
127 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
128 priority++;
129 return priority;
130}
131
132/*
133 * return the pic wanted interrupt. return -1 if none
134 */
135static int pic_get_irq(struct kvm_kpic_state *s)
136{
137 int mask, cur_priority, priority;
138
139 mask = s->irr & ~s->imr;
140 priority = get_priority(s, mask);
141 if (priority == 8)
142 return -1;
143 /*
144 * compute current priority. If special fully nested mode on the
145 * master, the IRQ coming from the slave is not taken into account
146 * for the priority computation.
147 */
148 mask = s->isr;
149 if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
150 mask &= ~(1 << 2);
151 cur_priority = get_priority(s, mask);
152 if (priority < cur_priority)
153 /*
154 * higher priority found: an irq should be generated
155 */
156 return (priority + s->priority_add) & 7;
157 else
158 return -1;
159}
160
161/*
162 * raise irq to CPU if necessary. must be called every time the active
163 * irq may change
164 */
165static void pic_update_irq(struct kvm_pic *s)
166{
167 int irq2, irq;
168
169 irq2 = pic_get_irq(&s->pics[1]);
170 if (irq2 >= 0) {
171 /*
172 * if irq request by slave pic, signal master PIC
173 */
174 pic_set_irq1(&s->pics[0], 2, 1);
175 pic_set_irq1(&s->pics[0], 2, 0);
176 }
177 irq = pic_get_irq(&s->pics[0]);
178 pic_irq_request(s->kvm, irq >= 0);
179}
180
181void kvm_pic_update_irq(struct kvm_pic *s)
182{
183 pic_lock(s);
184 pic_update_irq(s);
185 pic_unlock(s);
186}
187
188int kvm_pic_set_irq(void *opaque, int irq, int level)
189{
190 struct kvm_pic *s = opaque;
191 int ret = -1;
192
193 pic_lock(s);
194 if (irq >= 0 && irq < PIC_NUM_PINS) {
195 ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
196 pic_update_irq(s);
197 trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
198 s->pics[irq >> 3].imr, ret == 0);
199 }
200 pic_unlock(s);
201
202 return ret;
203}
204
205/*
206 * acknowledge interrupt 'irq'
207 */
208static inline void pic_intack(struct kvm_kpic_state *s, int irq)
209{
210 s->isr |= 1 << irq;
211 /*
212 * We don't clear a level sensitive interrupt here
213 */
214 if (!(s->elcr & (1 << irq)))
215 s->irr &= ~(1 << irq);
216
217 if (s->auto_eoi) {
218 if (s->rotate_on_auto_eoi)
219 s->priority_add = (irq + 1) & 7;
220 pic_clear_isr(s, irq);
221 }
222
223}
224
225int kvm_pic_read_irq(struct kvm *kvm)
226{
227 int irq, irq2, intno;
228 struct kvm_pic *s = pic_irqchip(kvm);
229
230 pic_lock(s);
231 irq = pic_get_irq(&s->pics[0]);
232 if (irq >= 0) {
233 pic_intack(&s->pics[0], irq);
234 if (irq == 2) {
235 irq2 = pic_get_irq(&s->pics[1]);
236 if (irq2 >= 0)
237 pic_intack(&s->pics[1], irq2);
238 else
239 /*
240 * spurious IRQ on slave controller
241 */
242 irq2 = 7;
243 intno = s->pics[1].irq_base + irq2;
244 irq = irq2 + 8;
245 } else
246 intno = s->pics[0].irq_base + irq;
247 } else {
248 /*
249 * spurious IRQ on host controller
250 */
251 irq = 7;
252 intno = s->pics[0].irq_base + irq;
253 }
254 pic_update_irq(s);
255 pic_unlock(s);
256
257 return intno;
258}
259
260void kvm_pic_reset(struct kvm_kpic_state *s)
261{
262 int irq;
263 struct kvm_vcpu *vcpu0 = s->pics_state->kvm->bsp_vcpu;
264 u8 irr = s->irr, isr = s->imr;
265
266 s->last_irr = 0;
267 s->irr = 0;
268 s->imr = 0;
269 s->isr = 0;
270 s->priority_add = 0;
271 s->irq_base = 0;
272 s->read_reg_select = 0;
273 s->poll = 0;
274 s->special_mask = 0;
275 s->init_state = 0;
276 s->auto_eoi = 0;
277 s->rotate_on_auto_eoi = 0;
278 s->special_fully_nested_mode = 0;
279 s->init4 = 0;
280
281 for (irq = 0; irq < PIC_NUM_PINS/2; irq++) {
282 if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0))
283 if (irr & (1 << irq) || isr & (1 << irq)) {
284 pic_clear_isr(s, irq);
285 }
286 }
287}
288
289static void pic_ioport_write(void *opaque, u32 addr, u32 val)
290{
291 struct kvm_kpic_state *s = opaque;
292 int priority, cmd, irq;
293
294 addr &= 1;
295 if (addr == 0) {
296 if (val & 0x10) {
297 s->init4 = val & 1;
298 s->last_irr = 0;
299 s->imr = 0;
300 s->priority_add = 0;
301 s->special_mask = 0;
302 s->read_reg_select = 0;
303 if (!s->init4) {
304 s->special_fully_nested_mode = 0;
305 s->auto_eoi = 0;
306 }
307 s->init_state = 1;
308 if (val & 0x02)
309 printk(KERN_ERR "single mode not supported");
310 if (val & 0x08)
311 printk(KERN_ERR
312 "level sensitive irq not supported");
313 } else if (val & 0x08) {
314 if (val & 0x04)
315 s->poll = 1;
316 if (val & 0x02)
317 s->read_reg_select = val & 1;
318 if (val & 0x40)
319 s->special_mask = (val >> 5) & 1;
320 } else {
321 cmd = val >> 5;
322 switch (cmd) {
323 case 0:
324 case 4:
325 s->rotate_on_auto_eoi = cmd >> 2;
326 break;
327 case 1: /* end of interrupt */
328 case 5:
329 priority = get_priority(s, s->isr);
330 if (priority != 8) {
331 irq = (priority + s->priority_add) & 7;
332 if (cmd == 5)
333 s->priority_add = (irq + 1) & 7;
334 pic_clear_isr(s, irq);
335 pic_update_irq(s->pics_state);
336 }
337 break;
338 case 3:
339 irq = val & 7;
340 pic_clear_isr(s, irq);
341 pic_update_irq(s->pics_state);
342 break;
343 case 6:
344 s->priority_add = (val + 1) & 7;
345 pic_update_irq(s->pics_state);
346 break;
347 case 7:
348 irq = val & 7;
349 s->priority_add = (irq + 1) & 7;
350 pic_clear_isr(s, irq);
351 pic_update_irq(s->pics_state);
352 break;
353 default:
354 break; /* no operation */
355 }
356 }
357 } else
358 switch (s->init_state) {
359 case 0: { /* normal mode */
360 u8 imr_diff = s->imr ^ val,
361 off = (s == &s->pics_state->pics[0]) ? 0 : 8;
362 s->imr = val;
363 for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
364 if (imr_diff & (1 << irq))
365 kvm_fire_mask_notifiers(
366 s->pics_state->kvm,
367 SELECT_PIC(irq + off),
368 irq + off,
369 !!(s->imr & (1 << irq)));
370 pic_update_irq(s->pics_state);
371 break;
372 }
373 case 1:
374 s->irq_base = val & 0xf8;
375 s->init_state = 2;
376 break;
377 case 2:
378 if (s->init4)
379 s->init_state = 3;
380 else
381 s->init_state = 0;
382 break;
383 case 3:
384 s->special_fully_nested_mode = (val >> 4) & 1;
385 s->auto_eoi = (val >> 1) & 1;
386 s->init_state = 0;
387 break;
388 }
389}
390
391static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
392{
393 int ret;
394
395 ret = pic_get_irq(s);
396 if (ret >= 0) {
397 if (addr1 >> 7) {
398 s->pics_state->pics[0].isr &= ~(1 << 2);
399 s->pics_state->pics[0].irr &= ~(1 << 2);
400 }
401 s->irr &= ~(1 << ret);
402 pic_clear_isr(s, ret);
403 if (addr1 >> 7 || ret != 2)
404 pic_update_irq(s->pics_state);
405 } else {
406 ret = 0x07;
407 pic_update_irq(s->pics_state);
408 }
409
410 return ret;
411}
412
413static u32 pic_ioport_read(void *opaque, u32 addr1)
414{
415 struct kvm_kpic_state *s = opaque;
416 unsigned int addr;
417 int ret;
418
419 addr = addr1;
420 addr &= 1;
421 if (s->poll) {
422 ret = pic_poll_read(s, addr1);
423 s->poll = 0;
424 } else
425 if (addr == 0)
426 if (s->read_reg_select)
427 ret = s->isr;
428 else
429 ret = s->irr;
430 else
431 ret = s->imr;
432 return ret;
433}
434
435static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
436{
437 struct kvm_kpic_state *s = opaque;
438 s->elcr = val & s->elcr_mask;
439}
440
441static u32 elcr_ioport_read(void *opaque, u32 addr1)
442{
443 struct kvm_kpic_state *s = opaque;
444 return s->elcr;
445}
446
447static int picdev_in_range(gpa_t addr)
448{
449 switch (addr) {
450 case 0x20:
451 case 0x21:
452 case 0xa0:
453 case 0xa1:
454 case 0x4d0:
455 case 0x4d1:
456 return 1;
457 default:
458 return 0;
459 }
460}
461
462static inline struct kvm_pic *to_pic(struct kvm_io_device *dev)
463{
464 return container_of(dev, struct kvm_pic, dev);
465}
466
467static int picdev_write(struct kvm_io_device *this,
468 gpa_t addr, int len, const void *val)
469{
470 struct kvm_pic *s = to_pic(this);
471 unsigned char data = *(unsigned char *)val;
472 if (!picdev_in_range(addr))
473 return -EOPNOTSUPP;
474
475 if (len != 1) {
476 if (printk_ratelimit())
477 printk(KERN_ERR "PIC: non byte write\n");
478 return 0;
479 }
480 pic_lock(s);
481 switch (addr) {
482 case 0x20:
483 case 0x21:
484 case 0xa0:
485 case 0xa1:
486 pic_ioport_write(&s->pics[addr >> 7], addr, data);
487 break;
488 case 0x4d0:
489 case 0x4d1:
490 elcr_ioport_write(&s->pics[addr & 1], addr, data);
491 break;
492 }
493 pic_unlock(s);
494 return 0;
495}
496
497static int picdev_read(struct kvm_io_device *this,
498 gpa_t addr, int len, void *val)
499{
500 struct kvm_pic *s = to_pic(this);
501 unsigned char data = 0;
502 if (!picdev_in_range(addr))
503 return -EOPNOTSUPP;
504
505 if (len != 1) {
506 if (printk_ratelimit())
507 printk(KERN_ERR "PIC: non byte read\n");
508 return 0;
509 }
510 pic_lock(s);
511 switch (addr) {
512 case 0x20:
513 case 0x21:
514 case 0xa0:
515 case 0xa1:
516 data = pic_ioport_read(&s->pics[addr >> 7], addr);
517 break;
518 case 0x4d0:
519 case 0x4d1:
520 data = elcr_ioport_read(&s->pics[addr & 1], addr);
521 break;
522 }
523 *(unsigned char *)val = data;
524 pic_unlock(s);
525 return 0;
526}
527
528/*
529 * callback when PIC0 irq status changed
530 */
531static void pic_irq_request(struct kvm *kvm, int level)
532{
533 struct kvm_pic *s = pic_irqchip(kvm);
534
535 if (!s->output)
536 s->wakeup_needed = true;
537 s->output = level;
538}
539
540static const struct kvm_io_device_ops picdev_ops = {
541 .read = picdev_read,
542 .write = picdev_write,
543};
544
545struct kvm_pic *kvm_create_pic(struct kvm *kvm)
546{
547 struct kvm_pic *s;
548 int ret;
549
550 s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
551 if (!s)
552 return NULL;
553 spin_lock_init(&s->lock);
554 s->kvm = kvm;
555 s->pics[0].elcr_mask = 0xf8;
556 s->pics[1].elcr_mask = 0xde;
557 s->pics[0].pics_state = s;
558 s->pics[1].pics_state = s;
559
560 /*
561 * Initialize PIO device
562 */
563 kvm_iodevice_init(&s->dev, &picdev_ops);
564 mutex_lock(&kvm->slots_lock);
565 ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, &s->dev);
566 mutex_unlock(&kvm->slots_lock);
567 if (ret < 0) {
568 kfree(s);
569 return NULL;
570 }
571
572 return s;
573}
574
575void kvm_destroy_pic(struct kvm *kvm)
576{
577 struct kvm_pic *vpic = kvm->arch.vpic;
578
579 if (vpic) {
580 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev);
581 kvm->arch.vpic = NULL;
582 kfree(vpic);
583 }
584}