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1/*
2 * P5020DS Device Tree Source
3 *
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "p5020si.dtsi"
36
37/ {
38 model = "fsl,P5020DS";
39 compatible = "fsl,P5020DS";
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 memory {
45 device_type = "memory";
46 };
47
48 soc: soc@ffe000000 {
49 spi@110000 {
50 flash@0 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 compatible = "spansion,s25sl12801";
54 reg = <0>;
55 spi-max-frequency = <40000000>; /* input clock */
56 partition@u-boot {
57 label = "u-boot";
58 reg = <0x00000000 0x00100000>;
59 read-only;
60 };
61 partition@kernel {
62 label = "kernel";
63 reg = <0x00100000 0x00500000>;
64 read-only;
65 };
66 partition@dtb {
67 label = "dtb";
68 reg = <0x00600000 0x00100000>;
69 read-only;
70 };
71 partition@fs {
72 label = "file system";
73 reg = <0x00700000 0x00900000>;
74 };
75 };
76 };
77
78 i2c@118100 {
79 eeprom@51 {
80 compatible = "at24,24c256";
81 reg = <0x51>;
82 };
83 eeprom@52 {
84 compatible = "at24,24c256";
85 reg = <0x52>;
86 };
87 };
88
89 i2c@119100 {
90 rtc@68 {
91 compatible = "dallas,ds3232";
92 reg = <0x68>;
93 interrupts = <0x1 0x1 0 0>;
94 };
95 };
96 };
97
98 localbus@ffe124000 {
99 reg = <0xf 0xfe124000 0 0x1000>;
100 ranges = <0 0 0xf 0xe8000000 0x08000000
101 2 0 0xf 0xffa00000 0x00040000
102 3 0 0xf 0xffdf0000 0x00008000>;
103
104 flash@0,0 {
105 compatible = "cfi-flash";
106 reg = <0 0 0x08000000>;
107 bank-width = <2>;
108 device-width = <2>;
109 };
110
111 nand@2,0 {
112 #address-cells = <1>;
113 #size-cells = <1>;
114 compatible = "fsl,elbc-fcm-nand";
115 reg = <0x2 0x0 0x40000>;
116
117 partition@0 {
118 label = "NAND U-Boot Image";
119 reg = <0x0 0x02000000>;
120 read-only;
121 };
122
123 partition@2000000 {
124 label = "NAND Root File System";
125 reg = <0x02000000 0x10000000>;
126 };
127
128 partition@12000000 {
129 label = "NAND Compressed RFS Image";
130 reg = <0x12000000 0x08000000>;
131 };
132
133 partition@1a000000 {
134 label = "NAND Linux Kernel Image";
135 reg = <0x1a000000 0x04000000>;
136 };
137
138 partition@1e000000 {
139 label = "NAND DTB Image";
140 reg = <0x1e000000 0x01000000>;
141 };
142
143 partition@1f000000 {
144 label = "NAND Writable User area";
145 reg = <0x1f000000 0x21000000>;
146 };
147 };
148
149 board-control@3,0 {
150 compatible = "fsl,p5020ds-pixis";
151 reg = <3 0 0x20>;
152 };
153 };
154
155 pci0: pcie@ffe200000 {
156 reg = <0xf 0xfe200000 0 0x1000>;
157 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
158 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
159
160 pcie@0 {
161 ranges = <0x02000000 0 0xe0000000
162 0x02000000 0 0xe0000000
163 0 0x20000000
164
165 0x01000000 0 0x00000000
166 0x01000000 0 0x00000000
167 0 0x00010000>;
168 };
169 };
170
171 pci1: pcie@ffe201000 {
172 reg = <0xf 0xfe201000 0 0x1000>;
173 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
174 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
175 pcie@0 {
176 ranges = <0x02000000 0 0xe0000000
177 0x02000000 0 0xe0000000
178 0 0x20000000
179
180 0x01000000 0 0x00000000
181 0x01000000 0 0x00000000
182 0 0x00010000>;
183 };
184 };
185
186 pci2: pcie@ffe202000 {
187 reg = <0xf 0xfe202000 0 0x1000>;
188 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
189 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
190 pcie@0 {
191 ranges = <0x02000000 0 0xe0000000
192 0x02000000 0 0xe0000000
193 0 0x20000000
194
195 0x01000000 0 0x00000000
196 0x01000000 0 0x00000000
197 0 0x00010000>;
198 };
199 };
200
201 pci3: pcie@ffe203000 {
202 reg = <0xf 0xfe203000 0 0x1000>;
203 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
204 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
205 pcie@0 {
206 ranges = <0x02000000 0 0xe0000000
207 0x02000000 0 0xe0000000
208 0 0x20000000
209
210 0x01000000 0 0x00000000
211 0x01000000 0 0x00000000
212 0 0x00010000>;
213 };
214 };
215};