1/*
  2 * P2040RDB Device Tree Source
  3 *
  4 * Copyright 2011 Freescale Semiconductor Inc.
  5 *
  6 * Redistribution and use in source and binary forms, with or without
  7 * modification, are permitted provided that the following conditions are met:
  8 *     * Redistributions of source code must retain the above copyright
  9 *       notice, this list of conditions and the following disclaimer.
 10 *     * Redistributions in binary form must reproduce the above copyright
 11 *       notice, this list of conditions and the following disclaimer in the
 12 *       documentation and/or other materials provided with the distribution.
 13 *     * Neither the name of Freescale Semiconductor nor the
 14 *       names of its contributors may be used to endorse or promote products
 15 *       derived from this software without specific prior written permission.
 16 *
 17 *
 18 * ALTERNATIVELY, this software may be distributed under the terms of the
 19 * GNU General Public License ("GPL") as published by the Free Software
 20 * Foundation, either version 2 of that License or (at your option) any
 21 * later version.
 22 *
 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 33 */
 34
 35/include/ "p2040si.dtsi"
 36
 37/ {
 38	model = "fsl,P2040RDB";
 39	compatible = "fsl,P2040RDB";
 40	#address-cells = <2>;
 41	#size-cells = <2>;
 42	interrupt-parent = <&mpic>;
 43
 44	memory {
 45		device_type = "memory";
 46	};
 47
 48	soc: soc@ffe000000 {
 49		spi@110000 {
 50			flash@0 {
 51				#address-cells = <1>;
 52				#size-cells = <1>;
 53				compatible = "spansion,s25sl12801";
 54				reg = <0>;
 55				spi-max-frequency = <40000000>; /* input clock */
 56				partition@u-boot {
 57					label = "u-boot";
 58					reg = <0x00000000 0x00100000>;
 59					read-only;
 60				};
 61				partition@kernel {
 62					label = "kernel";
 63					reg = <0x00100000 0x00500000>;
 64					read-only;
 65				};
 66				partition@dtb {
 67					label = "dtb";
 68					reg = <0x00600000 0x00100000>;
 69					read-only;
 70				};
 71				partition@fs {
 72					label = "file system";
 73					reg = <0x00700000 0x00900000>;
 74				};
 75			};
 76		};
 77
 78		i2c@118000 {
 79			lm75b@48 {
 80				compatible = "nxp,lm75a";
 81				reg = <0x48>;
 82			};
 83			eeprom@50 {
 84				compatible = "at24,24c256";
 85				reg = <0x50>;
 86			};
 87			rtc@68 {
 88				compatible = "pericom,pt7c4338";
 89				reg = <0x68>;
 90			};
 91		};
 92
 93		i2c@118100 {
 94			eeprom@50 {
 95				compatible = "at24,24c256";
 96				reg = <0x50>;
 97			};
 98		};
 99
100		usb0: usb@210000 {
101			phy_type = "utmi";
102		};
103
104		usb1: usb@211000 {
105			dr_mode = "host";
106			phy_type = "utmi";
107		};
108	};
109
110	localbus@ffe124000 {
111		reg = <0xf 0xfe124000 0 0x1000>;
112		ranges = <0 0 0xf 0xe8000000 0x08000000>;
113
114		flash@0,0 {
115			compatible = "cfi-flash";
116			reg = <0 0 0x08000000>;
117			bank-width = <2>;
118			device-width = <2>;
119		};
120	};
121
122	pci0: pcie@ffe200000 {
123		reg = <0xf 0xfe200000 0 0x1000>;
124		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
125			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
126		pcie@0 {
127			ranges = <0x02000000 0 0xe0000000
128				  0x02000000 0 0xe0000000
129				  0 0x20000000
130
131				  0x01000000 0 0x00000000
132				  0x01000000 0 0x00000000
133				  0 0x00010000>;
134		};
135	};
136
137	pci1: pcie@ffe201000 {
138		reg = <0xf 0xfe201000 0 0x1000>;
139		ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
140			  0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
141		pcie@0 {
142			ranges = <0x02000000 0 0xe0000000
143				  0x02000000 0 0xe0000000
144				  0 0x20000000
145
146				  0x01000000 0 0x00000000
147				  0x01000000 0 0x00000000
148				  0 0x00010000>;
149		};
150	};
151
152	pci2: pcie@ffe202000 {
153		reg = <0xf 0xfe202000 0 0x1000>;
154		ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
155			  0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
156		pcie@0 {
157			ranges = <0x02000000 0 0xe0000000
158				  0x02000000 0 0xe0000000
159				  0 0x20000000
160
161				  0x01000000 0 0x00000000
162				  0x01000000 0 0x00000000
163				  0 0x00010000>;
164		};
165	};
166};