1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  4 */
  5
  6#include <linux/init.h>
  7#include <linux/device.h>
  8#include <linux/errno.h>
  9#include <linux/io.h>
 10#include <linux/irqchip.h>
 11#include <linux/irqdomain.h>
 12#include <linux/of.h>
 13#include <linux/of_address.h>
 14
 15#include <asm/mach/irq.h>
 16#include <asm/exception.h>
 17
 18#include "common.h"
 19#include "hardware.h"
 20#include "irq-common.h"
 21
 22/*
 23 *****************************************
 24 * TZIC Registers                        *
 25 *****************************************
 26 */
 27
 28#define TZIC_INTCNTL	0x0000	/* Control register */
 29#define TZIC_INTTYPE	0x0004	/* Controller Type register */
 30#define TZIC_IMPID	0x0008	/* Distributor Implementer Identification */
 31#define TZIC_PRIOMASK	0x000C	/* Priority Mask Reg */
 32#define TZIC_SYNCCTRL	0x0010	/* Synchronizer Control register */
 33#define TZIC_DSMINT	0x0014	/* DSM interrupt Holdoffregister */
 34#define TZIC_INTSEC0(i)	(0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */
 35#define TZIC_ENSET0(i)	(0x0100 + ((i) << 2)) /* Enable Set Reg 0 */
 36#define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */
 37#define TZIC_SRCSET0	0x0200	/* Source Set Register 0 */
 38#define TZIC_SRCCLAR0	0x0280	/* Source Clear Register 0 */
 39#define TZIC_PRIORITY0	0x0400	/* Priority Register 0 */
 40#define TZIC_PND0	0x0D00	/* Pending Register 0 */
 41#define TZIC_HIPND(i)	(0x0D80+ ((i) << 2))	/* High Priority Pending Register */
 42#define TZIC_WAKEUP0(i)	(0x0E00 + ((i) << 2))	/* Wakeup Config Register */
 43#define TZIC_SWINT	0x0F00	/* Software Interrupt Rigger Register */
 44#define TZIC_ID0	0x0FD0	/* Indentification Register 0 */
 45
 46static void __iomem *tzic_base;
 47static struct irq_domain *domain;
 48
 49#define TZIC_NUM_IRQS 128
 50
 51#ifdef CONFIG_FIQ
 52static int tzic_set_irq_fiq(unsigned int hwirq, unsigned int type)
 53{
 54	unsigned int index, mask, value;
 55
 56	index = hwirq >> 5;
 57	if (unlikely(index >= 4))
 58		return -EINVAL;
 59	mask = 1U << (hwirq & 0x1F);
 60
 61	value = imx_readl(tzic_base + TZIC_INTSEC0(index)) | mask;
 62	if (type)
 63		value &= ~mask;
 64	imx_writel(value, tzic_base + TZIC_INTSEC0(index));
 65
 66	return 0;
 67}
 68#else
 69#define tzic_set_irq_fiq NULL
 70#endif
 71
 72#ifdef CONFIG_PM
 73static void tzic_irq_suspend(struct irq_data *d)
 74{
 75	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 76	int idx = d->hwirq >> 5;
 77
 78	imx_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx));
 79}
 80
 81static void tzic_irq_resume(struct irq_data *d)
 82{
 83	int idx = d->hwirq >> 5;
 84
 85	imx_writel(imx_readl(tzic_base + TZIC_ENSET0(idx)),
 86		   tzic_base + TZIC_WAKEUP0(idx));
 87}
 88
 89#else
 90#define tzic_irq_suspend NULL
 91#define tzic_irq_resume NULL
 92#endif
 93
 94static struct mxc_extra_irq tzic_extra_irq = {
 95#ifdef CONFIG_FIQ
 96	.set_irq_fiq = tzic_set_irq_fiq,
 97#endif
 98};
 99
100static __init void tzic_init_gc(int idx, unsigned int irq_start)
101{
102	struct irq_chip_generic *gc;
103	struct irq_chip_type *ct;
104
105	gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
106				    handle_level_irq);
107	gc->private = &tzic_extra_irq;
108	gc->wake_enabled = IRQ_MSK(32);
109
110	ct = gc->chip_types;
111	ct->chip.irq_mask = irq_gc_mask_disable_reg;
112	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
113	ct->chip.irq_set_wake = irq_gc_set_wake;
114	ct->chip.irq_suspend = tzic_irq_suspend;
115	ct->chip.irq_resume = tzic_irq_resume;
116	ct->regs.disable = TZIC_ENCLEAR0(idx);
117	ct->regs.enable = TZIC_ENSET0(idx);
118
119	irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
120}
121
122static void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
123{
124	u32 stat;
125	int i, irqofs, handled;
126
127	do {
128		handled = 0;
129
130		for (i = 0; i < 4; i++) {
131			stat = imx_readl(tzic_base + TZIC_HIPND(i)) &
132				imx_readl(tzic_base + TZIC_INTSEC0(i));
133
134			while (stat) {
135				handled = 1;
136				irqofs = fls(stat) - 1;
137				generic_handle_domain_irq(domain, irqofs + i * 32);
138				stat &= ~(1 << irqofs);
139			}
140		}
141	} while (handled);
142}
143
144/*
145 * This function initializes the TZIC hardware and disables all the
146 * interrupts. It registers the interrupt enable and disable functions
147 * to the kernel for each interrupt source.
148 */
149static int __init tzic_init_dt(struct device_node *np, struct device_node *p)
150{
151	int irq_base;
152	int i;
153
154	tzic_base = of_iomap(np, 0);
155	WARN_ON(!tzic_base);
156
157	/* put the TZIC into the reset value with
158	 * all interrupts disabled
159	 */
160	i = imx_readl(tzic_base + TZIC_INTCNTL);
161
162	imx_writel(0x80010001, tzic_base + TZIC_INTCNTL);
163	imx_writel(0x1f, tzic_base + TZIC_PRIOMASK);
164	imx_writel(0x02, tzic_base + TZIC_SYNCCTRL);
165
166	for (i = 0; i < 4; i++)
167		imx_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));
168
169	/* disable all interrupts */
170	for (i = 0; i < 4; i++)
171		imx_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));
172
173	/* all IRQ no FIQ Warning :: No selection */
174
175	irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id());
176	WARN_ON(irq_base < 0);
177
178	domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0,
179				       &irq_domain_simple_ops, NULL);
180	WARN_ON(!domain);
181
182	for (i = 0; i < 4; i++, irq_base += 32)
183		tzic_init_gc(i, irq_base);
184
185	set_handle_irq(tzic_handle_irq);
186
187#ifdef CONFIG_FIQ
188	/* Initialize FIQ */
189	init_FIQ(FIQ_START);
190#endif
191
192	pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
193
194	return 0;
195}
196IRQCHIP_DECLARE(tzic, "fsl,tzic", tzic_init_dt);
197
198/**
199 * tzic_enable_wake() - enable wakeup interrupt
200 *
201 * @return			0 if successful; non-zero otherwise
202 *
203 * This function provides an interrupt synchronization point that is required
204 * by tzic enabled platforms before entering imx specific low power modes (ie,
205 * those low power modes beyond the WAIT_CLOCKED basic ARM WFI only mode).
206 */
207int tzic_enable_wake(void)
208{
209	unsigned int i;
210
211	imx_writel(1, tzic_base + TZIC_DSMINT);
212	if (unlikely(imx_readl(tzic_base + TZIC_DSMINT) == 0))
213		return -EAGAIN;
214
215	for (i = 0; i < 4; i++)
216		imx_writel(imx_readl(tzic_base + TZIC_ENSET0(i)),
217			   tzic_base + TZIC_WAKEUP0(i));
218
219	return 0;
220}