1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 *  Copyright (C) 2012 Marvell Technology Group Ltd.
  4 *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
  5 */
  6
  7#include <dt-bindings/clock/marvell,pxa168.h>
  8
  9/ {
 10	#address-cells = <1>;
 11	#size-cells = <1>;
 12
 13	aliases {
 14		serial0 = &uart1;
 15		serial1 = &uart2;
 16		serial2 = &uart3;
 17		i2c0 = &twsi1;
 18		i2c1 = &twsi2;
 19	};
 20
 21	soc {
 22		#address-cells = <1>;
 23		#size-cells = <1>;
 24		compatible = "simple-bus";
 25		interrupt-parent = <&intc>;
 26		ranges;
 27
 28		axi@d4200000 {	/* AXI */
 29			compatible = "mrvl,axi-bus", "simple-bus";
 30			#address-cells = <1>;
 31			#size-cells = <1>;
 32			reg = <0xd4200000 0x00200000>;
 33			ranges;
 34
 35			intc: interrupt-controller@d4282000 {
 36				compatible = "mrvl,mmp-intc";
 37				interrupt-controller;
 38				#interrupt-cells = <1>;
 39				reg = <0xd4282000 0x1000>;
 40				mrvl,intc-nr-irqs = <64>;
 41			};
 42
 43		};
 44
 45		apb@d4000000 {	/* APB */
 46			compatible = "mrvl,apb-bus", "simple-bus";
 47			#address-cells = <1>;
 48			#size-cells = <1>;
 49			reg = <0xd4000000 0x00200000>;
 50			ranges;
 51
 52			timer0: timer@d4014000 {
 53				compatible = "mrvl,mmp-timer";
 54				reg = <0xd4014000 0x100>;
 55				interrupts = <13>;
 56				clocks = <&soc_clocks PXA168_CLK_TIMER>;
 57				resets = <&soc_clocks PXA168_CLK_TIMER>;
 58			};
 59
 60			uart1: serial@d4017000 {
 61				compatible = "mrvl,mmp-uart", "intel,xscale-uart";
 62				reg = <0xd4017000 0x1000>;
 63				reg-shift = <2>;
 64				interrupts = <27>;
 65				clocks = <&soc_clocks PXA168_CLK_UART0>;
 66				resets = <&soc_clocks PXA168_CLK_UART0>;
 67				status = "disabled";
 68			};
 69
 70			uart2: serial@d4018000 {
 71				compatible = "mrvl,mmp-uart", "intel,xscale-uart";
 72				reg = <0xd4018000 0x1000>;
 73				reg-shift = <2>;
 74				interrupts = <28>;
 75				clocks = <&soc_clocks PXA168_CLK_UART1>;
 76				resets = <&soc_clocks PXA168_CLK_UART1>;
 77				status = "disabled";
 78			};
 79
 80			uart3: serial@d4026000 {
 81				compatible = "mrvl,mmp-uart", "intel,xscale-uart";
 82				reg = <0xd4026000 0x1000>;
 83				reg-shift = <2>;
 84				interrupts = <29>;
 85				clocks = <&soc_clocks PXA168_CLK_UART2>;
 86				resets = <&soc_clocks PXA168_CLK_UART2>;
 87				status = "disabled";
 88			};
 89
 90			gpio@d4019000 {
 91				compatible = "marvell,mmp-gpio";
 92				#address-cells = <1>;
 93				#size-cells = <1>;
 94				reg = <0xd4019000 0x1000>;
 95				gpio-controller;
 96				#gpio-cells = <2>;
 97				interrupts = <49>;
 98				clocks = <&soc_clocks PXA168_CLK_GPIO>;
 99				resets = <&soc_clocks PXA168_CLK_GPIO>;
100				interrupt-names = "gpio_mux";
101				interrupt-controller;
102				#interrupt-cells = <2>;
103				ranges;
104
105				gcb0: gpio@d4019000 {
106					reg = <0xd4019000 0x4>;
107				};
108
109				gcb1: gpio@d4019004 {
110					reg = <0xd4019004 0x4>;
111				};
112
113				gcb2: gpio@d4019008 {
114					reg = <0xd4019008 0x4>;
115				};
116
117				gcb3: gpio@d4019100 {
118					reg = <0xd4019100 0x4>;
119				};
120			};
121
122			twsi1: i2c@d4011000 {
123				compatible = "mrvl,mmp-twsi";
124				#address-cells = <1>;
125				#size-cells = <0>;
126				reg = <0xd4011000 0x1000>;
127				interrupts = <7>;
128				clocks = <&soc_clocks PXA168_CLK_TWSI0>;
129				resets = <&soc_clocks PXA168_CLK_TWSI0>;
130				mrvl,i2c-fast-mode;
131				status = "disabled";
132			};
133
134			twsi2: i2c@d4025000 {
135				compatible = "mrvl,mmp-twsi";
136				#address-cells = <1>;
137				#size-cells = <0>;
138				reg = <0xd4025000 0x1000>;
139				interrupts = <58>;
140				clocks = <&soc_clocks PXA168_CLK_TWSI1>;
141				resets = <&soc_clocks PXA168_CLK_TWSI1>;
142				status = "disabled";
143			};
144
145			rtc: rtc@d4010000 {
146				compatible = "mrvl,mmp-rtc";
147				reg = <0xd4010000 0x1000>;
148				interrupts = <5>, <6>;
149				interrupt-names = "rtc 1Hz", "rtc alarm";
150				clocks = <&soc_clocks PXA168_CLK_RTC>;
151				resets = <&soc_clocks PXA168_CLK_RTC>;
152				status = "disabled";
153			};
154		};
155
156		soc_clocks: clocks{
157			compatible = "marvell,pxa168-clock";
158			reg = <0xd4050000 0x1000>,
159			      <0xd4282800 0x400>,
160			      <0xd4015000 0x1000>;
161			reg-names = "mpmu", "apmu", "apbc";
162			#clock-cells = <1>;
163			#reset-cells = <1>;
164		};
165	};
166};