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1// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2// Copyright 2021 Jonathan Neuschäfer
3
4#include <dt-bindings/interrupt-controller/irq.h>
5
6/ {
7 compatible = "nuvoton,wpcm450";
8 #address-cells = <1>;
9 #size-cells = <1>;
10
11 aliases {
12 gpio0 = &gpio0;
13 gpio1 = &gpio1;
14 gpio2 = &gpio2;
15 gpio3 = &gpio3;
16 gpio4 = &gpio4;
17 gpio5 = &gpio5;
18 gpio6 = &gpio6;
19 gpio7 = &gpio7;
20 };
21
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 cpu@0 {
27 compatible = "arm,arm926ej-s";
28 device_type = "cpu";
29 reg = <0>;
30 };
31 };
32
33 clk24m: clock-24mhz {
34 /* 24 MHz dummy clock */
35 compatible = "fixed-clock";
36 clock-frequency = <24000000>;
37 #clock-cells = <0>;
38 };
39
40 refclk: clock-48mhz {
41 /* 48 MHz reference oscillator */
42 compatible = "fixed-clock";
43 clock-output-names = "ref";
44 clock-frequency = <48000000>;
45 #clock-cells = <0>;
46 };
47
48 soc {
49 compatible = "simple-bus";
50 #address-cells = <1>;
51 #size-cells = <1>;
52 interrupt-parent = <&aic>;
53 ranges;
54
55 gcr: syscon@b0000000 {
56 compatible = "nuvoton,wpcm450-gcr", "syscon", "simple-mfd";
57 reg = <0xb0000000 0x200>;
58 };
59
60 clk: clock-controller@b0000200 {
61 compatible = "nuvoton,wpcm450-clk";
62 reg = <0xb0000200 0x100>;
63 clocks = <&refclk>;
64 clock-names = "ref";
65 #clock-cells = <1>;
66 #reset-cells = <1>;
67 };
68
69 serial0: serial@b8000000 {
70 compatible = "nuvoton,wpcm450-uart";
71 reg = <0xb8000000 0x20>;
72 reg-shift = <2>;
73 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
74 clocks = <&clk24m>;
75 pinctrl-names = "default";
76 pinctrl-0 = <&bsp_pins>;
77 status = "disabled";
78 };
79
80 serial1: serial@b8000100 {
81 compatible = "nuvoton,wpcm450-uart";
82 reg = <0xb8000100 0x20>;
83 reg-shift = <2>;
84 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
85 clocks = <&clk24m>;
86 status = "disabled";
87 };
88
89 timer0: timer@b8001000 {
90 compatible = "nuvoton,wpcm450-timer";
91 interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
92 reg = <0xb8001000 0x1c>;
93 clocks = <&clk24m>;
94 };
95
96 watchdog0: watchdog@b800101c {
97 compatible = "nuvoton,wpcm450-wdt";
98 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
99 reg = <0xb800101c 0x4>;
100 clocks = <&clk24m>;
101 };
102
103 aic: interrupt-controller@b8002000 {
104 compatible = "nuvoton,wpcm450-aic";
105 reg = <0xb8002000 0x1000>;
106 interrupt-controller;
107 #interrupt-cells = <2>;
108 };
109
110 pinctrl: pinctrl@b8003000 {
111 compatible = "nuvoton,wpcm450-pinctrl";
112 reg = <0xb8003000 0x1000>;
113 #address-cells = <1>;
114 #size-cells = <0>;
115
116 gpio0: gpio@0 {
117 reg = <0>;
118 gpio-controller;
119 #gpio-cells = <2>;
120 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
121 <3 IRQ_TYPE_LEVEL_HIGH>,
122 <4 IRQ_TYPE_LEVEL_HIGH>;
123 interrupt-controller;
124 };
125
126 gpio1: gpio@1 {
127 reg = <1>;
128 gpio-controller;
129 #gpio-cells = <2>;
130 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
131 interrupt-controller;
132 };
133
134 gpio2: gpio@2 {
135 reg = <2>;
136 gpio-controller;
137 #gpio-cells = <2>;
138 };
139
140 gpio3: gpio@3 {
141 reg = <3>;
142 gpio-controller;
143 #gpio-cells = <2>;
144 };
145
146 gpio4: gpio@4 {
147 reg = <4>;
148 gpio-controller;
149 #gpio-cells = <2>;
150 };
151
152 gpio5: gpio@5 {
153 reg = <5>;
154 gpio-controller;
155 #gpio-cells = <2>;
156 };
157
158 gpio6: gpio@6 {
159 reg = <6>;
160 gpio-controller;
161 #gpio-cells = <2>;
162 };
163
164 gpio7: gpio@7 {
165 reg = <7>;
166 gpio-controller;
167 #gpio-cells = <2>;
168 };
169
170 smb3_pins: mux-smb3 {
171 groups = "smb3";
172 function = "smb3";
173 };
174
175 smb4_pins: mux-smb4 {
176 groups = "smb4";
177 function = "smb4";
178 };
179
180 smb5_pins: mux-smb5 {
181 groups = "smb5";
182 function = "smb5";
183 };
184
185 scs1_pins: mux-scs1 {
186 groups = "scs1";
187 function = "scs1";
188 };
189
190 scs2_pins: mux-scs2 {
191 groups = "scs2";
192 function = "scs2";
193 };
194
195 scs3_pins: mux-scs3 {
196 groups = "scs3";
197 function = "scs3";
198 };
199
200 smb0_pins: mux-smb0 {
201 groups = "smb0";
202 function = "smb0";
203 };
204
205 smb1_pins: mux-smb1 {
206 groups = "smb1";
207 function = "smb1";
208 };
209
210 smb2_pins: mux-smb2 {
211 groups = "smb2";
212 function = "smb2";
213 };
214
215 bsp_pins: mux-bsp {
216 groups = "bsp";
217 function = "bsp";
218 };
219
220 hsp1_pins: mux-hsp1 {
221 groups = "hsp1";
222 function = "hsp1";
223 };
224
225 hsp2_pins: mux-hsp2 {
226 groups = "hsp2";
227 function = "hsp2";
228 };
229
230 r1err_pins: mux-r1err {
231 groups = "r1err";
232 function = "r1err";
233 };
234
235 r1md_pins: mux-r1md {
236 groups = "r1md";
237 function = "r1md";
238 };
239
240 rmii2_pins: mux-rmii2 {
241 groups = "rmii2";
242 function = "rmii2";
243 };
244
245 r2err_pins: mux-r2err {
246 groups = "r2err";
247 function = "r2err";
248 };
249
250 r2md_pins: mux-r2md {
251 groups = "r2md";
252 function = "r2md";
253 };
254
255 kbcc_pins: mux-kbcc {
256 groups = "kbcc";
257 function = "kbcc";
258 };
259
260 dvo0_pins: mux-dvo0 {
261 groups = "dvo";
262 function = "dvo0";
263 };
264
265 dvo3_pins: mux-dvo3 {
266 groups = "dvo";
267 function = "dvo3";
268 };
269
270 clko_pins: mux-clko {
271 groups = "clko";
272 function = "clko";
273 };
274
275 smi_pins: mux-smi {
276 groups = "smi";
277 function = "smi";
278 };
279
280 uinc_pins: mux-uinc {
281 groups = "uinc";
282 function = "uinc";
283 };
284
285 gspi_pins: mux-gspi {
286 groups = "gspi";
287 function = "gspi";
288 };
289
290 mben_pins: mux-mben {
291 groups = "mben";
292 function = "mben";
293 };
294
295 xcs2_pins: mux-xcs2 {
296 groups = "xcs2";
297 function = "xcs2";
298 };
299
300 xcs1_pins: mux-xcs1 {
301 groups = "xcs1";
302 function = "xcs1";
303 };
304
305 sdio_pins: mux-sdio {
306 groups = "sdio";
307 function = "sdio";
308 };
309
310 sspi_pins: mux-sspi {
311 groups = "sspi";
312 function = "sspi";
313 };
314
315 fi0_pins: mux-fi0 {
316 groups = "fi0";
317 function = "fi0";
318 };
319
320 fi1_pins: mux-fi1 {
321 groups = "fi1";
322 function = "fi1";
323 };
324
325 fi2_pins: mux-fi2 {
326 groups = "fi2";
327 function = "fi2";
328 };
329
330 fi3_pins: mux-fi3 {
331 groups = "fi3";
332 function = "fi3";
333 };
334
335 fi4_pins: mux-fi4 {
336 groups = "fi4";
337 function = "fi4";
338 };
339
340 fi5_pins: mux-fi5 {
341 groups = "fi5";
342 function = "fi5";
343 };
344
345 fi6_pins: mux-fi6 {
346 groups = "fi6";
347 function = "fi6";
348 };
349
350 fi7_pins: mux-fi7 {
351 groups = "fi7";
352 function = "fi7";
353 };
354
355 fi8_pins: mux-fi8 {
356 groups = "fi8";
357 function = "fi8";
358 };
359
360 fi9_pins: mux-fi9 {
361 groups = "fi9";
362 function = "fi9";
363 };
364
365 fi10_pins: mux-fi10 {
366 groups = "fi10";
367 function = "fi10";
368 };
369
370 fi11_pins: mux-fi11 {
371 groups = "fi11";
372 function = "fi11";
373 };
374
375 fi12_pins: mux-fi12 {
376 groups = "fi12";
377 function = "fi12";
378 };
379
380 fi13_pins: mux-fi13 {
381 groups = "fi13";
382 function = "fi13";
383 };
384
385 fi14_pins: mux-fi14 {
386 groups = "fi14";
387 function = "fi14";
388 };
389
390 fi15_pins: mux-fi15 {
391 groups = "fi15";
392 function = "fi15";
393 };
394
395 pwm0_pins: mux-pwm0 {
396 groups = "pwm0";
397 function = "pwm0";
398 };
399
400 pwm1_pins: mux-pwm1 {
401 groups = "pwm1";
402 function = "pwm1";
403 };
404
405 pwm2_pins: mux-pwm2 {
406 groups = "pwm2";
407 function = "pwm2";
408 };
409
410 pwm3_pins: mux-pwm3 {
411 groups = "pwm3";
412 function = "pwm3";
413 };
414
415 pwm4_pins: mux-pwm4 {
416 groups = "pwm4";
417 function = "pwm4";
418 };
419
420 pwm5_pins: mux-pwm5 {
421 groups = "pwm5";
422 function = "pwm5";
423 };
424
425 pwm6_pins: mux-pwm6 {
426 groups = "pwm6";
427 function = "pwm6";
428 };
429
430 pwm7_pins: mux-pwm7 {
431 groups = "pwm7";
432 function = "pwm7";
433 };
434
435 hg0_pins: mux-hg0 {
436 groups = "hg0";
437 function = "hg0";
438 };
439
440 hg1_pins: mux-hg1 {
441 groups = "hg1";
442 function = "hg1";
443 };
444
445 hg2_pins: mux-hg2 {
446 groups = "hg2";
447 function = "hg2";
448 };
449
450 hg3_pins: mux-hg3 {
451 groups = "hg3";
452 function = "hg3";
453 };
454
455 hg4_pins: mux-hg4 {
456 groups = "hg4";
457 function = "hg4";
458 };
459
460 hg5_pins: mux-hg5 {
461 groups = "hg5";
462 function = "hg5";
463 };
464
465 hg6_pins: mux-hg6 {
466 groups = "hg6";
467 function = "hg6";
468 };
469
470 hg7_pins: mux-hg7 {
471 groups = "hg7";
472 function = "hg7";
473 };
474 };
475
476 fiu: spi-controller@c8000000 {
477 compatible = "nuvoton,wpcm450-fiu";
478 #address-cells = <1>;
479 #size-cells = <0>;
480 reg = <0xc8000000 0x1000>, <0xc0000000 0x4000000>;
481 reg-names = "control", "memory";
482 clocks = <&clk 0>;
483 nuvoton,shm = <&shm>;
484 status = "disabled";
485 };
486
487 shm: syscon@c8001000 {
488 compatible = "nuvoton,wpcm450-shm", "syscon";
489 reg = <0xc8001000 0x1000>;
490 reg-io-width = <1>;
491 };
492 };
493};