1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates.
  4 * Synopsys DesignWare XPCS helpers
  5 *
  6 * Author: Jose Abreu <Jose.Abreu@synopsys.com>
  7 */
  8
  9#define SYNOPSYS_XPCS_ID		0x7996ced0
 10#define SYNOPSYS_XPCS_MASK		0xffffffff
 11
 12/* Vendor regs access */
 13#define DW_VENDOR			BIT(15)
 14
 15/* VR_XS_PCS */
 16#define DW_USXGMII_RST			BIT(10)
 17#define DW_USXGMII_EN			BIT(9)
 18#define DW_VR_XS_PCS_DIG_STS		0x0010
 19#define DW_RXFIFO_ERR			GENMASK(6, 5)
 20
 21/* SR_MII */
 22#define DW_USXGMII_FULL			BIT(8)
 23#define DW_USXGMII_SS_MASK		(BIT(13) | BIT(6) | BIT(5))
 24#define DW_USXGMII_10000		(BIT(13) | BIT(6))
 25#define DW_USXGMII_5000			(BIT(13) | BIT(5))
 26#define DW_USXGMII_2500			(BIT(5))
 27#define DW_USXGMII_1000			(BIT(6))
 28#define DW_USXGMII_100			(BIT(13))
 29#define DW_USXGMII_10			(0)
 30
 31/* SR_AN */
 32#define DW_SR_AN_ADV1			0x10
 33#define DW_SR_AN_ADV2			0x11
 34#define DW_SR_AN_ADV3			0x12
 35#define DW_SR_AN_LP_ABL1		0x13
 36#define DW_SR_AN_LP_ABL2		0x14
 37#define DW_SR_AN_LP_ABL3		0x15
 38
 39/* Clause 73 Defines */
 40/* AN_LP_ABL1 */
 41#define DW_C73_PAUSE			BIT(10)
 42#define DW_C73_ASYM_PAUSE		BIT(11)
 43#define DW_C73_AN_ADV_SF		0x1
 44/* AN_LP_ABL2 */
 45#define DW_C73_1000KX			BIT(5)
 46#define DW_C73_10000KX4			BIT(6)
 47#define DW_C73_10000KR			BIT(7)
 48/* AN_LP_ABL3 */
 49#define DW_C73_2500KX			BIT(0)
 50#define DW_C73_5000KR			BIT(1)
 51
 52/* Clause 37 Defines */
 53/* VR MII MMD registers offsets */
 54#define DW_VR_MII_MMD_CTRL		0x0000
 55#define DW_VR_MII_DIG_CTRL1		0x8000
 56#define DW_VR_MII_AN_CTRL		0x8001
 57#define DW_VR_MII_AN_INTR_STS		0x8002
 58/* Enable 2.5G Mode */
 59#define DW_VR_MII_DIG_CTRL1_2G5_EN	BIT(2)
 60/* EEE Mode Control Register */
 61#define DW_VR_MII_EEE_MCTRL0		0x8006
 62#define DW_VR_MII_EEE_MCTRL1		0x800b
 63#define DW_VR_MII_DIG_CTRL2		0x80e1
 64
 65/* VR_MII_DIG_CTRL1 */
 66#define DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW		BIT(9)
 67
 68/* VR_MII_DIG_CTRL2 */
 69#define DW_VR_MII_DIG_CTRL2_TX_POL_INV		BIT(4)
 70#define DW_VR_MII_DIG_CTRL2_RX_POL_INV		BIT(0)
 71
 72/* VR_MII_AN_CTRL */
 73#define DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT	3
 74#define DW_VR_MII_TX_CONFIG_MASK		BIT(3)
 75#define DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII	0x1
 76#define DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII	0x0
 77#define DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT	1
 78#define DW_VR_MII_PCS_MODE_MASK			GENMASK(2, 1)
 79#define DW_VR_MII_PCS_MODE_C37_1000BASEX	0x0
 80#define DW_VR_MII_PCS_MODE_C37_SGMII		0x2
 81
 82/* VR_MII_AN_INTR_STS */
 83#define DW_VR_MII_AN_STS_C37_ANSGM_FD		BIT(1)
 84#define DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT	2
 85#define DW_VR_MII_AN_STS_C37_ANSGM_SP		GENMASK(3, 2)
 86#define DW_VR_MII_C37_ANSGM_SP_10		0x0
 87#define DW_VR_MII_C37_ANSGM_SP_100		0x1
 88#define DW_VR_MII_C37_ANSGM_SP_1000		0x2
 89#define DW_VR_MII_C37_ANSGM_SP_LNKSTS		BIT(4)
 90
 91/* SR MII MMD Control defines */
 92#define AN_CL37_EN			BIT(12)	/* Enable Clause 37 auto-nego */
 93#define SGMII_SPEED_SS13		BIT(13)	/* SGMII speed along with SS6 */
 94#define SGMII_SPEED_SS6			BIT(6)	/* SGMII speed along with SS13 */
 95
 96/* VR MII EEE Control 0 defines */
 97#define DW_VR_MII_EEE_LTX_EN			BIT(0)  /* LPI Tx Enable */
 98#define DW_VR_MII_EEE_LRX_EN			BIT(1)  /* LPI Rx Enable */
 99#define DW_VR_MII_EEE_TX_QUIET_EN		BIT(2)  /* Tx Quiet Enable */
100#define DW_VR_MII_EEE_RX_QUIET_EN		BIT(3)  /* Rx Quiet Enable */
101#define DW_VR_MII_EEE_TX_EN_CTRL		BIT(4)  /* Tx Control Enable */
102#define DW_VR_MII_EEE_RX_EN_CTRL		BIT(7)  /* Rx Control Enable */
103
104#define DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT	8
105#define DW_VR_MII_EEE_MULT_FACT_100NS		GENMASK(11, 8)
106
107/* VR MII EEE Control 1 defines */
108#define DW_VR_MII_EEE_TRN_LPI		BIT(0)	/* Transparent Mode Enable */
109
110int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg);
111int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val);
112int nxp_sja1105_sgmii_pma_config(struct dw_xpcs *xpcs);
113int nxp_sja1110_sgmii_pma_config(struct dw_xpcs *xpcs);
114int nxp_sja1110_2500basex_pma_config(struct dw_xpcs *xpcs);