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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * davinci_mmc.c - TI DaVinci MMC/SD/SDIO driver
4 *
5 * Copyright (C) 2006 Texas Instruments.
6 * Original author: Purushotam Kumar
7 * Copyright (C) 2009 David Brownell
8 */
9
10#include <linux/module.h>
11#include <linux/ioport.h>
12#include <linux/platform_device.h>
13#include <linux/clk.h>
14#include <linux/err.h>
15#include <linux/cpufreq.h>
16#include <linux/mmc/host.h>
17#include <linux/io.h>
18#include <linux/irq.h>
19#include <linux/delay.h>
20#include <linux/dmaengine.h>
21#include <linux/dma-mapping.h>
22#include <linux/mmc/mmc.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
25#include <linux/mmc/slot-gpio.h>
26#include <linux/interrupt.h>
27
28#include <linux/platform_data/mmc-davinci.h>
29
30/*
31 * Register Definitions
32 */
33#define DAVINCI_MMCCTL 0x00 /* Control Register */
34#define DAVINCI_MMCCLK 0x04 /* Memory Clock Control Register */
35#define DAVINCI_MMCST0 0x08 /* Status Register 0 */
36#define DAVINCI_MMCST1 0x0C /* Status Register 1 */
37#define DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */
38#define DAVINCI_MMCTOR 0x14 /* Response Time-Out Register */
39#define DAVINCI_MMCTOD 0x18 /* Data Read Time-Out Register */
40#define DAVINCI_MMCBLEN 0x1C /* Block Length Register */
41#define DAVINCI_MMCNBLK 0x20 /* Number of Blocks Register */
42#define DAVINCI_MMCNBLC 0x24 /* Number of Blocks Counter Register */
43#define DAVINCI_MMCDRR 0x28 /* Data Receive Register */
44#define DAVINCI_MMCDXR 0x2C /* Data Transmit Register */
45#define DAVINCI_MMCCMD 0x30 /* Command Register */
46#define DAVINCI_MMCARGHL 0x34 /* Argument Register */
47#define DAVINCI_MMCRSP01 0x38 /* Response Register 0 and 1 */
48#define DAVINCI_MMCRSP23 0x3C /* Response Register 0 and 1 */
49#define DAVINCI_MMCRSP45 0x40 /* Response Register 0 and 1 */
50#define DAVINCI_MMCRSP67 0x44 /* Response Register 0 and 1 */
51#define DAVINCI_MMCDRSP 0x48 /* Data Response Register */
52#define DAVINCI_MMCETOK 0x4C
53#define DAVINCI_MMCCIDX 0x50 /* Command Index Register */
54#define DAVINCI_MMCCKC 0x54
55#define DAVINCI_MMCTORC 0x58
56#define DAVINCI_MMCTODC 0x5C
57#define DAVINCI_MMCBLNC 0x60
58#define DAVINCI_SDIOCTL 0x64
59#define DAVINCI_SDIOST0 0x68
60#define DAVINCI_SDIOIEN 0x6C
61#define DAVINCI_SDIOIST 0x70
62#define DAVINCI_MMCFIFOCTL 0x74 /* FIFO Control Register */
63
64/* DAVINCI_MMCCTL definitions */
65#define MMCCTL_DATRST (1 << 0)
66#define MMCCTL_CMDRST (1 << 1)
67#define MMCCTL_WIDTH_8_BIT (1 << 8)
68#define MMCCTL_WIDTH_4_BIT (1 << 2)
69#define MMCCTL_DATEG_DISABLED (0 << 6)
70#define MMCCTL_DATEG_RISING (1 << 6)
71#define MMCCTL_DATEG_FALLING (2 << 6)
72#define MMCCTL_DATEG_BOTH (3 << 6)
73#define MMCCTL_PERMDR_LE (0 << 9)
74#define MMCCTL_PERMDR_BE (1 << 9)
75#define MMCCTL_PERMDX_LE (0 << 10)
76#define MMCCTL_PERMDX_BE (1 << 10)
77
78/* DAVINCI_MMCCLK definitions */
79#define MMCCLK_CLKEN (1 << 8)
80#define MMCCLK_CLKRT_MASK (0xFF << 0)
81
82/* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */
83#define MMCST0_DATDNE BIT(0) /* data done */
84#define MMCST0_BSYDNE BIT(1) /* busy done */
85#define MMCST0_RSPDNE BIT(2) /* command done */
86#define MMCST0_TOUTRD BIT(3) /* data read timeout */
87#define MMCST0_TOUTRS BIT(4) /* command response timeout */
88#define MMCST0_CRCWR BIT(5) /* data write CRC error */
89#define MMCST0_CRCRD BIT(6) /* data read CRC error */
90#define MMCST0_CRCRS BIT(7) /* command response CRC error */
91#define MMCST0_DXRDY BIT(9) /* data transmit ready (fifo empty) */
92#define MMCST0_DRRDY BIT(10) /* data receive ready (data in fifo)*/
93#define MMCST0_DATED BIT(11) /* DAT3 edge detect */
94#define MMCST0_TRNDNE BIT(12) /* transfer done */
95
96/* DAVINCI_MMCST1 definitions */
97#define MMCST1_BUSY (1 << 0)
98
99/* DAVINCI_MMCCMD definitions */
100#define MMCCMD_CMD_MASK (0x3F << 0)
101#define MMCCMD_PPLEN (1 << 7)
102#define MMCCMD_BSYEXP (1 << 8)
103#define MMCCMD_RSPFMT_MASK (3 << 9)
104#define MMCCMD_RSPFMT_NONE (0 << 9)
105#define MMCCMD_RSPFMT_R1456 (1 << 9)
106#define MMCCMD_RSPFMT_R2 (2 << 9)
107#define MMCCMD_RSPFMT_R3 (3 << 9)
108#define MMCCMD_DTRW (1 << 11)
109#define MMCCMD_STRMTP (1 << 12)
110#define MMCCMD_WDATX (1 << 13)
111#define MMCCMD_INITCK (1 << 14)
112#define MMCCMD_DCLR (1 << 15)
113#define MMCCMD_DMATRIG (1 << 16)
114
115/* DAVINCI_MMCFIFOCTL definitions */
116#define MMCFIFOCTL_FIFORST (1 << 0)
117#define MMCFIFOCTL_FIFODIR_WR (1 << 1)
118#define MMCFIFOCTL_FIFODIR_RD (0 << 1)
119#define MMCFIFOCTL_FIFOLEV (1 << 2) /* 0 = 128 bits, 1 = 256 bits */
120#define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */
121#define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */
122#define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */
123#define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */
124
125/* DAVINCI_SDIOST0 definitions */
126#define SDIOST0_DAT1_HI BIT(0)
127
128/* DAVINCI_SDIOIEN definitions */
129#define SDIOIEN_IOINTEN BIT(0)
130
131/* DAVINCI_SDIOIST definitions */
132#define SDIOIST_IOINT BIT(0)
133
134/* MMCSD Init clock in Hz in opendrain mode */
135#define MMCSD_INIT_CLOCK 200000
136
137/*
138 * One scatterlist dma "segment" is at most MAX_CCNT rw_threshold units,
139 * and we handle up to MAX_NR_SG segments. MMC_BLOCK_BOUNCE kicks in only
140 * for drivers with max_segs == 1, making the segments bigger (64KB)
141 * than the page or two that's otherwise typical. nr_sg (passed from
142 * platform data) == 16 gives at least the same throughput boost, using
143 * EDMA transfer linkage instead of spending CPU time copying pages.
144 */
145#define MAX_CCNT ((1 << 16) - 1)
146
147#define MAX_NR_SG 16
148
149static unsigned rw_threshold = 32;
150module_param(rw_threshold, uint, S_IRUGO);
151MODULE_PARM_DESC(rw_threshold,
152 "Read/Write threshold. Default = 32");
153
154static unsigned poll_threshold = 128;
155module_param(poll_threshold, uint, S_IRUGO);
156MODULE_PARM_DESC(poll_threshold,
157 "Polling transaction size threshold. Default = 128");
158
159static unsigned poll_loopcount = 32;
160module_param(poll_loopcount, uint, S_IRUGO);
161MODULE_PARM_DESC(poll_loopcount,
162 "Maximum polling loop count. Default = 32");
163
164static unsigned use_dma = 1;
165module_param(use_dma, uint, 0);
166MODULE_PARM_DESC(use_dma, "Whether to use DMA or not. Default = 1");
167
168struct mmc_davinci_host {
169 struct mmc_command *cmd;
170 struct mmc_data *data;
171 struct mmc_host *mmc;
172 struct clk *clk;
173 unsigned int mmc_input_clk;
174 void __iomem *base;
175 struct resource *mem_res;
176 int mmc_irq, sdio_irq;
177 unsigned char bus_mode;
178
179#define DAVINCI_MMC_DATADIR_NONE 0
180#define DAVINCI_MMC_DATADIR_READ 1
181#define DAVINCI_MMC_DATADIR_WRITE 2
182 unsigned char data_dir;
183
184 /* buffer is used during PIO of one scatterlist segment, and
185 * is updated along with buffer_bytes_left. bytes_left applies
186 * to all N blocks of the PIO transfer.
187 */
188 u8 *buffer;
189 u32 buffer_bytes_left;
190 u32 bytes_left;
191
192 struct dma_chan *dma_tx;
193 struct dma_chan *dma_rx;
194 bool use_dma;
195 bool do_dma;
196 bool sdio_int;
197 bool active_request;
198
199 /* For PIO we walk scatterlists one segment at a time. */
200 unsigned int sg_len;
201 struct scatterlist *sg;
202
203 /* Version of the MMC/SD controller */
204 u8 version;
205 /* for ns in one cycle calculation */
206 unsigned ns_in_one_cycle;
207 /* Number of sg segments */
208 u8 nr_sg;
209#ifdef CONFIG_CPU_FREQ
210 struct notifier_block freq_transition;
211#endif
212};
213
214static irqreturn_t mmc_davinci_irq(int irq, void *dev_id);
215
216/* PIO only */
217static void mmc_davinci_sg_to_buf(struct mmc_davinci_host *host)
218{
219 host->buffer_bytes_left = sg_dma_len(host->sg);
220 host->buffer = sg_virt(host->sg);
221 if (host->buffer_bytes_left > host->bytes_left)
222 host->buffer_bytes_left = host->bytes_left;
223}
224
225static void davinci_fifo_data_trans(struct mmc_davinci_host *host,
226 unsigned int n)
227{
228 u8 *p;
229 unsigned int i;
230
231 if (host->buffer_bytes_left == 0) {
232 host->sg = sg_next(host->data->sg);
233 mmc_davinci_sg_to_buf(host);
234 }
235
236 p = host->buffer;
237 if (n > host->buffer_bytes_left)
238 n = host->buffer_bytes_left;
239 host->buffer_bytes_left -= n;
240 host->bytes_left -= n;
241
242 /* NOTE: we never transfer more than rw_threshold bytes
243 * to/from the fifo here; there's no I/O overlap.
244 * This also assumes that access width( i.e. ACCWD) is 4 bytes
245 */
246 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
247 for (i = 0; i < (n >> 2); i++) {
248 writel(*((u32 *)p), host->base + DAVINCI_MMCDXR);
249 p = p + 4;
250 }
251 if (n & 3) {
252 iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3));
253 p = p + (n & 3);
254 }
255 } else {
256 for (i = 0; i < (n >> 2); i++) {
257 *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR);
258 p = p + 4;
259 }
260 if (n & 3) {
261 ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3));
262 p = p + (n & 3);
263 }
264 }
265 host->buffer = p;
266}
267
268static void mmc_davinci_start_command(struct mmc_davinci_host *host,
269 struct mmc_command *cmd)
270{
271 u32 cmd_reg = 0;
272 u32 im_val;
273
274 dev_dbg(mmc_dev(host->mmc), "CMD%d, arg 0x%08x%s\n",
275 cmd->opcode, cmd->arg,
276 ({ char *s;
277 switch (mmc_resp_type(cmd)) {
278 case MMC_RSP_R1:
279 s = ", R1/R5/R6/R7 response";
280 break;
281 case MMC_RSP_R1B:
282 s = ", R1b response";
283 break;
284 case MMC_RSP_R2:
285 s = ", R2 response";
286 break;
287 case MMC_RSP_R3:
288 s = ", R3/R4 response";
289 break;
290 default:
291 s = ", (R? response)";
292 break;
293 } s; }));
294 host->cmd = cmd;
295
296 switch (mmc_resp_type(cmd)) {
297 case MMC_RSP_R1B:
298 /* There's some spec confusion about when R1B is
299 * allowed, but if the card doesn't issue a BUSY
300 * then it's harmless for us to allow it.
301 */
302 cmd_reg |= MMCCMD_BSYEXP;
303 fallthrough;
304 case MMC_RSP_R1: /* 48 bits, CRC */
305 cmd_reg |= MMCCMD_RSPFMT_R1456;
306 break;
307 case MMC_RSP_R2: /* 136 bits, CRC */
308 cmd_reg |= MMCCMD_RSPFMT_R2;
309 break;
310 case MMC_RSP_R3: /* 48 bits, no CRC */
311 cmd_reg |= MMCCMD_RSPFMT_R3;
312 break;
313 default:
314 cmd_reg |= MMCCMD_RSPFMT_NONE;
315 dev_dbg(mmc_dev(host->mmc), "unknown resp_type %04x\n",
316 mmc_resp_type(cmd));
317 break;
318 }
319
320 /* Set command index */
321 cmd_reg |= cmd->opcode;
322
323 /* Enable EDMA transfer triggers */
324 if (host->do_dma)
325 cmd_reg |= MMCCMD_DMATRIG;
326
327 if (host->version == MMC_CTLR_VERSION_2 && host->data != NULL &&
328 host->data_dir == DAVINCI_MMC_DATADIR_READ)
329 cmd_reg |= MMCCMD_DMATRIG;
330
331 /* Setting whether command involves data transfer or not */
332 if (cmd->data)
333 cmd_reg |= MMCCMD_WDATX;
334
335 /* Setting whether data read or write */
336 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)
337 cmd_reg |= MMCCMD_DTRW;
338
339 if (host->bus_mode == MMC_BUSMODE_PUSHPULL)
340 cmd_reg |= MMCCMD_PPLEN;
341
342 /* set Command timeout */
343 writel(0x1FFF, host->base + DAVINCI_MMCTOR);
344
345 /* Enable interrupt (calculate here, defer until FIFO is stuffed). */
346 im_val = MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS;
347 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
348 im_val |= MMCST0_DATDNE | MMCST0_CRCWR;
349
350 if (!host->do_dma)
351 im_val |= MMCST0_DXRDY;
352 } else if (host->data_dir == DAVINCI_MMC_DATADIR_READ) {
353 im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD;
354
355 if (!host->do_dma)
356 im_val |= MMCST0_DRRDY;
357 }
358
359 /*
360 * Before non-DMA WRITE commands the controller needs priming:
361 * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size
362 */
363 if (!host->do_dma && (host->data_dir == DAVINCI_MMC_DATADIR_WRITE))
364 davinci_fifo_data_trans(host, rw_threshold);
365
366 writel(cmd->arg, host->base + DAVINCI_MMCARGHL);
367 writel(cmd_reg, host->base + DAVINCI_MMCCMD);
368
369 host->active_request = true;
370
371 if (!host->do_dma && host->bytes_left <= poll_threshold) {
372 u32 count = poll_loopcount;
373
374 while (host->active_request && count--) {
375 mmc_davinci_irq(0, host);
376 cpu_relax();
377 }
378 }
379
380 if (host->active_request)
381 writel(im_val, host->base + DAVINCI_MMCIM);
382}
383
384/*----------------------------------------------------------------------*/
385
386/* DMA infrastructure */
387
388static void davinci_abort_dma(struct mmc_davinci_host *host)
389{
390 struct dma_chan *sync_dev;
391
392 if (host->data_dir == DAVINCI_MMC_DATADIR_READ)
393 sync_dev = host->dma_rx;
394 else
395 sync_dev = host->dma_tx;
396
397 dmaengine_terminate_all(sync_dev);
398}
399
400static int mmc_davinci_send_dma_request(struct mmc_davinci_host *host,
401 struct mmc_data *data)
402{
403 struct dma_chan *chan;
404 struct dma_async_tx_descriptor *desc;
405 int ret = 0;
406
407 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
408 struct dma_slave_config dma_tx_conf = {
409 .direction = DMA_MEM_TO_DEV,
410 .dst_addr = host->mem_res->start + DAVINCI_MMCDXR,
411 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
412 .dst_maxburst =
413 rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES,
414 };
415 chan = host->dma_tx;
416 dmaengine_slave_config(host->dma_tx, &dma_tx_conf);
417
418 desc = dmaengine_prep_slave_sg(host->dma_tx,
419 data->sg,
420 host->sg_len,
421 DMA_MEM_TO_DEV,
422 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
423 if (!desc) {
424 dev_dbg(mmc_dev(host->mmc),
425 "failed to allocate DMA TX descriptor");
426 ret = -1;
427 goto out;
428 }
429 } else {
430 struct dma_slave_config dma_rx_conf = {
431 .direction = DMA_DEV_TO_MEM,
432 .src_addr = host->mem_res->start + DAVINCI_MMCDRR,
433 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
434 .src_maxburst =
435 rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES,
436 };
437 chan = host->dma_rx;
438 dmaengine_slave_config(host->dma_rx, &dma_rx_conf);
439
440 desc = dmaengine_prep_slave_sg(host->dma_rx,
441 data->sg,
442 host->sg_len,
443 DMA_DEV_TO_MEM,
444 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
445 if (!desc) {
446 dev_dbg(mmc_dev(host->mmc),
447 "failed to allocate DMA RX descriptor");
448 ret = -1;
449 goto out;
450 }
451 }
452
453 dmaengine_submit(desc);
454 dma_async_issue_pending(chan);
455
456out:
457 return ret;
458}
459
460static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host,
461 struct mmc_data *data)
462{
463 int i;
464 int mask = rw_threshold - 1;
465 int ret = 0;
466
467 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
468 mmc_get_dma_dir(data));
469
470 /* no individual DMA segment should need a partial FIFO */
471 for (i = 0; i < host->sg_len; i++) {
472 if (sg_dma_len(data->sg + i) & mask) {
473 dma_unmap_sg(mmc_dev(host->mmc),
474 data->sg, data->sg_len,
475 mmc_get_dma_dir(data));
476 return -1;
477 }
478 }
479
480 host->do_dma = 1;
481 ret = mmc_davinci_send_dma_request(host, data);
482
483 return ret;
484}
485
486static void davinci_release_dma_channels(struct mmc_davinci_host *host)
487{
488 if (!host->use_dma)
489 return;
490
491 dma_release_channel(host->dma_tx);
492 dma_release_channel(host->dma_rx);
493}
494
495static int davinci_acquire_dma_channels(struct mmc_davinci_host *host)
496{
497 host->dma_tx = dma_request_chan(mmc_dev(host->mmc), "tx");
498 if (IS_ERR(host->dma_tx)) {
499 dev_err(mmc_dev(host->mmc), "Can't get dma_tx channel\n");
500 return PTR_ERR(host->dma_tx);
501 }
502
503 host->dma_rx = dma_request_chan(mmc_dev(host->mmc), "rx");
504 if (IS_ERR(host->dma_rx)) {
505 dev_err(mmc_dev(host->mmc), "Can't get dma_rx channel\n");
506 dma_release_channel(host->dma_tx);
507 return PTR_ERR(host->dma_rx);
508 }
509
510 return 0;
511}
512
513/*----------------------------------------------------------------------*/
514
515static void
516mmc_davinci_prepare_data(struct mmc_davinci_host *host, struct mmc_request *req)
517{
518 int fifo_lev = (rw_threshold == 32) ? MMCFIFOCTL_FIFOLEV : 0;
519 int timeout;
520 struct mmc_data *data = req->data;
521
522 if (host->version == MMC_CTLR_VERSION_2)
523 fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0;
524
525 host->data = data;
526 if (data == NULL) {
527 host->data_dir = DAVINCI_MMC_DATADIR_NONE;
528 writel(0, host->base + DAVINCI_MMCBLEN);
529 writel(0, host->base + DAVINCI_MMCNBLK);
530 return;
531 }
532
533 dev_dbg(mmc_dev(host->mmc), "%s, %d blocks of %d bytes\n",
534 (data->flags & MMC_DATA_WRITE) ? "write" : "read",
535 data->blocks, data->blksz);
536 dev_dbg(mmc_dev(host->mmc), " DTO %d cycles + %d ns\n",
537 data->timeout_clks, data->timeout_ns);
538 timeout = data->timeout_clks +
539 (data->timeout_ns / host->ns_in_one_cycle);
540 if (timeout > 0xffff)
541 timeout = 0xffff;
542
543 writel(timeout, host->base + DAVINCI_MMCTOD);
544 writel(data->blocks, host->base + DAVINCI_MMCNBLK);
545 writel(data->blksz, host->base + DAVINCI_MMCBLEN);
546
547 /* Configure the FIFO */
548 if (data->flags & MMC_DATA_WRITE) {
549 host->data_dir = DAVINCI_MMC_DATADIR_WRITE;
550 writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST,
551 host->base + DAVINCI_MMCFIFOCTL);
552 writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR,
553 host->base + DAVINCI_MMCFIFOCTL);
554 } else {
555 host->data_dir = DAVINCI_MMC_DATADIR_READ;
556 writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST,
557 host->base + DAVINCI_MMCFIFOCTL);
558 writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD,
559 host->base + DAVINCI_MMCFIFOCTL);
560 }
561
562 host->buffer = NULL;
563 host->bytes_left = data->blocks * data->blksz;
564
565 /* For now we try to use DMA whenever we won't need partial FIFO
566 * reads or writes, either for the whole transfer (as tested here)
567 * or for any individual scatterlist segment (tested when we call
568 * start_dma_transfer).
569 *
570 * While we *could* change that, unusual block sizes are rarely
571 * used. The occasional fallback to PIO should't hurt.
572 */
573 if (host->use_dma && (host->bytes_left & (rw_threshold - 1)) == 0
574 && mmc_davinci_start_dma_transfer(host, data) == 0) {
575 /* zero this to ensure we take no PIO paths */
576 host->bytes_left = 0;
577 } else {
578 /* Revert to CPU Copy */
579 host->sg_len = data->sg_len;
580 host->sg = host->data->sg;
581 mmc_davinci_sg_to_buf(host);
582 }
583}
584
585static void mmc_davinci_request(struct mmc_host *mmc, struct mmc_request *req)
586{
587 struct mmc_davinci_host *host = mmc_priv(mmc);
588 unsigned long timeout = jiffies + msecs_to_jiffies(900);
589 u32 mmcst1 = 0;
590
591 /* Card may still be sending BUSY after a previous operation,
592 * typically some kind of write. If so, we can't proceed yet.
593 */
594 while (time_before(jiffies, timeout)) {
595 mmcst1 = readl(host->base + DAVINCI_MMCST1);
596 if (!(mmcst1 & MMCST1_BUSY))
597 break;
598 cpu_relax();
599 }
600 if (mmcst1 & MMCST1_BUSY) {
601 dev_err(mmc_dev(host->mmc), "still BUSY? bad ... \n");
602 req->cmd->error = -ETIMEDOUT;
603 mmc_request_done(mmc, req);
604 return;
605 }
606
607 host->do_dma = 0;
608 mmc_davinci_prepare_data(host, req);
609 mmc_davinci_start_command(host, req->cmd);
610}
611
612static unsigned int calculate_freq_for_card(struct mmc_davinci_host *host,
613 unsigned int mmc_req_freq)
614{
615 unsigned int mmc_freq = 0, mmc_pclk = 0, mmc_push_pull_divisor = 0;
616
617 mmc_pclk = host->mmc_input_clk;
618 if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq))
619 mmc_push_pull_divisor = ((unsigned int)mmc_pclk
620 / (2 * mmc_req_freq)) - 1;
621 else
622 mmc_push_pull_divisor = 0;
623
624 mmc_freq = (unsigned int)mmc_pclk
625 / (2 * (mmc_push_pull_divisor + 1));
626
627 if (mmc_freq > mmc_req_freq)
628 mmc_push_pull_divisor = mmc_push_pull_divisor + 1;
629 /* Convert ns to clock cycles */
630 if (mmc_req_freq <= 400000)
631 host->ns_in_one_cycle = (1000000) / (((mmc_pclk
632 / (2 * (mmc_push_pull_divisor + 1)))/1000));
633 else
634 host->ns_in_one_cycle = (1000000) / (((mmc_pclk
635 / (2 * (mmc_push_pull_divisor + 1)))/1000000));
636
637 return mmc_push_pull_divisor;
638}
639
640static void calculate_clk_divider(struct mmc_host *mmc, struct mmc_ios *ios)
641{
642 unsigned int open_drain_freq = 0, mmc_pclk = 0;
643 unsigned int mmc_push_pull_freq = 0;
644 struct mmc_davinci_host *host = mmc_priv(mmc);
645
646 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
647 u32 temp;
648
649 /* Ignoring the init clock value passed for fixing the inter
650 * operability with different cards.
651 */
652 open_drain_freq = ((unsigned int)mmc_pclk
653 / (2 * MMCSD_INIT_CLOCK)) - 1;
654
655 if (open_drain_freq > 0xFF)
656 open_drain_freq = 0xFF;
657
658 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK;
659 temp |= open_drain_freq;
660 writel(temp, host->base + DAVINCI_MMCCLK);
661
662 /* Convert ns to clock cycles */
663 host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK/1000);
664 } else {
665 u32 temp;
666 mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock);
667
668 if (mmc_push_pull_freq > 0xFF)
669 mmc_push_pull_freq = 0xFF;
670
671 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN;
672 writel(temp, host->base + DAVINCI_MMCCLK);
673
674 udelay(10);
675
676 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK;
677 temp |= mmc_push_pull_freq;
678 writel(temp, host->base + DAVINCI_MMCCLK);
679
680 writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);
681
682 udelay(10);
683 }
684}
685
686static void mmc_davinci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
687{
688 struct mmc_davinci_host *host = mmc_priv(mmc);
689 struct platform_device *pdev = to_platform_device(mmc->parent);
690 struct davinci_mmc_config *config = pdev->dev.platform_data;
691
692 dev_dbg(mmc_dev(host->mmc),
693 "clock %dHz busmode %d powermode %d Vdd %04x\n",
694 ios->clock, ios->bus_mode, ios->power_mode,
695 ios->vdd);
696
697 switch (ios->power_mode) {
698 case MMC_POWER_OFF:
699 if (config && config->set_power)
700 config->set_power(pdev->id, false);
701 break;
702 case MMC_POWER_UP:
703 if (config && config->set_power)
704 config->set_power(pdev->id, true);
705 break;
706 }
707
708 switch (ios->bus_width) {
709 case MMC_BUS_WIDTH_8:
710 dev_dbg(mmc_dev(host->mmc), "Enabling 8 bit mode\n");
711 writel((readl(host->base + DAVINCI_MMCCTL) &
712 ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT,
713 host->base + DAVINCI_MMCCTL);
714 break;
715 case MMC_BUS_WIDTH_4:
716 dev_dbg(mmc_dev(host->mmc), "Enabling 4 bit mode\n");
717 if (host->version == MMC_CTLR_VERSION_2)
718 writel((readl(host->base + DAVINCI_MMCCTL) &
719 ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT,
720 host->base + DAVINCI_MMCCTL);
721 else
722 writel(readl(host->base + DAVINCI_MMCCTL) |
723 MMCCTL_WIDTH_4_BIT,
724 host->base + DAVINCI_MMCCTL);
725 break;
726 case MMC_BUS_WIDTH_1:
727 dev_dbg(mmc_dev(host->mmc), "Enabling 1 bit mode\n");
728 if (host->version == MMC_CTLR_VERSION_2)
729 writel(readl(host->base + DAVINCI_MMCCTL) &
730 ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT),
731 host->base + DAVINCI_MMCCTL);
732 else
733 writel(readl(host->base + DAVINCI_MMCCTL) &
734 ~MMCCTL_WIDTH_4_BIT,
735 host->base + DAVINCI_MMCCTL);
736 break;
737 }
738
739 calculate_clk_divider(mmc, ios);
740
741 host->bus_mode = ios->bus_mode;
742 if (ios->power_mode == MMC_POWER_UP) {
743 unsigned long timeout = jiffies + msecs_to_jiffies(50);
744 bool lose = true;
745
746 /* Send clock cycles, poll completion */
747 writel(0, host->base + DAVINCI_MMCARGHL);
748 writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD);
749 while (time_before(jiffies, timeout)) {
750 u32 tmp = readl(host->base + DAVINCI_MMCST0);
751
752 if (tmp & MMCST0_RSPDNE) {
753 lose = false;
754 break;
755 }
756 cpu_relax();
757 }
758 if (lose)
759 dev_warn(mmc_dev(host->mmc), "powerup timeout\n");
760 }
761
762 /* FIXME on power OFF, reset things ... */
763}
764
765static void
766mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data)
767{
768 host->data = NULL;
769
770 if (host->mmc->caps & MMC_CAP_SDIO_IRQ) {
771 /*
772 * SDIO Interrupt Detection work-around as suggested by
773 * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata
774 * 2.1.6): Signal SDIO interrupt only if it is enabled by core
775 */
776 if (host->sdio_int && !(readl(host->base + DAVINCI_SDIOST0) &
777 SDIOST0_DAT1_HI)) {
778 writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
779 mmc_signal_sdio_irq(host->mmc);
780 }
781 }
782
783 if (host->do_dma) {
784 davinci_abort_dma(host);
785
786 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
787 mmc_get_dma_dir(data));
788 host->do_dma = false;
789 }
790 host->data_dir = DAVINCI_MMC_DATADIR_NONE;
791
792 if (!data->stop || (host->cmd && host->cmd->error)) {
793 mmc_request_done(host->mmc, data->mrq);
794 writel(0, host->base + DAVINCI_MMCIM);
795 host->active_request = false;
796 } else
797 mmc_davinci_start_command(host, data->stop);
798}
799
800static void mmc_davinci_cmd_done(struct mmc_davinci_host *host,
801 struct mmc_command *cmd)
802{
803 host->cmd = NULL;
804
805 if (cmd->flags & MMC_RSP_PRESENT) {
806 if (cmd->flags & MMC_RSP_136) {
807 /* response type 2 */
808 cmd->resp[3] = readl(host->base + DAVINCI_MMCRSP01);
809 cmd->resp[2] = readl(host->base + DAVINCI_MMCRSP23);
810 cmd->resp[1] = readl(host->base + DAVINCI_MMCRSP45);
811 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67);
812 } else {
813 /* response types 1, 1b, 3, 4, 5, 6 */
814 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67);
815 }
816 }
817
818 if (host->data == NULL || cmd->error) {
819 if (cmd->error == -ETIMEDOUT)
820 cmd->mrq->cmd->retries = 0;
821 mmc_request_done(host->mmc, cmd->mrq);
822 writel(0, host->base + DAVINCI_MMCIM);
823 host->active_request = false;
824 }
825}
826
827static inline void mmc_davinci_reset_ctrl(struct mmc_davinci_host *host,
828 int val)
829{
830 u32 temp;
831
832 temp = readl(host->base + DAVINCI_MMCCTL);
833 if (val) /* reset */
834 temp |= MMCCTL_CMDRST | MMCCTL_DATRST;
835 else /* enable */
836 temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST);
837
838 writel(temp, host->base + DAVINCI_MMCCTL);
839 udelay(10);
840}
841
842static void
843davinci_abort_data(struct mmc_davinci_host *host, struct mmc_data *data)
844{
845 mmc_davinci_reset_ctrl(host, 1);
846 mmc_davinci_reset_ctrl(host, 0);
847}
848
849static irqreturn_t mmc_davinci_sdio_irq(int irq, void *dev_id)
850{
851 struct mmc_davinci_host *host = dev_id;
852 unsigned int status;
853
854 status = readl(host->base + DAVINCI_SDIOIST);
855 if (status & SDIOIST_IOINT) {
856 dev_dbg(mmc_dev(host->mmc),
857 "SDIO interrupt status %x\n", status);
858 writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
859 mmc_signal_sdio_irq(host->mmc);
860 }
861 return IRQ_HANDLED;
862}
863
864static irqreturn_t mmc_davinci_irq(int irq, void *dev_id)
865{
866 struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id;
867 unsigned int status, qstatus;
868 int end_command = 0;
869 int end_transfer = 0;
870 struct mmc_data *data = host->data;
871
872 if (host->cmd == NULL && host->data == NULL) {
873 status = readl(host->base + DAVINCI_MMCST0);
874 dev_dbg(mmc_dev(host->mmc),
875 "Spurious interrupt 0x%04x\n", status);
876 /* Disable the interrupt from mmcsd */
877 writel(0, host->base + DAVINCI_MMCIM);
878 return IRQ_NONE;
879 }
880
881 status = readl(host->base + DAVINCI_MMCST0);
882 qstatus = status;
883
884 /* handle FIFO first when using PIO for data.
885 * bytes_left will decrease to zero as I/O progress and status will
886 * read zero over iteration because this controller status
887 * register(MMCST0) reports any status only once and it is cleared
888 * by read. So, it is not unbouned loop even in the case of
889 * non-dma.
890 */
891 if (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) {
892 unsigned long im_val;
893
894 /*
895 * If interrupts fire during the following loop, they will be
896 * handled by the handler, but the PIC will still buffer these.
897 * As a result, the handler will be called again to serve these
898 * needlessly. In order to avoid these spurious interrupts,
899 * keep interrupts masked during the loop.
900 */
901 im_val = readl(host->base + DAVINCI_MMCIM);
902 writel(0, host->base + DAVINCI_MMCIM);
903
904 do {
905 davinci_fifo_data_trans(host, rw_threshold);
906 status = readl(host->base + DAVINCI_MMCST0);
907 qstatus |= status;
908 } while (host->bytes_left &&
909 (status & (MMCST0_DXRDY | MMCST0_DRRDY)));
910
911 /*
912 * If an interrupt is pending, it is assumed it will fire when
913 * it is unmasked. This assumption is also taken when the MMCIM
914 * is first set. Otherwise, writing to MMCIM after reading the
915 * status is race-prone.
916 */
917 writel(im_val, host->base + DAVINCI_MMCIM);
918 }
919
920 if (qstatus & MMCST0_DATDNE) {
921 /* All blocks sent/received, and CRC checks passed */
922 if (data != NULL) {
923 if ((host->do_dma == 0) && (host->bytes_left > 0)) {
924 /* if datasize < rw_threshold
925 * no RX ints are generated
926 */
927 davinci_fifo_data_trans(host, host->bytes_left);
928 }
929 end_transfer = 1;
930 data->bytes_xfered = data->blocks * data->blksz;
931 } else {
932 dev_err(mmc_dev(host->mmc),
933 "DATDNE with no host->data\n");
934 }
935 }
936
937 if (qstatus & MMCST0_TOUTRD) {
938 /* Read data timeout */
939 data->error = -ETIMEDOUT;
940 end_transfer = 1;
941
942 dev_dbg(mmc_dev(host->mmc),
943 "read data timeout, status %x\n",
944 qstatus);
945
946 davinci_abort_data(host, data);
947 }
948
949 if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) {
950 /* Data CRC error */
951 data->error = -EILSEQ;
952 end_transfer = 1;
953
954 /* NOTE: this controller uses CRCWR to report both CRC
955 * errors and timeouts (on writes). MMCDRSP values are
956 * only weakly documented, but 0x9f was clearly a timeout
957 * case and the two three-bit patterns in various SD specs
958 * (101, 010) aren't part of it ...
959 */
960 if (qstatus & MMCST0_CRCWR) {
961 u32 temp = readb(host->base + DAVINCI_MMCDRSP);
962
963 if (temp == 0x9f)
964 data->error = -ETIMEDOUT;
965 }
966 dev_dbg(mmc_dev(host->mmc), "data %s %s error\n",
967 (qstatus & MMCST0_CRCWR) ? "write" : "read",
968 (data->error == -ETIMEDOUT) ? "timeout" : "CRC");
969
970 davinci_abort_data(host, data);
971 }
972
973 if (qstatus & MMCST0_TOUTRS) {
974 /* Command timeout */
975 if (host->cmd) {
976 dev_dbg(mmc_dev(host->mmc),
977 "CMD%d timeout, status %x\n",
978 host->cmd->opcode, qstatus);
979 host->cmd->error = -ETIMEDOUT;
980 if (data) {
981 end_transfer = 1;
982 davinci_abort_data(host, data);
983 } else
984 end_command = 1;
985 }
986 }
987
988 if (qstatus & MMCST0_CRCRS) {
989 /* Command CRC error */
990 dev_dbg(mmc_dev(host->mmc), "Command CRC error\n");
991 if (host->cmd) {
992 host->cmd->error = -EILSEQ;
993 end_command = 1;
994 }
995 }
996
997 if (qstatus & MMCST0_RSPDNE) {
998 /* End of command phase */
999 end_command = host->cmd ? 1 : 0;
1000 }
1001
1002 if (end_command)
1003 mmc_davinci_cmd_done(host, host->cmd);
1004 if (end_transfer)
1005 mmc_davinci_xfer_done(host, data);
1006 return IRQ_HANDLED;
1007}
1008
1009static int mmc_davinci_get_cd(struct mmc_host *mmc)
1010{
1011 struct platform_device *pdev = to_platform_device(mmc->parent);
1012 struct davinci_mmc_config *config = pdev->dev.platform_data;
1013
1014 if (config && config->get_cd)
1015 return config->get_cd(pdev->id);
1016
1017 return mmc_gpio_get_cd(mmc);
1018}
1019
1020static int mmc_davinci_get_ro(struct mmc_host *mmc)
1021{
1022 struct platform_device *pdev = to_platform_device(mmc->parent);
1023 struct davinci_mmc_config *config = pdev->dev.platform_data;
1024
1025 if (config && config->get_ro)
1026 return config->get_ro(pdev->id);
1027
1028 return mmc_gpio_get_ro(mmc);
1029}
1030
1031static void mmc_davinci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1032{
1033 struct mmc_davinci_host *host = mmc_priv(mmc);
1034
1035 if (enable) {
1036 if (!(readl(host->base + DAVINCI_SDIOST0) & SDIOST0_DAT1_HI)) {
1037 writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
1038 mmc_signal_sdio_irq(host->mmc);
1039 } else {
1040 host->sdio_int = true;
1041 writel(readl(host->base + DAVINCI_SDIOIEN) |
1042 SDIOIEN_IOINTEN, host->base + DAVINCI_SDIOIEN);
1043 }
1044 } else {
1045 host->sdio_int = false;
1046 writel(readl(host->base + DAVINCI_SDIOIEN) & ~SDIOIEN_IOINTEN,
1047 host->base + DAVINCI_SDIOIEN);
1048 }
1049}
1050
1051static const struct mmc_host_ops mmc_davinci_ops = {
1052 .request = mmc_davinci_request,
1053 .set_ios = mmc_davinci_set_ios,
1054 .get_cd = mmc_davinci_get_cd,
1055 .get_ro = mmc_davinci_get_ro,
1056 .enable_sdio_irq = mmc_davinci_enable_sdio_irq,
1057};
1058
1059/*----------------------------------------------------------------------*/
1060
1061#ifdef CONFIG_CPU_FREQ
1062static int mmc_davinci_cpufreq_transition(struct notifier_block *nb,
1063 unsigned long val, void *data)
1064{
1065 struct mmc_davinci_host *host;
1066 unsigned int mmc_pclk;
1067 struct mmc_host *mmc;
1068 unsigned long flags;
1069
1070 host = container_of(nb, struct mmc_davinci_host, freq_transition);
1071 mmc = host->mmc;
1072 mmc_pclk = clk_get_rate(host->clk);
1073
1074 if (val == CPUFREQ_POSTCHANGE) {
1075 spin_lock_irqsave(&mmc->lock, flags);
1076 host->mmc_input_clk = mmc_pclk;
1077 calculate_clk_divider(mmc, &mmc->ios);
1078 spin_unlock_irqrestore(&mmc->lock, flags);
1079 }
1080
1081 return 0;
1082}
1083
1084static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host)
1085{
1086 host->freq_transition.notifier_call = mmc_davinci_cpufreq_transition;
1087
1088 return cpufreq_register_notifier(&host->freq_transition,
1089 CPUFREQ_TRANSITION_NOTIFIER);
1090}
1091
1092static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host)
1093{
1094 cpufreq_unregister_notifier(&host->freq_transition,
1095 CPUFREQ_TRANSITION_NOTIFIER);
1096}
1097#else
1098static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host)
1099{
1100 return 0;
1101}
1102
1103static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host)
1104{
1105}
1106#endif
1107static void init_mmcsd_host(struct mmc_davinci_host *host)
1108{
1109
1110 mmc_davinci_reset_ctrl(host, 1);
1111
1112 writel(0, host->base + DAVINCI_MMCCLK);
1113 writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);
1114
1115 writel(0x1FFF, host->base + DAVINCI_MMCTOR);
1116 writel(0xFFFF, host->base + DAVINCI_MMCTOD);
1117
1118 mmc_davinci_reset_ctrl(host, 0);
1119}
1120
1121static const struct platform_device_id davinci_mmc_devtype[] = {
1122 {
1123 .name = "dm6441-mmc",
1124 .driver_data = MMC_CTLR_VERSION_1,
1125 }, {
1126 .name = "da830-mmc",
1127 .driver_data = MMC_CTLR_VERSION_2,
1128 },
1129 {},
1130};
1131MODULE_DEVICE_TABLE(platform, davinci_mmc_devtype);
1132
1133static const struct of_device_id davinci_mmc_dt_ids[] = {
1134 {
1135 .compatible = "ti,dm6441-mmc",
1136 .data = &davinci_mmc_devtype[MMC_CTLR_VERSION_1],
1137 },
1138 {
1139 .compatible = "ti,da830-mmc",
1140 .data = &davinci_mmc_devtype[MMC_CTLR_VERSION_2],
1141 },
1142 {},
1143};
1144MODULE_DEVICE_TABLE(of, davinci_mmc_dt_ids);
1145
1146static int mmc_davinci_parse_pdata(struct mmc_host *mmc)
1147{
1148 struct platform_device *pdev = to_platform_device(mmc->parent);
1149 struct davinci_mmc_config *pdata = pdev->dev.platform_data;
1150 struct mmc_davinci_host *host;
1151 int ret;
1152
1153 if (!pdata)
1154 return -EINVAL;
1155
1156 host = mmc_priv(mmc);
1157 if (!host)
1158 return -EINVAL;
1159
1160 if (pdata && pdata->nr_sg)
1161 host->nr_sg = pdata->nr_sg - 1;
1162
1163 if (pdata && (pdata->wires == 4 || pdata->wires == 0))
1164 mmc->caps |= MMC_CAP_4_BIT_DATA;
1165
1166 if (pdata && (pdata->wires == 8))
1167 mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA);
1168
1169 mmc->f_min = 312500;
1170 mmc->f_max = 25000000;
1171 if (pdata && pdata->max_freq)
1172 mmc->f_max = pdata->max_freq;
1173 if (pdata && pdata->caps)
1174 mmc->caps |= pdata->caps;
1175
1176 /* Register a cd gpio, if there is not one, enable polling */
1177 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0);
1178 if (ret == -EPROBE_DEFER)
1179 return ret;
1180 else if (ret)
1181 mmc->caps |= MMC_CAP_NEEDS_POLL;
1182
1183 ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0);
1184 if (ret == -EPROBE_DEFER)
1185 return ret;
1186
1187 return 0;
1188}
1189
1190static int davinci_mmcsd_probe(struct platform_device *pdev)
1191{
1192 struct mmc_davinci_host *host = NULL;
1193 struct mmc_host *mmc = NULL;
1194 struct resource *r, *mem = NULL;
1195 int ret, irq;
1196 size_t mem_size;
1197 const struct platform_device_id *id_entry;
1198
1199 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1200 if (!r)
1201 return -ENODEV;
1202 irq = platform_get_irq(pdev, 0);
1203 if (irq < 0)
1204 return irq;
1205
1206 mem_size = resource_size(r);
1207 mem = devm_request_mem_region(&pdev->dev, r->start, mem_size,
1208 pdev->name);
1209 if (!mem)
1210 return -EBUSY;
1211
1212 mmc = mmc_alloc_host(sizeof(struct mmc_davinci_host), &pdev->dev);
1213 if (!mmc)
1214 return -ENOMEM;
1215
1216 host = mmc_priv(mmc);
1217 host->mmc = mmc; /* Important */
1218
1219 host->mem_res = mem;
1220 host->base = devm_ioremap(&pdev->dev, mem->start, mem_size);
1221 if (!host->base) {
1222 ret = -ENOMEM;
1223 goto ioremap_fail;
1224 }
1225
1226 host->clk = devm_clk_get(&pdev->dev, NULL);
1227 if (IS_ERR(host->clk)) {
1228 ret = PTR_ERR(host->clk);
1229 goto clk_get_fail;
1230 }
1231 ret = clk_prepare_enable(host->clk);
1232 if (ret)
1233 goto clk_prepare_enable_fail;
1234
1235 host->mmc_input_clk = clk_get_rate(host->clk);
1236
1237 pdev->id_entry = of_device_get_match_data(&pdev->dev);
1238 if (pdev->id_entry) {
1239 ret = mmc_of_parse(mmc);
1240 if (ret) {
1241 dev_err_probe(&pdev->dev, ret,
1242 "could not parse of data\n");
1243 goto parse_fail;
1244 }
1245 } else {
1246 ret = mmc_davinci_parse_pdata(mmc);
1247 if (ret) {
1248 dev_err(&pdev->dev,
1249 "could not parse platform data: %d\n", ret);
1250 goto parse_fail;
1251 } }
1252
1253 if (host->nr_sg > MAX_NR_SG || !host->nr_sg)
1254 host->nr_sg = MAX_NR_SG;
1255
1256 init_mmcsd_host(host);
1257
1258 host->use_dma = use_dma;
1259 host->mmc_irq = irq;
1260 host->sdio_irq = platform_get_irq(pdev, 1);
1261
1262 if (host->use_dma) {
1263 ret = davinci_acquire_dma_channels(host);
1264 if (ret == -EPROBE_DEFER)
1265 goto dma_probe_defer;
1266 else if (ret)
1267 host->use_dma = 0;
1268 }
1269
1270 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1271
1272 id_entry = platform_get_device_id(pdev);
1273 if (id_entry)
1274 host->version = id_entry->driver_data;
1275
1276 mmc->ops = &mmc_davinci_ops;
1277 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1278
1279 /* With no iommu coalescing pages, each phys_seg is a hw_seg.
1280 * Each hw_seg uses one EDMA parameter RAM slot, always one
1281 * channel and then usually some linked slots.
1282 */
1283 mmc->max_segs = MAX_NR_SG;
1284
1285 /* EDMA limit per hw segment (one or two MBytes) */
1286 mmc->max_seg_size = MAX_CCNT * rw_threshold;
1287
1288 /* MMC/SD controller limits for multiblock requests */
1289 mmc->max_blk_size = 4095; /* BLEN is 12 bits */
1290 mmc->max_blk_count = 65535; /* NBLK is 16 bits */
1291 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1292
1293 dev_dbg(mmc_dev(host->mmc), "max_segs=%d\n", mmc->max_segs);
1294 dev_dbg(mmc_dev(host->mmc), "max_blk_size=%d\n", mmc->max_blk_size);
1295 dev_dbg(mmc_dev(host->mmc), "max_req_size=%d\n", mmc->max_req_size);
1296 dev_dbg(mmc_dev(host->mmc), "max_seg_size=%d\n", mmc->max_seg_size);
1297
1298 platform_set_drvdata(pdev, host);
1299
1300 ret = mmc_davinci_cpufreq_register(host);
1301 if (ret) {
1302 dev_err(&pdev->dev, "failed to register cpufreq\n");
1303 goto cpu_freq_fail;
1304 }
1305
1306 ret = mmc_add_host(mmc);
1307 if (ret < 0)
1308 goto mmc_add_host_fail;
1309
1310 ret = devm_request_irq(&pdev->dev, irq, mmc_davinci_irq, 0,
1311 mmc_hostname(mmc), host);
1312 if (ret)
1313 goto request_irq_fail;
1314
1315 if (host->sdio_irq >= 0) {
1316 ret = devm_request_irq(&pdev->dev, host->sdio_irq,
1317 mmc_davinci_sdio_irq, 0,
1318 mmc_hostname(mmc), host);
1319 if (!ret)
1320 mmc->caps |= MMC_CAP_SDIO_IRQ;
1321 }
1322
1323 rename_region(mem, mmc_hostname(mmc));
1324
1325 dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n",
1326 host->use_dma ? "DMA" : "PIO",
1327 (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1);
1328
1329 return 0;
1330
1331request_irq_fail:
1332 mmc_remove_host(mmc);
1333mmc_add_host_fail:
1334 mmc_davinci_cpufreq_deregister(host);
1335cpu_freq_fail:
1336 davinci_release_dma_channels(host);
1337parse_fail:
1338dma_probe_defer:
1339 clk_disable_unprepare(host->clk);
1340clk_prepare_enable_fail:
1341clk_get_fail:
1342ioremap_fail:
1343 mmc_free_host(mmc);
1344
1345 return ret;
1346}
1347
1348static int __exit davinci_mmcsd_remove(struct platform_device *pdev)
1349{
1350 struct mmc_davinci_host *host = platform_get_drvdata(pdev);
1351
1352 mmc_remove_host(host->mmc);
1353 mmc_davinci_cpufreq_deregister(host);
1354 davinci_release_dma_channels(host);
1355 clk_disable_unprepare(host->clk);
1356 mmc_free_host(host->mmc);
1357
1358 return 0;
1359}
1360
1361#ifdef CONFIG_PM
1362static int davinci_mmcsd_suspend(struct device *dev)
1363{
1364 struct mmc_davinci_host *host = dev_get_drvdata(dev);
1365
1366 writel(0, host->base + DAVINCI_MMCIM);
1367 mmc_davinci_reset_ctrl(host, 1);
1368 clk_disable(host->clk);
1369
1370 return 0;
1371}
1372
1373static int davinci_mmcsd_resume(struct device *dev)
1374{
1375 struct mmc_davinci_host *host = dev_get_drvdata(dev);
1376 int ret;
1377
1378 ret = clk_enable(host->clk);
1379 if (ret)
1380 return ret;
1381
1382 mmc_davinci_reset_ctrl(host, 0);
1383
1384 return 0;
1385}
1386
1387static const struct dev_pm_ops davinci_mmcsd_pm = {
1388 .suspend = davinci_mmcsd_suspend,
1389 .resume = davinci_mmcsd_resume,
1390};
1391
1392#define davinci_mmcsd_pm_ops (&davinci_mmcsd_pm)
1393#else
1394#define davinci_mmcsd_pm_ops NULL
1395#endif
1396
1397static struct platform_driver davinci_mmcsd_driver = {
1398 .driver = {
1399 .name = "davinci_mmc",
1400 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1401 .pm = davinci_mmcsd_pm_ops,
1402 .of_match_table = davinci_mmc_dt_ids,
1403 },
1404 .probe = davinci_mmcsd_probe,
1405 .remove = __exit_p(davinci_mmcsd_remove),
1406 .id_table = davinci_mmc_devtype,
1407};
1408
1409module_platform_driver(davinci_mmcsd_driver);
1410
1411MODULE_AUTHOR("Texas Instruments India");
1412MODULE_LICENSE("GPL");
1413MODULE_DESCRIPTION("MMC/SD driver for Davinci MMC controller");
1414MODULE_ALIAS("platform:davinci_mmc");
1415
1/*
2 * davinci_mmc.c - TI DaVinci MMC/SD/SDIO driver
3 *
4 * Copyright (C) 2006 Texas Instruments.
5 * Original author: Purushotam Kumar
6 * Copyright (C) 2009 David Brownell
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/module.h>
24#include <linux/ioport.h>
25#include <linux/platform_device.h>
26#include <linux/clk.h>
27#include <linux/err.h>
28#include <linux/cpufreq.h>
29#include <linux/mmc/host.h>
30#include <linux/io.h>
31#include <linux/irq.h>
32#include <linux/delay.h>
33#include <linux/dma-mapping.h>
34#include <linux/mmc/mmc.h>
35
36#include <mach/mmc.h>
37#include <mach/edma.h>
38
39/*
40 * Register Definitions
41 */
42#define DAVINCI_MMCCTL 0x00 /* Control Register */
43#define DAVINCI_MMCCLK 0x04 /* Memory Clock Control Register */
44#define DAVINCI_MMCST0 0x08 /* Status Register 0 */
45#define DAVINCI_MMCST1 0x0C /* Status Register 1 */
46#define DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */
47#define DAVINCI_MMCTOR 0x14 /* Response Time-Out Register */
48#define DAVINCI_MMCTOD 0x18 /* Data Read Time-Out Register */
49#define DAVINCI_MMCBLEN 0x1C /* Block Length Register */
50#define DAVINCI_MMCNBLK 0x20 /* Number of Blocks Register */
51#define DAVINCI_MMCNBLC 0x24 /* Number of Blocks Counter Register */
52#define DAVINCI_MMCDRR 0x28 /* Data Receive Register */
53#define DAVINCI_MMCDXR 0x2C /* Data Transmit Register */
54#define DAVINCI_MMCCMD 0x30 /* Command Register */
55#define DAVINCI_MMCARGHL 0x34 /* Argument Register */
56#define DAVINCI_MMCRSP01 0x38 /* Response Register 0 and 1 */
57#define DAVINCI_MMCRSP23 0x3C /* Response Register 0 and 1 */
58#define DAVINCI_MMCRSP45 0x40 /* Response Register 0 and 1 */
59#define DAVINCI_MMCRSP67 0x44 /* Response Register 0 and 1 */
60#define DAVINCI_MMCDRSP 0x48 /* Data Response Register */
61#define DAVINCI_MMCETOK 0x4C
62#define DAVINCI_MMCCIDX 0x50 /* Command Index Register */
63#define DAVINCI_MMCCKC 0x54
64#define DAVINCI_MMCTORC 0x58
65#define DAVINCI_MMCTODC 0x5C
66#define DAVINCI_MMCBLNC 0x60
67#define DAVINCI_SDIOCTL 0x64
68#define DAVINCI_SDIOST0 0x68
69#define DAVINCI_SDIOIEN 0x6C
70#define DAVINCI_SDIOIST 0x70
71#define DAVINCI_MMCFIFOCTL 0x74 /* FIFO Control Register */
72
73/* DAVINCI_MMCCTL definitions */
74#define MMCCTL_DATRST (1 << 0)
75#define MMCCTL_CMDRST (1 << 1)
76#define MMCCTL_WIDTH_8_BIT (1 << 8)
77#define MMCCTL_WIDTH_4_BIT (1 << 2)
78#define MMCCTL_DATEG_DISABLED (0 << 6)
79#define MMCCTL_DATEG_RISING (1 << 6)
80#define MMCCTL_DATEG_FALLING (2 << 6)
81#define MMCCTL_DATEG_BOTH (3 << 6)
82#define MMCCTL_PERMDR_LE (0 << 9)
83#define MMCCTL_PERMDR_BE (1 << 9)
84#define MMCCTL_PERMDX_LE (0 << 10)
85#define MMCCTL_PERMDX_BE (1 << 10)
86
87/* DAVINCI_MMCCLK definitions */
88#define MMCCLK_CLKEN (1 << 8)
89#define MMCCLK_CLKRT_MASK (0xFF << 0)
90
91/* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */
92#define MMCST0_DATDNE BIT(0) /* data done */
93#define MMCST0_BSYDNE BIT(1) /* busy done */
94#define MMCST0_RSPDNE BIT(2) /* command done */
95#define MMCST0_TOUTRD BIT(3) /* data read timeout */
96#define MMCST0_TOUTRS BIT(4) /* command response timeout */
97#define MMCST0_CRCWR BIT(5) /* data write CRC error */
98#define MMCST0_CRCRD BIT(6) /* data read CRC error */
99#define MMCST0_CRCRS BIT(7) /* command response CRC error */
100#define MMCST0_DXRDY BIT(9) /* data transmit ready (fifo empty) */
101#define MMCST0_DRRDY BIT(10) /* data receive ready (data in fifo)*/
102#define MMCST0_DATED BIT(11) /* DAT3 edge detect */
103#define MMCST0_TRNDNE BIT(12) /* transfer done */
104
105/* DAVINCI_MMCST1 definitions */
106#define MMCST1_BUSY (1 << 0)
107
108/* DAVINCI_MMCCMD definitions */
109#define MMCCMD_CMD_MASK (0x3F << 0)
110#define MMCCMD_PPLEN (1 << 7)
111#define MMCCMD_BSYEXP (1 << 8)
112#define MMCCMD_RSPFMT_MASK (3 << 9)
113#define MMCCMD_RSPFMT_NONE (0 << 9)
114#define MMCCMD_RSPFMT_R1456 (1 << 9)
115#define MMCCMD_RSPFMT_R2 (2 << 9)
116#define MMCCMD_RSPFMT_R3 (3 << 9)
117#define MMCCMD_DTRW (1 << 11)
118#define MMCCMD_STRMTP (1 << 12)
119#define MMCCMD_WDATX (1 << 13)
120#define MMCCMD_INITCK (1 << 14)
121#define MMCCMD_DCLR (1 << 15)
122#define MMCCMD_DMATRIG (1 << 16)
123
124/* DAVINCI_MMCFIFOCTL definitions */
125#define MMCFIFOCTL_FIFORST (1 << 0)
126#define MMCFIFOCTL_FIFODIR_WR (1 << 1)
127#define MMCFIFOCTL_FIFODIR_RD (0 << 1)
128#define MMCFIFOCTL_FIFOLEV (1 << 2) /* 0 = 128 bits, 1 = 256 bits */
129#define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */
130#define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */
131#define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */
132#define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */
133
134/* DAVINCI_SDIOST0 definitions */
135#define SDIOST0_DAT1_HI BIT(0)
136
137/* DAVINCI_SDIOIEN definitions */
138#define SDIOIEN_IOINTEN BIT(0)
139
140/* DAVINCI_SDIOIST definitions */
141#define SDIOIST_IOINT BIT(0)
142
143/* MMCSD Init clock in Hz in opendrain mode */
144#define MMCSD_INIT_CLOCK 200000
145
146/*
147 * One scatterlist dma "segment" is at most MAX_CCNT rw_threshold units,
148 * and we handle up to MAX_NR_SG segments. MMC_BLOCK_BOUNCE kicks in only
149 * for drivers with max_segs == 1, making the segments bigger (64KB)
150 * than the page or two that's otherwise typical. nr_sg (passed from
151 * platform data) == 16 gives at least the same throughput boost, using
152 * EDMA transfer linkage instead of spending CPU time copying pages.
153 */
154#define MAX_CCNT ((1 << 16) - 1)
155
156#define MAX_NR_SG 16
157
158static unsigned rw_threshold = 32;
159module_param(rw_threshold, uint, S_IRUGO);
160MODULE_PARM_DESC(rw_threshold,
161 "Read/Write threshold. Default = 32");
162
163static unsigned __initdata use_dma = 1;
164module_param(use_dma, uint, 0);
165MODULE_PARM_DESC(use_dma, "Whether to use DMA or not. Default = 1");
166
167struct mmc_davinci_host {
168 struct mmc_command *cmd;
169 struct mmc_data *data;
170 struct mmc_host *mmc;
171 struct clk *clk;
172 unsigned int mmc_input_clk;
173 void __iomem *base;
174 struct resource *mem_res;
175 int mmc_irq, sdio_irq;
176 unsigned char bus_mode;
177
178#define DAVINCI_MMC_DATADIR_NONE 0
179#define DAVINCI_MMC_DATADIR_READ 1
180#define DAVINCI_MMC_DATADIR_WRITE 2
181 unsigned char data_dir;
182 unsigned char suspended;
183
184 /* buffer is used during PIO of one scatterlist segment, and
185 * is updated along with buffer_bytes_left. bytes_left applies
186 * to all N blocks of the PIO transfer.
187 */
188 u8 *buffer;
189 u32 buffer_bytes_left;
190 u32 bytes_left;
191
192 u32 rxdma, txdma;
193 bool use_dma;
194 bool do_dma;
195 bool sdio_int;
196
197 /* Scatterlist DMA uses one or more parameter RAM entries:
198 * the main one (associated with rxdma or txdma) plus zero or
199 * more links. The entries for a given transfer differ only
200 * by memory buffer (address, length) and link field.
201 */
202 struct edmacc_param tx_template;
203 struct edmacc_param rx_template;
204 unsigned n_link;
205 u32 links[MAX_NR_SG - 1];
206
207 /* For PIO we walk scatterlists one segment at a time. */
208 unsigned int sg_len;
209 struct scatterlist *sg;
210
211 /* Version of the MMC/SD controller */
212 u8 version;
213 /* for ns in one cycle calculation */
214 unsigned ns_in_one_cycle;
215 /* Number of sg segments */
216 u8 nr_sg;
217#ifdef CONFIG_CPU_FREQ
218 struct notifier_block freq_transition;
219#endif
220};
221
222
223/* PIO only */
224static void mmc_davinci_sg_to_buf(struct mmc_davinci_host *host)
225{
226 host->buffer_bytes_left = sg_dma_len(host->sg);
227 host->buffer = sg_virt(host->sg);
228 if (host->buffer_bytes_left > host->bytes_left)
229 host->buffer_bytes_left = host->bytes_left;
230}
231
232static void davinci_fifo_data_trans(struct mmc_davinci_host *host,
233 unsigned int n)
234{
235 u8 *p;
236 unsigned int i;
237
238 if (host->buffer_bytes_left == 0) {
239 host->sg = sg_next(host->data->sg);
240 mmc_davinci_sg_to_buf(host);
241 }
242
243 p = host->buffer;
244 if (n > host->buffer_bytes_left)
245 n = host->buffer_bytes_left;
246 host->buffer_bytes_left -= n;
247 host->bytes_left -= n;
248
249 /* NOTE: we never transfer more than rw_threshold bytes
250 * to/from the fifo here; there's no I/O overlap.
251 * This also assumes that access width( i.e. ACCWD) is 4 bytes
252 */
253 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
254 for (i = 0; i < (n >> 2); i++) {
255 writel(*((u32 *)p), host->base + DAVINCI_MMCDXR);
256 p = p + 4;
257 }
258 if (n & 3) {
259 iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3));
260 p = p + (n & 3);
261 }
262 } else {
263 for (i = 0; i < (n >> 2); i++) {
264 *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR);
265 p = p + 4;
266 }
267 if (n & 3) {
268 ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3));
269 p = p + (n & 3);
270 }
271 }
272 host->buffer = p;
273}
274
275static void mmc_davinci_start_command(struct mmc_davinci_host *host,
276 struct mmc_command *cmd)
277{
278 u32 cmd_reg = 0;
279 u32 im_val;
280
281 dev_dbg(mmc_dev(host->mmc), "CMD%d, arg 0x%08x%s\n",
282 cmd->opcode, cmd->arg,
283 ({ char *s;
284 switch (mmc_resp_type(cmd)) {
285 case MMC_RSP_R1:
286 s = ", R1/R5/R6/R7 response";
287 break;
288 case MMC_RSP_R1B:
289 s = ", R1b response";
290 break;
291 case MMC_RSP_R2:
292 s = ", R2 response";
293 break;
294 case MMC_RSP_R3:
295 s = ", R3/R4 response";
296 break;
297 default:
298 s = ", (R? response)";
299 break;
300 }; s; }));
301 host->cmd = cmd;
302
303 switch (mmc_resp_type(cmd)) {
304 case MMC_RSP_R1B:
305 /* There's some spec confusion about when R1B is
306 * allowed, but if the card doesn't issue a BUSY
307 * then it's harmless for us to allow it.
308 */
309 cmd_reg |= MMCCMD_BSYEXP;
310 /* FALLTHROUGH */
311 case MMC_RSP_R1: /* 48 bits, CRC */
312 cmd_reg |= MMCCMD_RSPFMT_R1456;
313 break;
314 case MMC_RSP_R2: /* 136 bits, CRC */
315 cmd_reg |= MMCCMD_RSPFMT_R2;
316 break;
317 case MMC_RSP_R3: /* 48 bits, no CRC */
318 cmd_reg |= MMCCMD_RSPFMT_R3;
319 break;
320 default:
321 cmd_reg |= MMCCMD_RSPFMT_NONE;
322 dev_dbg(mmc_dev(host->mmc), "unknown resp_type %04x\n",
323 mmc_resp_type(cmd));
324 break;
325 }
326
327 /* Set command index */
328 cmd_reg |= cmd->opcode;
329
330 /* Enable EDMA transfer triggers */
331 if (host->do_dma)
332 cmd_reg |= MMCCMD_DMATRIG;
333
334 if (host->version == MMC_CTLR_VERSION_2 && host->data != NULL &&
335 host->data_dir == DAVINCI_MMC_DATADIR_READ)
336 cmd_reg |= MMCCMD_DMATRIG;
337
338 /* Setting whether command involves data transfer or not */
339 if (cmd->data)
340 cmd_reg |= MMCCMD_WDATX;
341
342 /* Setting whether stream or block transfer */
343 if (cmd->flags & MMC_DATA_STREAM)
344 cmd_reg |= MMCCMD_STRMTP;
345
346 /* Setting whether data read or write */
347 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)
348 cmd_reg |= MMCCMD_DTRW;
349
350 if (host->bus_mode == MMC_BUSMODE_PUSHPULL)
351 cmd_reg |= MMCCMD_PPLEN;
352
353 /* set Command timeout */
354 writel(0x1FFF, host->base + DAVINCI_MMCTOR);
355
356 /* Enable interrupt (calculate here, defer until FIFO is stuffed). */
357 im_val = MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS;
358 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
359 im_val |= MMCST0_DATDNE | MMCST0_CRCWR;
360
361 if (!host->do_dma)
362 im_val |= MMCST0_DXRDY;
363 } else if (host->data_dir == DAVINCI_MMC_DATADIR_READ) {
364 im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD;
365
366 if (!host->do_dma)
367 im_val |= MMCST0_DRRDY;
368 }
369
370 /*
371 * Before non-DMA WRITE commands the controller needs priming:
372 * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size
373 */
374 if (!host->do_dma && (host->data_dir == DAVINCI_MMC_DATADIR_WRITE))
375 davinci_fifo_data_trans(host, rw_threshold);
376
377 writel(cmd->arg, host->base + DAVINCI_MMCARGHL);
378 writel(cmd_reg, host->base + DAVINCI_MMCCMD);
379 writel(im_val, host->base + DAVINCI_MMCIM);
380}
381
382/*----------------------------------------------------------------------*/
383
384/* DMA infrastructure */
385
386static void davinci_abort_dma(struct mmc_davinci_host *host)
387{
388 int sync_dev;
389
390 if (host->data_dir == DAVINCI_MMC_DATADIR_READ)
391 sync_dev = host->rxdma;
392 else
393 sync_dev = host->txdma;
394
395 edma_stop(sync_dev);
396 edma_clean_channel(sync_dev);
397}
398
399static void
400mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data);
401
402static void mmc_davinci_dma_cb(unsigned channel, u16 ch_status, void *data)
403{
404 if (DMA_COMPLETE != ch_status) {
405 struct mmc_davinci_host *host = data;
406
407 /* Currently means: DMA Event Missed, or "null" transfer
408 * request was seen. In the future, TC errors (like bad
409 * addresses) might be presented too.
410 */
411 dev_warn(mmc_dev(host->mmc), "DMA %s error\n",
412 (host->data->flags & MMC_DATA_WRITE)
413 ? "write" : "read");
414 host->data->error = -EIO;
415 mmc_davinci_xfer_done(host, host->data);
416 }
417}
418
419/* Set up tx or rx template, to be modified and updated later */
420static void __init mmc_davinci_dma_setup(struct mmc_davinci_host *host,
421 bool tx, struct edmacc_param *template)
422{
423 unsigned sync_dev;
424 const u16 acnt = 4;
425 const u16 bcnt = rw_threshold >> 2;
426 const u16 ccnt = 0;
427 u32 src_port = 0;
428 u32 dst_port = 0;
429 s16 src_bidx, dst_bidx;
430 s16 src_cidx, dst_cidx;
431
432 /*
433 * A-B Sync transfer: each DMA request is for one "frame" of
434 * rw_threshold bytes, broken into "acnt"-size chunks repeated
435 * "bcnt" times. Each segment needs "ccnt" such frames; since
436 * we tell the block layer our mmc->max_seg_size limit, we can
437 * trust (later) that it's within bounds.
438 *
439 * The FIFOs are read/written in 4-byte chunks (acnt == 4) and
440 * EDMA will optimize memory operations to use larger bursts.
441 */
442 if (tx) {
443 sync_dev = host->txdma;
444
445 /* src_prt, ccnt, and link to be set up later */
446 src_bidx = acnt;
447 src_cidx = acnt * bcnt;
448
449 dst_port = host->mem_res->start + DAVINCI_MMCDXR;
450 dst_bidx = 0;
451 dst_cidx = 0;
452 } else {
453 sync_dev = host->rxdma;
454
455 src_port = host->mem_res->start + DAVINCI_MMCDRR;
456 src_bidx = 0;
457 src_cidx = 0;
458
459 /* dst_prt, ccnt, and link to be set up later */
460 dst_bidx = acnt;
461 dst_cidx = acnt * bcnt;
462 }
463
464 /*
465 * We can't use FIFO mode for the FIFOs because MMC FIFO addresses
466 * are not 256-bit (32-byte) aligned. So we use INCR, and the W8BIT
467 * parameter is ignored.
468 */
469 edma_set_src(sync_dev, src_port, INCR, W8BIT);
470 edma_set_dest(sync_dev, dst_port, INCR, W8BIT);
471
472 edma_set_src_index(sync_dev, src_bidx, src_cidx);
473 edma_set_dest_index(sync_dev, dst_bidx, dst_cidx);
474
475 edma_set_transfer_params(sync_dev, acnt, bcnt, ccnt, 8, ABSYNC);
476
477 edma_read_slot(sync_dev, template);
478
479 /* don't bother with irqs or chaining */
480 template->opt |= EDMA_CHAN_SLOT(sync_dev) << 12;
481}
482
483static void mmc_davinci_send_dma_request(struct mmc_davinci_host *host,
484 struct mmc_data *data)
485{
486 struct edmacc_param *template;
487 int channel, slot;
488 unsigned link;
489 struct scatterlist *sg;
490 unsigned sg_len;
491 unsigned bytes_left = host->bytes_left;
492 const unsigned shift = ffs(rw_threshold) - 1;
493
494 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
495 template = &host->tx_template;
496 channel = host->txdma;
497 } else {
498 template = &host->rx_template;
499 channel = host->rxdma;
500 }
501
502 /* We know sg_len and ccnt will never be out of range because
503 * we told the mmc layer which in turn tells the block layer
504 * to ensure that it only hands us one scatterlist segment
505 * per EDMA PARAM entry. Update the PARAM
506 * entries needed for each segment of this scatterlist.
507 */
508 for (slot = channel, link = 0, sg = data->sg, sg_len = host->sg_len;
509 sg_len-- != 0 && bytes_left;
510 sg = sg_next(sg), slot = host->links[link++]) {
511 u32 buf = sg_dma_address(sg);
512 unsigned count = sg_dma_len(sg);
513
514 template->link_bcntrld = sg_len
515 ? (EDMA_CHAN_SLOT(host->links[link]) << 5)
516 : 0xffff;
517
518 if (count > bytes_left)
519 count = bytes_left;
520 bytes_left -= count;
521
522 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)
523 template->src = buf;
524 else
525 template->dst = buf;
526 template->ccnt = count >> shift;
527
528 edma_write_slot(slot, template);
529 }
530
531 if (host->version == MMC_CTLR_VERSION_2)
532 edma_clear_event(channel);
533
534 edma_start(channel);
535}
536
537static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host,
538 struct mmc_data *data)
539{
540 int i;
541 int mask = rw_threshold - 1;
542
543 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
544 ((data->flags & MMC_DATA_WRITE)
545 ? DMA_TO_DEVICE
546 : DMA_FROM_DEVICE));
547
548 /* no individual DMA segment should need a partial FIFO */
549 for (i = 0; i < host->sg_len; i++) {
550 if (sg_dma_len(data->sg + i) & mask) {
551 dma_unmap_sg(mmc_dev(host->mmc),
552 data->sg, data->sg_len,
553 (data->flags & MMC_DATA_WRITE)
554 ? DMA_TO_DEVICE
555 : DMA_FROM_DEVICE);
556 return -1;
557 }
558 }
559
560 host->do_dma = 1;
561 mmc_davinci_send_dma_request(host, data);
562
563 return 0;
564}
565
566static void __init_or_module
567davinci_release_dma_channels(struct mmc_davinci_host *host)
568{
569 unsigned i;
570
571 if (!host->use_dma)
572 return;
573
574 for (i = 0; i < host->n_link; i++)
575 edma_free_slot(host->links[i]);
576
577 edma_free_channel(host->txdma);
578 edma_free_channel(host->rxdma);
579}
580
581static int __init davinci_acquire_dma_channels(struct mmc_davinci_host *host)
582{
583 u32 link_size;
584 int r, i;
585
586 /* Acquire master DMA write channel */
587 r = edma_alloc_channel(host->txdma, mmc_davinci_dma_cb, host,
588 EVENTQ_DEFAULT);
589 if (r < 0) {
590 dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n",
591 "tx", r);
592 return r;
593 }
594 mmc_davinci_dma_setup(host, true, &host->tx_template);
595
596 /* Acquire master DMA read channel */
597 r = edma_alloc_channel(host->rxdma, mmc_davinci_dma_cb, host,
598 EVENTQ_DEFAULT);
599 if (r < 0) {
600 dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n",
601 "rx", r);
602 goto free_master_write;
603 }
604 mmc_davinci_dma_setup(host, false, &host->rx_template);
605
606 /* Allocate parameter RAM slots, which will later be bound to a
607 * channel as needed to handle a scatterlist.
608 */
609 link_size = min_t(unsigned, host->nr_sg, ARRAY_SIZE(host->links));
610 for (i = 0; i < link_size; i++) {
611 r = edma_alloc_slot(EDMA_CTLR(host->txdma), EDMA_SLOT_ANY);
612 if (r < 0) {
613 dev_dbg(mmc_dev(host->mmc), "dma PaRAM alloc --> %d\n",
614 r);
615 break;
616 }
617 host->links[i] = r;
618 }
619 host->n_link = i;
620
621 return 0;
622
623free_master_write:
624 edma_free_channel(host->txdma);
625
626 return r;
627}
628
629/*----------------------------------------------------------------------*/
630
631static void
632mmc_davinci_prepare_data(struct mmc_davinci_host *host, struct mmc_request *req)
633{
634 int fifo_lev = (rw_threshold == 32) ? MMCFIFOCTL_FIFOLEV : 0;
635 int timeout;
636 struct mmc_data *data = req->data;
637
638 if (host->version == MMC_CTLR_VERSION_2)
639 fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0;
640
641 host->data = data;
642 if (data == NULL) {
643 host->data_dir = DAVINCI_MMC_DATADIR_NONE;
644 writel(0, host->base + DAVINCI_MMCBLEN);
645 writel(0, host->base + DAVINCI_MMCNBLK);
646 return;
647 }
648
649 dev_dbg(mmc_dev(host->mmc), "%s %s, %d blocks of %d bytes\n",
650 (data->flags & MMC_DATA_STREAM) ? "stream" : "block",
651 (data->flags & MMC_DATA_WRITE) ? "write" : "read",
652 data->blocks, data->blksz);
653 dev_dbg(mmc_dev(host->mmc), " DTO %d cycles + %d ns\n",
654 data->timeout_clks, data->timeout_ns);
655 timeout = data->timeout_clks +
656 (data->timeout_ns / host->ns_in_one_cycle);
657 if (timeout > 0xffff)
658 timeout = 0xffff;
659
660 writel(timeout, host->base + DAVINCI_MMCTOD);
661 writel(data->blocks, host->base + DAVINCI_MMCNBLK);
662 writel(data->blksz, host->base + DAVINCI_MMCBLEN);
663
664 /* Configure the FIFO */
665 switch (data->flags & MMC_DATA_WRITE) {
666 case MMC_DATA_WRITE:
667 host->data_dir = DAVINCI_MMC_DATADIR_WRITE;
668 writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST,
669 host->base + DAVINCI_MMCFIFOCTL);
670 writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR,
671 host->base + DAVINCI_MMCFIFOCTL);
672 break;
673
674 default:
675 host->data_dir = DAVINCI_MMC_DATADIR_READ;
676 writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST,
677 host->base + DAVINCI_MMCFIFOCTL);
678 writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD,
679 host->base + DAVINCI_MMCFIFOCTL);
680 break;
681 }
682
683 host->buffer = NULL;
684 host->bytes_left = data->blocks * data->blksz;
685
686 /* For now we try to use DMA whenever we won't need partial FIFO
687 * reads or writes, either for the whole transfer (as tested here)
688 * or for any individual scatterlist segment (tested when we call
689 * start_dma_transfer).
690 *
691 * While we *could* change that, unusual block sizes are rarely
692 * used. The occasional fallback to PIO should't hurt.
693 */
694 if (host->use_dma && (host->bytes_left & (rw_threshold - 1)) == 0
695 && mmc_davinci_start_dma_transfer(host, data) == 0) {
696 /* zero this to ensure we take no PIO paths */
697 host->bytes_left = 0;
698 } else {
699 /* Revert to CPU Copy */
700 host->sg_len = data->sg_len;
701 host->sg = host->data->sg;
702 mmc_davinci_sg_to_buf(host);
703 }
704}
705
706static void mmc_davinci_request(struct mmc_host *mmc, struct mmc_request *req)
707{
708 struct mmc_davinci_host *host = mmc_priv(mmc);
709 unsigned long timeout = jiffies + msecs_to_jiffies(900);
710 u32 mmcst1 = 0;
711
712 /* Card may still be sending BUSY after a previous operation,
713 * typically some kind of write. If so, we can't proceed yet.
714 */
715 while (time_before(jiffies, timeout)) {
716 mmcst1 = readl(host->base + DAVINCI_MMCST1);
717 if (!(mmcst1 & MMCST1_BUSY))
718 break;
719 cpu_relax();
720 }
721 if (mmcst1 & MMCST1_BUSY) {
722 dev_err(mmc_dev(host->mmc), "still BUSY? bad ... \n");
723 req->cmd->error = -ETIMEDOUT;
724 mmc_request_done(mmc, req);
725 return;
726 }
727
728 host->do_dma = 0;
729 mmc_davinci_prepare_data(host, req);
730 mmc_davinci_start_command(host, req->cmd);
731}
732
733static unsigned int calculate_freq_for_card(struct mmc_davinci_host *host,
734 unsigned int mmc_req_freq)
735{
736 unsigned int mmc_freq = 0, mmc_pclk = 0, mmc_push_pull_divisor = 0;
737
738 mmc_pclk = host->mmc_input_clk;
739 if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq))
740 mmc_push_pull_divisor = ((unsigned int)mmc_pclk
741 / (2 * mmc_req_freq)) - 1;
742 else
743 mmc_push_pull_divisor = 0;
744
745 mmc_freq = (unsigned int)mmc_pclk
746 / (2 * (mmc_push_pull_divisor + 1));
747
748 if (mmc_freq > mmc_req_freq)
749 mmc_push_pull_divisor = mmc_push_pull_divisor + 1;
750 /* Convert ns to clock cycles */
751 if (mmc_req_freq <= 400000)
752 host->ns_in_one_cycle = (1000000) / (((mmc_pclk
753 / (2 * (mmc_push_pull_divisor + 1)))/1000));
754 else
755 host->ns_in_one_cycle = (1000000) / (((mmc_pclk
756 / (2 * (mmc_push_pull_divisor + 1)))/1000000));
757
758 return mmc_push_pull_divisor;
759}
760
761static void calculate_clk_divider(struct mmc_host *mmc, struct mmc_ios *ios)
762{
763 unsigned int open_drain_freq = 0, mmc_pclk = 0;
764 unsigned int mmc_push_pull_freq = 0;
765 struct mmc_davinci_host *host = mmc_priv(mmc);
766
767 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
768 u32 temp;
769
770 /* Ignoring the init clock value passed for fixing the inter
771 * operability with different cards.
772 */
773 open_drain_freq = ((unsigned int)mmc_pclk
774 / (2 * MMCSD_INIT_CLOCK)) - 1;
775
776 if (open_drain_freq > 0xFF)
777 open_drain_freq = 0xFF;
778
779 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK;
780 temp |= open_drain_freq;
781 writel(temp, host->base + DAVINCI_MMCCLK);
782
783 /* Convert ns to clock cycles */
784 host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK/1000);
785 } else {
786 u32 temp;
787 mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock);
788
789 if (mmc_push_pull_freq > 0xFF)
790 mmc_push_pull_freq = 0xFF;
791
792 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN;
793 writel(temp, host->base + DAVINCI_MMCCLK);
794
795 udelay(10);
796
797 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK;
798 temp |= mmc_push_pull_freq;
799 writel(temp, host->base + DAVINCI_MMCCLK);
800
801 writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);
802
803 udelay(10);
804 }
805}
806
807static void mmc_davinci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
808{
809 struct mmc_davinci_host *host = mmc_priv(mmc);
810
811 dev_dbg(mmc_dev(host->mmc),
812 "clock %dHz busmode %d powermode %d Vdd %04x\n",
813 ios->clock, ios->bus_mode, ios->power_mode,
814 ios->vdd);
815
816 switch (ios->bus_width) {
817 case MMC_BUS_WIDTH_8:
818 dev_dbg(mmc_dev(host->mmc), "Enabling 8 bit mode\n");
819 writel((readl(host->base + DAVINCI_MMCCTL) &
820 ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT,
821 host->base + DAVINCI_MMCCTL);
822 break;
823 case MMC_BUS_WIDTH_4:
824 dev_dbg(mmc_dev(host->mmc), "Enabling 4 bit mode\n");
825 if (host->version == MMC_CTLR_VERSION_2)
826 writel((readl(host->base + DAVINCI_MMCCTL) &
827 ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT,
828 host->base + DAVINCI_MMCCTL);
829 else
830 writel(readl(host->base + DAVINCI_MMCCTL) |
831 MMCCTL_WIDTH_4_BIT,
832 host->base + DAVINCI_MMCCTL);
833 break;
834 case MMC_BUS_WIDTH_1:
835 dev_dbg(mmc_dev(host->mmc), "Enabling 1 bit mode\n");
836 if (host->version == MMC_CTLR_VERSION_2)
837 writel(readl(host->base + DAVINCI_MMCCTL) &
838 ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT),
839 host->base + DAVINCI_MMCCTL);
840 else
841 writel(readl(host->base + DAVINCI_MMCCTL) &
842 ~MMCCTL_WIDTH_4_BIT,
843 host->base + DAVINCI_MMCCTL);
844 break;
845 }
846
847 calculate_clk_divider(mmc, ios);
848
849 host->bus_mode = ios->bus_mode;
850 if (ios->power_mode == MMC_POWER_UP) {
851 unsigned long timeout = jiffies + msecs_to_jiffies(50);
852 bool lose = true;
853
854 /* Send clock cycles, poll completion */
855 writel(0, host->base + DAVINCI_MMCARGHL);
856 writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD);
857 while (time_before(jiffies, timeout)) {
858 u32 tmp = readl(host->base + DAVINCI_MMCST0);
859
860 if (tmp & MMCST0_RSPDNE) {
861 lose = false;
862 break;
863 }
864 cpu_relax();
865 }
866 if (lose)
867 dev_warn(mmc_dev(host->mmc), "powerup timeout\n");
868 }
869
870 /* FIXME on power OFF, reset things ... */
871}
872
873static void
874mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data)
875{
876 host->data = NULL;
877
878 if (host->mmc->caps & MMC_CAP_SDIO_IRQ) {
879 /*
880 * SDIO Interrupt Detection work-around as suggested by
881 * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata
882 * 2.1.6): Signal SDIO interrupt only if it is enabled by core
883 */
884 if (host->sdio_int && !(readl(host->base + DAVINCI_SDIOST0) &
885 SDIOST0_DAT1_HI)) {
886 writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
887 mmc_signal_sdio_irq(host->mmc);
888 }
889 }
890
891 if (host->do_dma) {
892 davinci_abort_dma(host);
893
894 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
895 (data->flags & MMC_DATA_WRITE)
896 ? DMA_TO_DEVICE
897 : DMA_FROM_DEVICE);
898 host->do_dma = false;
899 }
900 host->data_dir = DAVINCI_MMC_DATADIR_NONE;
901
902 if (!data->stop || (host->cmd && host->cmd->error)) {
903 mmc_request_done(host->mmc, data->mrq);
904 writel(0, host->base + DAVINCI_MMCIM);
905 } else
906 mmc_davinci_start_command(host, data->stop);
907}
908
909static void mmc_davinci_cmd_done(struct mmc_davinci_host *host,
910 struct mmc_command *cmd)
911{
912 host->cmd = NULL;
913
914 if (cmd->flags & MMC_RSP_PRESENT) {
915 if (cmd->flags & MMC_RSP_136) {
916 /* response type 2 */
917 cmd->resp[3] = readl(host->base + DAVINCI_MMCRSP01);
918 cmd->resp[2] = readl(host->base + DAVINCI_MMCRSP23);
919 cmd->resp[1] = readl(host->base + DAVINCI_MMCRSP45);
920 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67);
921 } else {
922 /* response types 1, 1b, 3, 4, 5, 6 */
923 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67);
924 }
925 }
926
927 if (host->data == NULL || cmd->error) {
928 if (cmd->error == -ETIMEDOUT)
929 cmd->mrq->cmd->retries = 0;
930 mmc_request_done(host->mmc, cmd->mrq);
931 writel(0, host->base + DAVINCI_MMCIM);
932 }
933}
934
935static inline void mmc_davinci_reset_ctrl(struct mmc_davinci_host *host,
936 int val)
937{
938 u32 temp;
939
940 temp = readl(host->base + DAVINCI_MMCCTL);
941 if (val) /* reset */
942 temp |= MMCCTL_CMDRST | MMCCTL_DATRST;
943 else /* enable */
944 temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST);
945
946 writel(temp, host->base + DAVINCI_MMCCTL);
947 udelay(10);
948}
949
950static void
951davinci_abort_data(struct mmc_davinci_host *host, struct mmc_data *data)
952{
953 mmc_davinci_reset_ctrl(host, 1);
954 mmc_davinci_reset_ctrl(host, 0);
955}
956
957static irqreturn_t mmc_davinci_sdio_irq(int irq, void *dev_id)
958{
959 struct mmc_davinci_host *host = dev_id;
960 unsigned int status;
961
962 status = readl(host->base + DAVINCI_SDIOIST);
963 if (status & SDIOIST_IOINT) {
964 dev_dbg(mmc_dev(host->mmc),
965 "SDIO interrupt status %x\n", status);
966 writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
967 mmc_signal_sdio_irq(host->mmc);
968 }
969 return IRQ_HANDLED;
970}
971
972static irqreturn_t mmc_davinci_irq(int irq, void *dev_id)
973{
974 struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id;
975 unsigned int status, qstatus;
976 int end_command = 0;
977 int end_transfer = 0;
978 struct mmc_data *data = host->data;
979
980 if (host->cmd == NULL && host->data == NULL) {
981 status = readl(host->base + DAVINCI_MMCST0);
982 dev_dbg(mmc_dev(host->mmc),
983 "Spurious interrupt 0x%04x\n", status);
984 /* Disable the interrupt from mmcsd */
985 writel(0, host->base + DAVINCI_MMCIM);
986 return IRQ_NONE;
987 }
988
989 status = readl(host->base + DAVINCI_MMCST0);
990 qstatus = status;
991
992 /* handle FIFO first when using PIO for data.
993 * bytes_left will decrease to zero as I/O progress and status will
994 * read zero over iteration because this controller status
995 * register(MMCST0) reports any status only once and it is cleared
996 * by read. So, it is not unbouned loop even in the case of
997 * non-dma.
998 */
999 while (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) {
1000 davinci_fifo_data_trans(host, rw_threshold);
1001 status = readl(host->base + DAVINCI_MMCST0);
1002 if (!status)
1003 break;
1004 qstatus |= status;
1005 }
1006
1007 if (qstatus & MMCST0_DATDNE) {
1008 /* All blocks sent/received, and CRC checks passed */
1009 if (data != NULL) {
1010 if ((host->do_dma == 0) && (host->bytes_left > 0)) {
1011 /* if datasize < rw_threshold
1012 * no RX ints are generated
1013 */
1014 davinci_fifo_data_trans(host, host->bytes_left);
1015 }
1016 end_transfer = 1;
1017 data->bytes_xfered = data->blocks * data->blksz;
1018 } else {
1019 dev_err(mmc_dev(host->mmc),
1020 "DATDNE with no host->data\n");
1021 }
1022 }
1023
1024 if (qstatus & MMCST0_TOUTRD) {
1025 /* Read data timeout */
1026 data->error = -ETIMEDOUT;
1027 end_transfer = 1;
1028
1029 dev_dbg(mmc_dev(host->mmc),
1030 "read data timeout, status %x\n",
1031 qstatus);
1032
1033 davinci_abort_data(host, data);
1034 }
1035
1036 if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) {
1037 /* Data CRC error */
1038 data->error = -EILSEQ;
1039 end_transfer = 1;
1040
1041 /* NOTE: this controller uses CRCWR to report both CRC
1042 * errors and timeouts (on writes). MMCDRSP values are
1043 * only weakly documented, but 0x9f was clearly a timeout
1044 * case and the two three-bit patterns in various SD specs
1045 * (101, 010) aren't part of it ...
1046 */
1047 if (qstatus & MMCST0_CRCWR) {
1048 u32 temp = readb(host->base + DAVINCI_MMCDRSP);
1049
1050 if (temp == 0x9f)
1051 data->error = -ETIMEDOUT;
1052 }
1053 dev_dbg(mmc_dev(host->mmc), "data %s %s error\n",
1054 (qstatus & MMCST0_CRCWR) ? "write" : "read",
1055 (data->error == -ETIMEDOUT) ? "timeout" : "CRC");
1056
1057 davinci_abort_data(host, data);
1058 }
1059
1060 if (qstatus & MMCST0_TOUTRS) {
1061 /* Command timeout */
1062 if (host->cmd) {
1063 dev_dbg(mmc_dev(host->mmc),
1064 "CMD%d timeout, status %x\n",
1065 host->cmd->opcode, qstatus);
1066 host->cmd->error = -ETIMEDOUT;
1067 if (data) {
1068 end_transfer = 1;
1069 davinci_abort_data(host, data);
1070 } else
1071 end_command = 1;
1072 }
1073 }
1074
1075 if (qstatus & MMCST0_CRCRS) {
1076 /* Command CRC error */
1077 dev_dbg(mmc_dev(host->mmc), "Command CRC error\n");
1078 if (host->cmd) {
1079 host->cmd->error = -EILSEQ;
1080 end_command = 1;
1081 }
1082 }
1083
1084 if (qstatus & MMCST0_RSPDNE) {
1085 /* End of command phase */
1086 end_command = (int) host->cmd;
1087 }
1088
1089 if (end_command)
1090 mmc_davinci_cmd_done(host, host->cmd);
1091 if (end_transfer)
1092 mmc_davinci_xfer_done(host, data);
1093 return IRQ_HANDLED;
1094}
1095
1096static int mmc_davinci_get_cd(struct mmc_host *mmc)
1097{
1098 struct platform_device *pdev = to_platform_device(mmc->parent);
1099 struct davinci_mmc_config *config = pdev->dev.platform_data;
1100
1101 if (!config || !config->get_cd)
1102 return -ENOSYS;
1103 return config->get_cd(pdev->id);
1104}
1105
1106static int mmc_davinci_get_ro(struct mmc_host *mmc)
1107{
1108 struct platform_device *pdev = to_platform_device(mmc->parent);
1109 struct davinci_mmc_config *config = pdev->dev.platform_data;
1110
1111 if (!config || !config->get_ro)
1112 return -ENOSYS;
1113 return config->get_ro(pdev->id);
1114}
1115
1116static void mmc_davinci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1117{
1118 struct mmc_davinci_host *host = mmc_priv(mmc);
1119
1120 if (enable) {
1121 if (!(readl(host->base + DAVINCI_SDIOST0) & SDIOST0_DAT1_HI)) {
1122 writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
1123 mmc_signal_sdio_irq(host->mmc);
1124 } else {
1125 host->sdio_int = true;
1126 writel(readl(host->base + DAVINCI_SDIOIEN) |
1127 SDIOIEN_IOINTEN, host->base + DAVINCI_SDIOIEN);
1128 }
1129 } else {
1130 host->sdio_int = false;
1131 writel(readl(host->base + DAVINCI_SDIOIEN) & ~SDIOIEN_IOINTEN,
1132 host->base + DAVINCI_SDIOIEN);
1133 }
1134}
1135
1136static struct mmc_host_ops mmc_davinci_ops = {
1137 .request = mmc_davinci_request,
1138 .set_ios = mmc_davinci_set_ios,
1139 .get_cd = mmc_davinci_get_cd,
1140 .get_ro = mmc_davinci_get_ro,
1141 .enable_sdio_irq = mmc_davinci_enable_sdio_irq,
1142};
1143
1144/*----------------------------------------------------------------------*/
1145
1146#ifdef CONFIG_CPU_FREQ
1147static int mmc_davinci_cpufreq_transition(struct notifier_block *nb,
1148 unsigned long val, void *data)
1149{
1150 struct mmc_davinci_host *host;
1151 unsigned int mmc_pclk;
1152 struct mmc_host *mmc;
1153 unsigned long flags;
1154
1155 host = container_of(nb, struct mmc_davinci_host, freq_transition);
1156 mmc = host->mmc;
1157 mmc_pclk = clk_get_rate(host->clk);
1158
1159 if (val == CPUFREQ_POSTCHANGE) {
1160 spin_lock_irqsave(&mmc->lock, flags);
1161 host->mmc_input_clk = mmc_pclk;
1162 calculate_clk_divider(mmc, &mmc->ios);
1163 spin_unlock_irqrestore(&mmc->lock, flags);
1164 }
1165
1166 return 0;
1167}
1168
1169static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host)
1170{
1171 host->freq_transition.notifier_call = mmc_davinci_cpufreq_transition;
1172
1173 return cpufreq_register_notifier(&host->freq_transition,
1174 CPUFREQ_TRANSITION_NOTIFIER);
1175}
1176
1177static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host)
1178{
1179 cpufreq_unregister_notifier(&host->freq_transition,
1180 CPUFREQ_TRANSITION_NOTIFIER);
1181}
1182#else
1183static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host)
1184{
1185 return 0;
1186}
1187
1188static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host)
1189{
1190}
1191#endif
1192static void __init init_mmcsd_host(struct mmc_davinci_host *host)
1193{
1194
1195 mmc_davinci_reset_ctrl(host, 1);
1196
1197 writel(0, host->base + DAVINCI_MMCCLK);
1198 writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);
1199
1200 writel(0x1FFF, host->base + DAVINCI_MMCTOR);
1201 writel(0xFFFF, host->base + DAVINCI_MMCTOD);
1202
1203 mmc_davinci_reset_ctrl(host, 0);
1204}
1205
1206static int __init davinci_mmcsd_probe(struct platform_device *pdev)
1207{
1208 struct davinci_mmc_config *pdata = pdev->dev.platform_data;
1209 struct mmc_davinci_host *host = NULL;
1210 struct mmc_host *mmc = NULL;
1211 struct resource *r, *mem = NULL;
1212 int ret = 0, irq = 0;
1213 size_t mem_size;
1214
1215 /* REVISIT: when we're fully converted, fail if pdata is NULL */
1216
1217 ret = -ENODEV;
1218 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1219 irq = platform_get_irq(pdev, 0);
1220 if (!r || irq == NO_IRQ)
1221 goto out;
1222
1223 ret = -EBUSY;
1224 mem_size = resource_size(r);
1225 mem = request_mem_region(r->start, mem_size, pdev->name);
1226 if (!mem)
1227 goto out;
1228
1229 ret = -ENOMEM;
1230 mmc = mmc_alloc_host(sizeof(struct mmc_davinci_host), &pdev->dev);
1231 if (!mmc)
1232 goto out;
1233
1234 host = mmc_priv(mmc);
1235 host->mmc = mmc; /* Important */
1236
1237 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1238 if (!r)
1239 goto out;
1240 host->rxdma = r->start;
1241
1242 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1243 if (!r)
1244 goto out;
1245 host->txdma = r->start;
1246
1247 host->mem_res = mem;
1248 host->base = ioremap(mem->start, mem_size);
1249 if (!host->base)
1250 goto out;
1251
1252 ret = -ENXIO;
1253 host->clk = clk_get(&pdev->dev, "MMCSDCLK");
1254 if (IS_ERR(host->clk)) {
1255 ret = PTR_ERR(host->clk);
1256 goto out;
1257 }
1258 clk_enable(host->clk);
1259 host->mmc_input_clk = clk_get_rate(host->clk);
1260
1261 init_mmcsd_host(host);
1262
1263 if (pdata->nr_sg)
1264 host->nr_sg = pdata->nr_sg - 1;
1265
1266 if (host->nr_sg > MAX_NR_SG || !host->nr_sg)
1267 host->nr_sg = MAX_NR_SG;
1268
1269 host->use_dma = use_dma;
1270 host->mmc_irq = irq;
1271 host->sdio_irq = platform_get_irq(pdev, 1);
1272
1273 if (host->use_dma && davinci_acquire_dma_channels(host) != 0)
1274 host->use_dma = 0;
1275
1276 /* REVISIT: someday, support IRQ-driven card detection. */
1277 mmc->caps |= MMC_CAP_NEEDS_POLL;
1278 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1279
1280 if (pdata && (pdata->wires == 4 || pdata->wires == 0))
1281 mmc->caps |= MMC_CAP_4_BIT_DATA;
1282
1283 if (pdata && (pdata->wires == 8))
1284 mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA);
1285
1286 host->version = pdata->version;
1287
1288 mmc->ops = &mmc_davinci_ops;
1289 mmc->f_min = 312500;
1290 mmc->f_max = 25000000;
1291 if (pdata && pdata->max_freq)
1292 mmc->f_max = pdata->max_freq;
1293 if (pdata && pdata->caps)
1294 mmc->caps |= pdata->caps;
1295 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1296
1297 /* With no iommu coalescing pages, each phys_seg is a hw_seg.
1298 * Each hw_seg uses one EDMA parameter RAM slot, always one
1299 * channel and then usually some linked slots.
1300 */
1301 mmc->max_segs = 1 + host->n_link;
1302
1303 /* EDMA limit per hw segment (one or two MBytes) */
1304 mmc->max_seg_size = MAX_CCNT * rw_threshold;
1305
1306 /* MMC/SD controller limits for multiblock requests */
1307 mmc->max_blk_size = 4095; /* BLEN is 12 bits */
1308 mmc->max_blk_count = 65535; /* NBLK is 16 bits */
1309 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1310
1311 dev_dbg(mmc_dev(host->mmc), "max_segs=%d\n", mmc->max_segs);
1312 dev_dbg(mmc_dev(host->mmc), "max_blk_size=%d\n", mmc->max_blk_size);
1313 dev_dbg(mmc_dev(host->mmc), "max_req_size=%d\n", mmc->max_req_size);
1314 dev_dbg(mmc_dev(host->mmc), "max_seg_size=%d\n", mmc->max_seg_size);
1315
1316 platform_set_drvdata(pdev, host);
1317
1318 ret = mmc_davinci_cpufreq_register(host);
1319 if (ret) {
1320 dev_err(&pdev->dev, "failed to register cpufreq\n");
1321 goto cpu_freq_fail;
1322 }
1323
1324 ret = mmc_add_host(mmc);
1325 if (ret < 0)
1326 goto out;
1327
1328 ret = request_irq(irq, mmc_davinci_irq, 0, mmc_hostname(mmc), host);
1329 if (ret)
1330 goto out;
1331
1332 if (host->sdio_irq >= 0) {
1333 ret = request_irq(host->sdio_irq, mmc_davinci_sdio_irq, 0,
1334 mmc_hostname(mmc), host);
1335 if (!ret)
1336 mmc->caps |= MMC_CAP_SDIO_IRQ;
1337 }
1338
1339 rename_region(mem, mmc_hostname(mmc));
1340
1341 dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n",
1342 host->use_dma ? "DMA" : "PIO",
1343 (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1);
1344
1345 return 0;
1346
1347out:
1348 mmc_davinci_cpufreq_deregister(host);
1349cpu_freq_fail:
1350 if (host) {
1351 davinci_release_dma_channels(host);
1352
1353 if (host->clk) {
1354 clk_disable(host->clk);
1355 clk_put(host->clk);
1356 }
1357
1358 if (host->base)
1359 iounmap(host->base);
1360 }
1361
1362 if (mmc)
1363 mmc_free_host(mmc);
1364
1365 if (mem)
1366 release_resource(mem);
1367
1368 dev_dbg(&pdev->dev, "probe err %d\n", ret);
1369
1370 return ret;
1371}
1372
1373static int __exit davinci_mmcsd_remove(struct platform_device *pdev)
1374{
1375 struct mmc_davinci_host *host = platform_get_drvdata(pdev);
1376
1377 platform_set_drvdata(pdev, NULL);
1378 if (host) {
1379 mmc_davinci_cpufreq_deregister(host);
1380
1381 mmc_remove_host(host->mmc);
1382 free_irq(host->mmc_irq, host);
1383 if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
1384 free_irq(host->sdio_irq, host);
1385
1386 davinci_release_dma_channels(host);
1387
1388 clk_disable(host->clk);
1389 clk_put(host->clk);
1390
1391 iounmap(host->base);
1392
1393 release_resource(host->mem_res);
1394
1395 mmc_free_host(host->mmc);
1396 }
1397
1398 return 0;
1399}
1400
1401#ifdef CONFIG_PM
1402static int davinci_mmcsd_suspend(struct device *dev)
1403{
1404 struct platform_device *pdev = to_platform_device(dev);
1405 struct mmc_davinci_host *host = platform_get_drvdata(pdev);
1406 int ret;
1407
1408 mmc_host_enable(host->mmc);
1409 ret = mmc_suspend_host(host->mmc);
1410 if (!ret) {
1411 writel(0, host->base + DAVINCI_MMCIM);
1412 mmc_davinci_reset_ctrl(host, 1);
1413 mmc_host_disable(host->mmc);
1414 clk_disable(host->clk);
1415 host->suspended = 1;
1416 } else {
1417 host->suspended = 0;
1418 mmc_host_disable(host->mmc);
1419 }
1420
1421 return ret;
1422}
1423
1424static int davinci_mmcsd_resume(struct device *dev)
1425{
1426 struct platform_device *pdev = to_platform_device(dev);
1427 struct mmc_davinci_host *host = platform_get_drvdata(pdev);
1428 int ret;
1429
1430 if (!host->suspended)
1431 return 0;
1432
1433 clk_enable(host->clk);
1434 mmc_host_enable(host->mmc);
1435
1436 mmc_davinci_reset_ctrl(host, 0);
1437 ret = mmc_resume_host(host->mmc);
1438 if (!ret)
1439 host->suspended = 0;
1440
1441 return ret;
1442}
1443
1444static const struct dev_pm_ops davinci_mmcsd_pm = {
1445 .suspend = davinci_mmcsd_suspend,
1446 .resume = davinci_mmcsd_resume,
1447};
1448
1449#define davinci_mmcsd_pm_ops (&davinci_mmcsd_pm)
1450#else
1451#define davinci_mmcsd_pm_ops NULL
1452#endif
1453
1454static struct platform_driver davinci_mmcsd_driver = {
1455 .driver = {
1456 .name = "davinci_mmc",
1457 .owner = THIS_MODULE,
1458 .pm = davinci_mmcsd_pm_ops,
1459 },
1460 .remove = __exit_p(davinci_mmcsd_remove),
1461};
1462
1463static int __init davinci_mmcsd_init(void)
1464{
1465 return platform_driver_probe(&davinci_mmcsd_driver,
1466 davinci_mmcsd_probe);
1467}
1468module_init(davinci_mmcsd_init);
1469
1470static void __exit davinci_mmcsd_exit(void)
1471{
1472 platform_driver_unregister(&davinci_mmcsd_driver);
1473}
1474module_exit(davinci_mmcsd_exit);
1475
1476MODULE_AUTHOR("Texas Instruments India");
1477MODULE_LICENSE("GPL");
1478MODULE_DESCRIPTION("MMC/SD driver for Davinci MMC controller");
1479