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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * TI OMAP I2C master mode driver
4 *
5 * Copyright (C) 2003 MontaVista Software, Inc.
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2004 - 2007 Texas Instruments.
8 *
9 * Originally written by MontaVista Software, Inc.
10 * Additional contributions by:
11 * Tony Lindgren <tony@atomide.com>
12 * Imre Deak <imre.deak@nokia.com>
13 * Juha Yrjölä <juha.yrjola@solidboot.com>
14 * Syed Khasim <x0khasim@ti.com>
15 * Nishant Menon <nm@ti.com>
16 */
17
18#include <linux/module.h>
19#include <linux/delay.h>
20#include <linux/i2c.h>
21#include <linux/err.h>
22#include <linux/interrupt.h>
23#include <linux/completion.h>
24#include <linux/platform_device.h>
25#include <linux/clk.h>
26#include <linux/io.h>
27#include <linux/of.h>
28#include <linux/of_device.h>
29#include <linux/slab.h>
30#include <linux/platform_data/i2c-omap.h>
31#include <linux/pm_runtime.h>
32#include <linux/pinctrl/consumer.h>
33
34/* I2C controller revisions */
35#define OMAP_I2C_OMAP1_REV_2 0x20
36
37/* I2C controller revisions present on specific hardware */
38#define OMAP_I2C_REV_ON_2430 0x00000036
39#define OMAP_I2C_REV_ON_3430_3530 0x0000003C
40#define OMAP_I2C_REV_ON_3630 0x00000040
41#define OMAP_I2C_REV_ON_4430_PLUS 0x50400002
42
43/* timeout waiting for the controller to respond */
44#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
45
46/* timeout for pm runtime autosuspend */
47#define OMAP_I2C_PM_TIMEOUT 1000 /* ms */
48
49/* timeout for making decision on bus free status */
50#define OMAP_I2C_BUS_FREE_TIMEOUT (msecs_to_jiffies(10))
51
52/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
53enum {
54 OMAP_I2C_REV_REG = 0,
55 OMAP_I2C_IE_REG,
56 OMAP_I2C_STAT_REG,
57 OMAP_I2C_IV_REG,
58 OMAP_I2C_WE_REG,
59 OMAP_I2C_SYSS_REG,
60 OMAP_I2C_BUF_REG,
61 OMAP_I2C_CNT_REG,
62 OMAP_I2C_DATA_REG,
63 OMAP_I2C_SYSC_REG,
64 OMAP_I2C_CON_REG,
65 OMAP_I2C_OA_REG,
66 OMAP_I2C_SA_REG,
67 OMAP_I2C_PSC_REG,
68 OMAP_I2C_SCLL_REG,
69 OMAP_I2C_SCLH_REG,
70 OMAP_I2C_SYSTEST_REG,
71 OMAP_I2C_BUFSTAT_REG,
72 /* only on OMAP4430 */
73 OMAP_I2C_IP_V2_REVNB_LO,
74 OMAP_I2C_IP_V2_REVNB_HI,
75 OMAP_I2C_IP_V2_IRQSTATUS_RAW,
76 OMAP_I2C_IP_V2_IRQENABLE_SET,
77 OMAP_I2C_IP_V2_IRQENABLE_CLR,
78};
79
80/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
81#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
82#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
83#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
84#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
85#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
86#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
87#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
88
89/* I2C Status Register (OMAP_I2C_STAT): */
90#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
91#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
92#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
93#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
94#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
95#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
96#define OMAP_I2C_STAT_BF (1 << 8) /* Bus Free */
97#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
98#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
99#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
100#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
101#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
102
103/* I2C WE wakeup enable register */
104#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
105#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
106#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
107#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
108#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
109#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
110#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
111#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
112#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
113#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
114
115#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
116 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
117 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
118 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
119 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
120
121/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
122#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
123#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
124#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
125#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
126
127/* I2C Configuration Register (OMAP_I2C_CON): */
128#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
129#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
130#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
131#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
132#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
133#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
134#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
135#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
136#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
137#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
138
139/* I2C SCL time value when Master */
140#define OMAP_I2C_SCLL_HSSCLL 8
141#define OMAP_I2C_SCLH_HSSCLH 8
142
143/* I2C System Test Register (OMAP_I2C_SYSTEST): */
144#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
145#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
146#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
147#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
148/* Functional mode */
149#define OMAP_I2C_SYSTEST_SCL_I_FUNC (1 << 8) /* SCL line input value */
150#define OMAP_I2C_SYSTEST_SCL_O_FUNC (1 << 7) /* SCL line output value */
151#define OMAP_I2C_SYSTEST_SDA_I_FUNC (1 << 6) /* SDA line input value */
152#define OMAP_I2C_SYSTEST_SDA_O_FUNC (1 << 5) /* SDA line output value */
153/* SDA/SCL IO mode */
154#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
155#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
156#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
157#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
158
159/* OCP_SYSSTATUS bit definitions */
160#define SYSS_RESETDONE_MASK (1 << 0)
161
162/* OCP_SYSCONFIG bit definitions */
163#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
164#define SYSC_SIDLEMODE_MASK (0x3 << 3)
165#define SYSC_ENAWAKEUP_MASK (1 << 2)
166#define SYSC_SOFTRESET_MASK (1 << 1)
167#define SYSC_AUTOIDLE_MASK (1 << 0)
168
169#define SYSC_IDLEMODE_SMART 0x2
170#define SYSC_CLOCKACTIVITY_FCLK 0x2
171
172/* Errata definitions */
173#define I2C_OMAP_ERRATA_I207 (1 << 0)
174#define I2C_OMAP_ERRATA_I462 (1 << 1)
175
176#define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF
177
178struct omap_i2c_dev {
179 struct device *dev;
180 void __iomem *base; /* virtual */
181 int irq;
182 int reg_shift; /* bit shift for I2C register addresses */
183 struct completion cmd_complete;
184 struct resource *ioarea;
185 u32 latency; /* maximum mpu wkup latency */
186 void (*set_mpu_wkup_lat)(struct device *dev,
187 long latency);
188 u32 speed; /* Speed of bus in kHz */
189 u32 flags;
190 u16 scheme;
191 u16 cmd_err;
192 u8 *buf;
193 u8 *regs;
194 size_t buf_len;
195 struct i2c_adapter adapter;
196 u8 threshold;
197 u8 fifo_size; /* use as flag and value
198 * fifo_size==0 implies no fifo
199 * if set, should be trsh+1
200 */
201 u32 rev;
202 unsigned b_hw:1; /* bad h/w fixes */
203 unsigned bb_valid:1; /* true when BB-bit reflects
204 * the I2C bus state
205 */
206 unsigned receiver:1; /* true when we're in receiver mode */
207 u16 iestate; /* Saved interrupt register */
208 u16 pscstate;
209 u16 scllstate;
210 u16 sclhstate;
211 u16 syscstate;
212 u16 westate;
213 u16 errata;
214};
215
216static const u8 reg_map_ip_v1[] = {
217 [OMAP_I2C_REV_REG] = 0x00,
218 [OMAP_I2C_IE_REG] = 0x01,
219 [OMAP_I2C_STAT_REG] = 0x02,
220 [OMAP_I2C_IV_REG] = 0x03,
221 [OMAP_I2C_WE_REG] = 0x03,
222 [OMAP_I2C_SYSS_REG] = 0x04,
223 [OMAP_I2C_BUF_REG] = 0x05,
224 [OMAP_I2C_CNT_REG] = 0x06,
225 [OMAP_I2C_DATA_REG] = 0x07,
226 [OMAP_I2C_SYSC_REG] = 0x08,
227 [OMAP_I2C_CON_REG] = 0x09,
228 [OMAP_I2C_OA_REG] = 0x0a,
229 [OMAP_I2C_SA_REG] = 0x0b,
230 [OMAP_I2C_PSC_REG] = 0x0c,
231 [OMAP_I2C_SCLL_REG] = 0x0d,
232 [OMAP_I2C_SCLH_REG] = 0x0e,
233 [OMAP_I2C_SYSTEST_REG] = 0x0f,
234 [OMAP_I2C_BUFSTAT_REG] = 0x10,
235};
236
237static const u8 reg_map_ip_v2[] = {
238 [OMAP_I2C_REV_REG] = 0x04,
239 [OMAP_I2C_IE_REG] = 0x2c,
240 [OMAP_I2C_STAT_REG] = 0x28,
241 [OMAP_I2C_IV_REG] = 0x34,
242 [OMAP_I2C_WE_REG] = 0x34,
243 [OMAP_I2C_SYSS_REG] = 0x90,
244 [OMAP_I2C_BUF_REG] = 0x94,
245 [OMAP_I2C_CNT_REG] = 0x98,
246 [OMAP_I2C_DATA_REG] = 0x9c,
247 [OMAP_I2C_SYSC_REG] = 0x10,
248 [OMAP_I2C_CON_REG] = 0xa4,
249 [OMAP_I2C_OA_REG] = 0xa8,
250 [OMAP_I2C_SA_REG] = 0xac,
251 [OMAP_I2C_PSC_REG] = 0xb0,
252 [OMAP_I2C_SCLL_REG] = 0xb4,
253 [OMAP_I2C_SCLH_REG] = 0xb8,
254 [OMAP_I2C_SYSTEST_REG] = 0xbC,
255 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
256 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
257 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
258 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
259 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
260 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
261};
262
263static int omap_i2c_xfer_data(struct omap_i2c_dev *omap);
264
265static inline void omap_i2c_write_reg(struct omap_i2c_dev *omap,
266 int reg, u16 val)
267{
268 writew_relaxed(val, omap->base +
269 (omap->regs[reg] << omap->reg_shift));
270}
271
272static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *omap, int reg)
273{
274 return readw_relaxed(omap->base +
275 (omap->regs[reg] << omap->reg_shift));
276}
277
278static void __omap_i2c_init(struct omap_i2c_dev *omap)
279{
280
281 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
282
283 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
284 omap_i2c_write_reg(omap, OMAP_I2C_PSC_REG, omap->pscstate);
285
286 /* SCL low and high time values */
287 omap_i2c_write_reg(omap, OMAP_I2C_SCLL_REG, omap->scllstate);
288 omap_i2c_write_reg(omap, OMAP_I2C_SCLH_REG, omap->sclhstate);
289 if (omap->rev >= OMAP_I2C_REV_ON_3430_3530)
290 omap_i2c_write_reg(omap, OMAP_I2C_WE_REG, omap->westate);
291
292 /* Take the I2C module out of reset: */
293 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
294
295 /*
296 * NOTE: right after setting CON_EN, STAT_BB could be 0 while the
297 * bus is busy. It will be changed to 1 on the next IP FCLK clock.
298 * udelay(1) will be enough to fix that.
299 */
300
301 /*
302 * Don't write to this register if the IE state is 0 as it can
303 * cause deadlock.
304 */
305 if (omap->iestate)
306 omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, omap->iestate);
307}
308
309static int omap_i2c_reset(struct omap_i2c_dev *omap)
310{
311 unsigned long timeout;
312 u16 sysc;
313
314 if (omap->rev >= OMAP_I2C_OMAP1_REV_2) {
315 sysc = omap_i2c_read_reg(omap, OMAP_I2C_SYSC_REG);
316
317 /* Disable I2C controller before soft reset */
318 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG,
319 omap_i2c_read_reg(omap, OMAP_I2C_CON_REG) &
320 ~(OMAP_I2C_CON_EN));
321
322 omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
323 /* For some reason we need to set the EN bit before the
324 * reset done bit gets set. */
325 timeout = jiffies + OMAP_I2C_TIMEOUT;
326 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
327 while (!(omap_i2c_read_reg(omap, OMAP_I2C_SYSS_REG) &
328 SYSS_RESETDONE_MASK)) {
329 if (time_after(jiffies, timeout)) {
330 dev_warn(omap->dev, "timeout waiting "
331 "for controller reset\n");
332 return -ETIMEDOUT;
333 }
334 msleep(1);
335 }
336
337 /* SYSC register is cleared by the reset; rewrite it */
338 omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, sysc);
339
340 if (omap->rev > OMAP_I2C_REV_ON_3430_3530) {
341 /* Schedule I2C-bus monitoring on the next transfer */
342 omap->bb_valid = 0;
343 }
344 }
345
346 return 0;
347}
348
349static int omap_i2c_init(struct omap_i2c_dev *omap)
350{
351 u16 psc = 0, scll = 0, sclh = 0;
352 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
353 unsigned long fclk_rate = 12000000;
354 unsigned long internal_clk = 0;
355 struct clk *fclk;
356 int error;
357
358 if (omap->rev >= OMAP_I2C_REV_ON_3430_3530) {
359 /*
360 * Enabling all wakup sources to stop I2C freezing on
361 * WFI instruction.
362 * REVISIT: Some wkup sources might not be needed.
363 */
364 omap->westate = OMAP_I2C_WE_ALL;
365 }
366
367 if (omap->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
368 /*
369 * The I2C functional clock is the armxor_ck, so there's
370 * no need to get "armxor_ck" separately. Now, if OMAP2420
371 * always returns 12MHz for the functional clock, we can
372 * do this bit unconditionally.
373 */
374 fclk = clk_get(omap->dev, "fck");
375 if (IS_ERR(fclk)) {
376 error = PTR_ERR(fclk);
377 dev_err(omap->dev, "could not get fck: %i\n", error);
378
379 return error;
380 }
381
382 fclk_rate = clk_get_rate(fclk);
383 clk_put(fclk);
384
385 /* TRM for 5912 says the I2C clock must be prescaled to be
386 * between 7 - 12 MHz. The XOR input clock is typically
387 * 12, 13 or 19.2 MHz. So we should have code that produces:
388 *
389 * XOR MHz Divider Prescaler
390 * 12 1 0
391 * 13 2 1
392 * 19.2 2 1
393 */
394 if (fclk_rate > 12000000)
395 psc = fclk_rate / 12000000;
396 }
397
398 if (!(omap->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
399
400 /*
401 * HSI2C controller internal clk rate should be 19.2 Mhz for
402 * HS and for all modes on 2430. On 34xx we can use lower rate
403 * to get longer filter period for better noise suppression.
404 * The filter is iclk (fclk for HS) period.
405 */
406 if (omap->speed > 400 ||
407 omap->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
408 internal_clk = 19200;
409 else if (omap->speed > 100)
410 internal_clk = 9600;
411 else
412 internal_clk = 4000;
413 fclk = clk_get(omap->dev, "fck");
414 if (IS_ERR(fclk)) {
415 error = PTR_ERR(fclk);
416 dev_err(omap->dev, "could not get fck: %i\n", error);
417
418 return error;
419 }
420 fclk_rate = clk_get_rate(fclk) / 1000;
421 clk_put(fclk);
422
423 /* Compute prescaler divisor */
424 psc = fclk_rate / internal_clk;
425 psc = psc - 1;
426
427 /* If configured for High Speed */
428 if (omap->speed > 400) {
429 unsigned long scl;
430
431 /* For first phase of HS mode */
432 scl = internal_clk / 400;
433 fsscll = scl - (scl / 3) - 7;
434 fssclh = (scl / 3) - 5;
435
436 /* For second phase of HS mode */
437 scl = fclk_rate / omap->speed;
438 hsscll = scl - (scl / 3) - 7;
439 hssclh = (scl / 3) - 5;
440 } else if (omap->speed > 100) {
441 unsigned long scl;
442
443 /* Fast mode */
444 scl = internal_clk / omap->speed;
445 fsscll = scl - (scl / 3) - 7;
446 fssclh = (scl / 3) - 5;
447 } else {
448 /* Standard mode */
449 fsscll = internal_clk / (omap->speed * 2) - 7;
450 fssclh = internal_clk / (omap->speed * 2) - 5;
451 }
452 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
453 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
454 } else {
455 /* Program desired operating rate */
456 fclk_rate /= (psc + 1) * 1000;
457 if (psc > 2)
458 psc = 2;
459 scll = fclk_rate / (omap->speed * 2) - 7 + psc;
460 sclh = fclk_rate / (omap->speed * 2) - 7 + psc;
461 }
462
463 omap->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
464 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
465 OMAP_I2C_IE_AL) | ((omap->fifo_size) ?
466 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
467
468 omap->pscstate = psc;
469 omap->scllstate = scll;
470 omap->sclhstate = sclh;
471
472 if (omap->rev <= OMAP_I2C_REV_ON_3430_3530) {
473 /* Not implemented */
474 omap->bb_valid = 1;
475 }
476
477 __omap_i2c_init(omap);
478
479 return 0;
480}
481
482/*
483 * Try bus recovery, but only if SDA is actually low.
484 */
485static int omap_i2c_recover_bus(struct omap_i2c_dev *omap)
486{
487 u16 systest;
488
489 systest = omap_i2c_read_reg(omap, OMAP_I2C_SYSTEST_REG);
490 if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) &&
491 (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC))
492 return 0; /* bus seems to already be fine */
493 if (!(systest & OMAP_I2C_SYSTEST_SCL_I_FUNC))
494 return -EBUSY; /* recovery would not fix SCL */
495 return i2c_recover_bus(&omap->adapter);
496}
497
498/*
499 * Waiting on Bus Busy
500 */
501static int omap_i2c_wait_for_bb(struct omap_i2c_dev *omap)
502{
503 unsigned long timeout;
504
505 timeout = jiffies + OMAP_I2C_TIMEOUT;
506 while (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
507 if (time_after(jiffies, timeout))
508 return omap_i2c_recover_bus(omap);
509 msleep(1);
510 }
511
512 return 0;
513}
514
515/*
516 * Wait while BB-bit doesn't reflect the I2C bus state
517 *
518 * In a multimaster environment, after IP software reset, BB-bit value doesn't
519 * correspond to the current bus state. It may happen what BB-bit will be 0,
520 * while the bus is busy due to another I2C master activity.
521 * Here are BB-bit values after reset:
522 * SDA SCL BB NOTES
523 * 0 0 0 1, 2
524 * 1 0 0 1, 2
525 * 0 1 1
526 * 1 1 0 3
527 * Later, if IP detect SDA=0 and SCL=1 (ACK) or SDA 1->0 while SCL=1 (START)
528 * combinations on the bus, it set BB-bit to 1.
529 * If IP detect SDA 0->1 while SCL=1 (STOP) combination on the bus,
530 * it set BB-bit to 0 and BF to 1.
531 * BB and BF bits correctly tracks the bus state while IP is suspended
532 * BB bit became valid on the next FCLK clock after CON_EN bit set
533 *
534 * NOTES:
535 * 1. Any transfer started when BB=0 and bus is busy wouldn't be
536 * completed by IP and results in controller timeout.
537 * 2. Any transfer started when BB=0 and SCL=0 results in IP
538 * starting to drive SDA low. In that case IP corrupt data
539 * on the bus.
540 * 3. Any transfer started in the middle of another master's transfer
541 * results in unpredictable results and data corruption
542 */
543static int omap_i2c_wait_for_bb_valid(struct omap_i2c_dev *omap)
544{
545 unsigned long bus_free_timeout = 0;
546 unsigned long timeout;
547 int bus_free = 0;
548 u16 stat, systest;
549
550 if (omap->bb_valid)
551 return 0;
552
553 timeout = jiffies + OMAP_I2C_TIMEOUT;
554 while (1) {
555 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
556 /*
557 * We will see BB or BF event in a case IP had detected any
558 * activity on the I2C bus. Now IP correctly tracks the bus
559 * state. BB-bit value is valid.
560 */
561 if (stat & (OMAP_I2C_STAT_BB | OMAP_I2C_STAT_BF))
562 break;
563
564 /*
565 * Otherwise, we must look signals on the bus to make
566 * the right decision.
567 */
568 systest = omap_i2c_read_reg(omap, OMAP_I2C_SYSTEST_REG);
569 if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) &&
570 (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC)) {
571 if (!bus_free) {
572 bus_free_timeout = jiffies +
573 OMAP_I2C_BUS_FREE_TIMEOUT;
574 bus_free = 1;
575 }
576
577 /*
578 * SDA and SCL lines was high for 10 ms without bus
579 * activity detected. The bus is free. Consider
580 * BB-bit value is valid.
581 */
582 if (time_after(jiffies, bus_free_timeout))
583 break;
584 } else {
585 bus_free = 0;
586 }
587
588 if (time_after(jiffies, timeout)) {
589 /*
590 * SDA or SCL were low for the entire timeout without
591 * any activity detected. Most likely, a slave is
592 * locking up the bus with no master driving the clock.
593 */
594 dev_warn(omap->dev, "timeout waiting for bus ready\n");
595 return omap_i2c_recover_bus(omap);
596 }
597
598 msleep(1);
599 }
600
601 omap->bb_valid = 1;
602 return 0;
603}
604
605static void omap_i2c_resize_fifo(struct omap_i2c_dev *omap, u8 size, bool is_rx)
606{
607 u16 buf;
608
609 if (omap->flags & OMAP_I2C_FLAG_NO_FIFO)
610 return;
611
612 /*
613 * Set up notification threshold based on message size. We're doing
614 * this to try and avoid draining feature as much as possible. Whenever
615 * we have big messages to transfer (bigger than our total fifo size)
616 * then we might use draining feature to transfer the remaining bytes.
617 */
618
619 omap->threshold = clamp(size, (u8) 1, omap->fifo_size);
620
621 buf = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG);
622
623 if (is_rx) {
624 /* Clear RX Threshold */
625 buf &= ~(0x3f << 8);
626 buf |= ((omap->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
627 } else {
628 /* Clear TX Threshold */
629 buf &= ~0x3f;
630 buf |= (omap->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
631 }
632
633 omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, buf);
634
635 if (omap->rev < OMAP_I2C_REV_ON_3630)
636 omap->b_hw = 1; /* Enable hardware fixes */
637
638 /* calculate wakeup latency constraint for MPU */
639 if (omap->set_mpu_wkup_lat != NULL)
640 omap->latency = (1000000 * omap->threshold) /
641 (1000 * omap->speed / 8);
642}
643
644static void omap_i2c_wait(struct omap_i2c_dev *omap)
645{
646 u16 stat;
647 u16 mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
648 int count = 0;
649
650 do {
651 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
652 count++;
653 } while (!(stat & mask) && count < 5);
654}
655
656/*
657 * Low level master read/write transaction.
658 */
659static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
660 struct i2c_msg *msg, int stop, bool polling)
661{
662 struct omap_i2c_dev *omap = i2c_get_adapdata(adap);
663 unsigned long timeout;
664 u16 w;
665 int ret;
666
667 dev_dbg(omap->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
668 msg->addr, msg->len, msg->flags, stop);
669
670 omap->receiver = !!(msg->flags & I2C_M_RD);
671 omap_i2c_resize_fifo(omap, msg->len, omap->receiver);
672
673 omap_i2c_write_reg(omap, OMAP_I2C_SA_REG, msg->addr);
674
675 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
676 omap->buf = msg->buf;
677 omap->buf_len = msg->len;
678
679 /* make sure writes to omap->buf_len are ordered */
680 barrier();
681
682 omap_i2c_write_reg(omap, OMAP_I2C_CNT_REG, omap->buf_len);
683
684 /* Clear the FIFO Buffers */
685 w = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG);
686 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
687 omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, w);
688
689 if (!polling)
690 reinit_completion(&omap->cmd_complete);
691 omap->cmd_err = 0;
692
693 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
694
695 /* High speed configuration */
696 if (omap->speed > 400)
697 w |= OMAP_I2C_CON_OPMODE_HS;
698
699 if (msg->flags & I2C_M_STOP)
700 stop = 1;
701 if (msg->flags & I2C_M_TEN)
702 w |= OMAP_I2C_CON_XA;
703 if (!(msg->flags & I2C_M_RD))
704 w |= OMAP_I2C_CON_TRX;
705
706 if (!omap->b_hw && stop)
707 w |= OMAP_I2C_CON_STP;
708 /*
709 * NOTE: STAT_BB bit could became 1 here if another master occupy
710 * the bus. IP successfully complete transfer when the bus will be
711 * free again (BB reset to 0).
712 */
713 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
714
715 /*
716 * Don't write stt and stp together on some hardware.
717 */
718 if (omap->b_hw && stop) {
719 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
720 u16 con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
721 while (con & OMAP_I2C_CON_STT) {
722 con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
723
724 /* Let the user know if i2c is in a bad state */
725 if (time_after(jiffies, delay)) {
726 dev_err(omap->dev, "controller timed out "
727 "waiting for start condition to finish\n");
728 return -ETIMEDOUT;
729 }
730 cpu_relax();
731 }
732
733 w |= OMAP_I2C_CON_STP;
734 w &= ~OMAP_I2C_CON_STT;
735 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
736 }
737
738 /*
739 * REVISIT: We should abort the transfer on signals, but the bus goes
740 * into arbitration and we're currently unable to recover from it.
741 */
742 if (!polling) {
743 timeout = wait_for_completion_timeout(&omap->cmd_complete,
744 OMAP_I2C_TIMEOUT);
745 } else {
746 do {
747 omap_i2c_wait(omap);
748 ret = omap_i2c_xfer_data(omap);
749 } while (ret == -EAGAIN);
750
751 timeout = !ret;
752 }
753
754 if (timeout == 0) {
755 dev_err(omap->dev, "controller timed out\n");
756 omap_i2c_reset(omap);
757 __omap_i2c_init(omap);
758 return -ETIMEDOUT;
759 }
760
761 if (likely(!omap->cmd_err))
762 return 0;
763
764 /* We have an error */
765 if (omap->cmd_err & (OMAP_I2C_STAT_ROVR | OMAP_I2C_STAT_XUDF)) {
766 omap_i2c_reset(omap);
767 __omap_i2c_init(omap);
768 return -EIO;
769 }
770
771 if (omap->cmd_err & OMAP_I2C_STAT_AL)
772 return -EAGAIN;
773
774 if (omap->cmd_err & OMAP_I2C_STAT_NACK) {
775 if (msg->flags & I2C_M_IGNORE_NAK)
776 return 0;
777
778 w = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
779 w |= OMAP_I2C_CON_STP;
780 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
781 return -EREMOTEIO;
782 }
783 return -EIO;
784}
785
786
787/*
788 * Prepare controller for a transaction and call omap_i2c_xfer_msg
789 * to do the work during IRQ processing.
790 */
791static int
792omap_i2c_xfer_common(struct i2c_adapter *adap, struct i2c_msg msgs[], int num,
793 bool polling)
794{
795 struct omap_i2c_dev *omap = i2c_get_adapdata(adap);
796 int i;
797 int r;
798
799 r = pm_runtime_get_sync(omap->dev);
800 if (r < 0)
801 goto out;
802
803 r = omap_i2c_wait_for_bb_valid(omap);
804 if (r < 0)
805 goto out;
806
807 r = omap_i2c_wait_for_bb(omap);
808 if (r < 0)
809 goto out;
810
811 if (omap->set_mpu_wkup_lat != NULL)
812 omap->set_mpu_wkup_lat(omap->dev, omap->latency);
813
814 for (i = 0; i < num; i++) {
815 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)),
816 polling);
817 if (r != 0)
818 break;
819 }
820
821 if (r == 0)
822 r = num;
823
824 omap_i2c_wait_for_bb(omap);
825
826 if (omap->set_mpu_wkup_lat != NULL)
827 omap->set_mpu_wkup_lat(omap->dev, -1);
828
829out:
830 pm_runtime_mark_last_busy(omap->dev);
831 pm_runtime_put_autosuspend(omap->dev);
832 return r;
833}
834
835static int
836omap_i2c_xfer_irq(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
837{
838 return omap_i2c_xfer_common(adap, msgs, num, false);
839}
840
841static int
842omap_i2c_xfer_polling(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
843{
844 return omap_i2c_xfer_common(adap, msgs, num, true);
845}
846
847static u32
848omap_i2c_func(struct i2c_adapter *adap)
849{
850 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
851 I2C_FUNC_PROTOCOL_MANGLING;
852}
853
854static inline void
855omap_i2c_complete_cmd(struct omap_i2c_dev *omap, u16 err)
856{
857 omap->cmd_err |= err;
858 complete(&omap->cmd_complete);
859}
860
861static inline void
862omap_i2c_ack_stat(struct omap_i2c_dev *omap, u16 stat)
863{
864 omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, stat);
865}
866
867static inline void i2c_omap_errata_i207(struct omap_i2c_dev *omap, u16 stat)
868{
869 /*
870 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
871 * Not applicable for OMAP4.
872 * Under certain rare conditions, RDR could be set again
873 * when the bus is busy, then ignore the interrupt and
874 * clear the interrupt.
875 */
876 if (stat & OMAP_I2C_STAT_RDR) {
877 /* Step 1: If RDR is set, clear it */
878 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
879
880 /* Step 2: */
881 if (!(omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)
882 & OMAP_I2C_STAT_BB)) {
883
884 /* Step 3: */
885 if (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)
886 & OMAP_I2C_STAT_RDR) {
887 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
888 dev_dbg(omap->dev, "RDR when bus is busy.\n");
889 }
890
891 }
892 }
893}
894
895/* rev1 devices are apparently only on some 15xx */
896#ifdef CONFIG_ARCH_OMAP15XX
897
898static irqreturn_t
899omap_i2c_omap1_isr(int this_irq, void *dev_id)
900{
901 struct omap_i2c_dev *omap = dev_id;
902 u16 iv, w;
903
904 if (pm_runtime_suspended(omap->dev))
905 return IRQ_NONE;
906
907 iv = omap_i2c_read_reg(omap, OMAP_I2C_IV_REG);
908 switch (iv) {
909 case 0x00: /* None */
910 break;
911 case 0x01: /* Arbitration lost */
912 dev_err(omap->dev, "Arbitration lost\n");
913 omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_AL);
914 break;
915 case 0x02: /* No acknowledgement */
916 omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_NACK);
917 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
918 break;
919 case 0x03: /* Register access ready */
920 omap_i2c_complete_cmd(omap, 0);
921 break;
922 case 0x04: /* Receive data ready */
923 if (omap->buf_len) {
924 w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG);
925 *omap->buf++ = w;
926 omap->buf_len--;
927 if (omap->buf_len) {
928 *omap->buf++ = w >> 8;
929 omap->buf_len--;
930 }
931 } else
932 dev_err(omap->dev, "RRDY IRQ while no data requested\n");
933 break;
934 case 0x05: /* Transmit data ready */
935 if (omap->buf_len) {
936 w = *omap->buf++;
937 omap->buf_len--;
938 if (omap->buf_len) {
939 w |= *omap->buf++ << 8;
940 omap->buf_len--;
941 }
942 omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w);
943 } else
944 dev_err(omap->dev, "XRDY IRQ while no data to send\n");
945 break;
946 default:
947 return IRQ_NONE;
948 }
949
950 return IRQ_HANDLED;
951}
952#else
953#define omap_i2c_omap1_isr NULL
954#endif
955
956/*
957 * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing
958 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
959 * them from the memory to the I2C interface.
960 */
961static int errata_omap3_i462(struct omap_i2c_dev *omap)
962{
963 unsigned long timeout = 10000;
964 u16 stat;
965
966 do {
967 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
968 if (stat & OMAP_I2C_STAT_XUDF)
969 break;
970
971 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
972 omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_XRDY |
973 OMAP_I2C_STAT_XDR));
974 if (stat & OMAP_I2C_STAT_NACK) {
975 omap->cmd_err |= OMAP_I2C_STAT_NACK;
976 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK);
977 }
978
979 if (stat & OMAP_I2C_STAT_AL) {
980 dev_err(omap->dev, "Arbitration lost\n");
981 omap->cmd_err |= OMAP_I2C_STAT_AL;
982 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL);
983 }
984
985 return -EIO;
986 }
987
988 cpu_relax();
989 } while (--timeout);
990
991 if (!timeout) {
992 dev_err(omap->dev, "timeout waiting on XUDF bit\n");
993 return 0;
994 }
995
996 return 0;
997}
998
999static void omap_i2c_receive_data(struct omap_i2c_dev *omap, u8 num_bytes,
1000 bool is_rdr)
1001{
1002 u16 w;
1003
1004 while (num_bytes--) {
1005 w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG);
1006 *omap->buf++ = w;
1007 omap->buf_len--;
1008
1009 /*
1010 * Data reg in 2430, omap3 and
1011 * omap4 is 8 bit wide
1012 */
1013 if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
1014 *omap->buf++ = w >> 8;
1015 omap->buf_len--;
1016 }
1017 }
1018}
1019
1020static int omap_i2c_transmit_data(struct omap_i2c_dev *omap, u8 num_bytes,
1021 bool is_xdr)
1022{
1023 u16 w;
1024
1025 while (num_bytes--) {
1026 w = *omap->buf++;
1027 omap->buf_len--;
1028
1029 /*
1030 * Data reg in 2430, omap3 and
1031 * omap4 is 8 bit wide
1032 */
1033 if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
1034 w |= *omap->buf++ << 8;
1035 omap->buf_len--;
1036 }
1037
1038 if (omap->errata & I2C_OMAP_ERRATA_I462) {
1039 int ret;
1040
1041 ret = errata_omap3_i462(omap);
1042 if (ret < 0)
1043 return ret;
1044 }
1045
1046 omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w);
1047 }
1048
1049 return 0;
1050}
1051
1052static irqreturn_t
1053omap_i2c_isr(int irq, void *dev_id)
1054{
1055 struct omap_i2c_dev *omap = dev_id;
1056 irqreturn_t ret = IRQ_HANDLED;
1057 u16 mask;
1058 u16 stat;
1059
1060 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
1061 mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
1062
1063 if (stat & mask)
1064 ret = IRQ_WAKE_THREAD;
1065
1066 return ret;
1067}
1068
1069static int omap_i2c_xfer_data(struct omap_i2c_dev *omap)
1070{
1071 u16 bits;
1072 u16 stat;
1073 int err = 0, count = 0;
1074
1075 do {
1076 bits = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
1077 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
1078 stat &= bits;
1079
1080 /* If we're in receiver mode, ignore XDR/XRDY */
1081 if (omap->receiver)
1082 stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
1083 else
1084 stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
1085
1086 if (!stat) {
1087 /* my work here is done */
1088 err = -EAGAIN;
1089 break;
1090 }
1091
1092 dev_dbg(omap->dev, "IRQ (ISR = 0x%04x)\n", stat);
1093 if (count++ == 100) {
1094 dev_warn(omap->dev, "Too much work in one IRQ\n");
1095 break;
1096 }
1097
1098 if (stat & OMAP_I2C_STAT_NACK) {
1099 err |= OMAP_I2C_STAT_NACK;
1100 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK);
1101 }
1102
1103 if (stat & OMAP_I2C_STAT_AL) {
1104 dev_err(omap->dev, "Arbitration lost\n");
1105 err |= OMAP_I2C_STAT_AL;
1106 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL);
1107 }
1108
1109 /*
1110 * ProDB0017052: Clear ARDY bit twice
1111 */
1112 if (stat & OMAP_I2C_STAT_ARDY)
1113 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ARDY);
1114
1115 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
1116 OMAP_I2C_STAT_AL)) {
1117 omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_RRDY |
1118 OMAP_I2C_STAT_RDR |
1119 OMAP_I2C_STAT_XRDY |
1120 OMAP_I2C_STAT_XDR |
1121 OMAP_I2C_STAT_ARDY));
1122 break;
1123 }
1124
1125 if (stat & OMAP_I2C_STAT_RDR) {
1126 u8 num_bytes = 1;
1127
1128 if (omap->fifo_size)
1129 num_bytes = omap->buf_len;
1130
1131 if (omap->errata & I2C_OMAP_ERRATA_I207) {
1132 i2c_omap_errata_i207(omap, stat);
1133 num_bytes = (omap_i2c_read_reg(omap,
1134 OMAP_I2C_BUFSTAT_REG) >> 8) & 0x3F;
1135 }
1136
1137 omap_i2c_receive_data(omap, num_bytes, true);
1138 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
1139 continue;
1140 }
1141
1142 if (stat & OMAP_I2C_STAT_RRDY) {
1143 u8 num_bytes = 1;
1144
1145 if (omap->threshold)
1146 num_bytes = omap->threshold;
1147
1148 omap_i2c_receive_data(omap, num_bytes, false);
1149 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RRDY);
1150 continue;
1151 }
1152
1153 if (stat & OMAP_I2C_STAT_XDR) {
1154 u8 num_bytes = 1;
1155 int ret;
1156
1157 if (omap->fifo_size)
1158 num_bytes = omap->buf_len;
1159
1160 ret = omap_i2c_transmit_data(omap, num_bytes, true);
1161 if (ret < 0)
1162 break;
1163
1164 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XDR);
1165 continue;
1166 }
1167
1168 if (stat & OMAP_I2C_STAT_XRDY) {
1169 u8 num_bytes = 1;
1170 int ret;
1171
1172 if (omap->threshold)
1173 num_bytes = omap->threshold;
1174
1175 ret = omap_i2c_transmit_data(omap, num_bytes, false);
1176 if (ret < 0)
1177 break;
1178
1179 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XRDY);
1180 continue;
1181 }
1182
1183 if (stat & OMAP_I2C_STAT_ROVR) {
1184 dev_err(omap->dev, "Receive overrun\n");
1185 err |= OMAP_I2C_STAT_ROVR;
1186 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ROVR);
1187 break;
1188 }
1189
1190 if (stat & OMAP_I2C_STAT_XUDF) {
1191 dev_err(omap->dev, "Transmit underflow\n");
1192 err |= OMAP_I2C_STAT_XUDF;
1193 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XUDF);
1194 break;
1195 }
1196 } while (stat);
1197
1198 return err;
1199}
1200
1201static irqreturn_t
1202omap_i2c_isr_thread(int this_irq, void *dev_id)
1203{
1204 int ret;
1205 struct omap_i2c_dev *omap = dev_id;
1206
1207 ret = omap_i2c_xfer_data(omap);
1208 if (ret != -EAGAIN)
1209 omap_i2c_complete_cmd(omap, ret);
1210
1211 return IRQ_HANDLED;
1212}
1213
1214static const struct i2c_algorithm omap_i2c_algo = {
1215 .master_xfer = omap_i2c_xfer_irq,
1216 .master_xfer_atomic = omap_i2c_xfer_polling,
1217 .functionality = omap_i2c_func,
1218};
1219
1220static const struct i2c_adapter_quirks omap_i2c_quirks = {
1221 .flags = I2C_AQ_NO_ZERO_LEN,
1222};
1223
1224#ifdef CONFIG_OF
1225static struct omap_i2c_bus_platform_data omap2420_pdata = {
1226 .rev = OMAP_I2C_IP_VERSION_1,
1227 .flags = OMAP_I2C_FLAG_NO_FIFO |
1228 OMAP_I2C_FLAG_SIMPLE_CLOCK |
1229 OMAP_I2C_FLAG_16BIT_DATA_REG |
1230 OMAP_I2C_FLAG_BUS_SHIFT_2,
1231};
1232
1233static struct omap_i2c_bus_platform_data omap2430_pdata = {
1234 .rev = OMAP_I2C_IP_VERSION_1,
1235 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 |
1236 OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
1237};
1238
1239static struct omap_i2c_bus_platform_data omap3_pdata = {
1240 .rev = OMAP_I2C_IP_VERSION_1,
1241 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
1242};
1243
1244static struct omap_i2c_bus_platform_data omap4_pdata = {
1245 .rev = OMAP_I2C_IP_VERSION_2,
1246};
1247
1248static const struct of_device_id omap_i2c_of_match[] = {
1249 {
1250 .compatible = "ti,omap4-i2c",
1251 .data = &omap4_pdata,
1252 },
1253 {
1254 .compatible = "ti,omap3-i2c",
1255 .data = &omap3_pdata,
1256 },
1257 {
1258 .compatible = "ti,omap2430-i2c",
1259 .data = &omap2430_pdata,
1260 },
1261 {
1262 .compatible = "ti,omap2420-i2c",
1263 .data = &omap2420_pdata,
1264 },
1265 { },
1266};
1267MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
1268#endif
1269
1270#define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14)
1271
1272#define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4)
1273#define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf)
1274
1275#define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7)
1276#define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f)
1277#define OMAP_I2C_SCHEME_0 0
1278#define OMAP_I2C_SCHEME_1 1
1279
1280static int omap_i2c_get_scl(struct i2c_adapter *adap)
1281{
1282 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1283 u32 reg;
1284
1285 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1286
1287 return reg & OMAP_I2C_SYSTEST_SCL_I_FUNC;
1288}
1289
1290static int omap_i2c_get_sda(struct i2c_adapter *adap)
1291{
1292 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1293 u32 reg;
1294
1295 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1296
1297 return reg & OMAP_I2C_SYSTEST_SDA_I_FUNC;
1298}
1299
1300static void omap_i2c_set_scl(struct i2c_adapter *adap, int val)
1301{
1302 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1303 u32 reg;
1304
1305 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1306 if (val)
1307 reg |= OMAP_I2C_SYSTEST_SCL_O;
1308 else
1309 reg &= ~OMAP_I2C_SYSTEST_SCL_O;
1310 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1311}
1312
1313static void omap_i2c_prepare_recovery(struct i2c_adapter *adap)
1314{
1315 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1316 u32 reg;
1317
1318 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1319 /* enable test mode */
1320 reg |= OMAP_I2C_SYSTEST_ST_EN;
1321 /* select SDA/SCL IO mode */
1322 reg |= 3 << OMAP_I2C_SYSTEST_TMODE_SHIFT;
1323 /* set SCL to high-impedance state (reset value is 0) */
1324 reg |= OMAP_I2C_SYSTEST_SCL_O;
1325 /* set SDA to high-impedance state (reset value is 0) */
1326 reg |= OMAP_I2C_SYSTEST_SDA_O;
1327 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1328}
1329
1330static void omap_i2c_unprepare_recovery(struct i2c_adapter *adap)
1331{
1332 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1333 u32 reg;
1334
1335 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1336 /* restore reset values */
1337 reg &= ~OMAP_I2C_SYSTEST_ST_EN;
1338 reg &= ~OMAP_I2C_SYSTEST_TMODE_MASK;
1339 reg &= ~OMAP_I2C_SYSTEST_SCL_O;
1340 reg &= ~OMAP_I2C_SYSTEST_SDA_O;
1341 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1342}
1343
1344static struct i2c_bus_recovery_info omap_i2c_bus_recovery_info = {
1345 .get_scl = omap_i2c_get_scl,
1346 .get_sda = omap_i2c_get_sda,
1347 .set_scl = omap_i2c_set_scl,
1348 .prepare_recovery = omap_i2c_prepare_recovery,
1349 .unprepare_recovery = omap_i2c_unprepare_recovery,
1350 .recover_bus = i2c_generic_scl_recovery,
1351};
1352
1353static int
1354omap_i2c_probe(struct platform_device *pdev)
1355{
1356 struct omap_i2c_dev *omap;
1357 struct i2c_adapter *adap;
1358 const struct omap_i2c_bus_platform_data *pdata =
1359 dev_get_platdata(&pdev->dev);
1360 struct device_node *node = pdev->dev.of_node;
1361 const struct of_device_id *match;
1362 int irq;
1363 int r;
1364 u32 rev;
1365 u16 minor, major;
1366
1367 irq = platform_get_irq(pdev, 0);
1368 if (irq < 0)
1369 return irq;
1370
1371 omap = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
1372 if (!omap)
1373 return -ENOMEM;
1374
1375 omap->base = devm_platform_ioremap_resource(pdev, 0);
1376 if (IS_ERR(omap->base))
1377 return PTR_ERR(omap->base);
1378
1379 match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
1380 if (match) {
1381 u32 freq = I2C_MAX_STANDARD_MODE_FREQ;
1382
1383 pdata = match->data;
1384 omap->flags = pdata->flags;
1385
1386 of_property_read_u32(node, "clock-frequency", &freq);
1387 /* convert DT freq value in Hz into kHz for speed */
1388 omap->speed = freq / 1000;
1389 } else if (pdata != NULL) {
1390 omap->speed = pdata->clkrate;
1391 omap->flags = pdata->flags;
1392 omap->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1393 }
1394
1395 omap->dev = &pdev->dev;
1396 omap->irq = irq;
1397
1398 platform_set_drvdata(pdev, omap);
1399 init_completion(&omap->cmd_complete);
1400
1401 omap->reg_shift = (omap->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
1402
1403 pm_runtime_enable(omap->dev);
1404 pm_runtime_set_autosuspend_delay(omap->dev, OMAP_I2C_PM_TIMEOUT);
1405 pm_runtime_use_autosuspend(omap->dev);
1406
1407 r = pm_runtime_resume_and_get(omap->dev);
1408 if (r < 0)
1409 goto err_disable_pm;
1410
1411 /*
1412 * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.
1413 * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset.
1414 * Also since the omap_i2c_read_reg uses reg_map_ip_* a
1415 * readw_relaxed is done.
1416 */
1417 rev = readw_relaxed(omap->base + 0x04);
1418
1419 omap->scheme = OMAP_I2C_SCHEME(rev);
1420 switch (omap->scheme) {
1421 case OMAP_I2C_SCHEME_0:
1422 omap->regs = (u8 *)reg_map_ip_v1;
1423 omap->rev = omap_i2c_read_reg(omap, OMAP_I2C_REV_REG);
1424 minor = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);
1425 major = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);
1426 break;
1427 case OMAP_I2C_SCHEME_1:
1428 default:
1429 omap->regs = (u8 *)reg_map_ip_v2;
1430 rev = (rev << 16) |
1431 omap_i2c_read_reg(omap, OMAP_I2C_IP_V2_REVNB_LO);
1432 minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);
1433 major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);
1434 omap->rev = rev;
1435 }
1436
1437 omap->errata = 0;
1438
1439 if (omap->rev >= OMAP_I2C_REV_ON_2430 &&
1440 omap->rev < OMAP_I2C_REV_ON_4430_PLUS)
1441 omap->errata |= I2C_OMAP_ERRATA_I207;
1442
1443 if (omap->rev <= OMAP_I2C_REV_ON_3430_3530)
1444 omap->errata |= I2C_OMAP_ERRATA_I462;
1445
1446 if (!(omap->flags & OMAP_I2C_FLAG_NO_FIFO)) {
1447 u16 s;
1448
1449 /* Set up the fifo size - Get total size */
1450 s = (omap_i2c_read_reg(omap, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1451 omap->fifo_size = 0x8 << s;
1452
1453 /*
1454 * Set up notification threshold as half the total available
1455 * size. This is to ensure that we can handle the status on int
1456 * call back latencies.
1457 */
1458
1459 omap->fifo_size = (omap->fifo_size / 2);
1460
1461 if (omap->rev < OMAP_I2C_REV_ON_3630)
1462 omap->b_hw = 1; /* Enable hardware fixes */
1463
1464 /* calculate wakeup latency constraint for MPU */
1465 if (omap->set_mpu_wkup_lat != NULL)
1466 omap->latency = (1000000 * omap->fifo_size) /
1467 (1000 * omap->speed / 8);
1468 }
1469
1470 /* reset ASAP, clearing any IRQs */
1471 omap_i2c_init(omap);
1472
1473 if (omap->rev < OMAP_I2C_OMAP1_REV_2)
1474 r = devm_request_irq(&pdev->dev, omap->irq, omap_i2c_omap1_isr,
1475 IRQF_NO_SUSPEND, pdev->name, omap);
1476 else
1477 r = devm_request_threaded_irq(&pdev->dev, omap->irq,
1478 omap_i2c_isr, omap_i2c_isr_thread,
1479 IRQF_NO_SUSPEND | IRQF_ONESHOT,
1480 pdev->name, omap);
1481
1482 if (r) {
1483 dev_err(omap->dev, "failure requesting irq %i\n", omap->irq);
1484 goto err_unuse_clocks;
1485 }
1486
1487 adap = &omap->adapter;
1488 i2c_set_adapdata(adap, omap);
1489 adap->owner = THIS_MODULE;
1490 adap->class = I2C_CLASS_DEPRECATED;
1491 strscpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
1492 adap->algo = &omap_i2c_algo;
1493 adap->quirks = &omap_i2c_quirks;
1494 adap->dev.parent = &pdev->dev;
1495 adap->dev.of_node = pdev->dev.of_node;
1496 adap->bus_recovery_info = &omap_i2c_bus_recovery_info;
1497
1498 /* i2c device drivers may be active on return from add_adapter() */
1499 adap->nr = pdev->id;
1500 r = i2c_add_numbered_adapter(adap);
1501 if (r)
1502 goto err_unuse_clocks;
1503
1504 dev_info(omap->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,
1505 major, minor, omap->speed);
1506
1507 pm_runtime_mark_last_busy(omap->dev);
1508 pm_runtime_put_autosuspend(omap->dev);
1509
1510 return 0;
1511
1512err_unuse_clocks:
1513 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
1514 pm_runtime_dont_use_autosuspend(omap->dev);
1515 pm_runtime_put_sync(omap->dev);
1516err_disable_pm:
1517 pm_runtime_disable(&pdev->dev);
1518
1519 return r;
1520}
1521
1522static int omap_i2c_remove(struct platform_device *pdev)
1523{
1524 struct omap_i2c_dev *omap = platform_get_drvdata(pdev);
1525 int ret;
1526
1527 i2c_del_adapter(&omap->adapter);
1528 ret = pm_runtime_resume_and_get(&pdev->dev);
1529 if (ret < 0)
1530 return ret;
1531
1532 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
1533 pm_runtime_dont_use_autosuspend(&pdev->dev);
1534 pm_runtime_put_sync(&pdev->dev);
1535 pm_runtime_disable(&pdev->dev);
1536 return 0;
1537}
1538
1539static int __maybe_unused omap_i2c_runtime_suspend(struct device *dev)
1540{
1541 struct omap_i2c_dev *omap = dev_get_drvdata(dev);
1542
1543 omap->iestate = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
1544
1545 if (omap->scheme == OMAP_I2C_SCHEME_0)
1546 omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, 0);
1547 else
1548 omap_i2c_write_reg(omap, OMAP_I2C_IP_V2_IRQENABLE_CLR,
1549 OMAP_I2C_IP_V2_INTERRUPTS_MASK);
1550
1551 if (omap->rev < OMAP_I2C_OMAP1_REV_2) {
1552 omap_i2c_read_reg(omap, OMAP_I2C_IV_REG); /* Read clears */
1553 } else {
1554 omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, omap->iestate);
1555
1556 /* Flush posted write */
1557 omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
1558 }
1559
1560 pinctrl_pm_select_sleep_state(dev);
1561
1562 return 0;
1563}
1564
1565static int __maybe_unused omap_i2c_runtime_resume(struct device *dev)
1566{
1567 struct omap_i2c_dev *omap = dev_get_drvdata(dev);
1568
1569 pinctrl_pm_select_default_state(dev);
1570
1571 if (!omap->regs)
1572 return 0;
1573
1574 __omap_i2c_init(omap);
1575
1576 return 0;
1577}
1578
1579static const struct dev_pm_ops omap_i2c_pm_ops = {
1580 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1581 pm_runtime_force_resume)
1582 SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
1583 omap_i2c_runtime_resume, NULL)
1584};
1585
1586static struct platform_driver omap_i2c_driver = {
1587 .probe = omap_i2c_probe,
1588 .remove = omap_i2c_remove,
1589 .driver = {
1590 .name = "omap_i2c",
1591 .pm = &omap_i2c_pm_ops,
1592 .of_match_table = of_match_ptr(omap_i2c_of_match),
1593 },
1594};
1595
1596/* I2C may be needed to bring up other drivers */
1597static int __init
1598omap_i2c_init_driver(void)
1599{
1600 return platform_driver_register(&omap_i2c_driver);
1601}
1602subsys_initcall(omap_i2c_init_driver);
1603
1604static void __exit omap_i2c_exit_driver(void)
1605{
1606 platform_driver_unregister(&omap_i2c_driver);
1607}
1608module_exit(omap_i2c_exit_driver);
1609
1610MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1611MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1612MODULE_LICENSE("GPL");
1613MODULE_ALIAS("platform:omap_i2c");
1/*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2005 Nokia Corporation
6 * Copyright (C) 2004 - 2007 Texas Instruments.
7 *
8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/module.h>
32#include <linux/delay.h>
33#include <linux/i2c.h>
34#include <linux/err.h>
35#include <linux/interrupt.h>
36#include <linux/completion.h>
37#include <linux/platform_device.h>
38#include <linux/clk.h>
39#include <linux/io.h>
40#include <linux/slab.h>
41#include <linux/i2c-omap.h>
42#include <linux/pm_runtime.h>
43
44/* I2C controller revisions */
45#define OMAP_I2C_REV_2 0x20
46
47/* I2C controller revisions present on specific hardware */
48#define OMAP_I2C_REV_ON_2430 0x36
49#define OMAP_I2C_REV_ON_3430 0x3C
50#define OMAP_I2C_REV_ON_4430 0x40
51
52/* timeout waiting for the controller to respond */
53#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
54
55/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
56enum {
57 OMAP_I2C_REV_REG = 0,
58 OMAP_I2C_IE_REG,
59 OMAP_I2C_STAT_REG,
60 OMAP_I2C_IV_REG,
61 OMAP_I2C_WE_REG,
62 OMAP_I2C_SYSS_REG,
63 OMAP_I2C_BUF_REG,
64 OMAP_I2C_CNT_REG,
65 OMAP_I2C_DATA_REG,
66 OMAP_I2C_SYSC_REG,
67 OMAP_I2C_CON_REG,
68 OMAP_I2C_OA_REG,
69 OMAP_I2C_SA_REG,
70 OMAP_I2C_PSC_REG,
71 OMAP_I2C_SCLL_REG,
72 OMAP_I2C_SCLH_REG,
73 OMAP_I2C_SYSTEST_REG,
74 OMAP_I2C_BUFSTAT_REG,
75 OMAP_I2C_REVNB_LO,
76 OMAP_I2C_REVNB_HI,
77 OMAP_I2C_IRQSTATUS_RAW,
78 OMAP_I2C_IRQENABLE_SET,
79 OMAP_I2C_IRQENABLE_CLR,
80};
81
82/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
83#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
84#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
85#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
86#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
87#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
88#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
89#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
90
91/* I2C Status Register (OMAP_I2C_STAT): */
92#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
93#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
94#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
95#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
96#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
97#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
98#define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
99#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
100#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
101#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
102#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
103#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
104
105/* I2C WE wakeup enable register */
106#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
107#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
108#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
109#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
110#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
111#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
112#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
113#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
114#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
115#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
116
117#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
118 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
119 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
120 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
121 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
122
123/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
124#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
125#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
126#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
127#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
128
129/* I2C Configuration Register (OMAP_I2C_CON): */
130#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
131#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
132#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
133#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
134#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
135#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
136#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
137#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
138#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
139#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
140
141/* I2C SCL time value when Master */
142#define OMAP_I2C_SCLL_HSSCLL 8
143#define OMAP_I2C_SCLH_HSSCLH 8
144
145/* I2C System Test Register (OMAP_I2C_SYSTEST): */
146#ifdef DEBUG
147#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
148#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
149#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
150#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
151#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
152#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
153#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
154#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
155#endif
156
157/* OCP_SYSSTATUS bit definitions */
158#define SYSS_RESETDONE_MASK (1 << 0)
159
160/* OCP_SYSCONFIG bit definitions */
161#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
162#define SYSC_SIDLEMODE_MASK (0x3 << 3)
163#define SYSC_ENAWAKEUP_MASK (1 << 2)
164#define SYSC_SOFTRESET_MASK (1 << 1)
165#define SYSC_AUTOIDLE_MASK (1 << 0)
166
167#define SYSC_IDLEMODE_SMART 0x2
168#define SYSC_CLOCKACTIVITY_FCLK 0x2
169
170/* Errata definitions */
171#define I2C_OMAP_ERRATA_I207 (1 << 0)
172#define I2C_OMAP3_1P153 (1 << 1)
173
174struct omap_i2c_dev {
175 struct device *dev;
176 void __iomem *base; /* virtual */
177 int irq;
178 int reg_shift; /* bit shift for I2C register addresses */
179 struct completion cmd_complete;
180 struct resource *ioarea;
181 u32 latency; /* maximum mpu wkup latency */
182 void (*set_mpu_wkup_lat)(struct device *dev,
183 long latency);
184 u32 speed; /* Speed of bus in Khz */
185 u16 cmd_err;
186 u8 *buf;
187 u8 *regs;
188 size_t buf_len;
189 struct i2c_adapter adapter;
190 u8 fifo_size; /* use as flag and value
191 * fifo_size==0 implies no fifo
192 * if set, should be trsh+1
193 */
194 u8 rev;
195 unsigned b_hw:1; /* bad h/w fixes */
196 unsigned idle:1;
197 u16 iestate; /* Saved interrupt register */
198 u16 pscstate;
199 u16 scllstate;
200 u16 sclhstate;
201 u16 bufstate;
202 u16 syscstate;
203 u16 westate;
204 u16 errata;
205};
206
207static const u8 reg_map[] = {
208 [OMAP_I2C_REV_REG] = 0x00,
209 [OMAP_I2C_IE_REG] = 0x01,
210 [OMAP_I2C_STAT_REG] = 0x02,
211 [OMAP_I2C_IV_REG] = 0x03,
212 [OMAP_I2C_WE_REG] = 0x03,
213 [OMAP_I2C_SYSS_REG] = 0x04,
214 [OMAP_I2C_BUF_REG] = 0x05,
215 [OMAP_I2C_CNT_REG] = 0x06,
216 [OMAP_I2C_DATA_REG] = 0x07,
217 [OMAP_I2C_SYSC_REG] = 0x08,
218 [OMAP_I2C_CON_REG] = 0x09,
219 [OMAP_I2C_OA_REG] = 0x0a,
220 [OMAP_I2C_SA_REG] = 0x0b,
221 [OMAP_I2C_PSC_REG] = 0x0c,
222 [OMAP_I2C_SCLL_REG] = 0x0d,
223 [OMAP_I2C_SCLH_REG] = 0x0e,
224 [OMAP_I2C_SYSTEST_REG] = 0x0f,
225 [OMAP_I2C_BUFSTAT_REG] = 0x10,
226};
227
228static const u8 omap4_reg_map[] = {
229 [OMAP_I2C_REV_REG] = 0x04,
230 [OMAP_I2C_IE_REG] = 0x2c,
231 [OMAP_I2C_STAT_REG] = 0x28,
232 [OMAP_I2C_IV_REG] = 0x34,
233 [OMAP_I2C_WE_REG] = 0x34,
234 [OMAP_I2C_SYSS_REG] = 0x90,
235 [OMAP_I2C_BUF_REG] = 0x94,
236 [OMAP_I2C_CNT_REG] = 0x98,
237 [OMAP_I2C_DATA_REG] = 0x9c,
238 [OMAP_I2C_SYSC_REG] = 0x20,
239 [OMAP_I2C_CON_REG] = 0xa4,
240 [OMAP_I2C_OA_REG] = 0xa8,
241 [OMAP_I2C_SA_REG] = 0xac,
242 [OMAP_I2C_PSC_REG] = 0xb0,
243 [OMAP_I2C_SCLL_REG] = 0xb4,
244 [OMAP_I2C_SCLH_REG] = 0xb8,
245 [OMAP_I2C_SYSTEST_REG] = 0xbC,
246 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
247 [OMAP_I2C_REVNB_LO] = 0x00,
248 [OMAP_I2C_REVNB_HI] = 0x04,
249 [OMAP_I2C_IRQSTATUS_RAW] = 0x24,
250 [OMAP_I2C_IRQENABLE_SET] = 0x2c,
251 [OMAP_I2C_IRQENABLE_CLR] = 0x30,
252};
253
254static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
255 int reg, u16 val)
256{
257 __raw_writew(val, i2c_dev->base +
258 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
259}
260
261static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
262{
263 return __raw_readw(i2c_dev->base +
264 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
265}
266
267static void omap_i2c_unidle(struct omap_i2c_dev *dev)
268{
269 struct platform_device *pdev;
270 struct omap_i2c_bus_platform_data *pdata;
271
272 WARN_ON(!dev->idle);
273
274 pdev = to_platform_device(dev->dev);
275 pdata = pdev->dev.platform_data;
276
277 pm_runtime_get_sync(&pdev->dev);
278
279 if (cpu_is_omap34xx()) {
280 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
281 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
282 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
283 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
284 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev->bufstate);
285 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, dev->syscstate);
286 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
287 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
288 }
289 dev->idle = 0;
290
291 /*
292 * Don't write to this register if the IE state is 0 as it can
293 * cause deadlock.
294 */
295 if (dev->iestate)
296 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
297}
298
299static void omap_i2c_idle(struct omap_i2c_dev *dev)
300{
301 struct platform_device *pdev;
302 struct omap_i2c_bus_platform_data *pdata;
303 u16 iv;
304
305 WARN_ON(dev->idle);
306
307 pdev = to_platform_device(dev->dev);
308 pdata = pdev->dev.platform_data;
309
310 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
311 if (dev->rev >= OMAP_I2C_REV_ON_4430)
312 omap_i2c_write_reg(dev, OMAP_I2C_IRQENABLE_CLR, 1);
313 else
314 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
315
316 if (dev->rev < OMAP_I2C_REV_2) {
317 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
318 } else {
319 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
320
321 /* Flush posted write before the dev->idle store occurs */
322 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
323 }
324 dev->idle = 1;
325
326 pm_runtime_put_sync(&pdev->dev);
327}
328
329static int omap_i2c_init(struct omap_i2c_dev *dev)
330{
331 u16 psc = 0, scll = 0, sclh = 0, buf = 0;
332 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
333 unsigned long fclk_rate = 12000000;
334 unsigned long timeout;
335 unsigned long internal_clk = 0;
336 struct clk *fclk;
337
338 if (dev->rev >= OMAP_I2C_REV_2) {
339 /* Disable I2C controller before soft reset */
340 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
341 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
342 ~(OMAP_I2C_CON_EN));
343
344 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
345 /* For some reason we need to set the EN bit before the
346 * reset done bit gets set. */
347 timeout = jiffies + OMAP_I2C_TIMEOUT;
348 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
349 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
350 SYSS_RESETDONE_MASK)) {
351 if (time_after(jiffies, timeout)) {
352 dev_warn(dev->dev, "timeout waiting "
353 "for controller reset\n");
354 return -ETIMEDOUT;
355 }
356 msleep(1);
357 }
358
359 /* SYSC register is cleared by the reset; rewrite it */
360 if (dev->rev == OMAP_I2C_REV_ON_2430) {
361
362 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
363 SYSC_AUTOIDLE_MASK);
364
365 } else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
366 dev->syscstate = SYSC_AUTOIDLE_MASK;
367 dev->syscstate |= SYSC_ENAWAKEUP_MASK;
368 dev->syscstate |= (SYSC_IDLEMODE_SMART <<
369 __ffs(SYSC_SIDLEMODE_MASK));
370 dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
371 __ffs(SYSC_CLOCKACTIVITY_MASK));
372
373 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
374 dev->syscstate);
375 /*
376 * Enabling all wakup sources to stop I2C freezing on
377 * WFI instruction.
378 * REVISIT: Some wkup sources might not be needed.
379 */
380 dev->westate = OMAP_I2C_WE_ALL;
381 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
382 }
383 }
384 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
385
386 if (cpu_class_is_omap1()) {
387 /*
388 * The I2C functional clock is the armxor_ck, so there's
389 * no need to get "armxor_ck" separately. Now, if OMAP2420
390 * always returns 12MHz for the functional clock, we can
391 * do this bit unconditionally.
392 */
393 fclk = clk_get(dev->dev, "fck");
394 fclk_rate = clk_get_rate(fclk);
395 clk_put(fclk);
396
397 /* TRM for 5912 says the I2C clock must be prescaled to be
398 * between 7 - 12 MHz. The XOR input clock is typically
399 * 12, 13 or 19.2 MHz. So we should have code that produces:
400 *
401 * XOR MHz Divider Prescaler
402 * 12 1 0
403 * 13 2 1
404 * 19.2 2 1
405 */
406 if (fclk_rate > 12000000)
407 psc = fclk_rate / 12000000;
408 }
409
410 if (!(cpu_class_is_omap1() || cpu_is_omap2420())) {
411
412 /*
413 * HSI2C controller internal clk rate should be 19.2 Mhz for
414 * HS and for all modes on 2430. On 34xx we can use lower rate
415 * to get longer filter period for better noise suppression.
416 * The filter is iclk (fclk for HS) period.
417 */
418 if (dev->speed > 400 || cpu_is_omap2430())
419 internal_clk = 19200;
420 else if (dev->speed > 100)
421 internal_clk = 9600;
422 else
423 internal_clk = 4000;
424 fclk = clk_get(dev->dev, "fck");
425 fclk_rate = clk_get_rate(fclk) / 1000;
426 clk_put(fclk);
427
428 /* Compute prescaler divisor */
429 psc = fclk_rate / internal_clk;
430 psc = psc - 1;
431
432 /* If configured for High Speed */
433 if (dev->speed > 400) {
434 unsigned long scl;
435
436 /* For first phase of HS mode */
437 scl = internal_clk / 400;
438 fsscll = scl - (scl / 3) - 7;
439 fssclh = (scl / 3) - 5;
440
441 /* For second phase of HS mode */
442 scl = fclk_rate / dev->speed;
443 hsscll = scl - (scl / 3) - 7;
444 hssclh = (scl / 3) - 5;
445 } else if (dev->speed > 100) {
446 unsigned long scl;
447
448 /* Fast mode */
449 scl = internal_clk / dev->speed;
450 fsscll = scl - (scl / 3) - 7;
451 fssclh = (scl / 3) - 5;
452 } else {
453 /* Standard mode */
454 fsscll = internal_clk / (dev->speed * 2) - 7;
455 fssclh = internal_clk / (dev->speed * 2) - 5;
456 }
457 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
458 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
459 } else {
460 /* Program desired operating rate */
461 fclk_rate /= (psc + 1) * 1000;
462 if (psc > 2)
463 psc = 2;
464 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
465 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
466 }
467
468 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
469 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
470
471 /* SCL low and high time values */
472 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
473 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
474
475 if (dev->fifo_size) {
476 /* Note: setup required fifo size - 1. RTRSH and XTRSH */
477 buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR |
478 (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR;
479 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
480 }
481
482 /* Take the I2C module out of reset: */
483 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
484
485 dev->errata = 0;
486
487 if (cpu_is_omap2430() || cpu_is_omap34xx())
488 dev->errata |= I2C_OMAP_ERRATA_I207;
489
490 /* Enable interrupts */
491 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
492 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
493 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
494 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
495 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
496 if (cpu_is_omap34xx()) {
497 dev->pscstate = psc;
498 dev->scllstate = scll;
499 dev->sclhstate = sclh;
500 dev->bufstate = buf;
501 }
502 return 0;
503}
504
505/*
506 * Waiting on Bus Busy
507 */
508static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
509{
510 unsigned long timeout;
511
512 timeout = jiffies + OMAP_I2C_TIMEOUT;
513 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
514 if (time_after(jiffies, timeout)) {
515 dev_warn(dev->dev, "timeout waiting for bus ready\n");
516 return -ETIMEDOUT;
517 }
518 msleep(1);
519 }
520
521 return 0;
522}
523
524/*
525 * Low level master read/write transaction.
526 */
527static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
528 struct i2c_msg *msg, int stop)
529{
530 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
531 int r;
532 u16 w;
533
534 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
535 msg->addr, msg->len, msg->flags, stop);
536
537 if (msg->len == 0)
538 return -EINVAL;
539
540 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
541
542 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
543 dev->buf = msg->buf;
544 dev->buf_len = msg->len;
545
546 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
547
548 /* Clear the FIFO Buffers */
549 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
550 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
551 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
552
553 init_completion(&dev->cmd_complete);
554 dev->cmd_err = 0;
555
556 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
557
558 /* High speed configuration */
559 if (dev->speed > 400)
560 w |= OMAP_I2C_CON_OPMODE_HS;
561
562 if (msg->flags & I2C_M_TEN)
563 w |= OMAP_I2C_CON_XA;
564 if (!(msg->flags & I2C_M_RD))
565 w |= OMAP_I2C_CON_TRX;
566
567 if (!dev->b_hw && stop)
568 w |= OMAP_I2C_CON_STP;
569
570 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
571
572 /*
573 * Don't write stt and stp together on some hardware.
574 */
575 if (dev->b_hw && stop) {
576 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
577 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
578 while (con & OMAP_I2C_CON_STT) {
579 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
580
581 /* Let the user know if i2c is in a bad state */
582 if (time_after(jiffies, delay)) {
583 dev_err(dev->dev, "controller timed out "
584 "waiting for start condition to finish\n");
585 return -ETIMEDOUT;
586 }
587 cpu_relax();
588 }
589
590 w |= OMAP_I2C_CON_STP;
591 w &= ~OMAP_I2C_CON_STT;
592 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
593 }
594
595 /*
596 * REVISIT: We should abort the transfer on signals, but the bus goes
597 * into arbitration and we're currently unable to recover from it.
598 */
599 r = wait_for_completion_timeout(&dev->cmd_complete,
600 OMAP_I2C_TIMEOUT);
601 dev->buf_len = 0;
602 if (r < 0)
603 return r;
604 if (r == 0) {
605 dev_err(dev->dev, "controller timed out\n");
606 omap_i2c_init(dev);
607 return -ETIMEDOUT;
608 }
609
610 if (likely(!dev->cmd_err))
611 return 0;
612
613 /* We have an error */
614 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
615 OMAP_I2C_STAT_XUDF)) {
616 omap_i2c_init(dev);
617 return -EIO;
618 }
619
620 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
621 if (msg->flags & I2C_M_IGNORE_NAK)
622 return 0;
623 if (stop) {
624 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
625 w |= OMAP_I2C_CON_STP;
626 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
627 }
628 return -EREMOTEIO;
629 }
630 return -EIO;
631}
632
633
634/*
635 * Prepare controller for a transaction and call omap_i2c_xfer_msg
636 * to do the work during IRQ processing.
637 */
638static int
639omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
640{
641 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
642 int i;
643 int r;
644
645 omap_i2c_unidle(dev);
646
647 r = omap_i2c_wait_for_bb(dev);
648 if (r < 0)
649 goto out;
650
651 if (dev->set_mpu_wkup_lat != NULL)
652 dev->set_mpu_wkup_lat(dev->dev, dev->latency);
653
654 for (i = 0; i < num; i++) {
655 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
656 if (r != 0)
657 break;
658 }
659
660 if (dev->set_mpu_wkup_lat != NULL)
661 dev->set_mpu_wkup_lat(dev->dev, -1);
662
663 if (r == 0)
664 r = num;
665
666 omap_i2c_wait_for_bb(dev);
667out:
668 omap_i2c_idle(dev);
669 return r;
670}
671
672static u32
673omap_i2c_func(struct i2c_adapter *adap)
674{
675 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
676}
677
678static inline void
679omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
680{
681 dev->cmd_err |= err;
682 complete(&dev->cmd_complete);
683}
684
685static inline void
686omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
687{
688 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
689}
690
691static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
692{
693 /*
694 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
695 * Not applicable for OMAP4.
696 * Under certain rare conditions, RDR could be set again
697 * when the bus is busy, then ignore the interrupt and
698 * clear the interrupt.
699 */
700 if (stat & OMAP_I2C_STAT_RDR) {
701 /* Step 1: If RDR is set, clear it */
702 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
703
704 /* Step 2: */
705 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
706 & OMAP_I2C_STAT_BB)) {
707
708 /* Step 3: */
709 if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
710 & OMAP_I2C_STAT_RDR) {
711 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
712 dev_dbg(dev->dev, "RDR when bus is busy.\n");
713 }
714
715 }
716 }
717}
718
719/* rev1 devices are apparently only on some 15xx */
720#ifdef CONFIG_ARCH_OMAP15XX
721
722static irqreturn_t
723omap_i2c_rev1_isr(int this_irq, void *dev_id)
724{
725 struct omap_i2c_dev *dev = dev_id;
726 u16 iv, w;
727
728 if (dev->idle)
729 return IRQ_NONE;
730
731 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
732 switch (iv) {
733 case 0x00: /* None */
734 break;
735 case 0x01: /* Arbitration lost */
736 dev_err(dev->dev, "Arbitration lost\n");
737 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
738 break;
739 case 0x02: /* No acknowledgement */
740 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
741 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
742 break;
743 case 0x03: /* Register access ready */
744 omap_i2c_complete_cmd(dev, 0);
745 break;
746 case 0x04: /* Receive data ready */
747 if (dev->buf_len) {
748 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
749 *dev->buf++ = w;
750 dev->buf_len--;
751 if (dev->buf_len) {
752 *dev->buf++ = w >> 8;
753 dev->buf_len--;
754 }
755 } else
756 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
757 break;
758 case 0x05: /* Transmit data ready */
759 if (dev->buf_len) {
760 w = *dev->buf++;
761 dev->buf_len--;
762 if (dev->buf_len) {
763 w |= *dev->buf++ << 8;
764 dev->buf_len--;
765 }
766 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
767 } else
768 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
769 break;
770 default:
771 return IRQ_NONE;
772 }
773
774 return IRQ_HANDLED;
775}
776#else
777#define omap_i2c_rev1_isr NULL
778#endif
779
780/*
781 * OMAP3430 Errata 1.153: When an XRDY/XDR is hit, wait for XUDF before writing
782 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
783 * them from the memory to the I2C interface.
784 */
785static int errata_omap3_1p153(struct omap_i2c_dev *dev, u16 *stat, int *err)
786{
787 unsigned long timeout = 10000;
788
789 while (--timeout && !(*stat & OMAP_I2C_STAT_XUDF)) {
790 if (*stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
791 omap_i2c_ack_stat(dev, *stat & (OMAP_I2C_STAT_XRDY |
792 OMAP_I2C_STAT_XDR));
793 *err |= OMAP_I2C_STAT_XUDF;
794 return -ETIMEDOUT;
795 }
796
797 cpu_relax();
798 *stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
799 }
800
801 if (!timeout) {
802 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
803 return 0;
804 }
805
806 return 0;
807}
808
809static irqreturn_t
810omap_i2c_isr(int this_irq, void *dev_id)
811{
812 struct omap_i2c_dev *dev = dev_id;
813 u16 bits;
814 u16 stat, w;
815 int err, count = 0;
816
817 if (dev->idle)
818 return IRQ_NONE;
819
820 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
821 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
822 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
823 if (count++ == 100) {
824 dev_warn(dev->dev, "Too much work in one IRQ\n");
825 break;
826 }
827
828 err = 0;
829complete:
830 /*
831 * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be
832 * acked after the data operation is complete.
833 * Ref: TRM SWPU114Q Figure 18-31
834 */
835 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat &
836 ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
837 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
838
839 if (stat & OMAP_I2C_STAT_NACK) {
840 err |= OMAP_I2C_STAT_NACK;
841 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
842 OMAP_I2C_CON_STP);
843 }
844 if (stat & OMAP_I2C_STAT_AL) {
845 dev_err(dev->dev, "Arbitration lost\n");
846 err |= OMAP_I2C_STAT_AL;
847 }
848 /*
849 * ProDB0017052: Clear ARDY bit twice
850 */
851 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
852 OMAP_I2C_STAT_AL)) {
853 omap_i2c_ack_stat(dev, stat &
854 (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
855 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR |
856 OMAP_I2C_STAT_ARDY));
857 omap_i2c_complete_cmd(dev, err);
858 return IRQ_HANDLED;
859 }
860 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
861 u8 num_bytes = 1;
862
863 if (dev->errata & I2C_OMAP_ERRATA_I207)
864 i2c_omap_errata_i207(dev, stat);
865
866 if (dev->fifo_size) {
867 if (stat & OMAP_I2C_STAT_RRDY)
868 num_bytes = dev->fifo_size;
869 else /* read RXSTAT on RDR interrupt */
870 num_bytes = (omap_i2c_read_reg(dev,
871 OMAP_I2C_BUFSTAT_REG)
872 >> 8) & 0x3F;
873 }
874 while (num_bytes) {
875 num_bytes--;
876 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
877 if (dev->buf_len) {
878 *dev->buf++ = w;
879 dev->buf_len--;
880 /*
881 * Data reg in 2430, omap3 and
882 * omap4 is 8 bit wide
883 */
884 if (cpu_class_is_omap1() ||
885 cpu_is_omap2420()) {
886 if (dev->buf_len) {
887 *dev->buf++ = w >> 8;
888 dev->buf_len--;
889 }
890 }
891 } else {
892 if (stat & OMAP_I2C_STAT_RRDY)
893 dev_err(dev->dev,
894 "RRDY IRQ while no data"
895 " requested\n");
896 if (stat & OMAP_I2C_STAT_RDR)
897 dev_err(dev->dev,
898 "RDR IRQ while no data"
899 " requested\n");
900 break;
901 }
902 }
903 omap_i2c_ack_stat(dev,
904 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
905 continue;
906 }
907 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
908 u8 num_bytes = 1;
909 if (dev->fifo_size) {
910 if (stat & OMAP_I2C_STAT_XRDY)
911 num_bytes = dev->fifo_size;
912 else /* read TXSTAT on XDR interrupt */
913 num_bytes = omap_i2c_read_reg(dev,
914 OMAP_I2C_BUFSTAT_REG)
915 & 0x3F;
916 }
917 while (num_bytes) {
918 num_bytes--;
919 w = 0;
920 if (dev->buf_len) {
921 w = *dev->buf++;
922 dev->buf_len--;
923 /*
924 * Data reg in 2430, omap3 and
925 * omap4 is 8 bit wide
926 */
927 if (cpu_class_is_omap1() ||
928 cpu_is_omap2420()) {
929 if (dev->buf_len) {
930 w |= *dev->buf++ << 8;
931 dev->buf_len--;
932 }
933 }
934 } else {
935 if (stat & OMAP_I2C_STAT_XRDY)
936 dev_err(dev->dev,
937 "XRDY IRQ while no "
938 "data to send\n");
939 if (stat & OMAP_I2C_STAT_XDR)
940 dev_err(dev->dev,
941 "XDR IRQ while no "
942 "data to send\n");
943 break;
944 }
945
946 if ((dev->errata & I2C_OMAP3_1P153) &&
947 errata_omap3_1p153(dev, &stat, &err))
948 goto complete;
949
950 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
951 }
952 omap_i2c_ack_stat(dev,
953 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
954 continue;
955 }
956 if (stat & OMAP_I2C_STAT_ROVR) {
957 dev_err(dev->dev, "Receive overrun\n");
958 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
959 }
960 if (stat & OMAP_I2C_STAT_XUDF) {
961 dev_err(dev->dev, "Transmit underflow\n");
962 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
963 }
964 }
965
966 return count ? IRQ_HANDLED : IRQ_NONE;
967}
968
969static const struct i2c_algorithm omap_i2c_algo = {
970 .master_xfer = omap_i2c_xfer,
971 .functionality = omap_i2c_func,
972};
973
974static int __devinit
975omap_i2c_probe(struct platform_device *pdev)
976{
977 struct omap_i2c_dev *dev;
978 struct i2c_adapter *adap;
979 struct resource *mem, *irq, *ioarea;
980 struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data;
981 irq_handler_t isr;
982 int r;
983 u32 speed = 0;
984
985 /* NOTE: driver uses the static register mapping */
986 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
987 if (!mem) {
988 dev_err(&pdev->dev, "no mem resource?\n");
989 return -ENODEV;
990 }
991 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
992 if (!irq) {
993 dev_err(&pdev->dev, "no irq resource?\n");
994 return -ENODEV;
995 }
996
997 ioarea = request_mem_region(mem->start, resource_size(mem),
998 pdev->name);
999 if (!ioarea) {
1000 dev_err(&pdev->dev, "I2C region already claimed\n");
1001 return -EBUSY;
1002 }
1003
1004 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
1005 if (!dev) {
1006 r = -ENOMEM;
1007 goto err_release_region;
1008 }
1009
1010 if (pdata != NULL) {
1011 speed = pdata->clkrate;
1012 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1013 } else {
1014 speed = 100; /* Default speed */
1015 dev->set_mpu_wkup_lat = NULL;
1016 }
1017
1018 dev->speed = speed;
1019 dev->idle = 1;
1020 dev->dev = &pdev->dev;
1021 dev->irq = irq->start;
1022 dev->base = ioremap(mem->start, resource_size(mem));
1023 if (!dev->base) {
1024 r = -ENOMEM;
1025 goto err_free_mem;
1026 }
1027
1028 platform_set_drvdata(pdev, dev);
1029
1030 if (cpu_is_omap7xx())
1031 dev->reg_shift = 1;
1032 else if (cpu_is_omap44xx())
1033 dev->reg_shift = 0;
1034 else
1035 dev->reg_shift = 2;
1036
1037 if (cpu_is_omap44xx())
1038 dev->regs = (u8 *) omap4_reg_map;
1039 else
1040 dev->regs = (u8 *) reg_map;
1041
1042 pm_runtime_enable(&pdev->dev);
1043 omap_i2c_unidle(dev);
1044
1045 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
1046
1047 if (dev->rev <= OMAP_I2C_REV_ON_3430)
1048 dev->errata |= I2C_OMAP3_1P153;
1049
1050 if (!(cpu_class_is_omap1() || cpu_is_omap2420())) {
1051 u16 s;
1052
1053 /* Set up the fifo size - Get total size */
1054 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1055 dev->fifo_size = 0x8 << s;
1056
1057 /*
1058 * Set up notification threshold as half the total available
1059 * size. This is to ensure that we can handle the status on int
1060 * call back latencies.
1061 */
1062 if (dev->rev >= OMAP_I2C_REV_ON_4430) {
1063 dev->fifo_size = 0;
1064 dev->b_hw = 0; /* Disable hardware fixes */
1065 } else {
1066 dev->fifo_size = (dev->fifo_size / 2);
1067 dev->b_hw = 1; /* Enable hardware fixes */
1068 }
1069 /* calculate wakeup latency constraint for MPU */
1070 if (dev->set_mpu_wkup_lat != NULL)
1071 dev->latency = (1000000 * dev->fifo_size) /
1072 (1000 * speed / 8);
1073 }
1074
1075 /* reset ASAP, clearing any IRQs */
1076 omap_i2c_init(dev);
1077
1078 isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr;
1079 r = request_irq(dev->irq, isr, 0, pdev->name, dev);
1080
1081 if (r) {
1082 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1083 goto err_unuse_clocks;
1084 }
1085
1086 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
1087 pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);
1088
1089 omap_i2c_idle(dev);
1090
1091 adap = &dev->adapter;
1092 i2c_set_adapdata(adap, dev);
1093 adap->owner = THIS_MODULE;
1094 adap->class = I2C_CLASS_HWMON;
1095 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
1096 adap->algo = &omap_i2c_algo;
1097 adap->dev.parent = &pdev->dev;
1098
1099 /* i2c device drivers may be active on return from add_adapter() */
1100 adap->nr = pdev->id;
1101 r = i2c_add_numbered_adapter(adap);
1102 if (r) {
1103 dev_err(dev->dev, "failure adding adapter\n");
1104 goto err_free_irq;
1105 }
1106
1107 return 0;
1108
1109err_free_irq:
1110 free_irq(dev->irq, dev);
1111err_unuse_clocks:
1112 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1113 omap_i2c_idle(dev);
1114 iounmap(dev->base);
1115err_free_mem:
1116 platform_set_drvdata(pdev, NULL);
1117 kfree(dev);
1118err_release_region:
1119 release_mem_region(mem->start, resource_size(mem));
1120
1121 return r;
1122}
1123
1124static int
1125omap_i2c_remove(struct platform_device *pdev)
1126{
1127 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
1128 struct resource *mem;
1129
1130 platform_set_drvdata(pdev, NULL);
1131
1132 free_irq(dev->irq, dev);
1133 i2c_del_adapter(&dev->adapter);
1134 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1135 iounmap(dev->base);
1136 kfree(dev);
1137 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1138 release_mem_region(mem->start, resource_size(mem));
1139 return 0;
1140}
1141
1142static struct platform_driver omap_i2c_driver = {
1143 .probe = omap_i2c_probe,
1144 .remove = omap_i2c_remove,
1145 .driver = {
1146 .name = "omap_i2c",
1147 .owner = THIS_MODULE,
1148 },
1149};
1150
1151/* I2C may be needed to bring up other drivers */
1152static int __init
1153omap_i2c_init_driver(void)
1154{
1155 return platform_driver_register(&omap_i2c_driver);
1156}
1157subsys_initcall(omap_i2c_init_driver);
1158
1159static void __exit omap_i2c_exit_driver(void)
1160{
1161 platform_driver_unregister(&omap_i2c_driver);
1162}
1163module_exit(omap_i2c_exit_driver);
1164
1165MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1166MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1167MODULE_LICENSE("GPL");
1168MODULE_ALIAS("platform:omap_i2c");