1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * R-Car Gen3 Clock Pulse Generator
 4 *
 5 * Copyright (C) 2015-2018 Glider bvba
 6 * Copyright (C) 2018 Renesas Electronics Corp.
 7 *
 8 */
 9
10#ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
11#define __CLK_RENESAS_RCAR_GEN3_CPG_H__
12
13enum rcar_gen3_clk_types {
14	CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
15	CLK_TYPE_GEN3_PLL0,
16	CLK_TYPE_GEN3_PLL1,
17	CLK_TYPE_GEN3_PLL2,
18	CLK_TYPE_GEN3_PLL3,
19	CLK_TYPE_GEN3_PLL4,
20	CLK_TYPE_GEN3_SDH,
21	CLK_TYPE_GEN3_SD,
22	CLK_TYPE_GEN3_R,
23	CLK_TYPE_GEN3_MDSEL,	/* Select parent/divider using mode pin */
24	CLK_TYPE_GEN3_Z,
25	CLK_TYPE_GEN3_OSC,	/* OSC EXTAL predivider and fixed divider */
26	CLK_TYPE_GEN3_RCKSEL,	/* Select parent/divider using RCKCR.CKSEL */
27	CLK_TYPE_GEN3_RPCSRC,
28	CLK_TYPE_GEN3_E3_RPCSRC,/* Select parent/divider using RPCCKCR.DIV */
29	CLK_TYPE_GEN3_RPC,
30	CLK_TYPE_GEN3_RPCD2,
31
32	/* SoC specific definitions start here */
33	CLK_TYPE_GEN3_SOC_BASE,
34};
35
36#define DEF_GEN3_SDH(_name, _id, _parent, _offset)	\
37	DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset)
38
39#define DEF_GEN3_SD(_name, _id, _parent, _offset)	\
40	DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
41
42#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
43	DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL,	\
44		 (_parent0) << 16 | (_parent1),		\
45		 .div = (_div0) << 16 | (_div1), .offset = _md)
46
47#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
48		    _div_clean) \
49	DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg,	\
50		       _parent_clean, _div_clean)
51
52#define DEF_GEN3_OSC(_name, _id, _parent, _div)		\
53	DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
54
55#define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \
56	DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL,	\
57		 (_parent0) << 16 | (_parent1),	.div = (_div0) << 16 | (_div1))
58
59#define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset)	\
60	DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
61
62#define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1)	\
63	DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC,	\
64		 (_parent0) << 16 | (_parent1), .div = 8)
65#define DEF_FIXED_RPCSRC_D3(_name, _id, _parent0, _parent1)	\
66	DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC,	\
67		 (_parent0) << 16 | (_parent1), .div = 5)
68
69struct rcar_gen3_cpg_pll_config {
70	u8 extal_div;
71	u8 pll1_mult;
72	u8 pll1_div;
73	u8 pll3_mult;
74	u8 pll3_div;
75	u8 osc_prediv;
76};
77
78#define CPG_RPCCKCR	0x238
79#define CPG_RCKCR	0x240
80
81struct clk *rcar_gen3_cpg_clk_register(struct device *dev,
82	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
83	struct clk **clks, void __iomem *base,
84	struct raw_notifier_head *notifiers);
85int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
86		       unsigned int clk_extalr, u32 mode);
87
88#endif