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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2012 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <joerg.roedel@amd.com>
5 *
6 * This header file contains the interface of the interrupt remapping code to
7 * the x86 interrupt management code.
8 */
9
10#ifndef __X86_IRQ_REMAPPING_H
11#define __X86_IRQ_REMAPPING_H
12
13#include <asm/irqdomain.h>
14#include <asm/hw_irq.h>
15#include <asm/io_apic.h>
16
17struct msi_msg;
18struct irq_alloc_info;
19
20enum irq_remap_cap {
21 IRQ_POSTING_CAP = 0,
22};
23
24enum {
25 IRQ_REMAP_XAPIC_MODE,
26 IRQ_REMAP_X2APIC_MODE,
27};
28
29struct vcpu_data {
30 u64 pi_desc_addr; /* Physical address of PI Descriptor */
31 u32 vector; /* Guest vector of the interrupt */
32};
33
34#ifdef CONFIG_IRQ_REMAP
35
36extern raw_spinlock_t irq_2_ir_lock;
37
38extern bool irq_remapping_cap(enum irq_remap_cap cap);
39extern void set_irq_remapping_broken(void);
40extern int irq_remapping_prepare(void);
41extern int irq_remapping_enable(void);
42extern void irq_remapping_disable(void);
43extern int irq_remapping_reenable(int);
44extern int irq_remap_enable_fault_handling(void);
45extern void panic_if_irq_remap(const char *msg);
46
47/* Get parent irqdomain for interrupt remapping irqdomain */
48static inline struct irq_domain *arch_get_ir_parent_domain(void)
49{
50 return x86_vector_domain;
51}
52
53#else /* CONFIG_IRQ_REMAP */
54
55static inline bool irq_remapping_cap(enum irq_remap_cap cap) { return 0; }
56static inline void set_irq_remapping_broken(void) { }
57static inline int irq_remapping_prepare(void) { return -ENODEV; }
58static inline int irq_remapping_enable(void) { return -ENODEV; }
59static inline void irq_remapping_disable(void) { }
60static inline int irq_remapping_reenable(int eim) { return -ENODEV; }
61static inline int irq_remap_enable_fault_handling(void) { return -ENODEV; }
62
63static inline void panic_if_irq_remap(const char *msg)
64{
65}
66
67#endif /* CONFIG_IRQ_REMAP */
68#endif /* __X86_IRQ_REMAPPING_H */
1#ifndef _ASM_X86_IRQ_REMAPPING_H
2#define _ASM_X86_IRQ_REMAPPING_H
3
4#define IRTE_DEST(dest) ((x2apic_mode) ? dest : dest << 8)
5
6#ifdef CONFIG_INTR_REMAP
7static inline void prepare_irte(struct irte *irte, int vector,
8 unsigned int dest)
9{
10 memset(irte, 0, sizeof(*irte));
11
12 irte->present = 1;
13 irte->dst_mode = apic->irq_dest_mode;
14 /*
15 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
16 * actual level or edge trigger will be setup in the IO-APIC
17 * RTE. This will help simplify level triggered irq migration.
18 * For more details, see the comments (in io_apic.c) explainig IO-APIC
19 * irq migration in the presence of interrupt-remapping.
20 */
21 irte->trigger_mode = 0;
22 irte->dlvry_mode = apic->irq_delivery_mode;
23 irte->vector = vector;
24 irte->dest_id = IRTE_DEST(dest);
25 irte->redir_hint = 1;
26}
27static inline bool irq_remapped(struct irq_cfg *cfg)
28{
29 return cfg->irq_2_iommu.iommu != NULL;
30}
31#else
32static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
33{
34}
35static inline bool irq_remapped(struct irq_cfg *cfg)
36{
37 return false;
38}
39#endif
40
41#endif /* _ASM_X86_IRQ_REMAPPING_H */