Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/mach-omap2/io.c
4 *
5 * OMAP2 I/O mapping code
6 *
7 * Copyright (C) 2005 Nokia Corporation
8 * Copyright (C) 2007-2009 Texas Instruments
9 *
10 * Author:
11 * Juha Yrjola <juha.yrjola@nokia.com>
12 * Syed Khasim <x0khasim@ti.com>
13 *
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 */
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/io.h>
20#include <linux/clk.h>
21
22#include <asm/tlb.h>
23#include <asm/mach/map.h>
24
25#include <linux/omap-dma.h>
26
27#include "omap_hwmod.h"
28#include "soc.h"
29#include "iomap.h"
30#include "voltage.h"
31#include "powerdomain.h"
32#include "clockdomain.h"
33#include "common.h"
34#include "clock.h"
35#include "clock2xxx.h"
36#include "clock3xxx.h"
37#include "sdrc.h"
38#include "control.h"
39#include "serial.h"
40#include "sram.h"
41#include "cm2xxx.h"
42#include "cm3xxx.h"
43#include "cm33xx.h"
44#include "cm44xx.h"
45#include "prm.h"
46#include "cm.h"
47#include "prcm_mpu44xx.h"
48#include "prminst44xx.h"
49#include "prm2xxx.h"
50#include "prm3xxx.h"
51#include "prm33xx.h"
52#include "prm44xx.h"
53#include "opp2xxx.h"
54#include "omap-secure.h"
55
56/*
57 * omap_clk_soc_init: points to a function that does the SoC-specific
58 * clock initializations
59 */
60static int (*omap_clk_soc_init)(void);
61
62/*
63 * The machine specific code may provide the extra mapping besides the
64 * default mapping provided here.
65 */
66
67#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
68static struct map_desc omap24xx_io_desc[] __initdata = {
69 {
70 .virtual = L3_24XX_VIRT,
71 .pfn = __phys_to_pfn(L3_24XX_PHYS),
72 .length = L3_24XX_SIZE,
73 .type = MT_DEVICE
74 },
75 {
76 .virtual = L4_24XX_VIRT,
77 .pfn = __phys_to_pfn(L4_24XX_PHYS),
78 .length = L4_24XX_SIZE,
79 .type = MT_DEVICE
80 },
81};
82
83#ifdef CONFIG_SOC_OMAP2420
84static struct map_desc omap242x_io_desc[] __initdata = {
85 {
86 .virtual = DSP_MEM_2420_VIRT,
87 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
88 .length = DSP_MEM_2420_SIZE,
89 .type = MT_DEVICE
90 },
91 {
92 .virtual = DSP_IPI_2420_VIRT,
93 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
94 .length = DSP_IPI_2420_SIZE,
95 .type = MT_DEVICE
96 },
97 {
98 .virtual = DSP_MMU_2420_VIRT,
99 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
100 .length = DSP_MMU_2420_SIZE,
101 .type = MT_DEVICE
102 },
103};
104
105#endif
106
107#ifdef CONFIG_SOC_OMAP2430
108static struct map_desc omap243x_io_desc[] __initdata = {
109 {
110 .virtual = L4_WK_243X_VIRT,
111 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
112 .length = L4_WK_243X_SIZE,
113 .type = MT_DEVICE
114 },
115 {
116 .virtual = OMAP243X_GPMC_VIRT,
117 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
118 .length = OMAP243X_GPMC_SIZE,
119 .type = MT_DEVICE
120 },
121 {
122 .virtual = OMAP243X_SDRC_VIRT,
123 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
124 .length = OMAP243X_SDRC_SIZE,
125 .type = MT_DEVICE
126 },
127 {
128 .virtual = OMAP243X_SMS_VIRT,
129 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
130 .length = OMAP243X_SMS_SIZE,
131 .type = MT_DEVICE
132 },
133};
134#endif
135#endif
136
137#ifdef CONFIG_ARCH_OMAP3
138static struct map_desc omap34xx_io_desc[] __initdata = {
139 {
140 .virtual = L3_34XX_VIRT,
141 .pfn = __phys_to_pfn(L3_34XX_PHYS),
142 .length = L3_34XX_SIZE,
143 .type = MT_DEVICE
144 },
145 {
146 .virtual = L4_34XX_VIRT,
147 .pfn = __phys_to_pfn(L4_34XX_PHYS),
148 .length = L4_34XX_SIZE,
149 .type = MT_DEVICE
150 },
151 {
152 .virtual = OMAP34XX_GPMC_VIRT,
153 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
154 .length = OMAP34XX_GPMC_SIZE,
155 .type = MT_DEVICE
156 },
157 {
158 .virtual = OMAP343X_SMS_VIRT,
159 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
160 .length = OMAP343X_SMS_SIZE,
161 .type = MT_DEVICE
162 },
163 {
164 .virtual = OMAP343X_SDRC_VIRT,
165 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
166 .length = OMAP343X_SDRC_SIZE,
167 .type = MT_DEVICE
168 },
169 {
170 .virtual = L4_PER_34XX_VIRT,
171 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
172 .length = L4_PER_34XX_SIZE,
173 .type = MT_DEVICE
174 },
175 {
176 .virtual = L4_EMU_34XX_VIRT,
177 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
178 .length = L4_EMU_34XX_SIZE,
179 .type = MT_DEVICE
180 },
181};
182#endif
183
184#ifdef CONFIG_SOC_TI81XX
185static struct map_desc omapti81xx_io_desc[] __initdata = {
186 {
187 .virtual = L4_34XX_VIRT,
188 .pfn = __phys_to_pfn(L4_34XX_PHYS),
189 .length = L4_34XX_SIZE,
190 .type = MT_DEVICE
191 }
192};
193#endif
194
195#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
196static struct map_desc omapam33xx_io_desc[] __initdata = {
197 {
198 .virtual = L4_34XX_VIRT,
199 .pfn = __phys_to_pfn(L4_34XX_PHYS),
200 .length = L4_34XX_SIZE,
201 .type = MT_DEVICE
202 },
203 {
204 .virtual = L4_WK_AM33XX_VIRT,
205 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
206 .length = L4_WK_AM33XX_SIZE,
207 .type = MT_DEVICE
208 }
209};
210#endif
211
212#ifdef CONFIG_ARCH_OMAP4
213static struct map_desc omap44xx_io_desc[] __initdata = {
214 {
215 .virtual = L3_44XX_VIRT,
216 .pfn = __phys_to_pfn(L3_44XX_PHYS),
217 .length = L3_44XX_SIZE,
218 .type = MT_DEVICE,
219 },
220 {
221 .virtual = L4_44XX_VIRT,
222 .pfn = __phys_to_pfn(L4_44XX_PHYS),
223 .length = L4_44XX_SIZE,
224 .type = MT_DEVICE,
225 },
226 {
227 .virtual = L4_PER_44XX_VIRT,
228 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
229 .length = L4_PER_44XX_SIZE,
230 .type = MT_DEVICE,
231 },
232};
233#endif
234
235#ifdef CONFIG_SOC_OMAP5
236static struct map_desc omap54xx_io_desc[] __initdata = {
237 {
238 .virtual = L3_54XX_VIRT,
239 .pfn = __phys_to_pfn(L3_54XX_PHYS),
240 .length = L3_54XX_SIZE,
241 .type = MT_DEVICE,
242 },
243 {
244 .virtual = L4_54XX_VIRT,
245 .pfn = __phys_to_pfn(L4_54XX_PHYS),
246 .length = L4_54XX_SIZE,
247 .type = MT_DEVICE,
248 },
249 {
250 .virtual = L4_WK_54XX_VIRT,
251 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
252 .length = L4_WK_54XX_SIZE,
253 .type = MT_DEVICE,
254 },
255 {
256 .virtual = L4_PER_54XX_VIRT,
257 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
258 .length = L4_PER_54XX_SIZE,
259 .type = MT_DEVICE,
260 },
261};
262#endif
263
264#ifdef CONFIG_SOC_DRA7XX
265static struct map_desc dra7xx_io_desc[] __initdata = {
266 {
267 .virtual = L4_CFG_MPU_DRA7XX_VIRT,
268 .pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS),
269 .length = L4_CFG_MPU_DRA7XX_SIZE,
270 .type = MT_DEVICE,
271 },
272 {
273 .virtual = L3_MAIN_SN_DRA7XX_VIRT,
274 .pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS),
275 .length = L3_MAIN_SN_DRA7XX_SIZE,
276 .type = MT_DEVICE,
277 },
278 {
279 .virtual = L4_PER1_DRA7XX_VIRT,
280 .pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS),
281 .length = L4_PER1_DRA7XX_SIZE,
282 .type = MT_DEVICE,
283 },
284 {
285 .virtual = L4_PER2_DRA7XX_VIRT,
286 .pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS),
287 .length = L4_PER2_DRA7XX_SIZE,
288 .type = MT_DEVICE,
289 },
290 {
291 .virtual = L4_PER3_DRA7XX_VIRT,
292 .pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS),
293 .length = L4_PER3_DRA7XX_SIZE,
294 .type = MT_DEVICE,
295 },
296 {
297 .virtual = L4_CFG_DRA7XX_VIRT,
298 .pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS),
299 .length = L4_CFG_DRA7XX_SIZE,
300 .type = MT_DEVICE,
301 },
302 {
303 .virtual = L4_WKUP_DRA7XX_VIRT,
304 .pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS),
305 .length = L4_WKUP_DRA7XX_SIZE,
306 .type = MT_DEVICE,
307 },
308};
309#endif
310
311#ifdef CONFIG_SOC_OMAP2420
312void __init omap242x_map_io(void)
313{
314 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
315 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
316}
317#endif
318
319#ifdef CONFIG_SOC_OMAP2430
320void __init omap243x_map_io(void)
321{
322 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
323 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
324}
325#endif
326
327#ifdef CONFIG_ARCH_OMAP3
328void __init omap3_map_io(void)
329{
330 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
331}
332#endif
333
334#ifdef CONFIG_SOC_TI81XX
335void __init ti81xx_map_io(void)
336{
337 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
338}
339#endif
340
341#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
342void __init am33xx_map_io(void)
343{
344 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
345}
346#endif
347
348#ifdef CONFIG_ARCH_OMAP4
349void __init omap4_map_io(void)
350{
351 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
352 omap_barriers_init();
353}
354#endif
355
356#ifdef CONFIG_SOC_OMAP5
357void __init omap5_map_io(void)
358{
359 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
360 omap_barriers_init();
361}
362#endif
363
364#ifdef CONFIG_SOC_DRA7XX
365void __init dra7xx_map_io(void)
366{
367 iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
368 omap_barriers_init();
369}
370#endif
371/*
372 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
373 *
374 * Sets the CORE DPLL3 M2 divider to the same value that it's at
375 * currently. This has the effect of setting the SDRC SDRAM AC timing
376 * registers to the values currently defined by the kernel. Currently
377 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
378 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
379 * or passes along the return value of clk_set_rate().
380 */
381static int __init _omap2_init_reprogram_sdrc(void)
382{
383 struct clk *dpll3_m2_ck;
384 int v = -EINVAL;
385 long rate;
386
387 if (!cpu_is_omap34xx())
388 return 0;
389
390 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
391 if (IS_ERR(dpll3_m2_ck))
392 return -EINVAL;
393
394 rate = clk_get_rate(dpll3_m2_ck);
395 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
396 v = clk_set_rate(dpll3_m2_ck, rate);
397 if (v)
398 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
399
400 clk_put(dpll3_m2_ck);
401
402 return v;
403}
404
405#ifdef CONFIG_OMAP_HWMOD
406static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
407{
408 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
409}
410
411static void __init __maybe_unused omap_hwmod_init_postsetup(void)
412{
413 u8 postsetup_state = _HWMOD_STATE_DEFAULT;
414
415 /* Set the default postsetup state for all hwmods */
416 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
417}
418#else
419static inline void omap_hwmod_init_postsetup(void)
420{
421}
422#endif
423
424#ifdef CONFIG_SOC_OMAP2420
425void __init omap2420_init_early(void)
426{
427 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
428 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
429 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
430 omap2_control_base_init();
431 omap2xxx_check_revision();
432 omap2_prcm_base_init();
433 omap2xxx_voltagedomains_init();
434 omap242x_powerdomains_init();
435 omap242x_clockdomains_init();
436 omap2420_hwmod_init();
437 omap_hwmod_init_postsetup();
438 omap_clk_soc_init = omap2420_dt_clk_init;
439 rate_table = omap2420_rate_table;
440}
441
442void __init omap2420_init_late(void)
443{
444 omap_pm_soc_init = omap2_pm_init;
445}
446#endif
447
448#ifdef CONFIG_SOC_OMAP2430
449void __init omap2430_init_early(void)
450{
451 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
452 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
453 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
454 omap2_control_base_init();
455 omap2xxx_check_revision();
456 omap2_prcm_base_init();
457 omap2xxx_voltagedomains_init();
458 omap243x_powerdomains_init();
459 omap243x_clockdomains_init();
460 omap2430_hwmod_init();
461 omap_hwmod_init_postsetup();
462 omap_clk_soc_init = omap2430_dt_clk_init;
463 rate_table = omap2430_rate_table;
464}
465
466void __init omap2430_init_late(void)
467{
468 omap_pm_soc_init = omap2_pm_init;
469}
470#endif
471
472/*
473 * Currently only board-omap3beagle.c should call this because of the
474 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
475 */
476#ifdef CONFIG_ARCH_OMAP3
477void __init omap3_init_early(void)
478{
479 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
480 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
481 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
482 omap2_control_base_init();
483 omap3xxx_check_revision();
484 omap3xxx_check_features();
485 omap2_prcm_base_init();
486 omap3xxx_voltagedomains_init();
487 omap3xxx_powerdomains_init();
488 omap3xxx_clockdomains_init();
489 omap3xxx_hwmod_init();
490 omap_hwmod_init_postsetup();
491 omap_secure_init();
492}
493
494void __init omap3430_init_early(void)
495{
496 omap3_init_early();
497 omap_clk_soc_init = omap3430_dt_clk_init;
498}
499
500void __init omap35xx_init_early(void)
501{
502 omap3_init_early();
503 omap_clk_soc_init = omap3430_dt_clk_init;
504}
505
506void __init omap3630_init_early(void)
507{
508 omap3_init_early();
509 omap_clk_soc_init = omap3630_dt_clk_init;
510}
511
512void __init am35xx_init_early(void)
513{
514 omap3_init_early();
515 omap_clk_soc_init = am35xx_dt_clk_init;
516}
517
518void __init omap3_init_late(void)
519{
520 omap_pm_soc_init = omap3_pm_init;
521}
522
523void __init ti81xx_init_late(void)
524{
525 omap_pm_soc_init = omap_pm_nop_init;
526}
527#endif
528
529#ifdef CONFIG_SOC_TI81XX
530void __init ti814x_init_early(void)
531{
532 omap2_set_globals_tap(TI814X_CLASS,
533 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
534 omap2_control_base_init();
535 omap3xxx_check_revision();
536 ti81xx_check_features();
537 omap2_prcm_base_init();
538 omap3xxx_voltagedomains_init();
539 omap3xxx_powerdomains_init();
540 ti814x_clockdomains_init();
541 dm814x_hwmod_init();
542 omap_hwmod_init_postsetup();
543 omap_clk_soc_init = dm814x_dt_clk_init;
544 omap_secure_init();
545}
546
547void __init ti816x_init_early(void)
548{
549 omap2_set_globals_tap(TI816X_CLASS,
550 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
551 omap2_control_base_init();
552 omap3xxx_check_revision();
553 ti81xx_check_features();
554 omap2_prcm_base_init();
555 omap3xxx_voltagedomains_init();
556 omap3xxx_powerdomains_init();
557 ti816x_clockdomains_init();
558 dm816x_hwmod_init();
559 omap_hwmod_init_postsetup();
560 omap_clk_soc_init = dm816x_dt_clk_init;
561 omap_secure_init();
562}
563#endif
564
565#ifdef CONFIG_SOC_AM33XX
566void __init am33xx_init_early(void)
567{
568 omap2_set_globals_tap(AM335X_CLASS,
569 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
570 omap2_control_base_init();
571 omap3xxx_check_revision();
572 am33xx_check_features();
573 omap2_prcm_base_init();
574 am33xx_powerdomains_init();
575 am33xx_clockdomains_init();
576 omap_clk_soc_init = am33xx_dt_clk_init;
577 omap_secure_init();
578}
579
580void __init am33xx_init_late(void)
581{
582 omap_pm_soc_init = amx3_common_pm_init;
583}
584#endif
585
586#ifdef CONFIG_SOC_AM43XX
587void __init am43xx_init_early(void)
588{
589 omap2_set_globals_tap(AM335X_CLASS,
590 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
591 omap2_control_base_init();
592 omap3xxx_check_revision();
593 am33xx_check_features();
594 omap2_prcm_base_init();
595 am43xx_powerdomains_init();
596 am43xx_clockdomains_init();
597 omap_l2_cache_init();
598 omap_clk_soc_init = am43xx_dt_clk_init;
599 omap_secure_init();
600}
601
602void __init am43xx_init_late(void)
603{
604 omap_pm_soc_init = amx3_common_pm_init;
605}
606#endif
607
608#ifdef CONFIG_ARCH_OMAP4
609void __init omap4430_init_early(void)
610{
611 omap2_set_globals_tap(OMAP443X_CLASS,
612 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
613 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
614 omap2_control_base_init();
615 omap4xxx_check_revision();
616 omap4xxx_check_features();
617 omap2_prcm_base_init();
618 omap4_sar_ram_init();
619 omap4_mpuss_early_init();
620 omap4_pm_init_early();
621 omap44xx_voltagedomains_init();
622 omap44xx_powerdomains_init();
623 omap44xx_clockdomains_init();
624 omap_l2_cache_init();
625 omap_clk_soc_init = omap4xxx_dt_clk_init;
626 omap_secure_init();
627}
628
629void __init omap4430_init_late(void)
630{
631 omap_pm_soc_init = omap4_pm_init;
632}
633#endif
634
635#ifdef CONFIG_SOC_OMAP5
636void __init omap5_init_early(void)
637{
638 omap2_set_globals_tap(OMAP54XX_CLASS,
639 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
640 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
641 omap2_control_base_init();
642 omap2_prcm_base_init();
643 omap5xxx_check_revision();
644 omap4_sar_ram_init();
645 omap4_mpuss_early_init();
646 omap4_pm_init_early();
647 omap54xx_voltagedomains_init();
648 omap54xx_powerdomains_init();
649 omap54xx_clockdomains_init();
650 omap_clk_soc_init = omap5xxx_dt_clk_init;
651 omap_secure_init();
652}
653
654void __init omap5_init_late(void)
655{
656 omap_pm_soc_init = omap4_pm_init;
657}
658#endif
659
660#ifdef CONFIG_SOC_DRA7XX
661void __init dra7xx_init_early(void)
662{
663 omap2_set_globals_tap(DRA7XX_CLASS,
664 OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
665 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
666 omap2_control_base_init();
667 omap4_pm_init_early();
668 omap2_prcm_base_init();
669 dra7xxx_check_revision();
670 dra7xx_powerdomains_init();
671 dra7xx_clockdomains_init();
672 omap_clk_soc_init = dra7xx_dt_clk_init;
673 omap_secure_init();
674}
675
676void __init dra7xx_init_late(void)
677{
678 omap_pm_soc_init = omap4_pm_init;
679}
680#endif
681
682
683void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
684 struct omap_sdrc_params *sdrc_cs1)
685{
686 omap_sram_init();
687
688 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
689 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
690 _omap2_init_reprogram_sdrc();
691 }
692}
693
694int __init omap_clk_init(void)
695{
696 int ret = 0;
697
698 if (!omap_clk_soc_init)
699 return 0;
700
701 ti_clk_init_features();
702
703 omap2_clk_setup_ll_ops();
704
705 ret = omap_control_init();
706 if (ret)
707 return ret;
708
709 ret = omap_prcm_init();
710 if (ret)
711 return ret;
712
713 of_clk_init(NULL);
714
715 ti_dt_clk_init_retry_clks();
716
717 ti_dt_clockdomains_setup();
718
719 ret = omap_clk_soc_init();
720
721 return ret;
722}
1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
12 *
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/io.h>
24#include <linux/clk.h>
25#include <linux/omapfb.h>
26
27#include <asm/tlb.h>
28
29#include <asm/mach/map.h>
30
31#include <plat/sram.h>
32#include <plat/sdrc.h>
33#include <plat/serial.h>
34
35#include "clock2xxx.h"
36#include "clock3xxx.h"
37#include "clock44xx.h"
38#include "io.h"
39
40#include <plat/omap-pm.h>
41#include "powerdomain.h"
42
43#include "clockdomain.h"
44#include <plat/omap_hwmod.h>
45#include <plat/multi.h>
46
47/*
48 * The machine specific code may provide the extra mapping besides the
49 * default mapping provided here.
50 */
51
52#ifdef CONFIG_ARCH_OMAP2
53static struct map_desc omap24xx_io_desc[] __initdata = {
54 {
55 .virtual = L3_24XX_VIRT,
56 .pfn = __phys_to_pfn(L3_24XX_PHYS),
57 .length = L3_24XX_SIZE,
58 .type = MT_DEVICE
59 },
60 {
61 .virtual = L4_24XX_VIRT,
62 .pfn = __phys_to_pfn(L4_24XX_PHYS),
63 .length = L4_24XX_SIZE,
64 .type = MT_DEVICE
65 },
66};
67
68#ifdef CONFIG_SOC_OMAP2420
69static struct map_desc omap242x_io_desc[] __initdata = {
70 {
71 .virtual = DSP_MEM_2420_VIRT,
72 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
73 .length = DSP_MEM_2420_SIZE,
74 .type = MT_DEVICE
75 },
76 {
77 .virtual = DSP_IPI_2420_VIRT,
78 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
79 .length = DSP_IPI_2420_SIZE,
80 .type = MT_DEVICE
81 },
82 {
83 .virtual = DSP_MMU_2420_VIRT,
84 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
85 .length = DSP_MMU_2420_SIZE,
86 .type = MT_DEVICE
87 },
88};
89
90#endif
91
92#ifdef CONFIG_SOC_OMAP2430
93static struct map_desc omap243x_io_desc[] __initdata = {
94 {
95 .virtual = L4_WK_243X_VIRT,
96 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
97 .length = L4_WK_243X_SIZE,
98 .type = MT_DEVICE
99 },
100 {
101 .virtual = OMAP243X_GPMC_VIRT,
102 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
103 .length = OMAP243X_GPMC_SIZE,
104 .type = MT_DEVICE
105 },
106 {
107 .virtual = OMAP243X_SDRC_VIRT,
108 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
109 .length = OMAP243X_SDRC_SIZE,
110 .type = MT_DEVICE
111 },
112 {
113 .virtual = OMAP243X_SMS_VIRT,
114 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
115 .length = OMAP243X_SMS_SIZE,
116 .type = MT_DEVICE
117 },
118};
119#endif
120#endif
121
122#ifdef CONFIG_ARCH_OMAP3
123static struct map_desc omap34xx_io_desc[] __initdata = {
124 {
125 .virtual = L3_34XX_VIRT,
126 .pfn = __phys_to_pfn(L3_34XX_PHYS),
127 .length = L3_34XX_SIZE,
128 .type = MT_DEVICE
129 },
130 {
131 .virtual = L4_34XX_VIRT,
132 .pfn = __phys_to_pfn(L4_34XX_PHYS),
133 .length = L4_34XX_SIZE,
134 .type = MT_DEVICE
135 },
136 {
137 .virtual = OMAP34XX_GPMC_VIRT,
138 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
139 .length = OMAP34XX_GPMC_SIZE,
140 .type = MT_DEVICE
141 },
142 {
143 .virtual = OMAP343X_SMS_VIRT,
144 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
145 .length = OMAP343X_SMS_SIZE,
146 .type = MT_DEVICE
147 },
148 {
149 .virtual = OMAP343X_SDRC_VIRT,
150 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
151 .length = OMAP343X_SDRC_SIZE,
152 .type = MT_DEVICE
153 },
154 {
155 .virtual = L4_PER_34XX_VIRT,
156 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
157 .length = L4_PER_34XX_SIZE,
158 .type = MT_DEVICE
159 },
160 {
161 .virtual = L4_EMU_34XX_VIRT,
162 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
163 .length = L4_EMU_34XX_SIZE,
164 .type = MT_DEVICE
165 },
166#if defined(CONFIG_DEBUG_LL) && \
167 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
168 {
169 .virtual = ZOOM_UART_VIRT,
170 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
171 .length = SZ_1M,
172 .type = MT_DEVICE
173 },
174#endif
175};
176#endif
177
178#ifdef CONFIG_SOC_OMAPTI816X
179static struct map_desc omapti816x_io_desc[] __initdata = {
180 {
181 .virtual = L4_34XX_VIRT,
182 .pfn = __phys_to_pfn(L4_34XX_PHYS),
183 .length = L4_34XX_SIZE,
184 .type = MT_DEVICE
185 },
186};
187#endif
188
189#ifdef CONFIG_ARCH_OMAP4
190static struct map_desc omap44xx_io_desc[] __initdata = {
191 {
192 .virtual = L3_44XX_VIRT,
193 .pfn = __phys_to_pfn(L3_44XX_PHYS),
194 .length = L3_44XX_SIZE,
195 .type = MT_DEVICE,
196 },
197 {
198 .virtual = L4_44XX_VIRT,
199 .pfn = __phys_to_pfn(L4_44XX_PHYS),
200 .length = L4_44XX_SIZE,
201 .type = MT_DEVICE,
202 },
203 {
204 .virtual = OMAP44XX_GPMC_VIRT,
205 .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
206 .length = OMAP44XX_GPMC_SIZE,
207 .type = MT_DEVICE,
208 },
209 {
210 .virtual = OMAP44XX_EMIF1_VIRT,
211 .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
212 .length = OMAP44XX_EMIF1_SIZE,
213 .type = MT_DEVICE,
214 },
215 {
216 .virtual = OMAP44XX_EMIF2_VIRT,
217 .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
218 .length = OMAP44XX_EMIF2_SIZE,
219 .type = MT_DEVICE,
220 },
221 {
222 .virtual = OMAP44XX_DMM_VIRT,
223 .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
224 .length = OMAP44XX_DMM_SIZE,
225 .type = MT_DEVICE,
226 },
227 {
228 .virtual = L4_PER_44XX_VIRT,
229 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
230 .length = L4_PER_44XX_SIZE,
231 .type = MT_DEVICE,
232 },
233 {
234 .virtual = L4_EMU_44XX_VIRT,
235 .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
236 .length = L4_EMU_44XX_SIZE,
237 .type = MT_DEVICE,
238 },
239};
240#endif
241
242static void __init _omap2_map_common_io(void)
243{
244 /* Normally devicemaps_init() would flush caches and tlb after
245 * mdesc->map_io(), but we must also do it here because of the CPU
246 * revision check below.
247 */
248 local_flush_tlb_all();
249 flush_cache_all();
250
251 omap2_check_revision();
252 omap_sram_init();
253}
254
255#ifdef CONFIG_SOC_OMAP2420
256void __init omap242x_map_common_io(void)
257{
258 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
259 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
260 _omap2_map_common_io();
261}
262#endif
263
264#ifdef CONFIG_SOC_OMAP2430
265void __init omap243x_map_common_io(void)
266{
267 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
268 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
269 _omap2_map_common_io();
270}
271#endif
272
273#ifdef CONFIG_ARCH_OMAP3
274void __init omap34xx_map_common_io(void)
275{
276 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
277 _omap2_map_common_io();
278}
279#endif
280
281#ifdef CONFIG_SOC_OMAPTI816X
282void __init omapti816x_map_common_io(void)
283{
284 iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
285 _omap2_map_common_io();
286}
287#endif
288
289#ifdef CONFIG_ARCH_OMAP4
290void __init omap44xx_map_common_io(void)
291{
292 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
293 _omap2_map_common_io();
294}
295#endif
296
297/*
298 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
299 *
300 * Sets the CORE DPLL3 M2 divider to the same value that it's at
301 * currently. This has the effect of setting the SDRC SDRAM AC timing
302 * registers to the values currently defined by the kernel. Currently
303 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
304 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
305 * or passes along the return value of clk_set_rate().
306 */
307static int __init _omap2_init_reprogram_sdrc(void)
308{
309 struct clk *dpll3_m2_ck;
310 int v = -EINVAL;
311 long rate;
312
313 if (!cpu_is_omap34xx())
314 return 0;
315
316 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
317 if (IS_ERR(dpll3_m2_ck))
318 return -EINVAL;
319
320 rate = clk_get_rate(dpll3_m2_ck);
321 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
322 v = clk_set_rate(dpll3_m2_ck, rate);
323 if (v)
324 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
325
326 clk_put(dpll3_m2_ck);
327
328 return v;
329}
330
331static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
332{
333 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
334}
335
336/* See irq.c, omap4-common.c and entry-macro.S */
337void __iomem *omap_irq_base;
338
339void __init omap2_init_common_infrastructure(void)
340{
341 u8 postsetup_state;
342
343 if (cpu_is_omap242x()) {
344 omap2xxx_powerdomains_init();
345 omap2xxx_clockdomains_init();
346 omap2420_hwmod_init();
347 } else if (cpu_is_omap243x()) {
348 omap2xxx_powerdomains_init();
349 omap2xxx_clockdomains_init();
350 omap2430_hwmod_init();
351 } else if (cpu_is_omap34xx()) {
352 omap3xxx_powerdomains_init();
353 omap3xxx_clockdomains_init();
354 omap3xxx_hwmod_init();
355 } else if (cpu_is_omap44xx()) {
356 omap44xx_powerdomains_init();
357 omap44xx_clockdomains_init();
358 omap44xx_hwmod_init();
359 } else {
360 pr_err("Could not init hwmod data - unknown SoC\n");
361 }
362
363 /* Set the default postsetup state for all hwmods */
364#ifdef CONFIG_PM_RUNTIME
365 postsetup_state = _HWMOD_STATE_IDLE;
366#else
367 postsetup_state = _HWMOD_STATE_ENABLED;
368#endif
369 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
370
371 /*
372 * Set the default postsetup state for unusual modules (like
373 * MPU WDT).
374 *
375 * The postsetup_state is not actually used until
376 * omap_hwmod_late_init(), so boards that desire full watchdog
377 * coverage of kernel initialization can reprogram the
378 * postsetup_state between the calls to
379 * omap2_init_common_infra() and omap2_init_common_devices().
380 *
381 * XXX ideally we could detect whether the MPU WDT was currently
382 * enabled here and make this conditional
383 */
384 postsetup_state = _HWMOD_STATE_DISABLED;
385 omap_hwmod_for_each_by_class("wd_timer",
386 _set_hwmod_postsetup_state,
387 &postsetup_state);
388
389 omap_pm_if_early_init();
390
391 if (cpu_is_omap2420())
392 omap2420_clk_init();
393 else if (cpu_is_omap2430())
394 omap2430_clk_init();
395 else if (cpu_is_omap34xx())
396 omap3xxx_clk_init();
397 else if (cpu_is_omap44xx())
398 omap4xxx_clk_init();
399 else
400 pr_err("Could not init clock framework - unknown SoC\n");
401}
402
403void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
404 struct omap_sdrc_params *sdrc_cs1)
405{
406 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
407 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
408 _omap2_init_reprogram_sdrc();
409 }
410
411}
412
413/*
414 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
415 */
416
417u8 omap_readb(u32 pa)
418{
419 return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
420}
421EXPORT_SYMBOL(omap_readb);
422
423u16 omap_readw(u32 pa)
424{
425 return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
426}
427EXPORT_SYMBOL(omap_readw);
428
429u32 omap_readl(u32 pa)
430{
431 return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
432}
433EXPORT_SYMBOL(omap_readl);
434
435void omap_writeb(u8 v, u32 pa)
436{
437 __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
438}
439EXPORT_SYMBOL(omap_writeb);
440
441void omap_writew(u16 v, u32 pa)
442{
443 __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
444}
445EXPORT_SYMBOL(omap_writew);
446
447void omap_writel(u32 v, u32 pa)
448{
449 __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
450}
451EXPORT_SYMBOL(omap_writel);