1/* SPDX-License-Identifier: MIT */
  2/*
  3 * Copyright (c) 2015, Roger Pau Monne <roger.pau@citrix.com>
  4 */
  5
  6#ifndef __XEN_PUBLIC_HVM_HVM_VCPU_H__
  7#define __XEN_PUBLIC_HVM_HVM_VCPU_H__
  8
  9#include "../xen.h"
 10
 11struct vcpu_hvm_x86_32 {
 12    uint32_t eax;
 13    uint32_t ecx;
 14    uint32_t edx;
 15    uint32_t ebx;
 16    uint32_t esp;
 17    uint32_t ebp;
 18    uint32_t esi;
 19    uint32_t edi;
 20    uint32_t eip;
 21    uint32_t eflags;
 22
 23    uint32_t cr0;
 24    uint32_t cr3;
 25    uint32_t cr4;
 26
 27    uint32_t pad1;
 28
 29    /*
 30     * EFER should only be used to set the NXE bit (if required)
 31     * when starting a vCPU in 32bit mode with paging enabled or
 32     * to set the LME/LMA bits in order to start the vCPU in
 33     * compatibility mode.
 34     */
 35    uint64_t efer;
 36
 37    uint32_t cs_base;
 38    uint32_t ds_base;
 39    uint32_t ss_base;
 40    uint32_t es_base;
 41    uint32_t tr_base;
 42    uint32_t cs_limit;
 43    uint32_t ds_limit;
 44    uint32_t ss_limit;
 45    uint32_t es_limit;
 46    uint32_t tr_limit;
 47    uint16_t cs_ar;
 48    uint16_t ds_ar;
 49    uint16_t ss_ar;
 50    uint16_t es_ar;
 51    uint16_t tr_ar;
 52
 53    uint16_t pad2[3];
 54};
 55
 56/*
 57 * The layout of the _ar fields of the segment registers is the
 58 * following:
 59 *
 60 * Bits   [0,3]: type (bits 40-43).
 61 * Bit        4: s    (descriptor type, bit 44).
 62 * Bit    [5,6]: dpl  (descriptor privilege level, bits 45-46).
 63 * Bit        7: p    (segment-present, bit 47).
 64 * Bit        8: avl  (available for system software, bit 52).
 65 * Bit        9: l    (64-bit code segment, bit 53).
 66 * Bit       10: db   (meaning depends on the segment, bit 54).
 67 * Bit       11: g    (granularity, bit 55)
 68 * Bits [12,15]: unused, must be blank.
 69 *
 70 * A more complete description of the meaning of this fields can be
 71 * obtained from the Intel SDM, Volume 3, section 3.4.5.
 72 */
 73
 74struct vcpu_hvm_x86_64 {
 75    uint64_t rax;
 76    uint64_t rcx;
 77    uint64_t rdx;
 78    uint64_t rbx;
 79    uint64_t rsp;
 80    uint64_t rbp;
 81    uint64_t rsi;
 82    uint64_t rdi;
 83    uint64_t rip;
 84    uint64_t rflags;
 85
 86    uint64_t cr0;
 87    uint64_t cr3;
 88    uint64_t cr4;
 89    uint64_t efer;
 90
 91    /*
 92     * Using VCPU_HVM_MODE_64B implies that the vCPU is launched
 93     * directly in long mode, so the cached parts of the segment
 94     * registers get set to match that environment.
 95     *
 96     * If the user wants to launch the vCPU in compatibility mode
 97     * the 32-bit structure should be used instead.
 98     */
 99};
100
101struct vcpu_hvm_context {
102#define VCPU_HVM_MODE_32B 0  /* 32bit fields of the structure will be used. */
103#define VCPU_HVM_MODE_64B 1  /* 64bit fields of the structure will be used. */
104    uint32_t mode;
105
106    uint32_t pad;
107
108    /* CPU registers. */
109    union {
110        struct vcpu_hvm_x86_32 x86_32;
111        struct vcpu_hvm_x86_64 x86_64;
112    } cpu_regs;
113};
114typedef struct vcpu_hvm_context vcpu_hvm_context_t;
115
116#endif /* __XEN_PUBLIC_HVM_HVM_VCPU_H__ */