1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Copyright (c) 2021 HiSilicon Ltd. */
  3
  4#ifndef HISI_ACC_VFIO_PCI_H
  5#define HISI_ACC_VFIO_PCI_H
  6
  7#include <linux/hisi_acc_qm.h>
  8
  9#define MB_POLL_PERIOD_US		10
 10#define MB_POLL_TIMEOUT_US		1000
 11#define QM_CACHE_WB_START		0x204
 12#define QM_CACHE_WB_DONE		0x208
 13#define QM_MB_CMD_PAUSE_QM		0xe
 14#define QM_ABNORMAL_INT_STATUS		0x100008
 15#define QM_IFC_INT_STATUS		0x0028
 16#define SEC_CORE_INT_STATUS		0x301008
 17#define HPRE_HAC_INT_STATUS		0x301800
 18#define HZIP_CORE_INT_STATUS		0x3010AC
 19
 20#define QM_VFT_CFG_RDY			0x10006c
 21#define QM_VFT_CFG_OP_WR		0x100058
 22#define QM_VFT_CFG_TYPE			0x10005c
 23#define QM_VFT_CFG			0x100060
 24#define QM_VFT_CFG_OP_ENABLE		0x100054
 25#define QM_VFT_CFG_DATA_L		0x100064
 26#define QM_VFT_CFG_DATA_H		0x100068
 27
 28#define ERROR_CHECK_TIMEOUT		100
 29#define CHECK_DELAY_TIME		100
 30
 31#define QM_SQC_VFT_BASE_SHIFT_V2	28
 32#define QM_SQC_VFT_BASE_MASK_V2		GENMASK(15, 0)
 33#define QM_SQC_VFT_NUM_SHIFT_V2		45
 34#define QM_SQC_VFT_NUM_MASK_V2		GENMASK(9, 0)
 35#define QM_MB_CMD_NOT_READY	0xffffffff
 36
 37/* RW regs */
 38#define QM_REGS_MAX_LEN		7
 39#define QM_REG_ADDR_OFFSET	0x0004
 40
 41#define QM_XQC_ADDR_OFFSET	32U
 42#define QM_VF_AEQ_INT_MASK	0x0004
 43#define QM_VF_EQ_INT_MASK	0x000c
 44#define QM_IFC_INT_SOURCE_V	0x0020
 45#define QM_IFC_INT_MASK		0x0024
 46#define QM_IFC_INT_SET_V	0x002c
 47#define QM_QUE_ISO_CFG_V	0x0030
 48#define QM_PAGE_SIZE		0x0034
 49
 50#define QM_EQC_DW0		0X8000
 51#define QM_AEQC_DW0		0X8020
 52
 53struct acc_vf_data {
 54#define QM_MATCH_SIZE offsetofend(struct acc_vf_data, qm_rsv_state)
 55	/* QM match information */
 56#define ACC_DEV_MAGIC	0XCDCDCDCDFEEDAACC
 57	u64 acc_magic;
 58	u32 qp_num;
 59	u32 dev_id;
 60	u32 que_iso_cfg;
 61	u32 qp_base;
 62	u32 vf_qm_state;
 63	/* QM reserved match information */
 64	u32 qm_rsv_state[3];
 65
 66	/* QM RW regs */
 67	u32 aeq_int_mask;
 68	u32 eq_int_mask;
 69	u32 ifc_int_source;
 70	u32 ifc_int_mask;
 71	u32 ifc_int_set;
 72	u32 page_size;
 73
 74	/* QM_EQC_DW has 7 regs */
 75	u32 qm_eqc_dw[7];
 76
 77	/* QM_AEQC_DW has 7 regs */
 78	u32 qm_aeqc_dw[7];
 79
 80	/* QM reserved 5 regs */
 81	u32 qm_rsv_regs[5];
 82	u32 padding;
 83	/* QM memory init information */
 84	u64 eqe_dma;
 85	u64 aeqe_dma;
 86	u64 sqc_dma;
 87	u64 cqc_dma;
 88};
 89
 90struct hisi_acc_vf_migration_file {
 91	struct file *filp;
 92	struct mutex lock;
 93	bool disabled;
 94
 95	struct hisi_acc_vf_core_device *hisi_acc_vdev;
 96	struct acc_vf_data vf_data;
 97	size_t total_length;
 98};
 99
100struct hisi_acc_vf_core_device {
101	struct vfio_pci_core_device core_device;
102	u8 match_done;
103	/*
104	 * io_base is only valid when dev_opened is true,
105	 * which is protected by open_mutex.
106	 */
107	bool dev_opened;
108	/* Ensure the accuracy of dev_opened operation */
109	struct mutex open_mutex;
110
111	/* For migration state */
112	struct mutex state_mutex;
113	enum vfio_device_mig_state mig_state;
114	struct pci_dev *pf_dev;
115	struct pci_dev *vf_dev;
116	struct hisi_qm *pf_qm;
117	struct hisi_qm vf_qm;
118	/*
119	 * vf_qm_state represents the QM_VF_STATE register value.
120	 * It is set by Guest driver for the ACC VF dev indicating
121	 * the driver has loaded and configured the dev correctly.
122	 */
123	u32 vf_qm_state;
124	int vf_id;
125	struct hisi_acc_vf_migration_file *resuming_migf;
126	struct hisi_acc_vf_migration_file *saving_migf;
127
128	/*
129	 * It holds migration data corresponding to the last migration
130	 * and is used by the debugfs interface to report it.
131	 */
132	struct hisi_acc_vf_migration_file *debug_migf;
133};
134#endif /* HISI_ACC_VFIO_PCI_H */