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  1// SPDX-License-Identifier: GPL-2.0
  2/* Copyright(c) 2009-2012  Realtek Corporation.*/
  3
  4#include "../wifi.h"
  5#include "../core.h"
  6#include "../base.h"
  7#include "../pci.h"
  8#include "reg.h"
  9#include "def.h"
 10#include "phy.h"
 11#include "dm.h"
 12#include "fw.h"
 13#include "hw.h"
 14#include "trx.h"
 15#include "led.h"
 16
 17#include <linux/module.h>
 18
 19static void rtl92s_init_aspm_vars(struct ieee80211_hw *hw)
 20{
 21	struct rtl_priv *rtlpriv = rtl_priv(hw);
 22	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 23
 24	/* ASPM PS mode.
 25	 * 0 - Disable ASPM,
 26	 * 1 - Enable ASPM without Clock Req,
 27	 * 2 - Enable ASPM with Clock Req,
 28	 * 3 - Alwyas Enable ASPM with Clock Req,
 29	 * 4 - Always Enable ASPM without Clock Req.
 30	 * set default to RTL8192CE:3 RTL8192E:2
 31	 * */
 32	rtlpci->const_pci_aspm = 2;
 33
 34	/*Setting for PCI-E device */
 35	rtlpci->const_devicepci_aspm_setting = 0x03;
 36
 37	/*Setting for PCI-E bridge */
 38	rtlpci->const_hostpci_aspm_setting = 0x02;
 39
 40	/* In Hw/Sw Radio Off situation.
 41	 * 0 - Default,
 42	 * 1 - From ASPM setting without low Mac Pwr,
 43	 * 2 - From ASPM setting with low Mac Pwr,
 44	 * 3 - Bus D3
 45	 * set default to RTL8192CE:0 RTL8192SE:2
 46	 */
 47	rtlpci->const_hwsw_rfoff_d3 = 2;
 48
 49	/* This setting works for those device with
 50	 * backdoor ASPM setting such as EPHY setting.
 51	 * 0 - Not support ASPM,
 52	 * 1 - Support ASPM,
 53	 * 2 - According to chipset.
 54	 */
 55	rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;
 56}
 57
 58static void rtl92se_fw_cb(const struct firmware *firmware, void *context)
 59{
 60	struct ieee80211_hw *hw = context;
 61	struct rtl_priv *rtlpriv = rtl_priv(hw);
 62	struct rt_firmware *pfirmware = NULL;
 63	char *fw_name = "rtlwifi/rtl8192sefw.bin";
 64
 65	rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
 66		"Firmware callback routine entered!\n");
 67	if (!firmware) {
 68		pr_err("Firmware %s not available\n", fw_name);
 69		rtlpriv->max_fw_size = 0;
 70		goto exit;
 71	}
 72	if (firmware->size > rtlpriv->max_fw_size) {
 73		pr_err("Firmware is too big!\n");
 74		rtlpriv->max_fw_size = 0;
 75		release_firmware(firmware);
 76		goto exit;
 77	}
 78	pfirmware = (struct rt_firmware *)rtlpriv->rtlhal.pfirmware;
 79	memcpy(pfirmware->sz_fw_tmpbuffer, firmware->data, firmware->size);
 80	pfirmware->sz_fw_tmpbufferlen = firmware->size;
 81	release_firmware(firmware);
 82exit:
 83	complete(&rtlpriv->firmware_loading_complete);
 84}
 85
 86static int rtl92s_init_sw_vars(struct ieee80211_hw *hw)
 87{
 88	struct rtl_priv *rtlpriv = rtl_priv(hw);
 89	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 90	int err = 0;
 91	u16 earlyrxthreshold = 7;
 92	char *fw_name = "rtlwifi/rtl8192sefw.bin";
 93
 94	rtlpriv->dm.dm_initialgain_enable = true;
 95	rtlpriv->dm.dm_flag = 0;
 96	rtlpriv->dm.disable_framebursting = false;
 97	rtlpriv->dm.thermalvalue = 0;
 98	rtlpriv->dm.useramask = true;
 99
100	/* compatible 5G band 91se just 2.4G band & smsp */
101	rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
102	rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
103	rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
104
105	rtlpci->transmit_config = 0;
106
107	rtlpci->receive_config =
108			RCR_APPFCS |
109			RCR_APWRMGT |
110			/*RCR_ADD3 |*/
111			RCR_AMF	|
112			RCR_ADF |
113			RCR_APP_MIC |
114			RCR_APP_ICV |
115			RCR_AICV |
116			/* Accept ICV error, CRC32 Error */
117			RCR_ACRC32 |
118			RCR_AB |
119			/* Accept Broadcast, Multicast */
120			RCR_AM	|
121			/* Accept Physical match */
122			RCR_APM |
123			/* Accept Destination Address packets */
124			/*RCR_AAP |*/
125			RCR_APP_PHYST_STAFF |
126			/* Accept PHY status */
127			RCR_APP_PHYST_RXFF |
128			(earlyrxthreshold << RCR_FIFO_OFFSET);
129
130	rtlpci->irq_mask[0] = (u32)
131			(IMR_ROK |
132			IMR_VODOK |
133			IMR_VIDOK |
134			IMR_BEDOK |
135			IMR_BKDOK |
136			IMR_HCCADOK |
137			IMR_MGNTDOK |
138			IMR_COMDOK |
139			IMR_HIGHDOK |
140			IMR_BDOK |
141			IMR_RXCMDOK |
142			/*IMR_TIMEOUT0 |*/
143			IMR_RDU |
144			IMR_RXFOVW	|
145			IMR_BCNINT
146			/*| IMR_TXFOVW*/
147			/*| IMR_TBDOK |
148			IMR_TBDER*/);
149
150	rtlpci->irq_mask[1] = (u32) 0;
151
152	rtlpci->shortretry_limit = 0x30;
153	rtlpci->longretry_limit = 0x30;
154
155	rtlpci->first_init = true;
156
157	/* for LPS & IPS */
158	rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
159	rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
160	rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
161	if (!rtlpriv->psc.inactiveps)
162		pr_info("Power Save off (module option)\n");
163	if (!rtlpriv->psc.fwctrl_lps)
164		pr_info("FW Power Save off (module option)\n");
165	rtlpriv->psc.reg_fwctrl_lps = 3;
166	rtlpriv->psc.reg_max_lps_awakeintvl = 5;
167	/* for ASPM, you can close aspm through
168	 * set const_support_pciaspm = 0 */
169	rtl92s_init_aspm_vars(hw);
170
171	if (rtlpriv->psc.reg_fwctrl_lps == 1)
172		rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
173	else if (rtlpriv->psc.reg_fwctrl_lps == 2)
174		rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
175	else if (rtlpriv->psc.reg_fwctrl_lps == 3)
176		rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
177
178	/* for firmware buf */
179	rtlpriv->rtlhal.pfirmware = vzalloc(sizeof(struct rt_firmware));
180	if (!rtlpriv->rtlhal.pfirmware)
181		return 1;
182
183	rtlpriv->max_fw_size = RTL8190_MAX_FIRMWARE_CODE_SIZE*2 +
184			       sizeof(struct fw_hdr);
185	pr_info("Driver for Realtek RTL8192SE/RTL8191SE\n"
186		"Loading firmware %s\n", fw_name);
187	/* request fw */
188	err = request_firmware_nowait(THIS_MODULE, 1, fw_name,
189				      rtlpriv->io.dev, GFP_KERNEL, hw,
190				      rtl92se_fw_cb);
191	if (err) {
192		pr_err("Failed to request firmware!\n");
193		vfree(rtlpriv->rtlhal.pfirmware);
194		rtlpriv->rtlhal.pfirmware = NULL;
195		return 1;
196	}
197
198	return err;
199}
200
201static void rtl92s_deinit_sw_vars(struct ieee80211_hw *hw)
202{
203	struct rtl_priv *rtlpriv = rtl_priv(hw);
204
205	if (rtlpriv->rtlhal.pfirmware) {
206		vfree(rtlpriv->rtlhal.pfirmware);
207		rtlpriv->rtlhal.pfirmware = NULL;
208	}
209}
210
211static bool rtl92se_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue,
212				      u16 index)
213{
214	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
215	struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
216	u8 *entry = (u8 *)(&ring->desc[ring->idx]);
217	u8 own = (u8)rtl92se_get_desc(hw, entry, true, HW_DESC_OWN);
218
219	if (own)
220		return false;
221	return true;
222}
223
224static struct rtl_hal_ops rtl8192se_hal_ops = {
225	.init_sw_vars = rtl92s_init_sw_vars,
226	.deinit_sw_vars = rtl92s_deinit_sw_vars,
227	.read_eeprom_info = rtl92se_read_eeprom_info,
228	.interrupt_recognized = rtl92se_interrupt_recognized,
229	.hw_init = rtl92se_hw_init,
230	.hw_disable = rtl92se_card_disable,
231	.hw_suspend = rtl92se_suspend,
232	.hw_resume = rtl92se_resume,
233	.enable_interrupt = rtl92se_enable_interrupt,
234	.disable_interrupt = rtl92se_disable_interrupt,
235	.set_network_type = rtl92se_set_network_type,
236	.set_chk_bssid = rtl92se_set_check_bssid,
237	.set_qos = rtl92se_set_qos,
238	.set_bcn_reg = rtl92se_set_beacon_related_registers,
239	.set_bcn_intv = rtl92se_set_beacon_interval,
240	.update_interrupt_mask = rtl92se_update_interrupt_mask,
241	.get_hw_reg = rtl92se_get_hw_reg,
242	.set_hw_reg = rtl92se_set_hw_reg,
243	.update_rate_tbl = rtl92se_update_hal_rate_tbl,
244	.fill_tx_desc = rtl92se_tx_fill_desc,
245	.fill_tx_cmddesc = rtl92se_tx_fill_cmddesc,
246	.query_rx_desc = rtl92se_rx_query_desc,
247	.set_channel_access = rtl92se_update_channel_access_setting,
248	.radio_onoff_checking = rtl92se_gpio_radio_on_off_checking,
249	.set_bw_mode = rtl92s_phy_set_bw_mode,
250	.switch_channel = rtl92s_phy_sw_chnl,
251	.dm_watchdog = rtl92s_dm_watchdog,
252	.scan_operation_backup = rtl92s_phy_scan_operation_backup,
253	.set_rf_power_state = rtl92s_phy_set_rf_power_state,
254	.led_control = rtl92se_led_control,
255	.set_desc = rtl92se_set_desc,
256	.get_desc = rtl92se_get_desc,
257	.is_tx_desc_closed = rtl92se_is_tx_desc_closed,
258	.tx_polling = rtl92se_tx_polling,
259	.enable_hw_sec = rtl92se_enable_hw_security_config,
260	.set_key = rtl92se_set_key,
261	.get_bbreg = rtl92s_phy_query_bb_reg,
262	.set_bbreg = rtl92s_phy_set_bb_reg,
263	.get_rfreg = rtl92s_phy_query_rf_reg,
264	.set_rfreg = rtl92s_phy_set_rf_reg,
265	.get_btc_status = rtl_btc_status_false,
266};
267
268static struct rtl_mod_params rtl92se_mod_params = {
269	.sw_crypto = false,
270	.inactiveps = true,
271	.swctrl_lps = true,
272	.fwctrl_lps = false,
273	.aspm_support = 2,
274	.debug_level = 0,
275	.debug_mask = 0,
276};
277
278/* Because memory R/W bursting will cause system hang/crash
279 * for 92se, so we don't read back after every write action */
280static const struct rtl_hal_cfg rtl92se_hal_cfg = {
281	.bar_id = 1,
282	.write_readback = false,
283	.name = "rtl92s_pci",
284	.ops = &rtl8192se_hal_ops,
285	.mod_params = &rtl92se_mod_params,
286
287	.maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
288	.maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
289	.maps[SYS_CLK] = SYS_CLKR,
290	.maps[MAC_RCR_AM] = RCR_AM,
291	.maps[MAC_RCR_AB] = RCR_AB,
292	.maps[MAC_RCR_ACRC32] = RCR_ACRC32,
293	.maps[MAC_RCR_ACF] = RCR_ACF,
294	.maps[MAC_RCR_AAP] = RCR_AAP,
295	.maps[MAC_HIMR] = INTA_MASK,
296	.maps[MAC_HIMRE] = INTA_MASK + 4,
297
298	.maps[EFUSE_TEST] = REG_EFUSE_TEST,
299	.maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
300	.maps[EFUSE_CLK] = REG_EFUSE_CLK,
301	.maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
302	.maps[EFUSE_PWC_EV12V] = 0, /* nouse for 8192se */
303	.maps[EFUSE_FEN_ELDR] = 0, /* nouse for 8192se */
304	.maps[EFUSE_LOADER_CLK_EN] = 0,/* nouse for 8192se */
305	.maps[EFUSE_ANA8M] = EFUSE_ANA8M,
306	.maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE_92S,
307	.maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
308	.maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
309	.maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
310
311	.maps[RWCAM] = REG_RWCAM,
312	.maps[WCAMI] = REG_WCAMI,
313	.maps[RCAMO] = REG_RCAMO,
314	.maps[CAMDBG] = REG_CAMDBG,
315	.maps[SECR] = REG_SECR,
316	.maps[SEC_CAM_NONE] = CAM_NONE,
317	.maps[SEC_CAM_WEP40] = CAM_WEP40,
318	.maps[SEC_CAM_TKIP] = CAM_TKIP,
319	.maps[SEC_CAM_AES] = CAM_AES,
320	.maps[SEC_CAM_WEP104] = CAM_WEP104,
321
322	.maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
323	.maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
324	.maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
325	.maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
326	.maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
327	.maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
328	.maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
329	.maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
330	.maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
331	.maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
332	.maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
333	.maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
334	.maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
335	.maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
336	.maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
337	.maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
338
339	.maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
340	.maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
341	.maps[RTL_IMR_BCNINT] = IMR_BCNINT,
342	.maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
343	.maps[RTL_IMR_RDU] = IMR_RDU,
344	.maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
345	.maps[RTL_IMR_BDOK] = IMR_BDOK,
346	.maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
347	.maps[RTL_IMR_TBDER] = IMR_TBDER,
348	.maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
349	.maps[RTL_IMR_COMDOK] = IMR_COMDOK,
350	.maps[RTL_IMR_TBDOK] = IMR_TBDOK,
351	.maps[RTL_IMR_BKDOK] = IMR_BKDOK,
352	.maps[RTL_IMR_BEDOK] = IMR_BEDOK,
353	.maps[RTL_IMR_VIDOK] = IMR_VIDOK,
354	.maps[RTL_IMR_VODOK] = IMR_VODOK,
355	.maps[RTL_IMR_ROK] = IMR_ROK,
356	.maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
357
358	.maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M,
359	.maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M,
360	.maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M,
361	.maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M,
362	.maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M,
363	.maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M,
364	.maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M,
365	.maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M,
366	.maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M,
367	.maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M,
368	.maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M,
369	.maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M,
370
371	.maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7,
372	.maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15,
373};
374
375static const struct pci_device_id rtl92se_pci_ids[] = {
376	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8192, rtl92se_hal_cfg)},
377	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8171, rtl92se_hal_cfg)},
378	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8172, rtl92se_hal_cfg)},
379	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8173, rtl92se_hal_cfg)},
380	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8174, rtl92se_hal_cfg)},
381	{},
382};
383
384MODULE_DEVICE_TABLE(pci, rtl92se_pci_ids);
385
386MODULE_AUTHOR("lizhaoming	<chaoming_li@realsil.com.cn>");
387MODULE_AUTHOR("Realtek WlanFAE	<wlanfae@realtek.com>");
388MODULE_AUTHOR("Larry Finger	<Larry.Finger@lwfinger.net>");
389MODULE_LICENSE("GPL");
390MODULE_DESCRIPTION("Realtek 8192S/8191S 802.11n PCI wireless");
391MODULE_FIRMWARE("rtlwifi/rtl8192sefw.bin");
392
393module_param_named(swenc, rtl92se_mod_params.sw_crypto, bool, 0444);
394module_param_named(debug_level, rtl92se_mod_params.debug_level, int, 0644);
395module_param_named(debug_mask, rtl92se_mod_params.debug_mask, ullong, 0644);
396module_param_named(ips, rtl92se_mod_params.inactiveps, bool, 0444);
397module_param_named(swlps, rtl92se_mod_params.swctrl_lps, bool, 0444);
398module_param_named(fwlps, rtl92se_mod_params.fwctrl_lps, bool, 0444);
399module_param_named(aspm, rtl92se_mod_params.aspm_support, int, 0444);
400MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
401MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
402MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 1)\n");
403MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 0)\n");
404MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");
405MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");
406MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
407
408static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
409
410static struct pci_driver rtl92se_driver = {
411	.name = KBUILD_MODNAME,
412	.id_table = rtl92se_pci_ids,
413	.probe = rtl_pci_probe,
414	.remove = rtl_pci_disconnect,
415	.driver.pm = &rtlwifi_pm_ops,
416};
417
418module_pci_driver(rtl92se_driver);