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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * DW100 Hardware dewarper
4 *
5 * Copyright 2022 NXP
6 * Author: Xavier Roumegue (xavier.roumegue@oss.nxp.com)
7 *
8 */
9
10#include <linux/clk.h>
11#include <linux/debugfs.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/minmax.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19
20#include <media/v4l2-ctrls.h>
21#include <media/v4l2-device.h>
22#include <media/v4l2-event.h>
23#include <media/v4l2-ioctl.h>
24#include <media/v4l2-mem2mem.h>
25#include <media/videobuf2-dma-contig.h>
26
27#include <uapi/linux/dw100.h>
28
29#include "dw100_regs.h"
30
31#define DRV_NAME "dw100"
32
33#define DW100_MIN_W 176u
34#define DW100_MIN_H 144u
35#define DW100_MAX_W 4096u
36#define DW100_MAX_H 3072u
37#define DW100_ALIGN_W 3
38#define DW100_ALIGN_H 3
39
40#define DW100_BLOCK_SIZE 16
41
42#define DW100_DEF_W 640u
43#define DW100_DEF_H 480u
44#define DW100_DEF_LUT_W (DIV_ROUND_UP(DW100_DEF_W, DW100_BLOCK_SIZE) + 1)
45#define DW100_DEF_LUT_H (DIV_ROUND_UP(DW100_DEF_H, DW100_BLOCK_SIZE) + 1)
46
47/*
48 * 16 controls have been reserved for this driver for future extension, but
49 * let's limit the related driver allocation to the effective number of controls
50 * in use.
51 */
52#define DW100_MAX_CTRLS 1
53#define DW100_CTRL_DEWARPING_MAP 0
54
55enum {
56 DW100_QUEUE_SRC = 0,
57 DW100_QUEUE_DST = 1,
58};
59
60enum {
61 DW100_FMT_CAPTURE = BIT(0),
62 DW100_FMT_OUTPUT = BIT(1),
63};
64
65struct dw100_device {
66 struct platform_device *pdev;
67 struct v4l2_m2m_dev *m2m_dev;
68 struct v4l2_device v4l2_dev;
69 struct video_device vfd;
70 struct media_device mdev;
71 /* Video device lock */
72 struct mutex vfd_mutex;
73 void __iomem *mmio;
74 struct clk_bulk_data *clks;
75 int num_clks;
76 struct dentry *debugfs_root;
77};
78
79struct dw100_q_data {
80 struct v4l2_pix_format_mplane pix_fmt;
81 unsigned int sequence;
82 const struct dw100_fmt *fmt;
83 struct v4l2_rect crop;
84};
85
86struct dw100_ctx {
87 struct v4l2_fh fh;
88 struct dw100_device *dw_dev;
89 struct v4l2_ctrl_handler hdl;
90 struct v4l2_ctrl *ctrls[DW100_MAX_CTRLS];
91 /* per context m2m queue lock */
92 struct mutex vq_mutex;
93
94 /* Look Up Table for pixel remapping */
95 unsigned int *map;
96 dma_addr_t map_dma;
97 size_t map_size;
98 unsigned int map_width;
99 unsigned int map_height;
100 bool user_map_is_set;
101
102 /* Source and destination queue data */
103 struct dw100_q_data q_data[2];
104};
105
106static const struct v4l2_frmsize_stepwise dw100_frmsize_stepwise = {
107 .min_width = DW100_MIN_W,
108 .min_height = DW100_MIN_H,
109 .max_width = DW100_MAX_W,
110 .max_height = DW100_MAX_H,
111 .step_width = 1UL << DW100_ALIGN_W,
112 .step_height = 1UL << DW100_ALIGN_H,
113};
114
115static const struct dw100_fmt {
116 u32 fourcc;
117 u32 types;
118 u32 reg_format;
119 bool reg_swap_uv;
120} formats[] = {
121 {
122 .fourcc = V4L2_PIX_FMT_NV16,
123 .types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE,
124 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP,
125 .reg_swap_uv = false,
126 }, {
127 .fourcc = V4L2_PIX_FMT_NV16M,
128 .types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE,
129 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP,
130 .reg_swap_uv = false,
131 }, {
132 .fourcc = V4L2_PIX_FMT_NV61,
133 .types = DW100_FMT_CAPTURE,
134 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP,
135 .reg_swap_uv = true,
136 }, {
137 .fourcc = V4L2_PIX_FMT_NV61M,
138 .types = DW100_FMT_CAPTURE,
139 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP,
140 .reg_swap_uv = true,
141 }, {
142 .fourcc = V4L2_PIX_FMT_YUYV,
143 .types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE,
144 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED,
145 .reg_swap_uv = false,
146 }, {
147 .fourcc = V4L2_PIX_FMT_UYVY,
148 .types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE,
149 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED,
150 .reg_swap_uv = true,
151 }, {
152 .fourcc = V4L2_PIX_FMT_NV12,
153 .types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE,
154 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP,
155 .reg_swap_uv = false,
156 }, {
157 .fourcc = V4L2_PIX_FMT_NV12M,
158 .types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE,
159 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP,
160 .reg_swap_uv = false,
161 }, {
162 .fourcc = V4L2_PIX_FMT_NV21,
163 .types = DW100_FMT_CAPTURE,
164 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP,
165 .reg_swap_uv = true,
166 }, {
167 .fourcc = V4L2_PIX_FMT_NV21M,
168 .types = DW100_FMT_CAPTURE,
169 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP,
170 .reg_swap_uv = true,
171 },
172};
173
174static inline int to_dw100_fmt_type(enum v4l2_buf_type type)
175{
176 if (V4L2_TYPE_IS_OUTPUT(type))
177 return DW100_FMT_OUTPUT;
178 else
179 return DW100_FMT_CAPTURE;
180}
181
182static const struct dw100_fmt *dw100_find_pixel_format(u32 pixel_format,
183 int fmt_type)
184{
185 unsigned int i;
186
187 for (i = 0; i < ARRAY_SIZE(formats); i++) {
188 const struct dw100_fmt *fmt = &formats[i];
189
190 if (fmt->fourcc == pixel_format && fmt->types & fmt_type)
191 return fmt;
192 }
193
194 return NULL;
195}
196
197static const struct dw100_fmt *dw100_find_format(struct v4l2_format *f)
198{
199 return dw100_find_pixel_format(f->fmt.pix_mp.pixelformat,
200 to_dw100_fmt_type(f->type));
201}
202
203static inline u32 dw100_read(struct dw100_device *dw_dev, u32 reg)
204{
205 return readl(dw_dev->mmio + reg);
206}
207
208static inline void dw100_write(struct dw100_device *dw_dev, u32 reg, u32 val)
209{
210 writel(val, dw_dev->mmio + reg);
211}
212
213static inline int dw100_dump_regs(struct seq_file *m)
214{
215 struct dw100_device *dw_dev = m->private;
216#define __DECLARE_REG(x) { #x, x }
217 unsigned int i;
218 static const struct reg_desc {
219 const char * const name;
220 unsigned int addr;
221 } dw100_regs[] = {
222 __DECLARE_REG(DW100_DEWARP_ID),
223 __DECLARE_REG(DW100_DEWARP_CTRL),
224 __DECLARE_REG(DW100_MAP_LUT_ADDR),
225 __DECLARE_REG(DW100_MAP_LUT_SIZE),
226 __DECLARE_REG(DW100_MAP_LUT_ADDR2),
227 __DECLARE_REG(DW100_MAP_LUT_SIZE2),
228 __DECLARE_REG(DW100_SRC_IMG_Y_BASE),
229 __DECLARE_REG(DW100_SRC_IMG_UV_BASE),
230 __DECLARE_REG(DW100_SRC_IMG_SIZE),
231 __DECLARE_REG(DW100_SRC_IMG_STRIDE),
232 __DECLARE_REG(DW100_DST_IMG_Y_BASE),
233 __DECLARE_REG(DW100_DST_IMG_UV_BASE),
234 __DECLARE_REG(DW100_DST_IMG_SIZE),
235 __DECLARE_REG(DW100_DST_IMG_STRIDE),
236 __DECLARE_REG(DW100_DST_IMG_Y_SIZE1),
237 __DECLARE_REG(DW100_DST_IMG_UV_SIZE1),
238 __DECLARE_REG(DW100_SRC_IMG_Y_BASE2),
239 __DECLARE_REG(DW100_SRC_IMG_UV_BASE2),
240 __DECLARE_REG(DW100_SRC_IMG_SIZE2),
241 __DECLARE_REG(DW100_SRC_IMG_STRIDE2),
242 __DECLARE_REG(DW100_DST_IMG_Y_BASE2),
243 __DECLARE_REG(DW100_DST_IMG_UV_BASE2),
244 __DECLARE_REG(DW100_DST_IMG_SIZE2),
245 __DECLARE_REG(DW100_DST_IMG_STRIDE2),
246 __DECLARE_REG(DW100_DST_IMG_Y_SIZE2),
247 __DECLARE_REG(DW100_DST_IMG_UV_SIZE2),
248 __DECLARE_REG(DW100_SWAP_CONTROL),
249 __DECLARE_REG(DW100_VERTICAL_SPLIT_LINE),
250 __DECLARE_REG(DW100_HORIZON_SPLIT_LINE),
251 __DECLARE_REG(DW100_SCALE_FACTOR),
252 __DECLARE_REG(DW100_ROI_START),
253 __DECLARE_REG(DW100_BOUNDARY_PIXEL),
254 __DECLARE_REG(DW100_INTERRUPT_STATUS),
255 __DECLARE_REG(DW100_BUS_CTRL),
256 __DECLARE_REG(DW100_BUS_CTRL1),
257 __DECLARE_REG(DW100_BUS_TIME_OUT_CYCLE),
258 };
259
260 for (i = 0; i < ARRAY_SIZE(dw100_regs); i++)
261 seq_printf(m, "%s: %#x\n", dw100_regs[i].name,
262 dw100_read(dw_dev, dw100_regs[i].addr));
263
264 return 0;
265}
266
267static inline struct dw100_ctx *dw100_file2ctx(struct file *file)
268{
269 return container_of(file->private_data, struct dw100_ctx, fh);
270}
271
272static struct dw100_q_data *dw100_get_q_data(struct dw100_ctx *ctx,
273 enum v4l2_buf_type type)
274{
275 if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
276 return &ctx->q_data[DW100_QUEUE_SRC];
277 else
278 return &ctx->q_data[DW100_QUEUE_DST];
279}
280
281static u32 dw100_get_n_vertices_from_length(u32 length)
282{
283 return DIV_ROUND_UP(length, DW100_BLOCK_SIZE) + 1;
284}
285
286static u16 dw100_map_convert_to_uq12_4(u32 a)
287{
288 return (u16)((a & 0xfff) << 4);
289}
290
291static u32 dw100_map_format_coordinates(u16 xq, u16 yq)
292{
293 return (u32)((yq << 16) | xq);
294}
295
296static u32 *dw100_get_user_map(struct dw100_ctx *ctx)
297{
298 struct v4l2_ctrl *ctrl = ctx->ctrls[DW100_CTRL_DEWARPING_MAP];
299
300 return ctrl->p_cur.p_u32;
301}
302
303/*
304 * Create the dewarp map used by the hardware from the V4L2 control values which
305 * have been initialized with an identity map or set by the application.
306 */
307static int dw100_create_mapping(struct dw100_ctx *ctx)
308{
309 u32 *user_map;
310
311 if (ctx->map)
312 dma_free_coherent(&ctx->dw_dev->pdev->dev, ctx->map_size,
313 ctx->map, ctx->map_dma);
314
315 ctx->map = dma_alloc_coherent(&ctx->dw_dev->pdev->dev, ctx->map_size,
316 &ctx->map_dma, GFP_KERNEL);
317
318 if (!ctx->map)
319 return -ENOMEM;
320
321 user_map = dw100_get_user_map(ctx);
322 memcpy(ctx->map, user_map, ctx->map_size);
323
324 dev_dbg(&ctx->dw_dev->pdev->dev,
325 "%ux%u %s mapping created (d:%pad-c:%p) for stream %ux%u->%ux%u\n",
326 ctx->map_width, ctx->map_height,
327 ctx->user_map_is_set ? "user" : "identity",
328 &ctx->map_dma, ctx->map,
329 ctx->q_data[DW100_QUEUE_SRC].pix_fmt.width,
330 ctx->q_data[DW100_QUEUE_DST].pix_fmt.height,
331 ctx->q_data[DW100_QUEUE_SRC].pix_fmt.width,
332 ctx->q_data[DW100_QUEUE_DST].pix_fmt.height);
333
334 return 0;
335}
336
337static void dw100_destroy_mapping(struct dw100_ctx *ctx)
338{
339 if (ctx->map) {
340 dma_free_coherent(&ctx->dw_dev->pdev->dev, ctx->map_size,
341 ctx->map, ctx->map_dma);
342 ctx->map = NULL;
343 }
344}
345
346static int dw100_s_ctrl(struct v4l2_ctrl *ctrl)
347{
348 struct dw100_ctx *ctx =
349 container_of(ctrl->handler, struct dw100_ctx, hdl);
350
351 switch (ctrl->id) {
352 case V4L2_CID_DW100_DEWARPING_16x16_VERTEX_MAP:
353 ctx->user_map_is_set = true;
354 break;
355 }
356
357 return 0;
358}
359
360static const struct v4l2_ctrl_ops dw100_ctrl_ops = {
361 .s_ctrl = dw100_s_ctrl,
362};
363
364/*
365 * Initialize the dewarping map with an identity mapping.
366 *
367 * A 16 pixels cell size grid is mapped on the destination image.
368 * The last cells width/height might be lesser than 16 if the destination image
369 * width/height is not divisible by 16. This dewarping grid map specifies the
370 * source image pixel location (x, y) on each grid intersection point.
371 * Bilinear interpolation is used to compute inner cell points locations.
372 *
373 * The coordinates are saved in UQ12.4 fixed point format.
374 */
375static void dw100_ctrl_dewarping_map_init(const struct v4l2_ctrl *ctrl,
376 u32 from_idx,
377 union v4l2_ctrl_ptr ptr)
378{
379 struct dw100_ctx *ctx =
380 container_of(ctrl->handler, struct dw100_ctx, hdl);
381
382 u32 sw, sh, mw, mh, idx;
383 u16 qx, qy, qdx, qdy, qsh, qsw;
384 u32 *map = ctrl->p_cur.p_u32;
385
386 sw = ctx->q_data[DW100_QUEUE_SRC].pix_fmt.width;
387 sh = ctx->q_data[DW100_QUEUE_SRC].pix_fmt.height;
388
389 mw = ctrl->dims[0];
390 mh = ctrl->dims[1];
391
392 qsw = dw100_map_convert_to_uq12_4(sw);
393 qsh = dw100_map_convert_to_uq12_4(sh);
394 qdx = qsw / (mw - 1);
395 qdy = qsh / (mh - 1);
396
397 ctx->map_width = mw;
398 ctx->map_height = mh;
399 ctx->map_size = mh * mw * sizeof(u32);
400
401 for (idx = from_idx; idx < ctrl->elems; idx++) {
402 qy = min_t(u32, (idx / mw) * qdy, qsh);
403 qx = min_t(u32, (idx % mw) * qdx, qsw);
404 map[idx] = dw100_map_format_coordinates(qx, qy);
405 }
406
407 ctx->user_map_is_set = false;
408}
409
410static const struct v4l2_ctrl_type_ops dw100_ctrl_type_ops = {
411 .init = dw100_ctrl_dewarping_map_init,
412 .validate = v4l2_ctrl_type_op_validate,
413 .log = v4l2_ctrl_type_op_log,
414 .equal = v4l2_ctrl_type_op_equal,
415};
416
417static const struct v4l2_ctrl_config controls[] = {
418 [DW100_CTRL_DEWARPING_MAP] = {
419 .ops = &dw100_ctrl_ops,
420 .type_ops = &dw100_ctrl_type_ops,
421 .id = V4L2_CID_DW100_DEWARPING_16x16_VERTEX_MAP,
422 .name = "Dewarping Vertex Map",
423 .type = V4L2_CTRL_TYPE_U32,
424 .min = 0x00000000,
425 .max = 0xffffffff,
426 .step = 1,
427 .def = 0,
428 .dims = { DW100_DEF_LUT_W, DW100_DEF_LUT_H },
429 },
430};
431
432static int dw100_queue_setup(struct vb2_queue *vq,
433 unsigned int *nbuffers, unsigned int *nplanes,
434 unsigned int sizes[], struct device *alloc_devs[])
435{
436 struct dw100_ctx *ctx = vb2_get_drv_priv(vq);
437 const struct v4l2_pix_format_mplane *format;
438 unsigned int i;
439
440 format = &dw100_get_q_data(ctx, vq->type)->pix_fmt;
441
442 if (*nplanes) {
443 if (*nplanes != format->num_planes)
444 return -EINVAL;
445
446 for (i = 0; i < *nplanes; ++i) {
447 if (sizes[i] < format->plane_fmt[i].sizeimage)
448 return -EINVAL;
449 }
450
451 return 0;
452 }
453
454 *nplanes = format->num_planes;
455
456 for (i = 0; i < format->num_planes; ++i)
457 sizes[i] = format->plane_fmt[i].sizeimage;
458
459 return 0;
460}
461
462static int dw100_buf_prepare(struct vb2_buffer *vb)
463{
464 unsigned int i;
465 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
466 struct dw100_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
467 struct dw100_device *dw_dev = ctx->dw_dev;
468 const struct v4l2_pix_format_mplane *pix_fmt =
469 &dw100_get_q_data(ctx, vb->vb2_queue->type)->pix_fmt;
470
471 if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {
472 if (vbuf->field != V4L2_FIELD_NONE) {
473 dev_dbg(&dw_dev->pdev->dev, "%x field isn't supported\n",
474 vbuf->field);
475 return -EINVAL;
476 }
477 }
478
479 for (i = 0; i < pix_fmt->num_planes; i++) {
480 unsigned long size = pix_fmt->plane_fmt[i].sizeimage;
481
482 if (vb2_plane_size(vb, i) < size) {
483 dev_dbg(&dw_dev->pdev->dev,
484 "User buffer too small (%lu < %lu)\n",
485 vb2_plane_size(vb, i), size);
486 return -EINVAL;
487 }
488
489 vb2_set_plane_payload(vb, i, size);
490 }
491
492 return 0;
493}
494
495static void dw100_buf_queue(struct vb2_buffer *vb)
496{
497 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
498 struct dw100_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
499
500 v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
501}
502
503static void dw100_return_all_buffers(struct vb2_queue *q,
504 enum vb2_buffer_state state)
505{
506 struct dw100_ctx *ctx = vb2_get_drv_priv(q);
507 struct vb2_v4l2_buffer *vbuf;
508
509 for (;;) {
510 if (V4L2_TYPE_IS_OUTPUT(q->type))
511 vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
512 else
513 vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
514 if (!vbuf)
515 return;
516 v4l2_m2m_buf_done(vbuf, state);
517 }
518}
519
520static int dw100_start_streaming(struct vb2_queue *q, unsigned int count)
521{
522 struct dw100_ctx *ctx = vb2_get_drv_priv(q);
523 struct dw100_q_data *q_data = dw100_get_q_data(ctx, q->type);
524 int ret;
525
526 q_data->sequence = 0;
527
528 ret = dw100_create_mapping(ctx);
529 if (ret)
530 goto err;
531
532 ret = pm_runtime_resume_and_get(&ctx->dw_dev->pdev->dev);
533 if (ret) {
534 dw100_destroy_mapping(ctx);
535 goto err;
536 }
537
538 return 0;
539err:
540 dw100_return_all_buffers(q, VB2_BUF_STATE_QUEUED);
541 return ret;
542}
543
544static void dw100_stop_streaming(struct vb2_queue *q)
545{
546 struct dw100_ctx *ctx = vb2_get_drv_priv(q);
547
548 dw100_return_all_buffers(q, VB2_BUF_STATE_ERROR);
549
550 pm_runtime_put_sync(&ctx->dw_dev->pdev->dev);
551
552 dw100_destroy_mapping(ctx);
553}
554
555static const struct vb2_ops dw100_qops = {
556 .queue_setup = dw100_queue_setup,
557 .buf_prepare = dw100_buf_prepare,
558 .buf_queue = dw100_buf_queue,
559 .start_streaming = dw100_start_streaming,
560 .stop_streaming = dw100_stop_streaming,
561};
562
563static int dw100_m2m_queue_init(void *priv, struct vb2_queue *src_vq,
564 struct vb2_queue *dst_vq)
565{
566 struct dw100_ctx *ctx = priv;
567 int ret;
568
569 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
570 src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
571 src_vq->drv_priv = ctx;
572 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
573 src_vq->ops = &dw100_qops;
574 src_vq->mem_ops = &vb2_dma_contig_memops;
575 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
576 src_vq->lock = &ctx->vq_mutex;
577 src_vq->dev = ctx->dw_dev->v4l2_dev.dev;
578
579 ret = vb2_queue_init(src_vq);
580 if (ret)
581 return ret;
582
583 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
584 dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
585 dst_vq->drv_priv = ctx;
586 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
587 dst_vq->ops = &dw100_qops;
588 dst_vq->mem_ops = &vb2_dma_contig_memops;
589 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
590 dst_vq->lock = &ctx->vq_mutex;
591 dst_vq->dev = ctx->dw_dev->v4l2_dev.dev;
592
593 return vb2_queue_init(dst_vq);
594}
595
596static int dw100_open(struct file *file)
597{
598 struct dw100_device *dw_dev = video_drvdata(file);
599 struct dw100_ctx *ctx;
600 struct v4l2_ctrl_handler *hdl;
601 struct v4l2_pix_format_mplane *pix_fmt;
602 int ret, i;
603
604 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
605 if (!ctx)
606 return -ENOMEM;
607
608 mutex_init(&ctx->vq_mutex);
609 v4l2_fh_init(&ctx->fh, video_devdata(file));
610 file->private_data = &ctx->fh;
611 ctx->dw_dev = dw_dev;
612
613 ctx->q_data[DW100_QUEUE_SRC].fmt = &formats[0];
614
615 pix_fmt = &ctx->q_data[DW100_QUEUE_SRC].pix_fmt;
616 pix_fmt->field = V4L2_FIELD_NONE;
617 pix_fmt->colorspace = V4L2_COLORSPACE_REC709;
618 pix_fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(pix_fmt->colorspace);
619 pix_fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(pix_fmt->colorspace);
620 pix_fmt->quantization =
621 V4L2_MAP_QUANTIZATION_DEFAULT(false, pix_fmt->colorspace,
622 pix_fmt->ycbcr_enc);
623
624 v4l2_fill_pixfmt_mp(pix_fmt, formats[0].fourcc, DW100_DEF_W, DW100_DEF_H);
625
626 ctx->q_data[DW100_QUEUE_SRC].crop.top = 0;
627 ctx->q_data[DW100_QUEUE_SRC].crop.left = 0;
628 ctx->q_data[DW100_QUEUE_SRC].crop.width = DW100_DEF_W;
629 ctx->q_data[DW100_QUEUE_SRC].crop.height = DW100_DEF_H;
630
631 ctx->q_data[DW100_QUEUE_DST] = ctx->q_data[DW100_QUEUE_SRC];
632
633 hdl = &ctx->hdl;
634 v4l2_ctrl_handler_init(hdl, ARRAY_SIZE(controls));
635 for (i = 0; i < ARRAY_SIZE(controls); i++) {
636 ctx->ctrls[i] = v4l2_ctrl_new_custom(hdl, &controls[i], NULL);
637 if (hdl->error) {
638 dev_err(&ctx->dw_dev->pdev->dev,
639 "Adding control (%d) failed\n", i);
640 ret = hdl->error;
641 goto err;
642 }
643 }
644 ctx->fh.ctrl_handler = hdl;
645
646 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dw_dev->m2m_dev,
647 ctx, &dw100_m2m_queue_init);
648
649 if (IS_ERR(ctx->fh.m2m_ctx)) {
650 ret = PTR_ERR(ctx->fh.m2m_ctx);
651 goto err;
652 }
653
654 v4l2_fh_add(&ctx->fh);
655
656 return 0;
657
658err:
659 v4l2_ctrl_handler_free(hdl);
660 v4l2_fh_exit(&ctx->fh);
661 mutex_destroy(&ctx->vq_mutex);
662 kfree(ctx);
663
664 return ret;
665}
666
667static int dw100_release(struct file *file)
668{
669 struct dw100_ctx *ctx = dw100_file2ctx(file);
670
671 v4l2_fh_del(&ctx->fh);
672 v4l2_fh_exit(&ctx->fh);
673 v4l2_ctrl_handler_free(&ctx->hdl);
674 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
675 mutex_destroy(&ctx->vq_mutex);
676 kfree(ctx);
677
678 return 0;
679}
680
681static const struct v4l2_file_operations dw100_fops = {
682 .owner = THIS_MODULE,
683 .open = dw100_open,
684 .release = dw100_release,
685 .poll = v4l2_m2m_fop_poll,
686 .unlocked_ioctl = video_ioctl2,
687 .mmap = v4l2_m2m_fop_mmap,
688};
689
690static int dw100_querycap(struct file *file, void *priv,
691 struct v4l2_capability *cap)
692{
693 strscpy(cap->driver, DRV_NAME, sizeof(cap->driver));
694 strscpy(cap->card, "DW100 dewarper", sizeof(cap->card));
695
696 return 0;
697}
698
699static int dw100_enum_fmt_vid(struct file *file, void *priv,
700 struct v4l2_fmtdesc *f)
701{
702 int i, num = 0;
703
704 for (i = 0; i < ARRAY_SIZE(formats); i++) {
705 if (formats[i].types & to_dw100_fmt_type(f->type)) {
706 if (num == f->index) {
707 f->pixelformat = formats[i].fourcc;
708 return 0;
709 }
710 ++num;
711 }
712 }
713
714 return -EINVAL;
715}
716
717static int dw100_enum_framesizes(struct file *file, void *priv,
718 struct v4l2_frmsizeenum *fsize)
719{
720 const struct dw100_fmt *fmt;
721
722 if (fsize->index)
723 return -EINVAL;
724
725 fmt = dw100_find_pixel_format(fsize->pixel_format,
726 DW100_FMT_OUTPUT | DW100_FMT_CAPTURE);
727 if (!fmt)
728 return -EINVAL;
729
730 fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
731 fsize->stepwise = dw100_frmsize_stepwise;
732
733 return 0;
734}
735
736static int dw100_g_fmt_vid(struct file *file, void *priv, struct v4l2_format *f)
737{
738 struct dw100_ctx *ctx = dw100_file2ctx(file);
739 struct vb2_queue *vq;
740 struct dw100_q_data *q_data;
741
742 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
743 if (!vq)
744 return -EINVAL;
745
746 q_data = dw100_get_q_data(ctx, f->type);
747
748 f->fmt.pix_mp = q_data->pix_fmt;
749
750 return 0;
751}
752
753static int dw100_try_fmt(struct file *file, struct v4l2_format *f)
754{
755 struct dw100_ctx *ctx = dw100_file2ctx(file);
756 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
757 const struct dw100_fmt *fmt;
758
759 fmt = dw100_find_format(f);
760 if (!fmt) {
761 fmt = &formats[0];
762 pix->pixelformat = fmt->fourcc;
763 }
764
765 v4l2_apply_frmsize_constraints(&pix->width, &pix->height,
766 &dw100_frmsize_stepwise);
767
768 v4l2_fill_pixfmt_mp(pix, fmt->fourcc, pix->width, pix->height);
769
770 pix->field = V4L2_FIELD_NONE;
771
772 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
773 if (pix->colorspace == V4L2_COLORSPACE_DEFAULT)
774 pix->colorspace = V4L2_COLORSPACE_REC709;
775 if (pix->xfer_func == V4L2_XFER_FUNC_DEFAULT)
776 pix->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(pix->colorspace);
777 if (pix->ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT)
778 pix->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(pix->colorspace);
779 if (pix->quantization == V4L2_QUANTIZATION_DEFAULT)
780 pix->quantization =
781 V4L2_MAP_QUANTIZATION_DEFAULT(false,
782 pix->colorspace,
783 pix->ycbcr_enc);
784 } else {
785 /*
786 * The DW100 can't perform colorspace conversion, the colorspace
787 * on the capture queue must be identical to the output queue.
788 */
789 const struct dw100_q_data *q_data =
790 dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
791
792 pix->colorspace = q_data->pix_fmt.colorspace;
793 pix->xfer_func = q_data->pix_fmt.xfer_func;
794 pix->ycbcr_enc = q_data->pix_fmt.ycbcr_enc;
795 pix->quantization = q_data->pix_fmt.quantization;
796 }
797
798 return 0;
799}
800
801static int dw100_s_fmt(struct dw100_ctx *ctx, struct v4l2_format *f)
802{
803 struct dw100_q_data *q_data;
804 struct vb2_queue *vq;
805
806 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
807 if (!vq)
808 return -EINVAL;
809
810 q_data = dw100_get_q_data(ctx, f->type);
811 if (!q_data)
812 return -EINVAL;
813
814 if (vb2_is_busy(vq)) {
815 dev_dbg(&ctx->dw_dev->pdev->dev, "%s queue busy\n", __func__);
816 return -EBUSY;
817 }
818
819 q_data->fmt = dw100_find_format(f);
820 q_data->pix_fmt = f->fmt.pix_mp;
821 q_data->crop.top = 0;
822 q_data->crop.left = 0;
823 q_data->crop.width = f->fmt.pix_mp.width;
824 q_data->crop.height = f->fmt.pix_mp.height;
825
826 /* Propagate buffers encoding */
827
828 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
829 struct dw100_q_data *dst_q_data =
830 dw100_get_q_data(ctx,
831 V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
832
833 dst_q_data->pix_fmt.colorspace = q_data->pix_fmt.colorspace;
834 dst_q_data->pix_fmt.ycbcr_enc = q_data->pix_fmt.ycbcr_enc;
835 dst_q_data->pix_fmt.quantization = q_data->pix_fmt.quantization;
836 dst_q_data->pix_fmt.xfer_func = q_data->pix_fmt.xfer_func;
837 }
838
839 dev_dbg(&ctx->dw_dev->pdev->dev,
840 "Setting format for type %u, wxh: %ux%u, fmt: %p4cc\n",
841 f->type, q_data->pix_fmt.width, q_data->pix_fmt.height,
842 &q_data->pix_fmt.pixelformat);
843
844 if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
845 int ret;
846 u32 dims[V4L2_CTRL_MAX_DIMS] = {};
847 struct v4l2_ctrl *ctrl = ctx->ctrls[DW100_CTRL_DEWARPING_MAP];
848
849 dims[0] = dw100_get_n_vertices_from_length(q_data->pix_fmt.width);
850 dims[1] = dw100_get_n_vertices_from_length(q_data->pix_fmt.height);
851
852 ret = v4l2_ctrl_modify_dimensions(ctrl, dims);
853
854 if (ret) {
855 dev_err(&ctx->dw_dev->pdev->dev,
856 "Modifying LUT dimensions failed with error %d\n",
857 ret);
858 return ret;
859 }
860 }
861
862 return 0;
863}
864
865static int dw100_try_fmt_vid_cap(struct file *file, void *priv,
866 struct v4l2_format *f)
867{
868 if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
869 return -EINVAL;
870
871 return dw100_try_fmt(file, f);
872}
873
874static int dw100_s_fmt_vid_cap(struct file *file, void *priv,
875 struct v4l2_format *f)
876{
877 struct dw100_ctx *ctx = dw100_file2ctx(file);
878 int ret;
879
880 ret = dw100_try_fmt_vid_cap(file, priv, f);
881 if (ret)
882 return ret;
883
884 ret = dw100_s_fmt(ctx, f);
885 if (ret)
886 return ret;
887
888 return 0;
889}
890
891static int dw100_try_fmt_vid_out(struct file *file, void *priv,
892 struct v4l2_format *f)
893{
894 if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
895 return -EINVAL;
896
897 return dw100_try_fmt(file, f);
898}
899
900static int dw100_s_fmt_vid_out(struct file *file, void *priv,
901 struct v4l2_format *f)
902{
903 struct dw100_ctx *ctx = dw100_file2ctx(file);
904 int ret;
905
906 ret = dw100_try_fmt_vid_out(file, priv, f);
907 if (ret)
908 return ret;
909
910 ret = dw100_s_fmt(ctx, f);
911 if (ret)
912 return ret;
913
914 return 0;
915}
916
917static int dw100_g_selection(struct file *file, void *fh,
918 struct v4l2_selection *sel)
919{
920 struct dw100_ctx *ctx = dw100_file2ctx(file);
921 struct dw100_q_data *src_q_data;
922
923 if (sel->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
924 return -EINVAL;
925
926 src_q_data = dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
927
928 switch (sel->target) {
929 case V4L2_SEL_TGT_CROP_DEFAULT:
930 case V4L2_SEL_TGT_CROP_BOUNDS:
931 sel->r.top = 0;
932 sel->r.left = 0;
933 sel->r.width = src_q_data->pix_fmt.width;
934 sel->r.height = src_q_data->pix_fmt.height;
935 break;
936 case V4L2_SEL_TGT_CROP:
937 sel->r.top = src_q_data->crop.top;
938 sel->r.left = src_q_data->crop.left;
939 sel->r.width = src_q_data->crop.width;
940 sel->r.height = src_q_data->crop.height;
941 break;
942 default:
943 return -EINVAL;
944 }
945
946 return 0;
947}
948
949static int dw100_s_selection(struct file *file, void *fh,
950 struct v4l2_selection *sel)
951{
952 struct dw100_ctx *ctx = dw100_file2ctx(file);
953 struct dw100_q_data *src_q_data;
954 u32 qscalex, qscaley, qscale;
955 int x, y, w, h;
956 unsigned int wframe, hframe;
957
958 if (sel->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
959 return -EINVAL;
960
961 src_q_data = dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
962
963 dev_dbg(&ctx->dw_dev->pdev->dev,
964 ">>> Buffer Type: %u Target: %u Rect: %ux%u@%d.%d\n",
965 sel->type, sel->target,
966 sel->r.width, sel->r.height, sel->r.left, sel->r.top);
967
968 switch (sel->target) {
969 case V4L2_SEL_TGT_CROP:
970 wframe = src_q_data->pix_fmt.width;
971 hframe = src_q_data->pix_fmt.height;
972
973 sel->r.top = clamp_t(int, sel->r.top, 0, hframe - DW100_MIN_H);
974 sel->r.left = clamp_t(int, sel->r.left, 0, wframe - DW100_MIN_W);
975 sel->r.height =
976 clamp(sel->r.height, DW100_MIN_H, hframe - sel->r.top);
977 sel->r.width =
978 clamp(sel->r.width, DW100_MIN_W, wframe - sel->r.left);
979
980 /* UQ16.16 for float operations */
981 qscalex = (sel->r.width << 16) / wframe;
982 qscaley = (sel->r.height << 16) / hframe;
983 y = sel->r.top;
984 x = sel->r.left;
985 if (qscalex == qscaley) {
986 qscale = qscalex;
987 } else {
988 switch (sel->flags) {
989 case 0:
990 qscale = (qscalex + qscaley) / 2;
991 break;
992 case V4L2_SEL_FLAG_GE:
993 qscale = max(qscaley, qscalex);
994 break;
995 case V4L2_SEL_FLAG_LE:
996 qscale = min(qscaley, qscalex);
997 break;
998 case V4L2_SEL_FLAG_LE | V4L2_SEL_FLAG_GE:
999 return -ERANGE;
1000 default:
1001 return -EINVAL;
1002 }
1003 }
1004
1005 w = (u32)((((u64)wframe << 16) * qscale) >> 32);
1006 h = (u32)((((u64)hframe << 16) * qscale) >> 32);
1007 x = x + (sel->r.width - w) / 2;
1008 y = y + (sel->r.height - h) / 2;
1009 x = min(wframe - w, (unsigned int)max(0, x));
1010 y = min(hframe - h, (unsigned int)max(0, y));
1011
1012 sel->r.top = y;
1013 sel->r.left = x;
1014 sel->r.width = w;
1015 sel->r.height = h;
1016
1017 src_q_data->crop.top = sel->r.top;
1018 src_q_data->crop.left = sel->r.left;
1019 src_q_data->crop.width = sel->r.width;
1020 src_q_data->crop.height = sel->r.height;
1021 break;
1022
1023 default:
1024 return -EINVAL;
1025 }
1026
1027 dev_dbg(&ctx->dw_dev->pdev->dev,
1028 "<<< Buffer Type: %u Target: %u Rect: %ux%u@%d.%d\n",
1029 sel->type, sel->target,
1030 sel->r.width, sel->r.height, sel->r.left, sel->r.top);
1031
1032 return 0;
1033}
1034
1035static const struct v4l2_ioctl_ops dw100_ioctl_ops = {
1036 .vidioc_querycap = dw100_querycap,
1037
1038 .vidioc_enum_fmt_vid_cap = dw100_enum_fmt_vid,
1039 .vidioc_enum_framesizes = dw100_enum_framesizes,
1040 .vidioc_g_fmt_vid_cap_mplane = dw100_g_fmt_vid,
1041 .vidioc_try_fmt_vid_cap_mplane = dw100_try_fmt_vid_cap,
1042 .vidioc_s_fmt_vid_cap_mplane = dw100_s_fmt_vid_cap,
1043
1044 .vidioc_enum_fmt_vid_out = dw100_enum_fmt_vid,
1045 .vidioc_g_fmt_vid_out_mplane = dw100_g_fmt_vid,
1046 .vidioc_try_fmt_vid_out_mplane = dw100_try_fmt_vid_out,
1047 .vidioc_s_fmt_vid_out_mplane = dw100_s_fmt_vid_out,
1048
1049 .vidioc_g_selection = dw100_g_selection,
1050 .vidioc_s_selection = dw100_s_selection,
1051 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
1052 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
1053 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
1054 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
1055 .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
1056 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
1057 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
1058
1059 .vidioc_streamon = v4l2_m2m_ioctl_streamon,
1060 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
1061
1062 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1063 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1064};
1065
1066static void dw100_job_finish(struct dw100_device *dw_dev, bool with_error)
1067{
1068 struct dw100_ctx *curr_ctx;
1069 struct vb2_v4l2_buffer *src_vb, *dst_vb;
1070 enum vb2_buffer_state buf_state;
1071
1072 curr_ctx = v4l2_m2m_get_curr_priv(dw_dev->m2m_dev);
1073
1074 if (!curr_ctx) {
1075 dev_err(&dw_dev->pdev->dev,
1076 "Instance released before the end of transaction\n");
1077 return;
1078 }
1079
1080 src_vb = v4l2_m2m_src_buf_remove(curr_ctx->fh.m2m_ctx);
1081 dst_vb = v4l2_m2m_dst_buf_remove(curr_ctx->fh.m2m_ctx);
1082
1083 if (likely(!with_error))
1084 buf_state = VB2_BUF_STATE_DONE;
1085 else
1086 buf_state = VB2_BUF_STATE_ERROR;
1087
1088 v4l2_m2m_buf_done(src_vb, buf_state);
1089 v4l2_m2m_buf_done(dst_vb, buf_state);
1090
1091 dev_dbg(&dw_dev->pdev->dev, "Finishing transaction with%s error(s)\n",
1092 with_error ? "" : "out");
1093
1094 v4l2_m2m_job_finish(dw_dev->m2m_dev, curr_ctx->fh.m2m_ctx);
1095}
1096
1097static void dw100_hw_reset(struct dw100_device *dw_dev)
1098{
1099 u32 val;
1100
1101 val = dw100_read(dw_dev, DW100_DEWARP_CTRL);
1102 val |= DW100_DEWARP_CTRL_ENABLE;
1103 val |= DW100_DEWARP_CTRL_SOFT_RESET;
1104 dw100_write(dw_dev, DW100_DEWARP_CTRL, val);
1105 val &= ~DW100_DEWARP_CTRL_SOFT_RESET;
1106 dw100_write(dw_dev, DW100_DEWARP_CTRL, val);
1107}
1108
1109static void _dw100_hw_set_master_bus_enable(struct dw100_device *dw_dev,
1110 unsigned int enable)
1111{
1112 u32 val;
1113
1114 dev_dbg(&dw_dev->pdev->dev, "%sable master bus\n",
1115 enable ? "En" : "Dis");
1116
1117 val = dw100_read(dw_dev, DW100_BUS_CTRL);
1118
1119 if (enable)
1120 val |= DW100_BUS_CTRL_AXI_MASTER_ENABLE;
1121 else
1122 val &= ~DW100_BUS_CTRL_AXI_MASTER_ENABLE;
1123
1124 dw100_write(dw_dev, DW100_BUS_CTRL, val);
1125}
1126
1127static void dw100_hw_master_bus_enable(struct dw100_device *dw_dev)
1128{
1129 _dw100_hw_set_master_bus_enable(dw_dev, 1);
1130}
1131
1132static void dw100_hw_master_bus_disable(struct dw100_device *dw_dev)
1133{
1134 _dw100_hw_set_master_bus_enable(dw_dev, 0);
1135}
1136
1137static void dw100_hw_dewarp_start(struct dw100_device *dw_dev)
1138{
1139 u32 val;
1140
1141 val = dw100_read(dw_dev, DW100_DEWARP_CTRL);
1142
1143 dev_dbg(&dw_dev->pdev->dev, "Starting Hardware CTRL:0x%08x\n", val);
1144 dw100_write(dw_dev, DW100_DEWARP_CTRL, val | DW100_DEWARP_CTRL_START);
1145 dw100_write(dw_dev, DW100_DEWARP_CTRL, val);
1146}
1147
1148static void dw100_hw_init_ctrl(struct dw100_device *dw_dev)
1149{
1150 u32 val;
1151 /*
1152 * Input format YUV422_SP
1153 * Output format YUV422_SP
1154 * No hardware handshake (SW)
1155 * No automatic double src buffering (Single)
1156 * No automatic double dst buffering (Single)
1157 * No Black Line
1158 * Prefetch image pixel traversal
1159 */
1160
1161 val = DW100_DEWARP_CTRL_ENABLE
1162 /* Valid only for auto prefetch mode*/
1163 | DW100_DEWARP_CTRL_PREFETCH_THRESHOLD(32);
1164
1165 /*
1166 * Calculation mode required to support any scaling factor,
1167 * but x4 slower than traversal mode.
1168 *
1169 * DW100_DEWARP_CTRL_PREFETCH_MODE_TRAVERSAL
1170 * DW100_DEWARP_CTRL_PREFETCH_MODE_CALCULATION
1171 * DW100_DEWARP_CTRL_PREFETCH_MODE_AUTO
1172 *
1173 * TODO: Find heuristics requiring calculation mode
1174 */
1175 val |= DW100_DEWARP_CTRL_PREFETCH_MODE_CALCULATION;
1176
1177 dw100_write(dw_dev, DW100_DEWARP_CTRL, val);
1178}
1179
1180static void dw100_hw_set_pixel_boundary(struct dw100_device *dw_dev)
1181{
1182 u32 val;
1183
1184 val = DW100_BOUNDARY_PIXEL_V(128)
1185 | DW100_BOUNDARY_PIXEL_U(128)
1186 | DW100_BOUNDARY_PIXEL_Y(0);
1187
1188 dw100_write(dw_dev, DW100_BOUNDARY_PIXEL, val);
1189}
1190
1191static void dw100_hw_set_scale(struct dw100_device *dw_dev, u8 scale)
1192{
1193 dev_dbg(&dw_dev->pdev->dev, "Setting scale factor to %u\n", scale);
1194
1195 dw100_write(dw_dev, DW100_SCALE_FACTOR, scale);
1196}
1197
1198static void dw100_hw_set_roi(struct dw100_device *dw_dev, u32 x, u32 y)
1199{
1200 u32 val;
1201
1202 dev_dbg(&dw_dev->pdev->dev, "Setting ROI region to %u.%u\n", x, y);
1203
1204 val = DW100_ROI_START_X(x) | DW100_ROI_START_Y(y);
1205
1206 dw100_write(dw_dev, DW100_ROI_START, val);
1207}
1208
1209static void dw100_hw_set_src_crop(struct dw100_device *dw_dev,
1210 const struct dw100_q_data *src_q_data,
1211 const struct dw100_q_data *dst_q_data)
1212{
1213 const struct v4l2_rect *rect = &src_q_data->crop;
1214 u32 src_scale, qscale, left_scale, top_scale;
1215
1216 /* HW Scale is UQ1.7 encoded */
1217 src_scale = (rect->width << 7) / src_q_data->pix_fmt.width;
1218 dw100_hw_set_scale(dw_dev, src_scale);
1219
1220 qscale = (dst_q_data->pix_fmt.width << 7) / src_q_data->pix_fmt.width;
1221
1222 left_scale = ((rect->left << 7) * qscale) >> 14;
1223 top_scale = ((rect->top << 7) * qscale) >> 14;
1224
1225 dw100_hw_set_roi(dw_dev, left_scale, top_scale);
1226}
1227
1228static void dw100_hw_set_source(struct dw100_device *dw_dev,
1229 const struct dw100_q_data *q_data,
1230 struct vb2_buffer *buffer)
1231{
1232 u32 width, height, stride, fourcc, val;
1233 const struct dw100_fmt *fmt = q_data->fmt;
1234 dma_addr_t addr_y = vb2_dma_contig_plane_dma_addr(buffer, 0);
1235 dma_addr_t addr_uv;
1236
1237 width = q_data->pix_fmt.width;
1238 height = q_data->pix_fmt.height;
1239 stride = q_data->pix_fmt.plane_fmt[0].bytesperline;
1240 fourcc = q_data->fmt->fourcc;
1241
1242 if (q_data->pix_fmt.num_planes == 2)
1243 addr_uv = vb2_dma_contig_plane_dma_addr(buffer, 1);
1244 else
1245 addr_uv = addr_y + (stride * height);
1246
1247 dev_dbg(&dw_dev->pdev->dev,
1248 "Set HW source registers for %ux%u - stride %u, pixfmt: %p4cc, dma:%pad\n",
1249 width, height, stride, &fourcc, &addr_y);
1250
1251 /* Pixel Format */
1252 val = dw100_read(dw_dev, DW100_DEWARP_CTRL);
1253
1254 val &= ~DW100_DEWARP_CTRL_INPUT_FORMAT_MASK;
1255 val |= DW100_DEWARP_CTRL_INPUT_FORMAT(fmt->reg_format);
1256
1257 dw100_write(dw_dev, DW100_DEWARP_CTRL, val);
1258
1259 /* Swap */
1260 val = dw100_read(dw_dev, DW100_SWAP_CONTROL);
1261
1262 val &= ~DW100_SWAP_CONTROL_SRC_MASK;
1263 /*
1264 * Data swapping is performed only on Y plane for source image.
1265 */
1266 if (fmt->reg_swap_uv &&
1267 fmt->reg_format == DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED)
1268 val |= DW100_SWAP_CONTROL_SRC(DW100_SWAP_CONTROL_Y
1269 (DW100_SWAP_CONTROL_BYTE));
1270
1271 dw100_write(dw_dev, DW100_SWAP_CONTROL, val);
1272
1273 /* Image resolution */
1274 dw100_write(dw_dev, DW100_SRC_IMG_SIZE,
1275 DW100_IMG_SIZE_WIDTH(width) | DW100_IMG_SIZE_HEIGHT(height));
1276
1277 dw100_write(dw_dev, DW100_SRC_IMG_STRIDE, stride);
1278
1279 /* Buffers */
1280 dw100_write(dw_dev, DW100_SRC_IMG_Y_BASE, DW100_IMG_Y_BASE(addr_y));
1281 dw100_write(dw_dev, DW100_SRC_IMG_UV_BASE, DW100_IMG_UV_BASE(addr_uv));
1282}
1283
1284static void dw100_hw_set_destination(struct dw100_device *dw_dev,
1285 const struct dw100_q_data *q_data,
1286 const struct dw100_fmt *ifmt,
1287 struct vb2_buffer *buffer)
1288{
1289 u32 width, height, stride, fourcc, val, size_y, size_uv;
1290 const struct dw100_fmt *fmt = q_data->fmt;
1291 dma_addr_t addr_y, addr_uv;
1292
1293 width = q_data->pix_fmt.width;
1294 height = q_data->pix_fmt.height;
1295 stride = q_data->pix_fmt.plane_fmt[0].bytesperline;
1296 fourcc = fmt->fourcc;
1297
1298 addr_y = vb2_dma_contig_plane_dma_addr(buffer, 0);
1299 size_y = q_data->pix_fmt.plane_fmt[0].sizeimage;
1300
1301 if (q_data->pix_fmt.num_planes == 2) {
1302 addr_uv = vb2_dma_contig_plane_dma_addr(buffer, 1);
1303 size_uv = q_data->pix_fmt.plane_fmt[1].sizeimage;
1304 } else {
1305 addr_uv = addr_y + ALIGN(stride * height, 16);
1306 size_uv = size_y;
1307 if (fmt->reg_format == DW100_DEWARP_CTRL_FORMAT_YUV420_SP)
1308 size_uv /= 2;
1309 }
1310
1311 dev_dbg(&dw_dev->pdev->dev,
1312 "Set HW destination registers for %ux%u - stride %u, pixfmt: %p4cc, dma:%pad\n",
1313 width, height, stride, &fourcc, &addr_y);
1314
1315 /* Pixel Format */
1316 val = dw100_read(dw_dev, DW100_DEWARP_CTRL);
1317
1318 val &= ~DW100_DEWARP_CTRL_OUTPUT_FORMAT_MASK;
1319 val |= DW100_DEWARP_CTRL_OUTPUT_FORMAT(fmt->reg_format);
1320
1321 dw100_write(dw_dev, DW100_DEWARP_CTRL, val);
1322
1323 /* Swap */
1324 val = dw100_read(dw_dev, DW100_SWAP_CONTROL);
1325
1326 val &= ~DW100_SWAP_CONTROL_DST_MASK;
1327
1328 /*
1329 * Avoid to swap twice
1330 */
1331 if (fmt->reg_swap_uv ^
1332 (ifmt->reg_swap_uv && ifmt->reg_format !=
1333 DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED)) {
1334 if (fmt->reg_format == DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED)
1335 val |= DW100_SWAP_CONTROL_DST(DW100_SWAP_CONTROL_Y
1336 (DW100_SWAP_CONTROL_BYTE));
1337 else
1338 val |= DW100_SWAP_CONTROL_DST(DW100_SWAP_CONTROL_UV
1339 (DW100_SWAP_CONTROL_BYTE));
1340 }
1341
1342 dw100_write(dw_dev, DW100_SWAP_CONTROL, val);
1343
1344 /* Image resolution */
1345 dw100_write(dw_dev, DW100_DST_IMG_SIZE,
1346 DW100_IMG_SIZE_WIDTH(width) | DW100_IMG_SIZE_HEIGHT(height));
1347 dw100_write(dw_dev, DW100_DST_IMG_STRIDE, stride);
1348 dw100_write(dw_dev, DW100_DST_IMG_Y_BASE, DW100_IMG_Y_BASE(addr_y));
1349 dw100_write(dw_dev, DW100_DST_IMG_UV_BASE, DW100_IMG_UV_BASE(addr_uv));
1350 dw100_write(dw_dev, DW100_DST_IMG_Y_SIZE1, DW100_DST_IMG_Y_SIZE(size_y));
1351 dw100_write(dw_dev, DW100_DST_IMG_UV_SIZE1,
1352 DW100_DST_IMG_UV_SIZE(size_uv));
1353}
1354
1355static void dw100_hw_set_mapping(struct dw100_device *dw_dev, dma_addr_t addr,
1356 u32 width, u32 height)
1357{
1358 dev_dbg(&dw_dev->pdev->dev,
1359 "Set HW mapping registers for %ux%u addr:%pad",
1360 width, height, &addr);
1361
1362 dw100_write(dw_dev, DW100_MAP_LUT_ADDR, DW100_MAP_LUT_ADDR_ADDR(addr));
1363 dw100_write(dw_dev, DW100_MAP_LUT_SIZE, DW100_MAP_LUT_SIZE_WIDTH(width)
1364 | DW100_MAP_LUT_SIZE_HEIGHT(height));
1365}
1366
1367static void dw100_hw_clear_irq(struct dw100_device *dw_dev, unsigned int irq)
1368{
1369 dw100_write(dw_dev, DW100_INTERRUPT_STATUS,
1370 DW100_INTERRUPT_STATUS_INT_CLEAR(irq));
1371}
1372
1373static void dw100_hw_enable_irq(struct dw100_device *dw_dev)
1374{
1375 dw100_write(dw_dev, DW100_INTERRUPT_STATUS,
1376 DW100_INTERRUPT_STATUS_INT_ENABLE_MASK);
1377}
1378
1379static void dw100_hw_disable_irq(struct dw100_device *dw_dev)
1380{
1381 dw100_write(dw_dev, DW100_INTERRUPT_STATUS, 0);
1382}
1383
1384static u32 dw_hw_get_pending_irqs(struct dw100_device *dw_dev)
1385{
1386 u32 val;
1387
1388 val = dw100_read(dw_dev, DW100_INTERRUPT_STATUS);
1389
1390 return DW100_INTERRUPT_STATUS_INT_STATUS(val);
1391}
1392
1393static irqreturn_t dw100_irq_handler(int irq, void *dev_id)
1394{
1395 struct dw100_device *dw_dev = dev_id;
1396 u32 pending_irqs, err_irqs, frame_done_irq;
1397 bool with_error = true;
1398
1399 pending_irqs = dw_hw_get_pending_irqs(dw_dev);
1400 frame_done_irq = pending_irqs & DW100_INTERRUPT_STATUS_INT_FRAME_DONE;
1401 err_irqs = DW100_INTERRUPT_STATUS_INT_ERR_STATUS(pending_irqs);
1402
1403 if (frame_done_irq) {
1404 dev_dbg(&dw_dev->pdev->dev, "Frame done interrupt\n");
1405 with_error = false;
1406 err_irqs &= ~DW100_INTERRUPT_STATUS_INT_ERR_STATUS
1407 (DW100_INTERRUPT_STATUS_INT_ERR_FRAME_DONE);
1408 }
1409
1410 if (err_irqs)
1411 dev_err(&dw_dev->pdev->dev, "Interrupt error: %#x\n", err_irqs);
1412
1413 dw100_hw_disable_irq(dw_dev);
1414 dw100_hw_master_bus_disable(dw_dev);
1415 dw100_hw_clear_irq(dw_dev, pending_irqs |
1416 DW100_INTERRUPT_STATUS_INT_ERR_TIME_OUT);
1417
1418 dw100_job_finish(dw_dev, with_error);
1419
1420 return IRQ_HANDLED;
1421}
1422
1423static void dw100_start(struct dw100_ctx *ctx, struct vb2_v4l2_buffer *in_vb,
1424 struct vb2_v4l2_buffer *out_vb)
1425{
1426 struct dw100_device *dw_dev = ctx->dw_dev;
1427
1428 out_vb->sequence =
1429 dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)->sequence++;
1430 in_vb->sequence =
1431 dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)->sequence++;
1432
1433 dev_dbg(&ctx->dw_dev->pdev->dev,
1434 "Starting queues %p->%p, sequence %u->%u\n",
1435 v4l2_m2m_get_vq(ctx->fh.m2m_ctx,
1436 V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE),
1437 v4l2_m2m_get_vq(ctx->fh.m2m_ctx,
1438 V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE),
1439 in_vb->sequence, out_vb->sequence);
1440
1441 v4l2_m2m_buf_copy_metadata(in_vb, out_vb, true);
1442
1443 /* Now, let's deal with hardware ... */
1444 dw100_hw_master_bus_disable(dw_dev);
1445 dw100_hw_init_ctrl(dw_dev);
1446 dw100_hw_set_pixel_boundary(dw_dev);
1447 dw100_hw_set_src_crop(dw_dev, &ctx->q_data[DW100_QUEUE_SRC],
1448 &ctx->q_data[DW100_QUEUE_DST]);
1449 dw100_hw_set_source(dw_dev, &ctx->q_data[DW100_QUEUE_SRC],
1450 &in_vb->vb2_buf);
1451 dw100_hw_set_destination(dw_dev, &ctx->q_data[DW100_QUEUE_DST],
1452 ctx->q_data[DW100_QUEUE_SRC].fmt,
1453 &out_vb->vb2_buf);
1454 dw100_hw_set_mapping(dw_dev, ctx->map_dma,
1455 ctx->map_width, ctx->map_height);
1456 dw100_hw_enable_irq(dw_dev);
1457 dw100_hw_dewarp_start(dw_dev);
1458
1459 /* Enable Bus */
1460 dw100_hw_master_bus_enable(dw_dev);
1461}
1462
1463static void dw100_device_run(void *priv)
1464{
1465 struct dw100_ctx *ctx = priv;
1466 struct vb2_v4l2_buffer *src_buf, *dst_buf;
1467
1468 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
1469 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1470
1471 dw100_start(ctx, src_buf, dst_buf);
1472}
1473
1474static const struct v4l2_m2m_ops dw100_m2m_ops = {
1475 .device_run = dw100_device_run,
1476};
1477
1478static struct video_device *dw100_init_video_device(struct dw100_device *dw_dev)
1479{
1480 struct video_device *vfd = &dw_dev->vfd;
1481
1482 vfd->vfl_dir = VFL_DIR_M2M;
1483 vfd->fops = &dw100_fops;
1484 vfd->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;
1485 vfd->ioctl_ops = &dw100_ioctl_ops;
1486 vfd->minor = -1;
1487 vfd->release = video_device_release_empty;
1488 vfd->v4l2_dev = &dw_dev->v4l2_dev;
1489 vfd->lock = &dw_dev->vfd_mutex;
1490
1491 strscpy(vfd->name, DRV_NAME, sizeof(vfd->name));
1492 mutex_init(vfd->lock);
1493 video_set_drvdata(vfd, dw_dev);
1494
1495 return vfd;
1496}
1497
1498static int dw100_dump_regs_show(struct seq_file *m, void *private)
1499{
1500 struct dw100_device *dw_dev = m->private;
1501 int ret;
1502
1503 ret = pm_runtime_resume_and_get(&dw_dev->pdev->dev);
1504 if (ret < 0)
1505 return ret;
1506
1507 ret = dw100_dump_regs(m);
1508
1509 pm_runtime_put_sync(&dw_dev->pdev->dev);
1510
1511 return ret;
1512}
1513DEFINE_SHOW_ATTRIBUTE(dw100_dump_regs);
1514
1515static void dw100_debugfs_init(struct dw100_device *dw_dev)
1516{
1517 dw_dev->debugfs_root =
1518 debugfs_create_dir(dev_name(&dw_dev->pdev->dev), NULL);
1519
1520 debugfs_create_file("dump_regs", 0600, dw_dev->debugfs_root, dw_dev,
1521 &dw100_dump_regs_fops);
1522}
1523
1524static void dw100_debugfs_exit(struct dw100_device *dw_dev)
1525{
1526 debugfs_remove_recursive(dw_dev->debugfs_root);
1527}
1528
1529static int dw100_probe(struct platform_device *pdev)
1530{
1531 struct dw100_device *dw_dev;
1532 struct video_device *vfd;
1533 int ret, irq;
1534
1535 dw_dev = devm_kzalloc(&pdev->dev, sizeof(*dw_dev), GFP_KERNEL);
1536 if (!dw_dev)
1537 return -ENOMEM;
1538 dw_dev->pdev = pdev;
1539
1540 ret = devm_clk_bulk_get_all(&pdev->dev, &dw_dev->clks);
1541 if (ret < 0) {
1542 dev_err(&pdev->dev, "Unable to get clocks: %d\n", ret);
1543 return ret;
1544 }
1545 dw_dev->num_clks = ret;
1546
1547 dw_dev->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
1548 if (IS_ERR(dw_dev->mmio))
1549 return PTR_ERR(dw_dev->mmio);
1550
1551 irq = platform_get_irq(pdev, 0);
1552 if (irq < 0)
1553 return irq;
1554
1555 platform_set_drvdata(pdev, dw_dev);
1556
1557 pm_runtime_enable(&pdev->dev);
1558 ret = pm_runtime_resume_and_get(&pdev->dev);
1559 if (ret < 0) {
1560 dev_err(&pdev->dev, "Unable to resume the device: %d\n", ret);
1561 goto err_pm;
1562 }
1563
1564 pm_runtime_put_sync(&pdev->dev);
1565
1566 ret = devm_request_irq(&pdev->dev, irq, dw100_irq_handler, IRQF_ONESHOT,
1567 dev_name(&pdev->dev), dw_dev);
1568 if (ret < 0) {
1569 dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
1570 goto err_pm;
1571 }
1572
1573 ret = v4l2_device_register(&pdev->dev, &dw_dev->v4l2_dev);
1574 if (ret)
1575 goto err_pm;
1576
1577 vfd = dw100_init_video_device(dw_dev);
1578
1579 dw_dev->m2m_dev = v4l2_m2m_init(&dw100_m2m_ops);
1580 if (IS_ERR(dw_dev->m2m_dev)) {
1581 dev_err(&pdev->dev, "Failed to init mem2mem device\n");
1582 ret = PTR_ERR(dw_dev->m2m_dev);
1583 goto err_v4l2;
1584 }
1585
1586 dw_dev->mdev.dev = &pdev->dev;
1587 strscpy(dw_dev->mdev.model, "dw100", sizeof(dw_dev->mdev.model));
1588 media_device_init(&dw_dev->mdev);
1589 dw_dev->v4l2_dev.mdev = &dw_dev->mdev;
1590
1591 ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1);
1592 if (ret) {
1593 dev_err(&pdev->dev, "Failed to register video device\n");
1594 goto err_m2m;
1595 }
1596
1597 ret = v4l2_m2m_register_media_controller(dw_dev->m2m_dev, vfd,
1598 MEDIA_ENT_F_PROC_VIDEO_SCALER);
1599 if (ret) {
1600 dev_err(&pdev->dev, "Failed to init mem2mem media controller\n");
1601 goto error_v4l2;
1602 }
1603
1604 ret = media_device_register(&dw_dev->mdev);
1605 if (ret) {
1606 dev_err(&pdev->dev, "Failed to register mem2mem media device\n");
1607 goto error_m2m_mc;
1608 }
1609
1610 dw100_debugfs_init(dw_dev);
1611
1612 dev_info(&pdev->dev,
1613 "dw100 v4l2 m2m registered as /dev/video%u\n", vfd->num);
1614
1615 return 0;
1616
1617error_m2m_mc:
1618 v4l2_m2m_unregister_media_controller(dw_dev->m2m_dev);
1619error_v4l2:
1620 video_unregister_device(vfd);
1621err_m2m:
1622 media_device_cleanup(&dw_dev->mdev);
1623 v4l2_m2m_release(dw_dev->m2m_dev);
1624err_v4l2:
1625 v4l2_device_unregister(&dw_dev->v4l2_dev);
1626err_pm:
1627 pm_runtime_disable(&pdev->dev);
1628
1629 return ret;
1630}
1631
1632static void dw100_remove(struct platform_device *pdev)
1633{
1634 struct dw100_device *dw_dev = platform_get_drvdata(pdev);
1635
1636 dw100_debugfs_exit(dw_dev);
1637
1638 pm_runtime_disable(&pdev->dev);
1639
1640 media_device_unregister(&dw_dev->mdev);
1641 v4l2_m2m_unregister_media_controller(dw_dev->m2m_dev);
1642 media_device_cleanup(&dw_dev->mdev);
1643
1644 video_unregister_device(&dw_dev->vfd);
1645 mutex_destroy(dw_dev->vfd.lock);
1646 v4l2_m2m_release(dw_dev->m2m_dev);
1647 v4l2_device_unregister(&dw_dev->v4l2_dev);
1648}
1649
1650static int __maybe_unused dw100_runtime_suspend(struct device *dev)
1651{
1652 struct dw100_device *dw_dev = dev_get_drvdata(dev);
1653
1654 clk_bulk_disable_unprepare(dw_dev->num_clks, dw_dev->clks);
1655
1656 return 0;
1657}
1658
1659static int __maybe_unused dw100_runtime_resume(struct device *dev)
1660{
1661 int ret;
1662 struct dw100_device *dw_dev = dev_get_drvdata(dev);
1663
1664 ret = clk_bulk_prepare_enable(dw_dev->num_clks, dw_dev->clks);
1665
1666 if (ret)
1667 return ret;
1668
1669 dw100_hw_reset(dw_dev);
1670
1671 return 0;
1672}
1673
1674static const struct dev_pm_ops dw100_pm = {
1675 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1676 pm_runtime_force_resume)
1677 SET_RUNTIME_PM_OPS(dw100_runtime_suspend,
1678 dw100_runtime_resume, NULL)
1679};
1680
1681static const struct of_device_id dw100_dt_ids[] = {
1682 { .compatible = "nxp,imx8mp-dw100", .data = NULL },
1683 { },
1684};
1685MODULE_DEVICE_TABLE(of, dw100_dt_ids);
1686
1687static struct platform_driver dw100_driver = {
1688 .probe = dw100_probe,
1689 .remove = dw100_remove,
1690 .driver = {
1691 .name = DRV_NAME,
1692 .pm = &dw100_pm,
1693 .of_match_table = dw100_dt_ids,
1694 },
1695};
1696
1697module_platform_driver(dw100_driver);
1698
1699MODULE_DESCRIPTION("DW100 Hardware dewarper");
1700MODULE_AUTHOR("Xavier Roumegue <Xavier.Roumegue@oss.nxp.com>");
1701MODULE_LICENSE("GPL");