1/* SPDX-License-Identifier: GPL-2.0
 2 *
 3 * Copyright 2018-2020 HabanaLabs, Ltd.
 4 * All Rights Reserved.
 5 *
 6 */
 7
 8#ifndef GAUDI_H
 9#define GAUDI_H
10
11#define SRAM_BAR_ID		0
12#define CFG_BAR_ID		2
13#define HBM_BAR_ID		4
14
15#define SRAM_BAR_SIZE		0x4000000ull		/* 64MB */
16#define CFG_BAR_SIZE		0x8000000ull		/* 128MB */
17
18#define CFG_BASE		0x7FFC000000ull
19#define CFG_SIZE		0x4000000		/* 32MB CFG + 32MB DBG*/
20
21#define SRAM_BASE_ADDR		0x7FF0000000ull
22#define SRAM_SIZE		0x1400000		/* 20MB */
23
24#define SPI_FLASH_BASE_ADDR	0x7FF8000000ull
25
26#define PSOC_SCRATCHPAD_ADDR	0x7FFBFE0000ull
27#define PSOC_SCRATCHPAD_SIZE	0x10000			/* 64KB */
28
29#define PCIE_FW_SRAM_ADDR	0x7FFBFF0000ull
30#define PCIE_FW_SRAM_SIZE	0x8000			/* 32KB */
31
32#define DRAM_PHYS_BASE		0x0ull
33
34#define HOST_PHYS_BASE		0x8000000000ull		/* 0.5TB */
35#define HOST_PHYS_SIZE		0x1000000000000ull	/* 0.25PB (48 bits) */
36
37#define GAUDI_MSI_ENTRIES	32
38
39#define QMAN_PQ_ENTRY_SIZE	16			/* Bytes */
40
41#define MAX_ASID		2
42
43#define PROT_BITS_OFFS		0xF80
44
45#define MME_NUMBER_OF_MASTER_ENGINES	2
46
47#define MME_NUMBER_OF_SLAVE_ENGINES	2
48
49#define TPC_NUMBER_OF_ENGINES	8
50
51#define DMA_NUMBER_OF_CHANNELS	8
52
53#define NIC_NUMBER_OF_MACROS	5
54
55#define NIC_NUMBER_OF_ENGINES	(NIC_NUMBER_OF_MACROS * 2)
56
57#define NUMBER_OF_IF		8
58
59#define DEVICE_CACHE_LINE_SIZE	128
60
61#endif /* GAUDI_H */