1/* SPDX-License-Identifier: GPL-2.0-or-later */
 2/*
 3 *	CPU feature overrides for DECstation systems.  Two variations
 4 *	are generally applicable.
 5 *
 6 *	Copyright (C) 2013  Maciej W. Rozycki
 7 */
 8#ifndef __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H
 9#define __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H
10
11/* Generic ones first.  */
12#define cpu_has_tlb			1
13#define cpu_has_tlbinv			0
14#define cpu_has_segments		0
15#define cpu_has_eva			0
16#define cpu_has_htw			0
17#define cpu_has_rixiex			0
18#define cpu_has_maar			0
19#define cpu_has_rw_llb			0
20#define cpu_has_divec			0
21#define cpu_has_prefetch		0
22#define cpu_has_mcheck			0
23#define cpu_has_ejtag			0
24#define cpu_has_mips16			0
25#define cpu_has_mips16e2		0
26#define cpu_has_mdmx			0
27#define cpu_has_mips3d			0
28#define cpu_has_smartmips		0
29#define cpu_has_rixi			0
30#define cpu_has_xpa			0
31#define cpu_has_vtag_icache		0
32#define cpu_has_ic_fills_f_dc		0
33#define cpu_has_pindexed_dcache		0
34#define cpu_icache_snoops_remote_store	1
35#define cpu_has_mips_4			0
36#define cpu_has_mips_5			0
37#define cpu_has_mips32r1		0
38#define cpu_has_mips32r2		0
39#define cpu_has_mips64r1		0
40#define cpu_has_mips64r2		0
41#define cpu_has_dsp			0
42#define cpu_has_dsp2			0
43#define cpu_has_mipsmt			0
44#define cpu_has_userlocal		0
45#define cpu_has_perf_cntr_intr_bit	0
46#define cpu_has_vz			0
47#define cpu_has_fre			0
48#define cpu_has_cdmm			0
49
50/* R3k-specific ones.  */
51#ifdef CONFIG_CPU_R3000
52#define cpu_has_3kex			1
53#define cpu_has_4kex			0
54#define cpu_has_3k_cache		1
55#define cpu_has_4k_cache		0
56#define cpu_has_32fpr			0
57#define cpu_has_counter			0
58#define cpu_has_watch			0
59#define cpu_has_vce			0
60#define cpu_has_cache_cdex_p		0
61#define cpu_has_cache_cdex_s		0
62#define cpu_has_llsc			0
63#define cpu_has_dc_aliases		0
64#define cpu_has_mips_2			0
65#define cpu_has_mips_3			0
66#define cpu_has_nofpuex			1
67#define cpu_has_inclusive_pcaches	0
68#define cpu_dcache_line_size()		4
69#define cpu_icache_line_size()		4
70#define cpu_scache_line_size()		0
71#endif /* CONFIG_CPU_R3000 */
72
73/* R4k-specific ones.  */
74#ifdef CONFIG_CPU_R4X00
75#define cpu_has_3kex			0
76#define cpu_has_4kex			1
77#define cpu_has_3k_cache		0
78#define cpu_has_4k_cache		1
79#define cpu_has_32fpr			1
80#define cpu_has_counter			1
81#define cpu_has_watch			1
82#define cpu_has_vce			1
83#define cpu_has_cache_cdex_p		1
84#define cpu_has_cache_cdex_s		1
85#define cpu_has_llsc			1
86#define cpu_has_dc_aliases		(PAGE_SIZE < 0x4000)
87#define cpu_has_mips_2			1
88#define cpu_has_mips_3			1
89#define cpu_has_nofpuex			0
90#define cpu_has_inclusive_pcaches	1
91#define cpu_dcache_line_size()		16
92#define cpu_icache_line_size()		16
93#define cpu_scache_line_size()		32
94#endif /* CONFIG_CPU_R4X00 */
95
96#endif /* __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H */