1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * linux/sound/soc/codecs/tlv320aic32x4.c
   4 *
   5 * Copyright 2011 Vista Silicon S.L.
   6 *
   7 * Author: Javier Martin <javier.martin@vista-silicon.com>
   8 *
   9 * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
  10 */
  11
  12#include <linux/module.h>
  13#include <linux/moduleparam.h>
  14#include <linux/init.h>
  15#include <linux/delay.h>
  16#include <linux/pm.h>
  17#include <linux/gpio.h>
  18#include <linux/of_gpio.h>
  19#include <linux/cdev.h>
  20#include <linux/slab.h>
  21#include <linux/clk.h>
  22#include <linux/of_clk.h>
  23#include <linux/regulator/consumer.h>
  24
  25#include <sound/tlv320aic32x4.h>
  26#include <sound/core.h>
  27#include <sound/pcm.h>
  28#include <sound/pcm_params.h>
  29#include <sound/soc.h>
  30#include <sound/soc-dapm.h>
  31#include <sound/initval.h>
  32#include <sound/tlv.h>
  33
  34#include "tlv320aic32x4.h"
  35
  36struct aic32x4_priv {
  37	struct regmap *regmap;
  38	u32 power_cfg;
  39	u32 micpga_routing;
  40	bool swapdacs;
  41	int rstn_gpio;
  42	const char *mclk_name;
  43
  44	struct regulator *supply_ldo;
  45	struct regulator *supply_iov;
  46	struct regulator *supply_dv;
  47	struct regulator *supply_av;
  48
  49	struct aic32x4_setup_data *setup;
  50	struct device *dev;
  51	enum aic32x4_type type;
  52
  53	unsigned int fmt;
  54};
  55
  56static int aic32x4_reset_adc(struct snd_soc_dapm_widget *w,
  57			     struct snd_kcontrol *kcontrol, int event)
  58{
  59	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  60	u32 adc_reg;
  61
  62	/*
  63	 * Workaround: the datasheet does not mention a required programming
  64	 * sequence but experiments show the ADC needs to be reset after each
  65	 * capture to avoid audible artifacts.
  66	 */
  67	switch (event) {
  68	case SND_SOC_DAPM_POST_PMD:
  69		adc_reg = snd_soc_component_read(component, AIC32X4_ADCSETUP);
  70		snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg |
  71					AIC32X4_LADC_EN | AIC32X4_RADC_EN);
  72		snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg);
  73		break;
  74	}
  75	return 0;
  76};
  77
  78static int mic_bias_event(struct snd_soc_dapm_widget *w,
  79	struct snd_kcontrol *kcontrol, int event)
  80{
  81	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  82
  83	switch (event) {
  84	case SND_SOC_DAPM_POST_PMU:
  85		/* Change Mic Bias Registor */
  86		snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
  87				AIC32x4_MICBIAS_MASK,
  88				AIC32X4_MICBIAS_LDOIN |
  89				AIC32X4_MICBIAS_2075V);
  90		printk(KERN_DEBUG "%s: Mic Bias will be turned ON\n", __func__);
  91		break;
  92	case SND_SOC_DAPM_PRE_PMD:
  93		snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
  94				AIC32x4_MICBIAS_MASK, 0);
  95		printk(KERN_DEBUG "%s: Mic Bias will be turned OFF\n",
  96				__func__);
  97		break;
  98	}
  99
 100	return 0;
 101}
 102
 103
 104static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol,
 105	struct snd_ctl_elem_value *ucontrol)
 106{
 107	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 108	u8 val;
 109
 110	val = snd_soc_component_read(component, AIC32X4_DINCTL);
 111
 112	ucontrol->value.integer.value[0] = (val & 0x01);
 113
 114	return 0;
 115};
 116
 117static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol,
 118	struct snd_ctl_elem_value *ucontrol)
 119{
 120	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 121	u8 val;
 122	u8 gpio_check;
 123
 124	val = snd_soc_component_read(component, AIC32X4_DOUTCTL);
 125	gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
 126	if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
 127		printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n",
 128			__func__);
 129		return -EINVAL;
 130	}
 131
 132	if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH))
 133		return 0;
 134
 135	if (ucontrol->value.integer.value[0])
 136		val |= ucontrol->value.integer.value[0];
 137	else
 138		val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH;
 139
 140	snd_soc_component_write(component, AIC32X4_DOUTCTL, val);
 141
 142	return 0;
 143};
 144
 145static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol,
 146	struct snd_ctl_elem_value *ucontrol)
 147{
 148	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 149	u8 val;
 150
 151	val = snd_soc_component_read(component, AIC32X4_SCLKCTL);
 152
 153	ucontrol->value.integer.value[0] = (val & 0x01);
 154
 155	return 0;
 156};
 157
 158static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol,
 159	struct snd_ctl_elem_value *ucontrol)
 160{
 161	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 162	u8 val;
 163	u8 gpio_check;
 164
 165	val = snd_soc_component_read(component, AIC32X4_MISOCTL);
 166	gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
 167	if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
 168		printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n",
 169			__func__);
 170		return -EINVAL;
 171	}
 172
 173	if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH))
 174		return 0;
 175
 176	if (ucontrol->value.integer.value[0])
 177		val |= ucontrol->value.integer.value[0];
 178	else
 179		val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH;
 180
 181	snd_soc_component_write(component, AIC32X4_MISOCTL, val);
 182
 183	return 0;
 184};
 185
 186static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol,
 187	struct snd_ctl_elem_value *ucontrol)
 188{
 189	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 190	u8 val;
 191
 192	val = snd_soc_component_read(component, AIC32X4_GPIOCTL);
 193	ucontrol->value.integer.value[0] = ((val & 0x2) >> 1);
 194
 195	return 0;
 196};
 197
 198static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol,
 199	struct snd_ctl_elem_value *ucontrol)
 200{
 201	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 202	u8 val;
 203	u8 gpio_check;
 204
 205	val = snd_soc_component_read(component, AIC32X4_GPIOCTL);
 206	gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT);
 207	if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) {
 208		printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n",
 209			__func__);
 210		return -EINVAL;
 211	}
 212
 213	if (ucontrol->value.integer.value[0] == (val & 0x1))
 214		return 0;
 215
 216	if (ucontrol->value.integer.value[0])
 217		val |= ucontrol->value.integer.value[0];
 218	else
 219		val &= 0xfe;
 220
 221	snd_soc_component_write(component, AIC32X4_GPIOCTL, val);
 222
 223	return 0;
 224};
 225
 226static const struct snd_kcontrol_new aic32x4_mfp1[] = {
 227	SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL),
 228};
 229
 230static const struct snd_kcontrol_new aic32x4_mfp2[] = {
 231	SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio),
 232};
 233
 234static const struct snd_kcontrol_new aic32x4_mfp3[] = {
 235	SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL),
 236};
 237
 238static const struct snd_kcontrol_new aic32x4_mfp4[] = {
 239	SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio),
 240};
 241
 242static const struct snd_kcontrol_new aic32x4_mfp5[] = {
 243	SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio,
 244		aic32x4_set_mfp5_gpio),
 245};
 246
 247/* 0dB min, 0.5dB steps */
 248static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
 249/* -63.5dB min, 0.5dB steps */
 250static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0);
 251/* -6dB min, 1dB steps */
 252static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0);
 253/* -12dB min, 0.5dB steps */
 254static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0);
 255/* -6dB min, 1dB steps */
 256static DECLARE_TLV_DB_SCALE(tlv_tas_driver_gain, -5850, 50, 0);
 257static DECLARE_TLV_DB_SCALE(tlv_amp_vol, 0, 600, 1);
 258
 259static const char * const lo_cm_text[] = {
 260	"Full Chip", "1.65V",
 261};
 262
 263static SOC_ENUM_SINGLE_DECL(lo_cm_enum, AIC32X4_CMMODE, 3, lo_cm_text);
 264
 265static const char * const ptm_text[] = {
 266	"P3", "P2", "P1",
 267};
 268
 269static SOC_ENUM_SINGLE_DECL(l_ptm_enum, AIC32X4_LPLAYBACK, 2, ptm_text);
 270static SOC_ENUM_SINGLE_DECL(r_ptm_enum, AIC32X4_RPLAYBACK, 2, ptm_text);
 271
 272static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
 273	SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
 274			AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm),
 275	SOC_ENUM("DAC Left Playback PowerTune Switch", l_ptm_enum),
 276	SOC_ENUM("DAC Right Playback PowerTune Switch", r_ptm_enum),
 277	SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
 278			AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0,
 279			tlv_driver_gain),
 280	SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
 281			AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0,
 282			tlv_driver_gain),
 283	SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
 284			AIC32X4_HPRGAIN, 6, 0x01, 1),
 285	SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
 286			AIC32X4_LORGAIN, 6, 0x01, 1),
 287	SOC_ENUM("LO Playback Common Mode Switch", lo_cm_enum),
 288	SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
 289			AIC32X4_RMICPGAVOL, 7, 0x01, 1),
 290
 291	SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
 292	SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
 293
 294	SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL,
 295			AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol),
 296	SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
 297			AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
 298
 299	SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
 300
 301	SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
 302	SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
 303	SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
 304			4, 0x07, 0),
 305	SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
 306			0, 0x03, 0),
 307	SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
 308			6, 0x03, 0),
 309	SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
 310			1, 0x1F, 0),
 311	SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
 312			0, 0x7F, 0),
 313	SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
 314			3, 0x1F, 0),
 315	SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
 316			3, 0x1F, 0),
 317	SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
 318			0, 0x1F, 0),
 319	SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
 320			0, 0x0F, 0),
 321};
 322
 323static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
 324	SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
 325	SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
 326};
 327
 328static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
 329	SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
 330	SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
 331};
 332
 333static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
 334	SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
 335};
 336
 337static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
 338	SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
 339};
 340
 341static const char * const resistor_text[] = {
 342	"Off", "10 kOhm", "20 kOhm", "40 kOhm",
 343};
 344
 345/* Left mixer pins */
 346static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text);
 347static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text);
 348static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text);
 349static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text);
 350
 351static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text);
 352static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text);
 353static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text);
 354
 355static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = {
 356	SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum),
 357};
 358static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = {
 359	SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum),
 360};
 361static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = {
 362	SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum),
 363};
 364static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = {
 365	SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum),
 366};
 367static const struct snd_kcontrol_new cml_to_lmixer_controls[] = {
 368	SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum),
 369};
 370static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = {
 371	SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum),
 372};
 373static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = {
 374	SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum),
 375};
 376
 377/*	Right mixer pins */
 378static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text);
 379static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text);
 380static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text);
 381static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text);
 382static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text);
 383static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text);
 384static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text);
 385
 386static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = {
 387	SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum),
 388};
 389static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = {
 390	SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum),
 391};
 392static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = {
 393	SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum),
 394};
 395static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = {
 396	SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum),
 397};
 398static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = {
 399	SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum),
 400};
 401static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = {
 402	SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum),
 403};
 404static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = {
 405	SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum),
 406};
 407
 408static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
 409	SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
 410	SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
 411			   &hpl_output_mixer_controls[0],
 412			   ARRAY_SIZE(hpl_output_mixer_controls)),
 413	SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
 414
 415	SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
 416			   &lol_output_mixer_controls[0],
 417			   ARRAY_SIZE(lol_output_mixer_controls)),
 418	SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
 419
 420	SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
 421	SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
 422			   &hpr_output_mixer_controls[0],
 423			   ARRAY_SIZE(hpr_output_mixer_controls)),
 424	SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
 425	SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
 426			   &lor_output_mixer_controls[0],
 427			   ARRAY_SIZE(lor_output_mixer_controls)),
 428	SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
 429
 430	SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
 431	SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
 432			in1r_to_rmixer_controls),
 433	SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
 434			in2r_to_rmixer_controls),
 435	SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
 436			in3r_to_rmixer_controls),
 437	SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
 438			in2l_to_rmixer_controls),
 439	SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
 440			cmr_to_rmixer_controls),
 441	SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
 442			in1l_to_rmixer_controls),
 443	SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
 444			in3l_to_rmixer_controls),
 445
 446	SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
 447	SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
 448			in1l_to_lmixer_controls),
 449	SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
 450			in2l_to_lmixer_controls),
 451	SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
 452			in3l_to_lmixer_controls),
 453	SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
 454			in1r_to_lmixer_controls),
 455	SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
 456			cml_to_lmixer_controls),
 457	SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
 458			in2r_to_lmixer_controls),
 459	SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
 460			in3r_to_lmixer_controls),
 461
 462	SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event,
 463			SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 464
 465	SND_SOC_DAPM_POST("ADC Reset", aic32x4_reset_adc),
 466
 467	SND_SOC_DAPM_OUTPUT("HPL"),
 468	SND_SOC_DAPM_OUTPUT("HPR"),
 469	SND_SOC_DAPM_OUTPUT("LOL"),
 470	SND_SOC_DAPM_OUTPUT("LOR"),
 471	SND_SOC_DAPM_INPUT("IN1_L"),
 472	SND_SOC_DAPM_INPUT("IN1_R"),
 473	SND_SOC_DAPM_INPUT("IN2_L"),
 474	SND_SOC_DAPM_INPUT("IN2_R"),
 475	SND_SOC_DAPM_INPUT("IN3_L"),
 476	SND_SOC_DAPM_INPUT("IN3_R"),
 477	SND_SOC_DAPM_INPUT("CM_L"),
 478	SND_SOC_DAPM_INPUT("CM_R"),
 479};
 480
 481static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
 482	/* Left Output */
 483	{"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
 484	{"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
 485
 486	{"HPL Power", NULL, "HPL Output Mixer"},
 487	{"HPL", NULL, "HPL Power"},
 488
 489	{"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
 490
 491	{"LOL Power", NULL, "LOL Output Mixer"},
 492	{"LOL", NULL, "LOL Power"},
 493
 494	/* Right Output */
 495	{"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
 496	{"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
 497
 498	{"HPR Power", NULL, "HPR Output Mixer"},
 499	{"HPR", NULL, "HPR Power"},
 500
 501	{"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
 502
 503	{"LOR Power", NULL, "LOR Output Mixer"},
 504	{"LOR", NULL, "LOR Power"},
 505
 506	/* Right Input */
 507	{"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"},
 508	{"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"},
 509	{"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"},
 510	{"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"},
 511
 512	{"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"},
 513	{"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"},
 514	{"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"},
 515	{"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"},
 516
 517	{"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"},
 518	{"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"},
 519	{"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"},
 520	{"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"},
 521
 522	{"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"},
 523	{"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"},
 524	{"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"},
 525	{"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"},
 526
 527	{"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"},
 528	{"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"},
 529	{"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"},
 530	{"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"},
 531
 532	{"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"},
 533	{"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"},
 534	{"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"},
 535	{"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"},
 536
 537	{"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"},
 538	{"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"},
 539	{"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"},
 540	{"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"},
 541
 542	/* Left Input */
 543	{"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"},
 544	{"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"},
 545	{"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"},
 546	{"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"},
 547
 548	{"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"},
 549	{"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"},
 550	{"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"},
 551	{"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"},
 552
 553	{"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"},
 554	{"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"},
 555	{"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"},
 556	{"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"},
 557
 558	{"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"},
 559	{"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"},
 560	{"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"},
 561	{"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"},
 562
 563	{"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"},
 564	{"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"},
 565	{"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"},
 566	{"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"},
 567
 568	{"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"},
 569	{"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"},
 570	{"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"},
 571	{"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"},
 572
 573	{"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"},
 574	{"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"},
 575	{"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"},
 576	{"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"},
 577};
 578
 579static const struct regmap_range_cfg aic32x4_regmap_pages[] = {
 580	{
 581		.selector_reg = 0,
 582		.selector_mask	= 0xff,
 583		.window_start = 0,
 584		.window_len = 128,
 585		.range_min = 0,
 586		.range_max = AIC32X4_REFPOWERUP,
 587	},
 588};
 589
 590const struct regmap_config aic32x4_regmap_config = {
 591	.max_register = AIC32X4_REFPOWERUP,
 592	.ranges = aic32x4_regmap_pages,
 593	.num_ranges = ARRAY_SIZE(aic32x4_regmap_pages),
 594};
 595EXPORT_SYMBOL(aic32x4_regmap_config);
 596
 597static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 598				  int clk_id, unsigned int freq, int dir)
 599{
 600	struct snd_soc_component *component = codec_dai->component;
 601	struct clk *mclk;
 602	struct clk *pll;
 603
 604	pll = devm_clk_get(component->dev, "pll");
 605	if (IS_ERR(pll))
 606		return PTR_ERR(pll);
 607
 608	mclk = clk_get_parent(pll);
 609
 610	return clk_set_rate(mclk, freq);
 611}
 612
 613static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 614{
 615	struct snd_soc_component *component = codec_dai->component;
 616	struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
 617	u8 iface_reg_1 = 0;
 618	u8 iface_reg_2 = 0;
 619	u8 iface_reg_3 = 0;
 620
 621	switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
 622	case SND_SOC_DAIFMT_CBP_CFP:
 623		iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
 624		break;
 625	case SND_SOC_DAIFMT_CBC_CFC:
 626		break;
 627	default:
 628		printk(KERN_ERR "aic32x4: invalid clock provider\n");
 629		return -EINVAL;
 630	}
 631
 632	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 633	case SND_SOC_DAIFMT_I2S:
 634		break;
 635	case SND_SOC_DAIFMT_DSP_A:
 636		iface_reg_1 |= (AIC32X4_DSP_MODE <<
 637				AIC32X4_IFACE1_DATATYPE_SHIFT);
 638		iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
 639		iface_reg_2 = 0x01; /* add offset 1 */
 640		break;
 641	case SND_SOC_DAIFMT_DSP_B:
 642		iface_reg_1 |= (AIC32X4_DSP_MODE <<
 643				AIC32X4_IFACE1_DATATYPE_SHIFT);
 644		iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
 645		break;
 646	case SND_SOC_DAIFMT_RIGHT_J:
 647		iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE <<
 648				AIC32X4_IFACE1_DATATYPE_SHIFT);
 649		break;
 650	case SND_SOC_DAIFMT_LEFT_J:
 651		iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE <<
 652				AIC32X4_IFACE1_DATATYPE_SHIFT);
 653		break;
 654	default:
 655		printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
 656		return -EINVAL;
 657	}
 658
 659	aic32x4->fmt = fmt;
 660
 661	snd_soc_component_update_bits(component, AIC32X4_IFACE1,
 662				AIC32X4_IFACE1_DATATYPE_MASK |
 663				AIC32X4_IFACE1_MASTER_MASK, iface_reg_1);
 664	snd_soc_component_update_bits(component, AIC32X4_IFACE2,
 665				AIC32X4_DATA_OFFSET_MASK, iface_reg_2);
 666	snd_soc_component_update_bits(component, AIC32X4_IFACE3,
 667				AIC32X4_BCLKINV_MASK, iface_reg_3);
 668
 669	return 0;
 670}
 671
 672static int aic32x4_set_aosr(struct snd_soc_component *component, u8 aosr)
 673{
 674	return snd_soc_component_write(component, AIC32X4_AOSR, aosr);
 675}
 676
 677static int aic32x4_set_dosr(struct snd_soc_component *component, u16 dosr)
 678{
 679	snd_soc_component_write(component, AIC32X4_DOSRMSB, dosr >> 8);
 680	snd_soc_component_write(component, AIC32X4_DOSRLSB,
 681		      (dosr & 0xff));
 682
 683	return 0;
 684}
 685
 686static int aic32x4_set_processing_blocks(struct snd_soc_component *component,
 687						u8 r_block, u8 p_block)
 688{
 689	struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
 690
 691	if (aic32x4->type == AIC32X4_TYPE_TAS2505) {
 692		if (r_block || p_block > 3)
 693			return -EINVAL;
 694
 695		snd_soc_component_write(component, AIC32X4_DACSPB, p_block);
 696	} else { /* AIC32x4 */
 697		if (r_block > 18 || p_block > 25)
 698			return -EINVAL;
 699
 700		snd_soc_component_write(component, AIC32X4_ADCSPB, r_block);
 701		snd_soc_component_write(component, AIC32X4_DACSPB, p_block);
 702	}
 703
 704	return 0;
 705}
 706
 707static int aic32x4_setup_clocks(struct snd_soc_component *component,
 708				unsigned int sample_rate, unsigned int channels,
 709				unsigned int bit_depth)
 710{
 711	struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
 712	u8 aosr;
 713	u16 dosr;
 714	u8 adc_resource_class, dac_resource_class;
 715	u8 madc, nadc, mdac, ndac, max_nadc, min_mdac, max_ndac;
 716	u8 dosr_increment;
 717	u16 max_dosr, min_dosr;
 718	unsigned long adc_clock_rate, dac_clock_rate;
 719	int ret;
 720
 721	static struct clk_bulk_data clocks[] = {
 722		{ .id = "pll" },
 723		{ .id = "nadc" },
 724		{ .id = "madc" },
 725		{ .id = "ndac" },
 726		{ .id = "mdac" },
 727		{ .id = "bdiv" },
 728	};
 729	ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
 730	if (ret)
 731		return ret;
 732
 733	if (sample_rate <= 48000) {
 734		aosr = 128;
 735		adc_resource_class = 6;
 736		dac_resource_class = 8;
 737		dosr_increment = 8;
 738		if (aic32x4->type == AIC32X4_TYPE_TAS2505)
 739			aic32x4_set_processing_blocks(component, 0, 1);
 740		else
 741			aic32x4_set_processing_blocks(component, 1, 1);
 742	} else if (sample_rate <= 96000) {
 743		aosr = 64;
 744		adc_resource_class = 6;
 745		dac_resource_class = 8;
 746		dosr_increment = 4;
 747		if (aic32x4->type == AIC32X4_TYPE_TAS2505)
 748			aic32x4_set_processing_blocks(component, 0, 1);
 749		else
 750			aic32x4_set_processing_blocks(component, 1, 9);
 751	} else if (sample_rate == 192000) {
 752		aosr = 32;
 753		adc_resource_class = 3;
 754		dac_resource_class = 4;
 755		dosr_increment = 2;
 756		if (aic32x4->type == AIC32X4_TYPE_TAS2505)
 757			aic32x4_set_processing_blocks(component, 0, 1);
 758		else
 759			aic32x4_set_processing_blocks(component, 13, 19);
 760	} else {
 761		dev_err(component->dev, "Sampling rate not supported\n");
 762		return -EINVAL;
 763	}
 764
 765	/* PCM over I2S is always 2-channel */
 766	if ((aic32x4->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S)
 767		channels = 2;
 768
 769	madc = DIV_ROUND_UP((32 * adc_resource_class), aosr);
 770	max_dosr = (AIC32X4_MAX_DOSR_FREQ / sample_rate / dosr_increment) *
 771			dosr_increment;
 772	min_dosr = (AIC32X4_MIN_DOSR_FREQ / sample_rate / dosr_increment) *
 773			dosr_increment;
 774	max_nadc = AIC32X4_MAX_CODEC_CLKIN_FREQ / (madc * aosr * sample_rate);
 775
 776	for (nadc = max_nadc; nadc > 0; --nadc) {
 777		adc_clock_rate = nadc * madc * aosr * sample_rate;
 778		for (dosr = max_dosr; dosr >= min_dosr;
 779				dosr -= dosr_increment) {
 780			min_mdac = DIV_ROUND_UP((32 * dac_resource_class), dosr);
 781			max_ndac = AIC32X4_MAX_CODEC_CLKIN_FREQ /
 782					(min_mdac * dosr * sample_rate);
 783			for (mdac = min_mdac; mdac <= 128; ++mdac) {
 784				for (ndac = max_ndac; ndac > 0; --ndac) {
 785					dac_clock_rate = ndac * mdac * dosr *
 786							sample_rate;
 787					if (dac_clock_rate == adc_clock_rate) {
 788						if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0)
 789							continue;
 790
 791						clk_set_rate(clocks[0].clk,
 792							dac_clock_rate);
 793
 794						clk_set_rate(clocks[1].clk,
 795							sample_rate * aosr *
 796							madc);
 797						clk_set_rate(clocks[2].clk,
 798							sample_rate * aosr);
 799						aic32x4_set_aosr(component,
 800							aosr);
 801
 802						clk_set_rate(clocks[3].clk,
 803							sample_rate * dosr *
 804							mdac);
 805						clk_set_rate(clocks[4].clk,
 806							sample_rate * dosr);
 807						aic32x4_set_dosr(component,
 808							dosr);
 809
 810						clk_set_rate(clocks[5].clk,
 811							sample_rate * channels *
 812							bit_depth);
 813
 814						return 0;
 815					}
 816				}
 817			}
 818		}
 819	}
 820
 821	dev_err(component->dev,
 822		"Could not set clocks to support sample rate.\n");
 823	return -EINVAL;
 824}
 825
 826static int aic32x4_hw_params(struct snd_pcm_substream *substream,
 827				 struct snd_pcm_hw_params *params,
 828				 struct snd_soc_dai *dai)
 829{
 830	struct snd_soc_component *component = dai->component;
 831	struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
 832	u8 iface1_reg = 0;
 833	u8 dacsetup_reg = 0;
 834
 835	aic32x4_setup_clocks(component, params_rate(params),
 836			     params_channels(params),
 837			     params_physical_width(params));
 838
 839	switch (params_physical_width(params)) {
 840	case 16:
 841		iface1_reg |= (AIC32X4_WORD_LEN_16BITS <<
 842				   AIC32X4_IFACE1_DATALEN_SHIFT);
 843		break;
 844	case 20:
 845		iface1_reg |= (AIC32X4_WORD_LEN_20BITS <<
 846				   AIC32X4_IFACE1_DATALEN_SHIFT);
 847		break;
 848	case 24:
 849		iface1_reg |= (AIC32X4_WORD_LEN_24BITS <<
 850				   AIC32X4_IFACE1_DATALEN_SHIFT);
 851		break;
 852	case 32:
 853		iface1_reg |= (AIC32X4_WORD_LEN_32BITS <<
 854				   AIC32X4_IFACE1_DATALEN_SHIFT);
 855		break;
 856	}
 857	snd_soc_component_update_bits(component, AIC32X4_IFACE1,
 858				AIC32X4_IFACE1_DATALEN_MASK, iface1_reg);
 859
 860	if (params_channels(params) == 1) {
 861		dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
 862	} else {
 863		if (aic32x4->swapdacs)
 864			dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN;
 865		else
 866			dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
 867	}
 868	snd_soc_component_update_bits(component, AIC32X4_DACSETUP,
 869				AIC32X4_DAC_CHAN_MASK, dacsetup_reg);
 870
 871	return 0;
 872}
 873
 874static int aic32x4_mute(struct snd_soc_dai *dai, int mute, int direction)
 875{
 876	struct snd_soc_component *component = dai->component;
 877
 878	snd_soc_component_update_bits(component, AIC32X4_DACMUTE,
 879				AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0);
 880
 881	return 0;
 882}
 883
 884static int aic32x4_set_bias_level(struct snd_soc_component *component,
 885				  enum snd_soc_bias_level level)
 886{
 887	int ret;
 888
 889	static struct clk_bulk_data clocks[] = {
 890		{ .id = "madc" },
 891		{ .id = "mdac" },
 892		{ .id = "bdiv" },
 893	};
 894
 895	ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
 896	if (ret)
 897		return ret;
 898
 899	switch (level) {
 900	case SND_SOC_BIAS_ON:
 901		ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks);
 902		if (ret) {
 903			dev_err(component->dev, "Failed to enable clocks\n");
 904			return ret;
 905		}
 906		break;
 907	case SND_SOC_BIAS_PREPARE:
 908		break;
 909	case SND_SOC_BIAS_STANDBY:
 910		/* Initial cold start */
 911		if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
 912			break;
 913
 914		clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks);
 915		break;
 916	case SND_SOC_BIAS_OFF:
 917		break;
 918	}
 919	return 0;
 920}
 921
 922#define AIC32X4_RATES	SNDRV_PCM_RATE_8000_192000
 923#define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
 924			 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_3LE \
 925			 | SNDRV_PCM_FMTBIT_S32_LE)
 926
 927static const struct snd_soc_dai_ops aic32x4_ops = {
 928	.hw_params = aic32x4_hw_params,
 929	.mute_stream = aic32x4_mute,
 930	.set_fmt = aic32x4_set_dai_fmt,
 931	.set_sysclk = aic32x4_set_dai_sysclk,
 932	.no_capture_mute = 1,
 933};
 934
 935static struct snd_soc_dai_driver aic32x4_dai = {
 936	.name = "tlv320aic32x4-hifi",
 937	.playback = {
 938			 .stream_name = "Playback",
 939			 .channels_min = 1,
 940			 .channels_max = 2,
 941			 .rates = AIC32X4_RATES,
 942			 .formats = AIC32X4_FORMATS,},
 943	.capture = {
 944			.stream_name = "Capture",
 945			.channels_min = 1,
 946			.channels_max = 8,
 947			.rates = AIC32X4_RATES,
 948			.formats = AIC32X4_FORMATS,},
 949	.ops = &aic32x4_ops,
 950	.symmetric_rate = 1,
 951};
 952
 953static void aic32x4_setup_gpios(struct snd_soc_component *component)
 954{
 955	struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
 956
 957	/* setup GPIO functions */
 958	/* MFP1 */
 959	if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) {
 960		snd_soc_component_write(component, AIC32X4_DINCTL,
 961			  aic32x4->setup->gpio_func[0]);
 962		snd_soc_add_component_controls(component, aic32x4_mfp1,
 963			ARRAY_SIZE(aic32x4_mfp1));
 964	}
 965
 966	/* MFP2 */
 967	if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) {
 968		snd_soc_component_write(component, AIC32X4_DOUTCTL,
 969			  aic32x4->setup->gpio_func[1]);
 970		snd_soc_add_component_controls(component, aic32x4_mfp2,
 971			ARRAY_SIZE(aic32x4_mfp2));
 972	}
 973
 974	/* MFP3 */
 975	if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) {
 976		snd_soc_component_write(component, AIC32X4_SCLKCTL,
 977			  aic32x4->setup->gpio_func[2]);
 978		snd_soc_add_component_controls(component, aic32x4_mfp3,
 979			ARRAY_SIZE(aic32x4_mfp3));
 980	}
 981
 982	/* MFP4 */
 983	if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) {
 984		snd_soc_component_write(component, AIC32X4_MISOCTL,
 985			  aic32x4->setup->gpio_func[3]);
 986		snd_soc_add_component_controls(component, aic32x4_mfp4,
 987			ARRAY_SIZE(aic32x4_mfp4));
 988	}
 989
 990	/* MFP5 */
 991	if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) {
 992		snd_soc_component_write(component, AIC32X4_GPIOCTL,
 993			  aic32x4->setup->gpio_func[4]);
 994		snd_soc_add_component_controls(component, aic32x4_mfp5,
 995			ARRAY_SIZE(aic32x4_mfp5));
 996	}
 997}
 998
 999static int aic32x4_component_probe(struct snd_soc_component *component)
1000{
1001	struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
1002	u32 tmp_reg;
1003	int ret;
1004
1005	static struct clk_bulk_data clocks[] = {
1006		{ .id = "codec_clkin" },
1007		{ .id = "pll" },
1008		{ .id = "bdiv" },
1009		{ .id = "mdac" },
1010	};
1011
1012	ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
1013	if (ret)
1014		return ret;
1015
1016	if (aic32x4->setup)
1017		aic32x4_setup_gpios(component);
1018
1019	clk_set_parent(clocks[0].clk, clocks[1].clk);
1020	clk_set_parent(clocks[2].clk, clocks[3].clk);
1021
1022	/* Power platform configuration */
1023	if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
1024		snd_soc_component_write(component, AIC32X4_MICBIAS,
1025				AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V);
1026	}
1027	if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
1028		snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
1029
1030	tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
1031			AIC32X4_LDOCTLEN : 0;
1032	snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg);
1033
1034	tmp_reg = snd_soc_component_read(component, AIC32X4_CMMODE);
1035	if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
1036		tmp_reg |= AIC32X4_LDOIN_18_36;
1037	if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
1038		tmp_reg |= AIC32X4_LDOIN2HP;
1039	snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg);
1040
1041	/* Mic PGA routing */
1042	if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
1043		snd_soc_component_write(component, AIC32X4_LMICPGANIN,
1044				AIC32X4_LMICPGANIN_IN2R_10K);
1045	else
1046		snd_soc_component_write(component, AIC32X4_LMICPGANIN,
1047				AIC32X4_LMICPGANIN_CM1L_10K);
1048	if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
1049		snd_soc_component_write(component, AIC32X4_RMICPGANIN,
1050				AIC32X4_RMICPGANIN_IN1L_10K);
1051	else
1052		snd_soc_component_write(component, AIC32X4_RMICPGANIN,
1053				AIC32X4_RMICPGANIN_CM1R_10K);
1054
1055	/*
1056	 * Workaround: for an unknown reason, the ADC needs to be powered up
1057	 * and down for the first capture to work properly. It seems related to
1058	 * a HW BUG or some kind of behavior not documented in the datasheet.
1059	 */
1060	tmp_reg = snd_soc_component_read(component, AIC32X4_ADCSETUP);
1061	snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg |
1062				AIC32X4_LADC_EN | AIC32X4_RADC_EN);
1063	snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg);
1064
1065	/*
1066	 * Enable the fast charging feature and ensure the needed 40ms ellapsed
1067	 * before using the analog circuits.
1068	 */
1069	snd_soc_component_write(component, AIC32X4_REFPOWERUP,
1070				AIC32X4_REFPOWERUP_40MS);
1071	msleep(40);
1072
1073	return 0;
1074}
1075
1076static int aic32x4_of_xlate_dai_id(struct snd_soc_component *component,
1077				   struct device_node *endpoint)
1078{
1079	/* return dai id 0, whatever the endpoint index */
1080	return 0;
1081}
1082
1083static const struct snd_soc_component_driver soc_component_dev_aic32x4 = {
1084	.probe			= aic32x4_component_probe,
1085	.set_bias_level		= aic32x4_set_bias_level,
1086	.controls		= aic32x4_snd_controls,
1087	.num_controls		= ARRAY_SIZE(aic32x4_snd_controls),
1088	.dapm_widgets		= aic32x4_dapm_widgets,
1089	.num_dapm_widgets	= ARRAY_SIZE(aic32x4_dapm_widgets),
1090	.dapm_routes		= aic32x4_dapm_routes,
1091	.num_dapm_routes	= ARRAY_SIZE(aic32x4_dapm_routes),
1092	.of_xlate_dai_id	= aic32x4_of_xlate_dai_id,
1093	.suspend_bias_off	= 1,
1094	.idle_bias_on		= 1,
1095	.use_pmdown_time	= 1,
1096	.endianness		= 1,
1097};
1098
1099static const struct snd_kcontrol_new aic32x4_tas2505_snd_controls[] = {
1100	SOC_SINGLE_S8_TLV("PCM Playback Volume",
1101			  AIC32X4_LDACVOL, -0x7f, 0x30, tlv_pcm),
1102	SOC_ENUM("DAC Playback PowerTune Switch", l_ptm_enum),
1103
1104	SOC_SINGLE_TLV("HP Driver Gain Volume",
1105			AIC32X4_HPLGAIN, 0, 0x74, 1, tlv_tas_driver_gain),
1106	SOC_SINGLE("HP DAC Playback Switch", AIC32X4_HPLGAIN, 6, 1, 1),
1107
1108	SOC_SINGLE_TLV("Speaker Driver Playback Volume",
1109			TAS2505_SPKVOL1, 0, 0x74, 1, tlv_tas_driver_gain),
1110	SOC_SINGLE_TLV("Speaker Amplifier Playback Volume",
1111			TAS2505_SPKVOL2, 4, 5, 0, tlv_amp_vol),
1112
1113	SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
1114};
1115
1116static const struct snd_kcontrol_new hp_output_mixer_controls[] = {
1117	SOC_DAPM_SINGLE("DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
1118};
1119
1120static const struct snd_soc_dapm_widget aic32x4_tas2505_dapm_widgets[] = {
1121	SND_SOC_DAPM_DAC("DAC", "Playback", AIC32X4_DACSETUP, 7, 0),
1122	SND_SOC_DAPM_MIXER("HP Output Mixer", SND_SOC_NOPM, 0, 0,
1123			   &hp_output_mixer_controls[0],
1124			   ARRAY_SIZE(hp_output_mixer_controls)),
1125	SND_SOC_DAPM_PGA("HP Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
1126
1127	SND_SOC_DAPM_PGA("Speaker Driver", TAS2505_SPK, 1, 0, NULL, 0),
1128
1129	SND_SOC_DAPM_OUTPUT("HP"),
1130	SND_SOC_DAPM_OUTPUT("Speaker"),
1131};
1132
1133static const struct snd_soc_dapm_route aic32x4_tas2505_dapm_routes[] = {
1134	/* Left Output */
1135	{"HP Output Mixer", "DAC Switch", "DAC"},
1136
1137	{"HP Power", NULL, "HP Output Mixer"},
1138	{"HP", NULL, "HP Power"},
1139
1140	{"Speaker Driver", NULL, "DAC"},
1141	{"Speaker", NULL, "Speaker Driver"},
1142};
1143
1144static struct snd_soc_dai_driver aic32x4_tas2505_dai = {
1145	.name = "tas2505-hifi",
1146	.playback = {
1147			 .stream_name = "Playback",
1148			 .channels_min = 1,
1149			 .channels_max = 2,
1150			 .rates = SNDRV_PCM_RATE_8000_96000,
1151			 .formats = AIC32X4_FORMATS,},
1152	.ops = &aic32x4_ops,
1153	.symmetric_rate = 1,
1154};
1155
1156static int aic32x4_tas2505_component_probe(struct snd_soc_component *component)
1157{
1158	struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
1159	u32 tmp_reg;
1160	int ret;
1161
1162	static struct clk_bulk_data clocks[] = {
1163		{ .id = "codec_clkin" },
1164		{ .id = "pll" },
1165		{ .id = "bdiv" },
1166		{ .id = "mdac" },
1167	};
1168
1169	ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
1170	if (ret)
1171		return ret;
1172
1173	if (aic32x4->setup)
1174		aic32x4_setup_gpios(component);
1175
1176	clk_set_parent(clocks[0].clk, clocks[1].clk);
1177	clk_set_parent(clocks[2].clk, clocks[3].clk);
1178
1179	/* Power platform configuration */
1180	if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
1181		snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
1182
1183	tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
1184			AIC32X4_LDOCTLEN : 0;
1185	snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg);
1186
1187	tmp_reg = snd_soc_component_read(component, AIC32X4_CMMODE);
1188	if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
1189		tmp_reg |= AIC32X4_LDOIN_18_36;
1190	if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
1191		tmp_reg |= AIC32X4_LDOIN2HP;
1192	snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg);
1193
1194	/*
1195	 * Enable the fast charging feature and ensure the needed 40ms ellapsed
1196	 * before using the analog circuits.
1197	 */
1198	snd_soc_component_write(component, TAS2505_REFPOWERUP,
1199				AIC32X4_REFPOWERUP_40MS);
1200	msleep(40);
1201
1202	return 0;
1203}
1204
1205static const struct snd_soc_component_driver soc_component_dev_aic32x4_tas2505 = {
1206	.probe			= aic32x4_tas2505_component_probe,
1207	.set_bias_level		= aic32x4_set_bias_level,
1208	.controls		= aic32x4_tas2505_snd_controls,
1209	.num_controls		= ARRAY_SIZE(aic32x4_tas2505_snd_controls),
1210	.dapm_widgets		= aic32x4_tas2505_dapm_widgets,
1211	.num_dapm_widgets	= ARRAY_SIZE(aic32x4_tas2505_dapm_widgets),
1212	.dapm_routes		= aic32x4_tas2505_dapm_routes,
1213	.num_dapm_routes	= ARRAY_SIZE(aic32x4_tas2505_dapm_routes),
1214	.of_xlate_dai_id	= aic32x4_of_xlate_dai_id,
1215	.suspend_bias_off	= 1,
1216	.idle_bias_on		= 1,
1217	.use_pmdown_time	= 1,
1218	.endianness		= 1,
1219};
1220
1221static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4,
1222		struct device_node *np)
1223{
1224	struct aic32x4_setup_data *aic32x4_setup;
1225	int ret;
1226
1227	aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup),
1228							GFP_KERNEL);
1229	if (!aic32x4_setup)
1230		return -ENOMEM;
1231
1232	ret = of_property_match_string(np, "clock-names", "mclk");
1233	if (ret < 0)
1234		return -EINVAL;
1235	aic32x4->mclk_name = of_clk_get_parent_name(np, ret);
1236
1237	aic32x4->swapdacs = false;
1238	aic32x4->micpga_routing = 0;
1239	aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0);
1240
1241	if (of_property_read_u32_array(np, "aic32x4-gpio-func",
1242				aic32x4_setup->gpio_func, 5) >= 0)
1243		aic32x4->setup = aic32x4_setup;
1244	return 0;
1245}
1246
1247static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4)
1248{
1249	regulator_disable(aic32x4->supply_iov);
1250
1251	if (!IS_ERR(aic32x4->supply_ldo))
1252		regulator_disable(aic32x4->supply_ldo);
1253
1254	if (!IS_ERR(aic32x4->supply_dv))
1255		regulator_disable(aic32x4->supply_dv);
1256
1257	if (!IS_ERR(aic32x4->supply_av))
1258		regulator_disable(aic32x4->supply_av);
1259}
1260
1261static int aic32x4_setup_regulators(struct device *dev,
1262		struct aic32x4_priv *aic32x4)
1263{
1264	int ret = 0;
1265
1266	aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin");
1267	aic32x4->supply_iov = devm_regulator_get(dev, "iov");
1268	aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv");
1269	aic32x4->supply_av = devm_regulator_get_optional(dev, "av");
1270
1271	/* Check if the regulator requirements are fulfilled */
1272
1273	if (IS_ERR(aic32x4->supply_iov)) {
1274		dev_err(dev, "Missing supply 'iov'\n");
1275		return PTR_ERR(aic32x4->supply_iov);
1276	}
1277
1278	if (IS_ERR(aic32x4->supply_ldo)) {
1279		if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER)
1280			return -EPROBE_DEFER;
1281
1282		if (IS_ERR(aic32x4->supply_dv)) {
1283			dev_err(dev, "Missing supply 'dv' or 'ldoin'\n");
1284			return PTR_ERR(aic32x4->supply_dv);
1285		}
1286		if (IS_ERR(aic32x4->supply_av)) {
1287			dev_err(dev, "Missing supply 'av' or 'ldoin'\n");
1288			return PTR_ERR(aic32x4->supply_av);
1289		}
1290	} else {
1291		if (PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER)
1292			return -EPROBE_DEFER;
1293		if (PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER)
1294			return -EPROBE_DEFER;
1295	}
1296
1297	ret = regulator_enable(aic32x4->supply_iov);
1298	if (ret) {
1299		dev_err(dev, "Failed to enable regulator iov\n");
1300		return ret;
1301	}
1302
1303	if (!IS_ERR(aic32x4->supply_ldo)) {
1304		ret = regulator_enable(aic32x4->supply_ldo);
1305		if (ret) {
1306			dev_err(dev, "Failed to enable regulator ldo\n");
1307			goto error_ldo;
1308		}
1309	}
1310
1311	if (!IS_ERR(aic32x4->supply_dv)) {
1312		ret = regulator_enable(aic32x4->supply_dv);
1313		if (ret) {
1314			dev_err(dev, "Failed to enable regulator dv\n");
1315			goto error_dv;
1316		}
1317	}
1318
1319	if (!IS_ERR(aic32x4->supply_av)) {
1320		ret = regulator_enable(aic32x4->supply_av);
1321		if (ret) {
1322			dev_err(dev, "Failed to enable regulator av\n");
1323			goto error_av;
1324		}
1325	}
1326
1327	if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av))
1328		aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE;
1329
1330	return 0;
1331
1332error_av:
1333	if (!IS_ERR(aic32x4->supply_dv))
1334		regulator_disable(aic32x4->supply_dv);
1335
1336error_dv:
1337	if (!IS_ERR(aic32x4->supply_ldo))
1338		regulator_disable(aic32x4->supply_ldo);
1339
1340error_ldo:
1341	regulator_disable(aic32x4->supply_iov);
1342	return ret;
1343}
1344
1345int aic32x4_probe(struct device *dev, struct regmap *regmap,
1346		  enum aic32x4_type type)
1347{
1348	struct aic32x4_priv *aic32x4;
1349	struct aic32x4_pdata *pdata = dev->platform_data;
1350	struct device_node *np = dev->of_node;
1351	int ret;
1352
1353	if (IS_ERR(regmap))
1354		return PTR_ERR(regmap);
1355
1356	aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv),
1357				   GFP_KERNEL);
1358	if (aic32x4 == NULL)
1359		return -ENOMEM;
1360
1361	aic32x4->dev = dev;
1362	aic32x4->type = type;
1363
1364	dev_set_drvdata(dev, aic32x4);
1365
1366	if (pdata) {
1367		aic32x4->power_cfg = pdata->power_cfg;
1368		aic32x4->swapdacs = pdata->swapdacs;
1369		aic32x4->micpga_routing = pdata->micpga_routing;
1370		aic32x4->rstn_gpio = pdata->rstn_gpio;
1371		aic32x4->mclk_name = "mclk";
1372	} else if (np) {
1373		ret = aic32x4_parse_dt(aic32x4, np);
1374		if (ret) {
1375			dev_err(dev, "Failed to parse DT node\n");
1376			return ret;
1377		}
1378	} else {
1379		aic32x4->power_cfg = 0;
1380		aic32x4->swapdacs = false;
1381		aic32x4->micpga_routing = 0;
1382		aic32x4->rstn_gpio = -1;
1383		aic32x4->mclk_name = "mclk";
1384	}
1385
1386	if (gpio_is_valid(aic32x4->rstn_gpio)) {
1387		ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio,
1388				GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn");
1389		if (ret != 0)
1390			return ret;
1391	}
1392
1393	ret = aic32x4_setup_regulators(dev, aic32x4);
1394	if (ret) {
1395		dev_err(dev, "Failed to setup regulators\n");
1396		return ret;
1397	}
1398
1399	if (gpio_is_valid(aic32x4->rstn_gpio)) {
1400		ndelay(10);
1401		gpio_set_value_cansleep(aic32x4->rstn_gpio, 1);
1402		mdelay(1);
1403	}
1404
1405	ret = regmap_write(regmap, AIC32X4_RESET, 0x01);
1406	if (ret)
1407		goto err_disable_regulators;
1408
1409	ret = aic32x4_register_clocks(dev, aic32x4->mclk_name);
1410	if (ret)
1411		goto err_disable_regulators;
1412
1413	switch (aic32x4->type) {
1414	case AIC32X4_TYPE_TAS2505:
1415		ret = devm_snd_soc_register_component(dev,
1416			&soc_component_dev_aic32x4_tas2505, &aic32x4_tas2505_dai, 1);
1417		break;
1418	default:
1419		ret = devm_snd_soc_register_component(dev,
1420			&soc_component_dev_aic32x4, &aic32x4_dai, 1);
1421	}
1422
1423	if (ret) {
1424		dev_err(dev, "Failed to register component\n");
1425		goto err_disable_regulators;
1426	}
1427
1428	return 0;
1429
1430err_disable_regulators:
1431	aic32x4_disable_regulators(aic32x4);
1432
1433	return ret;
1434}
1435EXPORT_SYMBOL(aic32x4_probe);
1436
1437void aic32x4_remove(struct device *dev)
1438{
1439	struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev);
1440
1441	aic32x4_disable_regulators(aic32x4);
1442}
1443EXPORT_SYMBOL(aic32x4_remove);
1444
1445MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
1446MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
1447MODULE_LICENSE("GPL");