1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
   4 * Copyright (C) 2013, 2021 Intel Corporation
   5 */
   6
   7#include <linux/atomic.h>
   8#include <linux/bitops.h>
   9#include <linux/bug.h>
  10#include <linux/clk.h>
  11#include <linux/delay.h>
  12#include <linux/device.h>
  13#include <linux/dmaengine.h>
  14#include <linux/err.h>
 
  15#include <linux/gpio/consumer.h>
 
  16#include <linux/interrupt.h>
  17#include <linux/io.h>
  18#include <linux/ioport.h>
  19#include <linux/math64.h>
  20#include <linux/minmax.h>
  21#include <linux/module.h>
 
 
 
  22#include <linux/pm_runtime.h>
  23#include <linux/property.h>
  24#include <linux/slab.h>
  25#include <linux/types.h>
  26
 
  27#include <linux/spi/spi.h>
  28
  29#include "internals.h"
  30#include "spi-pxa2xx.h"
  31
 
 
 
 
 
  32#define TIMOUT_DFLT		1000
  33
  34/*
  35 * For testing SSCR1 changes that require SSP restart, basically
  36 * everything except the service and interrupt enables, the PXA270 developer
  37 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
  38 * list, but the PXA255 developer manual says all bits without really meaning
  39 * the service and interrupt enables.
  40 */
  41#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
  42				| SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
  43				| SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
  44				| SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
  45				| SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
  46				| SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  47
  48#define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF	\
  49				| QUARK_X1000_SSCR1_EFWR	\
  50				| QUARK_X1000_SSCR1_RFT		\
  51				| QUARK_X1000_SSCR1_TFT		\
  52				| SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  53
  54#define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
  55				| SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
  56				| SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
  57				| SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
  58				| CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
  59				| SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  60
  61struct chip_data {
  62	u32 cr1;
  63	u32 dds_rate;
  64	u32 threshold;
  65	u16 lpss_rx_threshold;
  66	u16 lpss_tx_threshold;
  67};
  68
  69#define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE	BIT(24)
  70#define LPSS_CS_CONTROL_SW_MODE			BIT(0)
  71#define LPSS_CS_CONTROL_CS_HIGH			BIT(1)
  72#define LPSS_CAPS_CS_EN_SHIFT			9
  73#define LPSS_CAPS_CS_EN_MASK			(0xf << LPSS_CAPS_CS_EN_SHIFT)
  74
  75#define LPSS_PRIV_CLOCK_GATE 0x38
  76#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
  77#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
  78
  79struct lpss_config {
  80	/* LPSS offset from drv_data->ioaddr */
  81	unsigned offset;
  82	/* Register offsets from drv_data->lpss_base or -1 */
  83	int reg_general;
  84	int reg_ssp;
  85	int reg_cs_ctrl;
  86	int reg_capabilities;
  87	/* FIFO thresholds */
  88	u32 rx_threshold;
  89	u32 tx_threshold_lo;
  90	u32 tx_threshold_hi;
  91	/* Chip select control */
  92	unsigned cs_sel_shift;
  93	unsigned cs_sel_mask;
 
  94	/* Quirks */
  95	unsigned cs_clk_stays_gated : 1;
  96};
  97
  98/* Keep these sorted with enum pxa_ssp_type */
  99static const struct lpss_config lpss_platforms[] = {
 100	{	/* LPSS_LPT_SSP */
 101		.offset = 0x800,
 102		.reg_general = 0x08,
 103		.reg_ssp = 0x0c,
 104		.reg_cs_ctrl = 0x18,
 105		.reg_capabilities = -1,
 106		.rx_threshold = 64,
 107		.tx_threshold_lo = 160,
 108		.tx_threshold_hi = 224,
 109	},
 110	{	/* LPSS_BYT_SSP */
 111		.offset = 0x400,
 112		.reg_general = 0x08,
 113		.reg_ssp = 0x0c,
 114		.reg_cs_ctrl = 0x18,
 115		.reg_capabilities = -1,
 116		.rx_threshold = 64,
 117		.tx_threshold_lo = 160,
 118		.tx_threshold_hi = 224,
 119	},
 120	{	/* LPSS_BSW_SSP */
 121		.offset = 0x400,
 122		.reg_general = 0x08,
 123		.reg_ssp = 0x0c,
 124		.reg_cs_ctrl = 0x18,
 125		.reg_capabilities = -1,
 126		.rx_threshold = 64,
 127		.tx_threshold_lo = 160,
 128		.tx_threshold_hi = 224,
 129		.cs_sel_shift = 2,
 130		.cs_sel_mask = 1 << 2,
 
 131	},
 132	{	/* LPSS_SPT_SSP */
 133		.offset = 0x200,
 134		.reg_general = -1,
 135		.reg_ssp = 0x20,
 136		.reg_cs_ctrl = 0x24,
 137		.reg_capabilities = -1,
 138		.rx_threshold = 1,
 139		.tx_threshold_lo = 32,
 140		.tx_threshold_hi = 56,
 141	},
 142	{	/* LPSS_BXT_SSP */
 143		.offset = 0x200,
 144		.reg_general = -1,
 145		.reg_ssp = 0x20,
 146		.reg_cs_ctrl = 0x24,
 147		.reg_capabilities = 0xfc,
 148		.rx_threshold = 1,
 149		.tx_threshold_lo = 16,
 150		.tx_threshold_hi = 48,
 151		.cs_sel_shift = 8,
 152		.cs_sel_mask = 3 << 8,
 153		.cs_clk_stays_gated = true,
 154	},
 155	{	/* LPSS_CNL_SSP */
 156		.offset = 0x200,
 157		.reg_general = -1,
 158		.reg_ssp = 0x20,
 159		.reg_cs_ctrl = 0x24,
 160		.reg_capabilities = 0xfc,
 161		.rx_threshold = 1,
 162		.tx_threshold_lo = 32,
 163		.tx_threshold_hi = 56,
 164		.cs_sel_shift = 8,
 165		.cs_sel_mask = 3 << 8,
 166		.cs_clk_stays_gated = true,
 167	},
 168};
 169
 170static inline const struct lpss_config
 171*lpss_get_config(const struct driver_data *drv_data)
 172{
 173	return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
 174}
 175
 176static bool is_lpss_ssp(const struct driver_data *drv_data)
 177{
 178	switch (drv_data->ssp_type) {
 179	case LPSS_LPT_SSP:
 180	case LPSS_BYT_SSP:
 181	case LPSS_BSW_SSP:
 182	case LPSS_SPT_SSP:
 183	case LPSS_BXT_SSP:
 184	case LPSS_CNL_SSP:
 185		return true;
 186	default:
 187		return false;
 188	}
 189}
 190
 191static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
 192{
 193	return drv_data->ssp_type == QUARK_X1000_SSP;
 194}
 195
 196static bool is_mmp2_ssp(const struct driver_data *drv_data)
 197{
 198	return drv_data->ssp_type == MMP2_SSP;
 199}
 200
 201static bool is_mrfld_ssp(const struct driver_data *drv_data)
 202{
 203	return drv_data->ssp_type == MRFLD_SSP;
 204}
 205
 206static void pxa2xx_spi_update(const struct driver_data *drv_data, u32 reg, u32 mask, u32 value)
 207{
 208	if ((pxa2xx_spi_read(drv_data, reg) & mask) != value)
 209		pxa2xx_spi_write(drv_data, reg, value & mask);
 210}
 211
 212static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
 213{
 214	switch (drv_data->ssp_type) {
 215	case QUARK_X1000_SSP:
 216		return QUARK_X1000_SSCR1_CHANGE_MASK;
 217	case CE4100_SSP:
 218		return CE4100_SSCR1_CHANGE_MASK;
 219	default:
 220		return SSCR1_CHANGE_MASK;
 221	}
 222}
 223
 224static u32
 225pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
 226{
 227	switch (drv_data->ssp_type) {
 228	case QUARK_X1000_SSP:
 229		return RX_THRESH_QUARK_X1000_DFLT;
 230	case CE4100_SSP:
 231		return RX_THRESH_CE4100_DFLT;
 232	default:
 233		return RX_THRESH_DFLT;
 234	}
 235}
 236
 237static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
 238{
 239	u32 mask;
 240
 241	switch (drv_data->ssp_type) {
 242	case QUARK_X1000_SSP:
 243		mask = QUARK_X1000_SSSR_TFL_MASK;
 244		break;
 245	case CE4100_SSP:
 246		mask = CE4100_SSSR_TFL_MASK;
 247		break;
 248	default:
 249		mask = SSSR_TFL_MASK;
 250		break;
 251	}
 252
 253	return read_SSSR_bits(drv_data, mask) == mask;
 254}
 255
 256static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
 257				     u32 *sccr1_reg)
 258{
 259	u32 mask;
 260
 261	switch (drv_data->ssp_type) {
 262	case QUARK_X1000_SSP:
 263		mask = QUARK_X1000_SSCR1_RFT;
 264		break;
 265	case CE4100_SSP:
 266		mask = CE4100_SSCR1_RFT;
 267		break;
 268	default:
 269		mask = SSCR1_RFT;
 270		break;
 271	}
 272	*sccr1_reg &= ~mask;
 273}
 274
 275static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
 276				   u32 *sccr1_reg, u32 threshold)
 277{
 278	switch (drv_data->ssp_type) {
 279	case QUARK_X1000_SSP:
 280		*sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
 281		break;
 282	case CE4100_SSP:
 283		*sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
 284		break;
 285	default:
 286		*sccr1_reg |= SSCR1_RxTresh(threshold);
 287		break;
 288	}
 289}
 290
 291static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
 292				  u32 clk_div, u8 bits)
 293{
 294	switch (drv_data->ssp_type) {
 295	case QUARK_X1000_SSP:
 296		return clk_div
 297			| QUARK_X1000_SSCR0_Motorola
 298			| QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits);
 299	default:
 300		return clk_div
 301			| SSCR0_Motorola
 302			| SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
 303			| (bits > 16 ? SSCR0_EDSS : 0);
 304	}
 305}
 306
 307/*
 308 * Read and write LPSS SSP private registers. Caller must first check that
 309 * is_lpss_ssp() returns true before these can be called.
 310 */
 311static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
 312{
 313	WARN_ON(!drv_data->lpss_base);
 314	return readl(drv_data->lpss_base + offset);
 315}
 316
 317static void __lpss_ssp_write_priv(struct driver_data *drv_data,
 318				  unsigned offset, u32 value)
 319{
 320	WARN_ON(!drv_data->lpss_base);
 321	writel(value, drv_data->lpss_base + offset);
 322}
 323
 324/*
 325 * lpss_ssp_setup - perform LPSS SSP specific setup
 326 * @drv_data: pointer to the driver private data
 327 *
 328 * Perform LPSS SSP specific setup. This function must be called first if
 329 * one is going to use LPSS SSP private registers.
 330 */
 331static void lpss_ssp_setup(struct driver_data *drv_data)
 332{
 333	const struct lpss_config *config;
 334	u32 value;
 335
 336	config = lpss_get_config(drv_data);
 337	drv_data->lpss_base = drv_data->ssp->mmio_base + config->offset;
 338
 339	/* Enable software chip select control */
 340	value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 341	value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
 342	value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
 343	__lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
 344
 345	/* Enable multiblock DMA transfers */
 346	if (drv_data->controller_info->enable_dma) {
 347		__lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
 348
 349		if (config->reg_general >= 0) {
 350			value = __lpss_ssp_read_priv(drv_data,
 351						     config->reg_general);
 352			value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
 353			__lpss_ssp_write_priv(drv_data,
 354					      config->reg_general, value);
 355		}
 356	}
 357}
 358
 359static void lpss_ssp_select_cs(struct spi_device *spi,
 360			       const struct lpss_config *config)
 361{
 362	struct driver_data *drv_data =
 363		spi_controller_get_devdata(spi->controller);
 364	u32 value, cs;
 365
 366	if (!config->cs_sel_mask)
 367		return;
 368
 369	value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 370
 371	cs = spi_get_chipselect(spi, 0);
 372	cs <<= config->cs_sel_shift;
 373	if (cs != (value & config->cs_sel_mask)) {
 374		/*
 375		 * When switching another chip select output active the
 376		 * output must be selected first and wait 2 ssp_clk cycles
 377		 * before changing state to active. Otherwise a short
 378		 * glitch will occur on the previous chip select since
 379		 * output select is latched but state control is not.
 380		 */
 381		value &= ~config->cs_sel_mask;
 382		value |= cs;
 383		__lpss_ssp_write_priv(drv_data,
 384				      config->reg_cs_ctrl, value);
 385		ndelay(1000000000 /
 386		       (drv_data->controller->max_speed_hz / 2));
 387	}
 388}
 389
 390static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
 391{
 392	struct driver_data *drv_data =
 393		spi_controller_get_devdata(spi->controller);
 394	const struct lpss_config *config;
 395	u32 value;
 396
 397	config = lpss_get_config(drv_data);
 398
 399	if (enable)
 400		lpss_ssp_select_cs(spi, config);
 401
 402	value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 403	if (enable)
 404		value &= ~LPSS_CS_CONTROL_CS_HIGH;
 405	else
 406		value |= LPSS_CS_CONTROL_CS_HIGH;
 407	__lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
 408	if (config->cs_clk_stays_gated) {
 409		u32 clkgate;
 410
 411		/*
 412		 * Changing CS alone when dynamic clock gating is on won't
 413		 * actually flip CS at that time. This ruins SPI transfers
 414		 * that specify delays, or have no data. Toggle the clock mode
 415		 * to force on briefly to poke the CS pin to move.
 416		 */
 417		clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
 418		value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) |
 419			LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON;
 420
 421		__lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
 422		__lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
 423	}
 424}
 425
 426static void cs_assert(struct spi_device *spi)
 427{
 428	struct driver_data *drv_data =
 429		spi_controller_get_devdata(spi->controller);
 430
 431	if (drv_data->ssp_type == CE4100_SSP) {
 432		pxa2xx_spi_write(drv_data, SSSR, spi_get_chipselect(spi, 0));
 433		return;
 434	}
 435
 436	if (is_lpss_ssp(drv_data))
 437		lpss_ssp_cs_control(spi, true);
 438}
 439
 440static void cs_deassert(struct spi_device *spi)
 441{
 442	struct driver_data *drv_data =
 443		spi_controller_get_devdata(spi->controller);
 444	unsigned long timeout;
 445
 446	if (drv_data->ssp_type == CE4100_SSP)
 447		return;
 448
 449	/* Wait until SSP becomes idle before deasserting the CS */
 450	timeout = jiffies + msecs_to_jiffies(10);
 451	while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
 452	       !time_after(jiffies, timeout))
 453		cpu_relax();
 454
 455	if (is_lpss_ssp(drv_data))
 456		lpss_ssp_cs_control(spi, false);
 457}
 458
 459static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level)
 460{
 461	if (level)
 462		cs_deassert(spi);
 463	else
 464		cs_assert(spi);
 465}
 466
 467int pxa2xx_spi_flush(struct driver_data *drv_data)
 468{
 469	unsigned long limit = loops_per_jiffy << 1;
 470
 471	do {
 472		while (read_SSSR_bits(drv_data, SSSR_RNE))
 473			pxa2xx_spi_read(drv_data, SSDR);
 474	} while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
 475	write_SSSR_CS(drv_data, SSSR_ROR);
 476
 477	return limit;
 478}
 479
 480static void pxa2xx_spi_off(struct driver_data *drv_data)
 481{
 482	/* On MMP, disabling SSE seems to corrupt the Rx FIFO */
 483	if (is_mmp2_ssp(drv_data))
 484		return;
 485
 486	pxa_ssp_disable(drv_data->ssp);
 487}
 488
 489static int null_writer(struct driver_data *drv_data)
 490{
 491	u8 n_bytes = drv_data->n_bytes;
 492
 493	if (pxa2xx_spi_txfifo_full(drv_data)
 494		|| (drv_data->tx == drv_data->tx_end))
 495		return 0;
 496
 497	pxa2xx_spi_write(drv_data, SSDR, 0);
 498	drv_data->tx += n_bytes;
 499
 500	return 1;
 501}
 502
 503static int null_reader(struct driver_data *drv_data)
 504{
 505	u8 n_bytes = drv_data->n_bytes;
 506
 507	while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
 508		pxa2xx_spi_read(drv_data, SSDR);
 509		drv_data->rx += n_bytes;
 510	}
 511
 512	return drv_data->rx == drv_data->rx_end;
 513}
 514
 515static int u8_writer(struct driver_data *drv_data)
 516{
 517	if (pxa2xx_spi_txfifo_full(drv_data)
 518		|| (drv_data->tx == drv_data->tx_end))
 519		return 0;
 520
 521	pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
 522	++drv_data->tx;
 523
 524	return 1;
 525}
 526
 527static int u8_reader(struct driver_data *drv_data)
 528{
 529	while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
 530		*(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 531		++drv_data->rx;
 532	}
 533
 534	return drv_data->rx == drv_data->rx_end;
 535}
 536
 537static int u16_writer(struct driver_data *drv_data)
 538{
 539	if (pxa2xx_spi_txfifo_full(drv_data)
 540		|| (drv_data->tx == drv_data->tx_end))
 541		return 0;
 542
 543	pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
 544	drv_data->tx += 2;
 545
 546	return 1;
 547}
 548
 549static int u16_reader(struct driver_data *drv_data)
 550{
 551	while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
 552		*(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 553		drv_data->rx += 2;
 554	}
 555
 556	return drv_data->rx == drv_data->rx_end;
 557}
 558
 559static int u32_writer(struct driver_data *drv_data)
 560{
 561	if (pxa2xx_spi_txfifo_full(drv_data)
 562		|| (drv_data->tx == drv_data->tx_end))
 563		return 0;
 564
 565	pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
 566	drv_data->tx += 4;
 567
 568	return 1;
 569}
 570
 571static int u32_reader(struct driver_data *drv_data)
 572{
 573	while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
 574		*(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 575		drv_data->rx += 4;
 576	}
 577
 578	return drv_data->rx == drv_data->rx_end;
 579}
 580
 581static void reset_sccr1(struct driver_data *drv_data)
 582{
 583	u32 mask = drv_data->int_cr1 | drv_data->dma_cr1, threshold;
 584	struct chip_data *chip;
 585
 586	if (drv_data->controller->cur_msg) {
 587		chip = spi_get_ctldata(drv_data->controller->cur_msg->spi);
 588		threshold = chip->threshold;
 589	} else {
 590		threshold = 0;
 591	}
 592
 593	switch (drv_data->ssp_type) {
 594	case QUARK_X1000_SSP:
 595		mask |= QUARK_X1000_SSCR1_RFT;
 596		break;
 597	case CE4100_SSP:
 598		mask |= CE4100_SSCR1_RFT;
 599		break;
 600	default:
 601		mask |= SSCR1_RFT;
 602		break;
 603	}
 604
 605	pxa2xx_spi_update(drv_data, SSCR1, mask, threshold);
 606}
 607
 608static void int_stop_and_reset(struct driver_data *drv_data)
 609{
 610	/* Clear and disable interrupts */
 611	write_SSSR_CS(drv_data, drv_data->clear_sr);
 612	reset_sccr1(drv_data);
 613	if (pxa25x_ssp_comp(drv_data))
 614		return;
 615
 616	pxa2xx_spi_write(drv_data, SSTO, 0);
 617}
 618
 619static void int_error_stop(struct driver_data *drv_data, const char *msg, int err)
 620{
 621	int_stop_and_reset(drv_data);
 622	pxa2xx_spi_flush(drv_data);
 623	pxa2xx_spi_off(drv_data);
 624
 625	dev_err(drv_data->ssp->dev, "%s\n", msg);
 626
 627	drv_data->controller->cur_msg->status = err;
 628	spi_finalize_current_transfer(drv_data->controller);
 629}
 630
 631static void int_transfer_complete(struct driver_data *drv_data)
 632{
 633	int_stop_and_reset(drv_data);
 634
 635	spi_finalize_current_transfer(drv_data->controller);
 636}
 637
 638static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
 639{
 640	u32 irq_status;
 641
 642	irq_status = read_SSSR_bits(drv_data, drv_data->mask_sr);
 643	if (!(pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE))
 644		irq_status &= ~SSSR_TFS;
 645
 646	if (irq_status & SSSR_ROR) {
 647		int_error_stop(drv_data, "interrupt_transfer: FIFO overrun", -EIO);
 648		return IRQ_HANDLED;
 649	}
 650
 651	if (irq_status & SSSR_TUR) {
 652		int_error_stop(drv_data, "interrupt_transfer: FIFO underrun", -EIO);
 653		return IRQ_HANDLED;
 654	}
 655
 656	if (irq_status & SSSR_TINT) {
 657		pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
 658		if (drv_data->read(drv_data)) {
 659			int_transfer_complete(drv_data);
 660			return IRQ_HANDLED;
 661		}
 662	}
 663
 664	/* Drain Rx FIFO, Fill Tx FIFO and prevent overruns */
 665	do {
 666		if (drv_data->read(drv_data)) {
 667			int_transfer_complete(drv_data);
 668			return IRQ_HANDLED;
 669		}
 670	} while (drv_data->write(drv_data));
 671
 672	if (drv_data->read(drv_data)) {
 673		int_transfer_complete(drv_data);
 674		return IRQ_HANDLED;
 675	}
 676
 677	if (drv_data->tx == drv_data->tx_end) {
 678		u32 bytes_left;
 679		u32 sccr1_reg;
 680
 681		sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
 682		sccr1_reg &= ~SSCR1_TIE;
 683
 684		/*
 685		 * PXA25x_SSP has no timeout, set up Rx threshold for
 686		 * the remaining Rx bytes.
 687		 */
 688		if (pxa25x_ssp_comp(drv_data)) {
 689			u32 rx_thre;
 690
 691			pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
 692
 693			bytes_left = drv_data->rx_end - drv_data->rx;
 694			switch (drv_data->n_bytes) {
 695			case 4:
 696				bytes_left >>= 2;
 697				break;
 698			case 2:
 699				bytes_left >>= 1;
 700				break;
 701			}
 702
 703			rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
 704			if (rx_thre > bytes_left)
 705				rx_thre = bytes_left;
 706
 707			pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
 708		}
 709		pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 710	}
 711
 712	/* We did something */
 713	return IRQ_HANDLED;
 714}
 715
 716static void handle_bad_msg(struct driver_data *drv_data)
 717{
 718	int_stop_and_reset(drv_data);
 719	pxa2xx_spi_off(drv_data);
 720
 721	dev_err(drv_data->ssp->dev, "bad message state in interrupt handler\n");
 722}
 723
 724static irqreturn_t ssp_int(int irq, void *dev_id)
 725{
 726	struct driver_data *drv_data = dev_id;
 727	u32 sccr1_reg;
 728	u32 mask = drv_data->mask_sr;
 729	u32 status;
 730
 731	/*
 732	 * The IRQ might be shared with other peripherals so we must first
 733	 * check that are we RPM suspended or not. If we are we assume that
 734	 * the IRQ was not for us (we shouldn't be RPM suspended when the
 735	 * interrupt is enabled).
 736	 */
 737	if (pm_runtime_suspended(drv_data->ssp->dev))
 738		return IRQ_NONE;
 739
 740	/*
 741	 * If the device is not yet in RPM suspended state and we get an
 742	 * interrupt that is meant for another device, check if status bits
 743	 * are all set to one. That means that the device is already
 744	 * powered off.
 745	 */
 746	status = pxa2xx_spi_read(drv_data, SSSR);
 747	if (status == ~0)
 748		return IRQ_NONE;
 749
 750	sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
 751
 752	/* Ignore possible writes if we don't need to write */
 753	if (!(sccr1_reg & SSCR1_TIE))
 754		mask &= ~SSSR_TFS;
 755
 756	/* Ignore RX timeout interrupt if it is disabled */
 757	if (!(sccr1_reg & SSCR1_TINTE))
 758		mask &= ~SSSR_TINT;
 759
 760	if (!(status & mask))
 761		return IRQ_NONE;
 762
 763	pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
 764	pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 765
 766	if (!drv_data->controller->cur_msg) {
 767		handle_bad_msg(drv_data);
 768		/* Never fail */
 769		return IRQ_HANDLED;
 770	}
 771
 772	return drv_data->transfer_handler(drv_data);
 773}
 774
 775/*
 776 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
 777 * input frequency by fractions of 2^24. It also has a divider by 5.
 778 *
 779 * There are formulas to get baud rate value for given input frequency and
 780 * divider parameters, such as DDS_CLK_RATE and SCR:
 781 *
 782 * Fsys = 200MHz
 783 *
 784 * Fssp = Fsys * DDS_CLK_RATE / 2^24			(1)
 785 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1))		(2)
 786 *
 787 * DDS_CLK_RATE either 2^n or 2^n / 5.
 788 * SCR is in range 0 .. 255
 789 *
 790 * Divisor = 5^i * 2^j * 2 * k
 791 *       i = [0, 1]      i = 1 iff j = 0 or j > 3
 792 *       j = [0, 23]     j = 0 iff i = 1
 793 *       k = [1, 256]
 794 * Special case: j = 0, i = 1: Divisor = 2 / 5
 795 *
 796 * Accordingly to the specification the recommended values for DDS_CLK_RATE
 797 * are:
 798 *	Case 1:		2^n, n = [0, 23]
 799 *	Case 2:		2^24 * 2 / 5 (0x666666)
 800 *	Case 3:		less than or equal to 2^24 / 5 / 16 (0x33333)
 801 *
 802 * In all cases the lowest possible value is better.
 803 *
 804 * The function calculates parameters for all cases and chooses the one closest
 805 * to the asked baud rate.
 806 */
 807static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
 808{
 809	unsigned long xtal = 200000000;
 810	unsigned long fref = xtal / 2;		/* mandatory division by 2,
 811						   see (2) */
 812						/* case 3 */
 813	unsigned long fref1 = fref / 2;		/* case 1 */
 814	unsigned long fref2 = fref * 2 / 5;	/* case 2 */
 815	unsigned long scale;
 816	unsigned long q, q1, q2;
 817	long r, r1, r2;
 818	u32 mul;
 819
 820	/* Case 1 */
 821
 822	/* Set initial value for DDS_CLK_RATE */
 823	mul = (1 << 24) >> 1;
 824
 825	/* Calculate initial quot */
 826	q1 = DIV_ROUND_UP(fref1, rate);
 827
 828	/* Scale q1 if it's too big */
 829	if (q1 > 256) {
 830		/* Scale q1 to range [1, 512] */
 831		scale = fls_long(q1 - 1);
 832		if (scale > 9) {
 833			q1 >>= scale - 9;
 834			mul >>= scale - 9;
 835		}
 836
 837		/* Round the result if we have a remainder */
 838		q1 += q1 & 1;
 839	}
 840
 841	/* Decrease DDS_CLK_RATE as much as we can without loss in precision */
 842	scale = __ffs(q1);
 843	q1 >>= scale;
 844	mul >>= scale;
 845
 846	/* Get the remainder */
 847	r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
 848
 849	/* Case 2 */
 850
 851	q2 = DIV_ROUND_UP(fref2, rate);
 852	r2 = abs(fref2 / q2 - rate);
 853
 854	/*
 855	 * Choose the best between two: less remainder we have the better. We
 856	 * can't go case 2 if q2 is greater than 256 since SCR register can
 857	 * hold only values 0 .. 255.
 858	 */
 859	if (r2 >= r1 || q2 > 256) {
 860		/* case 1 is better */
 861		r = r1;
 862		q = q1;
 863	} else {
 864		/* case 2 is better */
 865		r = r2;
 866		q = q2;
 867		mul = (1 << 24) * 2 / 5;
 868	}
 869
 870	/* Check case 3 only if the divisor is big enough */
 871	if (fref / rate >= 80) {
 872		u64 fssp;
 873		u32 m;
 874
 875		/* Calculate initial quot */
 876		q1 = DIV_ROUND_UP(fref, rate);
 877		m = (1 << 24) / q1;
 878
 879		/* Get the remainder */
 880		fssp = (u64)fref * m;
 881		do_div(fssp, 1 << 24);
 882		r1 = abs(fssp - rate);
 883
 884		/* Choose this one if it suits better */
 885		if (r1 < r) {
 886			/* case 3 is better */
 887			q = 1;
 888			mul = m;
 889		}
 890	}
 891
 892	*dds = mul;
 893	return q - 1;
 894}
 895
 896static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
 897{
 898	unsigned long ssp_clk = drv_data->controller->max_speed_hz;
 899	const struct ssp_device *ssp = drv_data->ssp;
 900
 901	rate = min_t(int, ssp_clk, rate);
 902
 903	/*
 904	 * Calculate the divisor for the SCR (Serial Clock Rate), avoiding
 905	 * that the SSP transmission rate can be greater than the device rate.
 906	 */
 907	if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
 908		return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff;
 909	else
 910		return (DIV_ROUND_UP(ssp_clk, rate) - 1)  & 0xfff;
 911}
 912
 913static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
 914					   int rate)
 915{
 916	struct chip_data *chip =
 917		spi_get_ctldata(drv_data->controller->cur_msg->spi);
 918	unsigned int clk_div;
 919
 920	switch (drv_data->ssp_type) {
 921	case QUARK_X1000_SSP:
 922		clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
 923		break;
 924	default:
 925		clk_div = ssp_get_clk_div(drv_data, rate);
 926		break;
 927	}
 928	return clk_div << 8;
 929}
 930
 931static bool pxa2xx_spi_can_dma(struct spi_controller *controller,
 932			       struct spi_device *spi,
 933			       struct spi_transfer *xfer)
 934{
 935	struct driver_data *drv_data = spi_controller_get_devdata(controller);
 936
 937	return drv_data->controller_info->enable_dma &&
 938	       xfer->len <= MAX_DMA_LEN &&
 939	       xfer->len >= drv_data->controller_info->dma_burst_size;
 940}
 941
 942static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
 943				   struct spi_device *spi,
 944				   struct spi_transfer *transfer)
 945{
 946	struct driver_data *drv_data = spi_controller_get_devdata(controller);
 
 947	struct chip_data *chip = spi_get_ctldata(spi);
 
 
 948	u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
 949	u32 dma_thresh;
 950	u32 clk_div;
 951	u8 bits;
 952	u32 speed;
 953	u32 cr0;
 954	u32 cr1;
 955	int err;
 956	int dma_mapped;
 957
 958	/* Check if we can DMA this transfer */
 959	if (transfer->len > MAX_DMA_LEN && drv_data->controller_info->enable_dma) {
 
 
 
 
 
 
 
 
 
 
 960		/* Warn ... we force this to PIO mode */
 961		dev_warn_ratelimited(&spi->dev,
 962				     "DMA disabled for transfer length %u greater than %d\n",
 963				     transfer->len, MAX_DMA_LEN);
 964	}
 965
 966	/* Setup the transfer state based on the type of transfer */
 967	if (pxa2xx_spi_flush(drv_data) == 0) {
 968		dev_err(&spi->dev, "Flush failed\n");
 969		return -EIO;
 970	}
 971	drv_data->tx = (void *)transfer->tx_buf;
 972	drv_data->tx_end = drv_data->tx + transfer->len;
 973	drv_data->rx = transfer->rx_buf;
 974	drv_data->rx_end = drv_data->rx + transfer->len;
 975
 976	/* Change speed and bit per word on a per transfer */
 977	bits = transfer->bits_per_word;
 978	speed = transfer->speed_hz;
 979
 980	clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
 981
 982	if (bits <= 8) {
 983		drv_data->n_bytes = 1;
 984		drv_data->read = drv_data->rx ? u8_reader : null_reader;
 985		drv_data->write = drv_data->tx ? u8_writer : null_writer;
 986	} else if (bits <= 16) {
 987		drv_data->n_bytes = 2;
 988		drv_data->read = drv_data->rx ? u16_reader : null_reader;
 989		drv_data->write = drv_data->tx ? u16_writer : null_writer;
 990	} else if (bits <= 32) {
 991		drv_data->n_bytes = 4;
 992		drv_data->read = drv_data->rx ? u32_reader : null_reader;
 993		drv_data->write = drv_data->tx ? u32_writer : null_writer;
 994	}
 
 
 
 
 
 
 
 
 
 
 
 
 995
 996	dma_thresh = SSCR1_RxTresh(RX_THRESH_DFLT) | SSCR1_TxTresh(TX_THRESH_DFLT);
 997	dma_mapped = spi_xfer_is_dma_mapped(controller, spi, transfer);
 
 998	if (dma_mapped) {
 
 999		/* Ensure we have the correct interrupt handler */
1000		drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1001
1002		err = pxa2xx_spi_dma_prepare(drv_data, transfer);
1003		if (err)
1004			return err;
1005
1006		/* Clear status and start DMA engine */
1007		cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1008		pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1009
1010		pxa2xx_spi_dma_start(drv_data);
1011	} else {
1012		/* Ensure we have the correct interrupt handler	*/
1013		drv_data->transfer_handler = interrupt_transfer;
1014
1015		/* Clear status  */
1016		cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1017		write_SSSR_CS(drv_data, drv_data->clear_sr);
1018	}
1019
1020	/* NOTE:  PXA25x_SSP _could_ use external clocking ... */
1021	cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1022	if (!pxa25x_ssp_comp(drv_data))
1023		dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1024			controller->max_speed_hz
1025				/ (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1026			dma_mapped ? "DMA" : "PIO");
1027	else
1028		dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1029			controller->max_speed_hz / 2
1030				/ (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1031			dma_mapped ? "DMA" : "PIO");
1032
1033	if (is_lpss_ssp(drv_data)) {
1034		pxa2xx_spi_update(drv_data, SSIRF, GENMASK(7, 0), chip->lpss_rx_threshold);
1035		pxa2xx_spi_update(drv_data, SSITF, GENMASK(15, 0), chip->lpss_tx_threshold);
1036	}
1037
1038	if (is_mrfld_ssp(drv_data)) {
1039		u32 mask = SFIFOTT_RFT | SFIFOTT_TFT;
1040		u32 thresh = 0;
1041
1042		thresh |= SFIFOTT_RxThresh(chip->lpss_rx_threshold);
1043		thresh |= SFIFOTT_TxThresh(chip->lpss_tx_threshold);
1044
1045		pxa2xx_spi_update(drv_data, SFIFOTT, mask, thresh);
1046	}
1047
1048	if (is_quark_x1000_ssp(drv_data))
1049		pxa2xx_spi_update(drv_data, DDS_RATE, GENMASK(23, 0), chip->dds_rate);
1050
1051	/* Stop the SSP */
1052	if (!is_mmp2_ssp(drv_data))
1053		pxa_ssp_disable(drv_data->ssp);
1054
1055	if (!pxa25x_ssp_comp(drv_data))
1056		pxa2xx_spi_write(drv_data, SSTO, TIMOUT_DFLT);
1057
1058	/* First set CR1 without interrupt and service enables */
1059	pxa2xx_spi_update(drv_data, SSCR1, change_mask, cr1);
1060
1061	/* See if we need to reload the configuration registers */
1062	pxa2xx_spi_update(drv_data, SSCR0, GENMASK(31, 0), cr0);
1063
1064	/* Restart the SSP */
1065	pxa_ssp_enable(drv_data->ssp);
1066
1067	if (is_mmp2_ssp(drv_data)) {
1068		u8 tx_level = read_SSSR_bits(drv_data, SSSR_TFL_MASK) >> 8;
1069
1070		if (tx_level) {
1071			/* On MMP2, flipping SSE doesn't to empty Tx FIFO. */
1072			dev_warn(&spi->dev, "%u bytes of garbage in Tx FIFO!\n", tx_level);
1073			if (tx_level > transfer->len)
1074				tx_level = transfer->len;
1075			drv_data->tx += tx_level;
1076		}
1077	}
1078
1079	if (spi_controller_is_target(controller)) {
1080		while (drv_data->write(drv_data))
1081			;
1082		if (drv_data->gpiod_ready) {
1083			gpiod_set_value(drv_data->gpiod_ready, 1);
1084			udelay(1);
1085			gpiod_set_value(drv_data->gpiod_ready, 0);
1086		}
1087	}
1088
1089	/*
1090	 * Release the data by enabling service requests and interrupts,
1091	 * without changing any mode bits.
1092	 */
1093	pxa2xx_spi_write(drv_data, SSCR1, cr1);
1094
1095	return 1;
1096}
1097
1098static int pxa2xx_spi_target_abort(struct spi_controller *controller)
1099{
1100	struct driver_data *drv_data = spi_controller_get_devdata(controller);
1101
1102	int_error_stop(drv_data, "transfer aborted", -EINTR);
1103
1104	return 0;
1105}
1106
1107static void pxa2xx_spi_handle_err(struct spi_controller *controller,
1108				 struct spi_message *msg)
1109{
1110	struct driver_data *drv_data = spi_controller_get_devdata(controller);
1111
1112	int_stop_and_reset(drv_data);
1113
1114	/* Disable the SSP */
1115	pxa2xx_spi_off(drv_data);
1116
1117	/*
1118	 * Stop the DMA if running. Note DMA callback handler may have unset
1119	 * the dma_running already, which is fine as stopping is not needed
1120	 * then but we shouldn't rely this flag for anything else than
1121	 * stopping. For instance to differentiate between PIO and DMA
1122	 * transfers.
1123	 */
1124	if (atomic_read(&drv_data->dma_running))
1125		pxa2xx_spi_dma_stop(drv_data);
1126}
1127
1128static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
1129{
1130	struct driver_data *drv_data = spi_controller_get_devdata(controller);
1131
1132	/* Disable the SSP now */
1133	pxa2xx_spi_off(drv_data);
1134
1135	return 0;
1136}
1137
1138static int setup(struct spi_device *spi)
1139{
 
1140	struct chip_data *chip;
1141	const struct lpss_config *config;
1142	struct driver_data *drv_data =
1143		spi_controller_get_devdata(spi->controller);
1144	uint tx_thres, tx_hi_thres, rx_thres;
1145
1146	switch (drv_data->ssp_type) {
1147	case QUARK_X1000_SSP:
1148		tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1149		tx_hi_thres = 0;
1150		rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1151		break;
1152	case MRFLD_SSP:
1153		tx_thres = TX_THRESH_MRFLD_DFLT;
1154		tx_hi_thres = 0;
1155		rx_thres = RX_THRESH_MRFLD_DFLT;
1156		break;
1157	case CE4100_SSP:
1158		tx_thres = TX_THRESH_CE4100_DFLT;
1159		tx_hi_thres = 0;
1160		rx_thres = RX_THRESH_CE4100_DFLT;
1161		break;
1162	case LPSS_LPT_SSP:
1163	case LPSS_BYT_SSP:
1164	case LPSS_BSW_SSP:
1165	case LPSS_SPT_SSP:
1166	case LPSS_BXT_SSP:
1167	case LPSS_CNL_SSP:
1168		config = lpss_get_config(drv_data);
1169		tx_thres = config->tx_threshold_lo;
1170		tx_hi_thres = config->tx_threshold_hi;
1171		rx_thres = config->rx_threshold;
1172		break;
1173	default:
1174		tx_hi_thres = 0;
1175		if (spi_controller_is_target(drv_data->controller)) {
1176			tx_thres = 1;
1177			rx_thres = 2;
1178		} else {
1179			tx_thres = TX_THRESH_DFLT;
1180			rx_thres = RX_THRESH_DFLT;
1181		}
1182		break;
1183	}
1184
1185	if (drv_data->ssp_type == CE4100_SSP) {
1186		if (spi_get_chipselect(spi, 0) > 4) {
1187			dev_err(&spi->dev, "failed setup: cs number must not be > 4.\n");
1188			return -EINVAL;
1189		}
1190	}
1191
1192	/* Only allocate on the first setup */
1193	chip = spi_get_ctldata(spi);
1194	if (!chip) {
1195		chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1196		if (!chip)
1197			return -ENOMEM;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1198	}
1199
1200	chip->cr1 = 0;
1201	if (spi_controller_is_target(drv_data->controller)) {
1202		chip->cr1 |= SSCR1_SCFR;
1203		chip->cr1 |= SSCR1_SCLKDIR;
1204		chip->cr1 |= SSCR1_SFRMDIR;
1205		chip->cr1 |= SSCR1_SPH;
1206	}
1207
1208	if (is_lpss_ssp(drv_data)) {
1209		chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1210		chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) |
1211					  SSITF_TxHiThresh(tx_hi_thres);
1212	}
1213
1214	if (is_mrfld_ssp(drv_data)) {
1215		chip->lpss_rx_threshold = rx_thres;
1216		chip->lpss_tx_threshold = tx_thres;
1217	}
1218
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1219	switch (drv_data->ssp_type) {
1220	case QUARK_X1000_SSP:
1221		chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1222				   & QUARK_X1000_SSCR1_RFT)
1223				   | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1224				   & QUARK_X1000_SSCR1_TFT);
1225		break;
1226	case CE4100_SSP:
1227		chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
1228			(CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
1229		break;
1230	default:
1231		chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1232			(SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1233		break;
1234	}
1235
1236	chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1237	chip->cr1 |= ((spi->mode & SPI_CPHA) ? SSCR1_SPH : 0) |
1238		     ((spi->mode & SPI_CPOL) ? SSCR1_SPO : 0);
1239
1240	if (spi->mode & SPI_LOOP)
1241		chip->cr1 |= SSCR1_LBM;
1242
1243	spi_set_ctldata(spi, chip);
1244
1245	return 0;
1246}
1247
1248static void cleanup(struct spi_device *spi)
1249{
1250	struct chip_data *chip = spi_get_ctldata(spi);
1251
1252	kfree(chip);
1253}
1254
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1255static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller,
1256				      unsigned int cs)
1257{
1258	struct driver_data *drv_data = spi_controller_get_devdata(controller);
1259
1260	switch (drv_data->ssp_type) {
1261	/*
1262	 * For some of Intel Atoms the ACPI DeviceSelection used by the Windows
1263	 * driver starts from 1 instead of 0 so translate it here to match what
1264	 * Linux expects.
1265	 */
1266	case LPSS_BYT_SSP:
1267	case LPSS_BSW_SSP:
1268		return cs - 1;
 
1269
1270	default:
1271		return cs;
 
1272	}
 
 
1273}
1274
1275static size_t pxa2xx_spi_max_dma_transfer_size(struct spi_device *spi)
1276{
1277	return MAX_DMA_LEN;
1278}
1279
1280int pxa2xx_spi_probe(struct device *dev, struct ssp_device *ssp,
1281		     struct pxa2xx_spi_controller *platform_info)
1282{
 
 
1283	struct spi_controller *controller;
1284	struct driver_data *drv_data;
 
1285	const struct lpss_config *config;
1286	int status;
1287	u32 tmp;
1288
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1289	if (platform_info->is_target)
1290		controller = devm_spi_alloc_target(dev, sizeof(*drv_data));
1291	else
1292		controller = devm_spi_alloc_host(dev, sizeof(*drv_data));
1293	if (!controller)
1294		return dev_err_probe(dev, -ENOMEM, "cannot alloc spi_controller\n");
1295
 
 
 
 
 
1296	drv_data = spi_controller_get_devdata(controller);
1297	drv_data->controller = controller;
1298	drv_data->controller_info = platform_info;
1299	drv_data->ssp = ssp;
1300
1301	device_set_node(&controller->dev, dev_fwnode(dev));
1302
1303	/* The spi->mode bits understood by this driver: */
1304	controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1305
1306	controller->bus_num = ssp->port_id;
1307	controller->dma_alignment = DMA_ALIGNMENT;
1308	controller->cleanup = cleanup;
1309	controller->setup = setup;
1310	controller->set_cs = pxa2xx_spi_set_cs;
1311	controller->transfer_one = pxa2xx_spi_transfer_one;
1312	controller->target_abort = pxa2xx_spi_target_abort;
1313	controller->handle_err = pxa2xx_spi_handle_err;
1314	controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1315	controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1316	controller->auto_runtime_pm = true;
1317	controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
1318
1319	drv_data->ssp_type = ssp->type;
1320
1321	if (pxa25x_ssp_comp(drv_data)) {
1322		switch (drv_data->ssp_type) {
1323		case QUARK_X1000_SSP:
1324			controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1325			break;
1326		default:
1327			controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1328			break;
1329		}
1330
1331		drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1332		drv_data->dma_cr1 = 0;
1333		drv_data->clear_sr = SSSR_ROR;
1334		drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1335	} else {
1336		controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1337		drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1338		drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1339		drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1340		drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS
1341						| SSSR_ROR | SSSR_TUR;
1342	}
1343
1344	status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1345			drv_data);
1346	if (status < 0)
1347		return dev_err_probe(dev, status, "cannot get IRQ %d\n", ssp->irq);
 
 
1348
1349	/* Setup DMA if requested */
1350	if (platform_info->enable_dma) {
1351		status = pxa2xx_spi_dma_setup(drv_data);
1352		if (status) {
1353			dev_warn(dev, "no DMA channels available, using PIO\n");
1354			platform_info->enable_dma = false;
1355		} else {
1356			controller->can_dma = pxa2xx_spi_can_dma;
1357			controller->max_dma_len = MAX_DMA_LEN;
1358			controller->max_transfer_size =
1359				pxa2xx_spi_max_dma_transfer_size;
1360
1361			dev_dbg(dev, "DMA burst size set to %u\n", platform_info->dma_burst_size);
1362		}
1363	}
1364
1365	/* Enable SOC clock */
1366	status = clk_prepare_enable(ssp->clk);
1367	if (status)
1368		goto out_error_dma_irq_alloc;
1369
1370	controller->max_speed_hz = clk_get_rate(ssp->clk);
1371	/*
1372	 * Set minimum speed for all other platforms than Intel Quark which is
1373	 * able do under 1 Hz transfers.
1374	 */
1375	if (!pxa25x_ssp_comp(drv_data))
1376		controller->min_speed_hz =
1377			DIV_ROUND_UP(controller->max_speed_hz, 4096);
1378	else if (!is_quark_x1000_ssp(drv_data))
1379		controller->min_speed_hz =
1380			DIV_ROUND_UP(controller->max_speed_hz, 512);
1381
1382	pxa_ssp_disable(ssp);
1383
1384	/* Load default SSP configuration */
1385	switch (drv_data->ssp_type) {
1386	case QUARK_X1000_SSP:
1387		tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1388		      QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1389		pxa2xx_spi_write(drv_data, SSCR1, tmp);
1390
1391		/* Using the Motorola SPI protocol and use 8 bit frame */
1392		tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
1393		pxa2xx_spi_write(drv_data, SSCR0, tmp);
1394		break;
1395	case CE4100_SSP:
1396		tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
1397		      CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
1398		pxa2xx_spi_write(drv_data, SSCR1, tmp);
1399		tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1400		pxa2xx_spi_write(drv_data, SSCR0, tmp);
1401		break;
1402	default:
1403
1404		if (spi_controller_is_target(controller)) {
1405			tmp = SSCR1_SCFR |
1406			      SSCR1_SCLKDIR |
1407			      SSCR1_SFRMDIR |
1408			      SSCR1_RxTresh(2) |
1409			      SSCR1_TxTresh(1) |
1410			      SSCR1_SPH;
1411		} else {
1412			tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1413			      SSCR1_TxTresh(TX_THRESH_DFLT);
1414		}
1415		pxa2xx_spi_write(drv_data, SSCR1, tmp);
1416		tmp = SSCR0_Motorola | SSCR0_DataSize(8);
1417		if (!spi_controller_is_target(controller))
1418			tmp |= SSCR0_SCR(2);
1419		pxa2xx_spi_write(drv_data, SSCR0, tmp);
1420		break;
1421	}
1422
1423	if (!pxa25x_ssp_comp(drv_data))
1424		pxa2xx_spi_write(drv_data, SSTO, 0);
1425
1426	if (!is_quark_x1000_ssp(drv_data))
1427		pxa2xx_spi_write(drv_data, SSPSP, 0);
1428
1429	if (is_lpss_ssp(drv_data)) {
1430		lpss_ssp_setup(drv_data);
1431		config = lpss_get_config(drv_data);
1432		if (config->reg_capabilities >= 0) {
1433			tmp = __lpss_ssp_read_priv(drv_data,
1434						   config->reg_capabilities);
1435			tmp &= LPSS_CAPS_CS_EN_MASK;
1436			tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1437			platform_info->num_chipselect = ffz(tmp);
 
 
1438		}
1439	}
1440	controller->num_chipselect = platform_info->num_chipselect;
1441	controller->use_gpio_descriptors = true;
1442
1443	if (platform_info->is_target) {
1444		drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
1445						"ready", GPIOD_OUT_LOW);
1446		if (IS_ERR(drv_data->gpiod_ready)) {
1447			status = PTR_ERR(drv_data->gpiod_ready);
1448			goto out_error_clock_enabled;
1449		}
1450	}
1451
 
 
 
 
 
1452	/* Register with the SPI framework */
1453	dev_set_drvdata(dev, drv_data);
1454	status = spi_register_controller(controller);
1455	if (status) {
1456		dev_err_probe(dev, status, "problem registering SPI controller\n");
1457		goto out_error_clock_enabled;
1458	}
1459
1460	return status;
1461
 
 
 
1462out_error_clock_enabled:
1463	clk_disable_unprepare(ssp->clk);
1464
1465out_error_dma_irq_alloc:
1466	pxa2xx_spi_dma_release(drv_data);
1467	free_irq(ssp->irq, drv_data);
1468
 
 
1469	return status;
1470}
1471EXPORT_SYMBOL_NS_GPL(pxa2xx_spi_probe, "SPI_PXA2xx");
1472
1473void pxa2xx_spi_remove(struct device *dev)
1474{
1475	struct driver_data *drv_data = dev_get_drvdata(dev);
1476	struct ssp_device *ssp = drv_data->ssp;
1477
 
 
1478	spi_unregister_controller(drv_data->controller);
1479
1480	/* Disable the SSP at the peripheral and SOC level */
1481	pxa_ssp_disable(ssp);
1482	clk_disable_unprepare(ssp->clk);
1483
1484	/* Release DMA */
1485	if (drv_data->controller_info->enable_dma)
1486		pxa2xx_spi_dma_release(drv_data);
1487
 
 
 
1488	/* Release IRQ */
1489	free_irq(ssp->irq, drv_data);
 
 
 
1490}
1491EXPORT_SYMBOL_NS_GPL(pxa2xx_spi_remove, "SPI_PXA2xx");
1492
1493static int pxa2xx_spi_suspend(struct device *dev)
1494{
1495	struct driver_data *drv_data = dev_get_drvdata(dev);
1496	struct ssp_device *ssp = drv_data->ssp;
1497	int status;
1498
1499	status = spi_controller_suspend(drv_data->controller);
1500	if (status)
1501		return status;
1502
1503	pxa_ssp_disable(ssp);
1504
1505	if (!pm_runtime_suspended(dev))
1506		clk_disable_unprepare(ssp->clk);
1507
1508	return 0;
1509}
1510
1511static int pxa2xx_spi_resume(struct device *dev)
1512{
1513	struct driver_data *drv_data = dev_get_drvdata(dev);
1514	struct ssp_device *ssp = drv_data->ssp;
1515	int status;
1516
1517	/* Enable the SSP clock */
1518	if (!pm_runtime_suspended(dev)) {
1519		status = clk_prepare_enable(ssp->clk);
1520		if (status)
1521			return status;
1522	}
1523
1524	/* Start the queue running */
1525	return spi_controller_resume(drv_data->controller);
1526}
1527
1528static int pxa2xx_spi_runtime_suspend(struct device *dev)
1529{
1530	struct driver_data *drv_data = dev_get_drvdata(dev);
1531
1532	clk_disable_unprepare(drv_data->ssp->clk);
1533	return 0;
1534}
1535
1536static int pxa2xx_spi_runtime_resume(struct device *dev)
1537{
1538	struct driver_data *drv_data = dev_get_drvdata(dev);
1539
1540	return clk_prepare_enable(drv_data->ssp->clk);
1541}
1542
1543EXPORT_NS_GPL_DEV_PM_OPS(pxa2xx_spi_pm_ops, SPI_PXA2xx) = {
1544	SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1545	RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, pxa2xx_spi_runtime_resume, NULL)
1546};
1547
1548MODULE_AUTHOR("Stephen Street");
1549MODULE_DESCRIPTION("PXA2xx SSP SPI Controller core driver");
1550MODULE_LICENSE("GPL");