Loading...
1// SPDX-License-Identifier: GPL-2.0+
2/* Copyright (C) 2021 Maxlinear Corporation
3 * Copyright (C) 2020 Intel Corporation
4 *
5 * Drivers for Maxlinear Ethernet GPY
6 *
7 */
8
9#include <linux/module.h>
10#include <linux/bitfield.h>
11#include <linux/hwmon.h>
12#include <linux/mutex.h>
13#include <linux/phy.h>
14#include <linux/polynomial.h>
15#include <linux/property.h>
16#include <linux/netdevice.h>
17
18/* PHY ID */
19#define PHY_ID_GPYx15B_MASK 0xFFFFFFFC
20#define PHY_ID_GPY21xB_MASK 0xFFFFFFF9
21#define PHY_ID_GPY2xx 0x67C9DC00
22#define PHY_ID_GPY115B 0x67C9DF00
23#define PHY_ID_GPY115C 0x67C9DF10
24#define PHY_ID_GPY211B 0x67C9DE08
25#define PHY_ID_GPY211C 0x67C9DE10
26#define PHY_ID_GPY212B 0x67C9DE09
27#define PHY_ID_GPY212C 0x67C9DE20
28#define PHY_ID_GPY215B 0x67C9DF04
29#define PHY_ID_GPY215C 0x67C9DF20
30#define PHY_ID_GPY241B 0x67C9DE40
31#define PHY_ID_GPY241BM 0x67C9DE80
32#define PHY_ID_GPY245B 0x67C9DEC0
33
34#define PHY_CTL1 0x13
35#define PHY_CTL1_MDICD BIT(3)
36#define PHY_CTL1_MDIAB BIT(2)
37#define PHY_CTL1_AMDIX BIT(0)
38#define PHY_MIISTAT 0x18 /* MII state */
39#define PHY_IMASK 0x19 /* interrupt mask */
40#define PHY_ISTAT 0x1A /* interrupt status */
41#define PHY_LED 0x1B /* LEDs */
42#define PHY_FWV 0x1E /* firmware version */
43
44#define PHY_MIISTAT_SPD_MASK GENMASK(2, 0)
45#define PHY_MIISTAT_DPX BIT(3)
46#define PHY_MIISTAT_LS BIT(10)
47
48#define PHY_MIISTAT_SPD_10 0
49#define PHY_MIISTAT_SPD_100 1
50#define PHY_MIISTAT_SPD_1000 2
51#define PHY_MIISTAT_SPD_2500 4
52
53#define PHY_IMASK_WOL BIT(15) /* Wake-on-LAN */
54#define PHY_IMASK_ANC BIT(10) /* Auto-Neg complete */
55#define PHY_IMASK_ADSC BIT(5) /* Link auto-downspeed detect */
56#define PHY_IMASK_DXMC BIT(2) /* Duplex mode change */
57#define PHY_IMASK_LSPC BIT(1) /* Link speed change */
58#define PHY_IMASK_LSTC BIT(0) /* Link state change */
59#define PHY_IMASK_MASK (PHY_IMASK_LSTC | \
60 PHY_IMASK_LSPC | \
61 PHY_IMASK_DXMC | \
62 PHY_IMASK_ADSC | \
63 PHY_IMASK_ANC)
64
65#define GPY_MAX_LEDS 4
66#define PHY_LED_POLARITY(idx) BIT(12 + (idx))
67#define PHY_LED_HWCONTROL(idx) BIT(8 + (idx))
68#define PHY_LED_ON(idx) BIT(idx)
69
70#define PHY_FWV_REL_MASK BIT(15)
71#define PHY_FWV_MAJOR_MASK GENMASK(11, 8)
72#define PHY_FWV_MINOR_MASK GENMASK(7, 0)
73
74#define PHY_PMA_MGBT_POLARITY 0x82
75#define PHY_MDI_MDI_X_MASK GENMASK(1, 0)
76#define PHY_MDI_MDI_X_NORMAL 0x3
77#define PHY_MDI_MDI_X_AB 0x2
78#define PHY_MDI_MDI_X_CD 0x1
79#define PHY_MDI_MDI_X_CROSS 0x0
80
81/* LED */
82#define VSPEC1_LED(idx) (1 + (idx))
83#define VSPEC1_LED_BLINKS GENMASK(15, 12)
84#define VSPEC1_LED_PULSE GENMASK(11, 8)
85#define VSPEC1_LED_CON GENMASK(7, 4)
86#define VSPEC1_LED_BLINKF GENMASK(3, 0)
87
88#define VSPEC1_LED_LINK10 BIT(0)
89#define VSPEC1_LED_LINK100 BIT(1)
90#define VSPEC1_LED_LINK1000 BIT(2)
91#define VSPEC1_LED_LINK2500 BIT(3)
92
93#define VSPEC1_LED_TXACT BIT(0)
94#define VSPEC1_LED_RXACT BIT(1)
95#define VSPEC1_LED_COL BIT(2)
96#define VSPEC1_LED_NO_CON BIT(3)
97
98/* SGMII */
99#define VSPEC1_SGMII_CTRL 0x08
100#define VSPEC1_SGMII_CTRL_ANEN BIT(12) /* Aneg enable */
101#define VSPEC1_SGMII_CTRL_ANRS BIT(9) /* Restart Aneg */
102#define VSPEC1_SGMII_ANEN_ANRS (VSPEC1_SGMII_CTRL_ANEN | \
103 VSPEC1_SGMII_CTRL_ANRS)
104
105/* Temperature sensor */
106#define VSPEC1_TEMP_STA 0x0E
107#define VSPEC1_TEMP_STA_DATA GENMASK(9, 0)
108
109/* Mailbox */
110#define VSPEC1_MBOX_DATA 0x5
111#define VSPEC1_MBOX_ADDRLO 0x6
112#define VSPEC1_MBOX_CMD 0x7
113#define VSPEC1_MBOX_CMD_ADDRHI GENMASK(7, 0)
114#define VSPEC1_MBOX_CMD_RD (0 << 8)
115#define VSPEC1_MBOX_CMD_READY BIT(15)
116
117/* WoL */
118#define VPSPEC2_WOL_CTL 0x0E06
119#define VPSPEC2_WOL_AD01 0x0E08
120#define VPSPEC2_WOL_AD23 0x0E09
121#define VPSPEC2_WOL_AD45 0x0E0A
122#define WOL_EN BIT(0)
123
124/* Internal registers, access via mbox */
125#define REG_GPIO0_OUT 0xd3ce00
126
127struct gpy_priv {
128 /* serialize mailbox acesses */
129 struct mutex mbox_lock;
130
131 u8 fw_major;
132 u8 fw_minor;
133 u32 wolopts;
134
135 /* It takes 3 seconds to fully switch out of loopback mode before
136 * it can safely re-enter loopback mode. Record the time when
137 * loopback is disabled. Check and wait if necessary before loopback
138 * is enabled.
139 */
140 u64 lb_dis_to;
141};
142
143static const struct {
144 int major;
145 int minor;
146} ver_need_sgmii_reaneg[] = {
147 {7, 0x6D},
148 {8, 0x6D},
149 {9, 0x73},
150};
151
152#if IS_ENABLED(CONFIG_HWMON)
153/* The original translation formulae of the temperature (in degrees of Celsius)
154 * are as follows:
155 *
156 * T = -2.5761e-11*(N^4) + 9.7332e-8*(N^3) + -1.9165e-4*(N^2) +
157 * 3.0762e-1*(N^1) + -5.2156e1
158 *
159 * where [-52.156, 137.961]C and N = [0, 1023].
160 *
161 * They must be accordingly altered to be suitable for the integer arithmetics.
162 * The technique is called 'factor redistribution', which just makes sure the
163 * multiplications and divisions are made so to have a result of the operations
164 * within the integer numbers limit. In addition we need to translate the
165 * formulae to accept millidegrees of Celsius. Here what it looks like after
166 * the alterations:
167 *
168 * T = -25761e-12*(N^4) + 97332e-9*(N^3) + -191650e-6*(N^2) +
169 * 307620e-3*(N^1) + -52156
170 *
171 * where T = [-52156, 137961]mC and N = [0, 1023].
172 */
173static const struct polynomial poly_N_to_temp = {
174 .terms = {
175 {4, -25761, 1000, 1},
176 {3, 97332, 1000, 1},
177 {2, -191650, 1000, 1},
178 {1, 307620, 1000, 1},
179 {0, -52156, 1, 1}
180 }
181};
182
183static int gpy_hwmon_read(struct device *dev,
184 enum hwmon_sensor_types type,
185 u32 attr, int channel, long *value)
186{
187 struct phy_device *phydev = dev_get_drvdata(dev);
188 int ret;
189
190 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_TEMP_STA);
191 if (ret < 0)
192 return ret;
193 if (!ret)
194 return -ENODATA;
195
196 *value = polynomial_calc(&poly_N_to_temp,
197 FIELD_GET(VSPEC1_TEMP_STA_DATA, ret));
198
199 return 0;
200}
201
202static umode_t gpy_hwmon_is_visible(const void *data,
203 enum hwmon_sensor_types type,
204 u32 attr, int channel)
205{
206 return 0444;
207}
208
209static const struct hwmon_channel_info * const gpy_hwmon_info[] = {
210 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT),
211 NULL
212};
213
214static const struct hwmon_ops gpy_hwmon_hwmon_ops = {
215 .is_visible = gpy_hwmon_is_visible,
216 .read = gpy_hwmon_read,
217};
218
219static const struct hwmon_chip_info gpy_hwmon_chip_info = {
220 .ops = &gpy_hwmon_hwmon_ops,
221 .info = gpy_hwmon_info,
222};
223
224static int gpy_hwmon_register(struct phy_device *phydev)
225{
226 struct device *dev = &phydev->mdio.dev;
227 struct device *hwmon_dev;
228 char *hwmon_name;
229
230 hwmon_name = devm_hwmon_sanitize_name(dev, dev_name(dev));
231 if (IS_ERR(hwmon_name))
232 return PTR_ERR(hwmon_name);
233
234 hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name,
235 phydev,
236 &gpy_hwmon_chip_info,
237 NULL);
238
239 return PTR_ERR_OR_ZERO(hwmon_dev);
240}
241#else
242static int gpy_hwmon_register(struct phy_device *phydev)
243{
244 return 0;
245}
246#endif
247
248static int gpy_ack_interrupt(struct phy_device *phydev)
249{
250 int ret;
251
252 /* Clear all pending interrupts */
253 ret = phy_read(phydev, PHY_ISTAT);
254 return ret < 0 ? ret : 0;
255}
256
257static int gpy_mbox_read(struct phy_device *phydev, u32 addr)
258{
259 struct gpy_priv *priv = phydev->priv;
260 int val, ret;
261 u16 cmd;
262
263 mutex_lock(&priv->mbox_lock);
264
265 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_ADDRLO,
266 addr);
267 if (ret)
268 goto out;
269
270 cmd = VSPEC1_MBOX_CMD_RD;
271 cmd |= FIELD_PREP(VSPEC1_MBOX_CMD_ADDRHI, addr >> 16);
272
273 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_CMD, cmd);
274 if (ret)
275 goto out;
276
277 /* The mbox read is used in the interrupt workaround. It was observed
278 * that a read might take up to 2.5ms. This is also the time for which
279 * the interrupt line is stuck low. To be on the safe side, poll the
280 * ready bit for 10ms.
281 */
282 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
283 VSPEC1_MBOX_CMD, val,
284 (val & VSPEC1_MBOX_CMD_READY),
285 500, 10000, false);
286 if (ret)
287 goto out;
288
289 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_DATA);
290
291out:
292 mutex_unlock(&priv->mbox_lock);
293 return ret;
294}
295
296static int gpy_config_init(struct phy_device *phydev)
297{
298 /* Nothing to configure. Configuration Requirement Placeholder */
299 return 0;
300}
301
302static int gpy21x_config_init(struct phy_device *phydev)
303{
304 __set_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces);
305 __set_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces);
306
307 return gpy_config_init(phydev);
308}
309
310static int gpy_probe(struct phy_device *phydev)
311{
312 struct device *dev = &phydev->mdio.dev;
313 struct gpy_priv *priv;
314 int fw_version;
315 int ret;
316
317 if (!phydev->is_c45) {
318 ret = phy_get_c45_ids(phydev);
319 if (ret < 0)
320 return ret;
321 }
322
323 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
324 if (!priv)
325 return -ENOMEM;
326 phydev->priv = priv;
327 mutex_init(&priv->mbox_lock);
328
329 if (!device_property_present(dev, "maxlinear,use-broken-interrupts"))
330 phydev->dev_flags |= PHY_F_NO_IRQ;
331
332 fw_version = phy_read(phydev, PHY_FWV);
333 if (fw_version < 0)
334 return fw_version;
335 priv->fw_major = FIELD_GET(PHY_FWV_MAJOR_MASK, fw_version);
336 priv->fw_minor = FIELD_GET(PHY_FWV_MINOR_MASK, fw_version);
337
338 ret = gpy_hwmon_register(phydev);
339 if (ret)
340 return ret;
341
342 /* Show GPY PHY FW version in dmesg */
343 phydev_info(phydev, "Firmware Version: %d.%d (0x%04X%s)\n",
344 priv->fw_major, priv->fw_minor, fw_version,
345 fw_version & PHY_FWV_REL_MASK ? "" : " test version");
346
347 return 0;
348}
349
350static bool gpy_sgmii_need_reaneg(struct phy_device *phydev)
351{
352 struct gpy_priv *priv = phydev->priv;
353 size_t i;
354
355 for (i = 0; i < ARRAY_SIZE(ver_need_sgmii_reaneg); i++) {
356 if (priv->fw_major != ver_need_sgmii_reaneg[i].major)
357 continue;
358 if (priv->fw_minor < ver_need_sgmii_reaneg[i].minor)
359 return true;
360 break;
361 }
362
363 return false;
364}
365
366static bool gpy_2500basex_chk(struct phy_device *phydev)
367{
368 int ret;
369
370 ret = phy_read(phydev, PHY_MIISTAT);
371 if (ret < 0) {
372 phydev_err(phydev, "Error: MDIO register access failed: %d\n",
373 ret);
374 return false;
375 }
376
377 if (!(ret & PHY_MIISTAT_LS) ||
378 FIELD_GET(PHY_MIISTAT_SPD_MASK, ret) != PHY_MIISTAT_SPD_2500)
379 return false;
380
381 phydev->speed = SPEED_2500;
382 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
383 phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
384 VSPEC1_SGMII_CTRL_ANEN, 0);
385 return true;
386}
387
388static bool gpy_sgmii_aneg_en(struct phy_device *phydev)
389{
390 int ret;
391
392 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL);
393 if (ret < 0) {
394 phydev_err(phydev, "Error: MMD register access failed: %d\n",
395 ret);
396 return true;
397 }
398
399 return (ret & VSPEC1_SGMII_CTRL_ANEN) ? true : false;
400}
401
402static int gpy_config_mdix(struct phy_device *phydev, u8 ctrl)
403{
404 int ret;
405 u16 val;
406
407 switch (ctrl) {
408 case ETH_TP_MDI_AUTO:
409 val = PHY_CTL1_AMDIX;
410 break;
411 case ETH_TP_MDI_X:
412 val = (PHY_CTL1_MDIAB | PHY_CTL1_MDICD);
413 break;
414 case ETH_TP_MDI:
415 val = 0;
416 break;
417 default:
418 return 0;
419 }
420
421 ret = phy_modify(phydev, PHY_CTL1, PHY_CTL1_AMDIX | PHY_CTL1_MDIAB |
422 PHY_CTL1_MDICD, val);
423 if (ret < 0)
424 return ret;
425
426 return genphy_c45_restart_aneg(phydev);
427}
428
429static int gpy_config_aneg(struct phy_device *phydev)
430{
431 bool changed = false;
432 u32 adv;
433 int ret;
434
435 if (phydev->autoneg == AUTONEG_DISABLE) {
436 /* Configure half duplex with genphy_setup_forced,
437 * because genphy_c45_pma_setup_forced does not support.
438 */
439 return phydev->duplex != DUPLEX_FULL
440 ? genphy_setup_forced(phydev)
441 : genphy_c45_pma_setup_forced(phydev);
442 }
443
444 ret = gpy_config_mdix(phydev, phydev->mdix_ctrl);
445 if (ret < 0)
446 return ret;
447
448 ret = genphy_c45_an_config_aneg(phydev);
449 if (ret < 0)
450 return ret;
451 if (ret > 0)
452 changed = true;
453
454 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
455 ret = phy_modify_changed(phydev, MII_CTRL1000,
456 ADVERTISE_1000FULL | ADVERTISE_1000HALF,
457 adv);
458 if (ret < 0)
459 return ret;
460 if (ret > 0)
461 changed = true;
462
463 ret = genphy_c45_check_and_restart_aneg(phydev, changed);
464 if (ret < 0)
465 return ret;
466
467 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII ||
468 phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
469 return 0;
470
471 /* No need to trigger re-ANEG if link speed is 2.5G or SGMII ANEG is
472 * disabled.
473 */
474 if (!gpy_sgmii_need_reaneg(phydev) || gpy_2500basex_chk(phydev) ||
475 !gpy_sgmii_aneg_en(phydev))
476 return 0;
477
478 /* There is a design constraint in GPY2xx device where SGMII AN is
479 * only triggered when there is change of speed. If, PHY link
480 * partner`s speed is still same even after PHY TPI is down and up
481 * again, SGMII AN is not triggered and hence no new in-band message
482 * from GPY to MAC side SGMII.
483 * This could cause an issue during power up, when PHY is up prior to
484 * MAC. At this condition, once MAC side SGMII is up, MAC side SGMII
485 * wouldn`t receive new in-band message from GPY with correct link
486 * status, speed and duplex info.
487 *
488 * 1) If PHY is already up and TPI link status is still down (such as
489 * hard reboot), TPI link status is polled for 4 seconds before
490 * retriggerring SGMII AN.
491 * 2) If PHY is already up and TPI link status is also up (such as soft
492 * reboot), polling of TPI link status is not needed and SGMII AN is
493 * immediately retriggered.
494 * 3) Other conditions such as PHY is down, speed change etc, skip
495 * retriggering SGMII AN. Note: in case of speed change, GPY FW will
496 * initiate SGMII AN.
497 */
498
499 if (phydev->state != PHY_UP)
500 return 0;
501
502 ret = phy_read_poll_timeout(phydev, MII_BMSR, ret, ret & BMSR_LSTATUS,
503 20000, 4000000, false);
504 if (ret == -ETIMEDOUT)
505 return 0;
506 else if (ret < 0)
507 return ret;
508
509 /* Trigger SGMII AN. */
510 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
511 VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS);
512}
513
514static int gpy_update_mdix(struct phy_device *phydev)
515{
516 int ret;
517
518 ret = phy_read(phydev, PHY_CTL1);
519 if (ret < 0)
520 return ret;
521
522 if (ret & PHY_CTL1_AMDIX)
523 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
524 else
525 if (ret & PHY_CTL1_MDICD || ret & PHY_CTL1_MDIAB)
526 phydev->mdix_ctrl = ETH_TP_MDI_X;
527 else
528 phydev->mdix_ctrl = ETH_TP_MDI;
529
530 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PHY_PMA_MGBT_POLARITY);
531 if (ret < 0)
532 return ret;
533
534 if ((ret & PHY_MDI_MDI_X_MASK) < PHY_MDI_MDI_X_NORMAL)
535 phydev->mdix = ETH_TP_MDI_X;
536 else
537 phydev->mdix = ETH_TP_MDI;
538
539 return 0;
540}
541
542static int gpy_update_interface(struct phy_device *phydev)
543{
544 int ret;
545
546 /* Interface mode is fixed for USXGMII and integrated PHY */
547 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII ||
548 phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
549 return -EINVAL;
550
551 /* Automatically switch SERDES interface between SGMII and 2500-BaseX
552 * according to speed. Disable ANEG in 2500-BaseX mode.
553 */
554 switch (phydev->speed) {
555 case SPEED_2500:
556 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
557 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
558 VSPEC1_SGMII_CTRL_ANEN, 0);
559 if (ret < 0) {
560 phydev_err(phydev,
561 "Error: Disable of SGMII ANEG failed: %d\n",
562 ret);
563 return ret;
564 }
565 break;
566 case SPEED_1000:
567 case SPEED_100:
568 case SPEED_10:
569 phydev->interface = PHY_INTERFACE_MODE_SGMII;
570 if (gpy_sgmii_aneg_en(phydev))
571 break;
572 /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed
573 * if ANEG is disabled (in 2500-BaseX mode).
574 */
575 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
576 VSPEC1_SGMII_ANEN_ANRS,
577 VSPEC1_SGMII_ANEN_ANRS);
578 if (ret < 0) {
579 phydev_err(phydev,
580 "Error: Enable of SGMII ANEG failed: %d\n",
581 ret);
582 return ret;
583 }
584 break;
585 }
586
587 if (phydev->speed == SPEED_2500 || phydev->speed == SPEED_1000) {
588 ret = genphy_read_master_slave(phydev);
589 if (ret < 0)
590 return ret;
591 }
592
593 return gpy_update_mdix(phydev);
594}
595
596static int gpy_read_status(struct phy_device *phydev)
597{
598 int ret;
599
600 ret = genphy_update_link(phydev);
601 if (ret)
602 return ret;
603
604 phydev->speed = SPEED_UNKNOWN;
605 phydev->duplex = DUPLEX_UNKNOWN;
606 phydev->pause = 0;
607 phydev->asym_pause = 0;
608
609 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
610 ret = genphy_c45_read_lpa(phydev);
611 if (ret < 0)
612 return ret;
613
614 /* Read the link partner's 1G advertisement */
615 ret = phy_read(phydev, MII_STAT1000);
616 if (ret < 0)
617 return ret;
618 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
619 } else if (phydev->autoneg == AUTONEG_DISABLE) {
620 linkmode_zero(phydev->lp_advertising);
621 }
622
623 ret = phy_read(phydev, PHY_MIISTAT);
624 if (ret < 0)
625 return ret;
626
627 phydev->link = (ret & PHY_MIISTAT_LS) ? 1 : 0;
628 phydev->duplex = (ret & PHY_MIISTAT_DPX) ? DUPLEX_FULL : DUPLEX_HALF;
629 switch (FIELD_GET(PHY_MIISTAT_SPD_MASK, ret)) {
630 case PHY_MIISTAT_SPD_10:
631 phydev->speed = SPEED_10;
632 break;
633 case PHY_MIISTAT_SPD_100:
634 phydev->speed = SPEED_100;
635 break;
636 case PHY_MIISTAT_SPD_1000:
637 phydev->speed = SPEED_1000;
638 break;
639 case PHY_MIISTAT_SPD_2500:
640 phydev->speed = SPEED_2500;
641 break;
642 }
643
644 if (phydev->link) {
645 ret = gpy_update_interface(phydev);
646 if (ret < 0)
647 return ret;
648 }
649
650 return 0;
651}
652
653static int gpy_config_intr(struct phy_device *phydev)
654{
655 struct gpy_priv *priv = phydev->priv;
656 u16 mask = 0;
657 int ret;
658
659 ret = gpy_ack_interrupt(phydev);
660 if (ret)
661 return ret;
662
663 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
664 mask = PHY_IMASK_MASK;
665
666 if (priv->wolopts & WAKE_MAGIC)
667 mask |= PHY_IMASK_WOL;
668
669 if (priv->wolopts & WAKE_PHY)
670 mask |= PHY_IMASK_LSTC;
671
672 return phy_write(phydev, PHY_IMASK, mask);
673}
674
675static irqreturn_t gpy_handle_interrupt(struct phy_device *phydev)
676{
677 int reg;
678
679 reg = phy_read(phydev, PHY_ISTAT);
680 if (reg < 0) {
681 phy_error(phydev);
682 return IRQ_NONE;
683 }
684
685 if (!(reg & PHY_IMASK_MASK))
686 return IRQ_NONE;
687
688 /* The PHY might leave the interrupt line asserted even after PHY_ISTAT
689 * is read. To avoid interrupt storms, delay the interrupt handling as
690 * long as the PHY drives the interrupt line. An internal bus read will
691 * stall as long as the interrupt line is asserted, thus just read a
692 * random register here.
693 * Because we cannot access the internal bus at all while the interrupt
694 * is driven by the PHY, there is no way to make the interrupt line
695 * unstuck (e.g. by changing the pinmux to GPIO input) during that time
696 * frame. Therefore, polling is the best we can do and won't do any more
697 * harm.
698 * It was observed that this bug happens on link state and link speed
699 * changes independent of the firmware version.
700 */
701 if (reg & (PHY_IMASK_LSTC | PHY_IMASK_LSPC)) {
702 reg = gpy_mbox_read(phydev, REG_GPIO0_OUT);
703 if (reg < 0) {
704 phy_error(phydev);
705 return IRQ_NONE;
706 }
707 }
708
709 phy_trigger_machine(phydev);
710
711 return IRQ_HANDLED;
712}
713
714static int gpy_set_wol(struct phy_device *phydev,
715 struct ethtool_wolinfo *wol)
716{
717 struct net_device *attach_dev = phydev->attached_dev;
718 struct gpy_priv *priv = phydev->priv;
719 int ret;
720
721 if (wol->wolopts & WAKE_MAGIC) {
722 /* MAC address - Byte0:Byte1:Byte2:Byte3:Byte4:Byte5
723 * VPSPEC2_WOL_AD45 = Byte0:Byte1
724 * VPSPEC2_WOL_AD23 = Byte2:Byte3
725 * VPSPEC2_WOL_AD01 = Byte4:Byte5
726 */
727 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
728 VPSPEC2_WOL_AD45,
729 ((attach_dev->dev_addr[0] << 8) |
730 attach_dev->dev_addr[1]));
731 if (ret < 0)
732 return ret;
733
734 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
735 VPSPEC2_WOL_AD23,
736 ((attach_dev->dev_addr[2] << 8) |
737 attach_dev->dev_addr[3]));
738 if (ret < 0)
739 return ret;
740
741 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
742 VPSPEC2_WOL_AD01,
743 ((attach_dev->dev_addr[4] << 8) |
744 attach_dev->dev_addr[5]));
745 if (ret < 0)
746 return ret;
747
748 /* Enable the WOL interrupt */
749 ret = phy_write(phydev, PHY_IMASK, PHY_IMASK_WOL);
750 if (ret < 0)
751 return ret;
752
753 /* Enable magic packet matching */
754 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
755 VPSPEC2_WOL_CTL,
756 WOL_EN);
757 if (ret < 0)
758 return ret;
759
760 /* Clear the interrupt status register.
761 * Only WoL is enabled so clear all.
762 */
763 ret = phy_read(phydev, PHY_ISTAT);
764 if (ret < 0)
765 return ret;
766
767 priv->wolopts |= WAKE_MAGIC;
768 } else {
769 /* Disable magic packet matching */
770 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
771 VPSPEC2_WOL_CTL,
772 WOL_EN);
773 if (ret < 0)
774 return ret;
775
776 /* Disable the WOL interrupt */
777 ret = phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_WOL);
778 if (ret < 0)
779 return ret;
780
781 priv->wolopts &= ~WAKE_MAGIC;
782 }
783
784 if (wol->wolopts & WAKE_PHY) {
785 /* Enable the link state change interrupt */
786 ret = phy_set_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC);
787 if (ret < 0)
788 return ret;
789
790 /* Clear the interrupt status register */
791 ret = phy_read(phydev, PHY_ISTAT);
792 if (ret < 0)
793 return ret;
794
795 if (ret & (PHY_IMASK_MASK & ~PHY_IMASK_LSTC))
796 phy_trigger_machine(phydev);
797
798 priv->wolopts |= WAKE_PHY;
799 return 0;
800 }
801
802 priv->wolopts &= ~WAKE_PHY;
803 /* Disable the link state change interrupt */
804 return phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC);
805}
806
807static void gpy_get_wol(struct phy_device *phydev,
808 struct ethtool_wolinfo *wol)
809{
810 struct gpy_priv *priv = phydev->priv;
811
812 wol->supported = WAKE_MAGIC | WAKE_PHY;
813 wol->wolopts = priv->wolopts;
814}
815
816static int gpy_loopback(struct phy_device *phydev, bool enable)
817{
818 struct gpy_priv *priv = phydev->priv;
819 u16 set = 0;
820 int ret;
821
822 if (enable) {
823 u64 now = get_jiffies_64();
824
825 /* wait until 3 seconds from last disable */
826 if (time_before64(now, priv->lb_dis_to))
827 msleep(jiffies64_to_msecs(priv->lb_dis_to - now));
828
829 set = BMCR_LOOPBACK;
830 }
831
832 ret = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, set);
833 if (ret <= 0)
834 return ret;
835
836 if (enable) {
837 /* It takes some time for PHY device to switch into
838 * loopback mode.
839 */
840 msleep(100);
841 } else {
842 priv->lb_dis_to = get_jiffies_64() + HZ * 3;
843 }
844
845 return 0;
846}
847
848static int gpy115_loopback(struct phy_device *phydev, bool enable)
849{
850 struct gpy_priv *priv = phydev->priv;
851
852 if (enable)
853 return gpy_loopback(phydev, enable);
854
855 if (priv->fw_minor > 0x76)
856 return gpy_loopback(phydev, 0);
857
858 return genphy_soft_reset(phydev);
859}
860
861static int gpy_led_brightness_set(struct phy_device *phydev,
862 u8 index, enum led_brightness value)
863{
864 int ret;
865
866 if (index >= GPY_MAX_LEDS)
867 return -EINVAL;
868
869 /* clear HWCONTROL and set manual LED state */
870 ret = phy_modify(phydev, PHY_LED,
871 ((value == LED_OFF) ? PHY_LED_HWCONTROL(index) : 0) |
872 PHY_LED_ON(index),
873 (value == LED_OFF) ? 0 : PHY_LED_ON(index));
874 if (ret)
875 return ret;
876
877 /* ToDo: set PWM brightness */
878
879 /* clear HW LED setup */
880 if (value == LED_OFF)
881 return phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index), 0);
882 else
883 return 0;
884}
885
886static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_LINK) |
887 BIT(TRIGGER_NETDEV_LINK_10) |
888 BIT(TRIGGER_NETDEV_LINK_100) |
889 BIT(TRIGGER_NETDEV_LINK_1000) |
890 BIT(TRIGGER_NETDEV_LINK_2500) |
891 BIT(TRIGGER_NETDEV_RX) |
892 BIT(TRIGGER_NETDEV_TX));
893
894static int gpy_led_hw_is_supported(struct phy_device *phydev, u8 index,
895 unsigned long rules)
896{
897 if (index >= GPY_MAX_LEDS)
898 return -EINVAL;
899
900 /* All combinations of the supported triggers are allowed */
901 if (rules & ~supported_triggers)
902 return -EOPNOTSUPP;
903
904 return 0;
905}
906
907static int gpy_led_hw_control_get(struct phy_device *phydev, u8 index,
908 unsigned long *rules)
909{
910 int val;
911
912 if (index >= GPY_MAX_LEDS)
913 return -EINVAL;
914
915 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index));
916 if (val < 0)
917 return val;
918
919 if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK10)
920 *rules |= BIT(TRIGGER_NETDEV_LINK_10);
921
922 if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK100)
923 *rules |= BIT(TRIGGER_NETDEV_LINK_100);
924
925 if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK1000)
926 *rules |= BIT(TRIGGER_NETDEV_LINK_1000);
927
928 if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK2500)
929 *rules |= BIT(TRIGGER_NETDEV_LINK_2500);
930
931 if (FIELD_GET(VSPEC1_LED_CON, val) == (VSPEC1_LED_LINK10 |
932 VSPEC1_LED_LINK100 |
933 VSPEC1_LED_LINK1000 |
934 VSPEC1_LED_LINK2500))
935 *rules |= BIT(TRIGGER_NETDEV_LINK);
936
937 if (FIELD_GET(VSPEC1_LED_PULSE, val) & VSPEC1_LED_TXACT)
938 *rules |= BIT(TRIGGER_NETDEV_TX);
939
940 if (FIELD_GET(VSPEC1_LED_PULSE, val) & VSPEC1_LED_RXACT)
941 *rules |= BIT(TRIGGER_NETDEV_RX);
942
943 return 0;
944}
945
946static int gpy_led_hw_control_set(struct phy_device *phydev, u8 index,
947 unsigned long rules)
948{
949 u16 val = 0;
950 int ret;
951
952 if (index >= GPY_MAX_LEDS)
953 return -EINVAL;
954
955 if (rules & BIT(TRIGGER_NETDEV_LINK) ||
956 rules & BIT(TRIGGER_NETDEV_LINK_10))
957 val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK10);
958
959 if (rules & BIT(TRIGGER_NETDEV_LINK) ||
960 rules & BIT(TRIGGER_NETDEV_LINK_100))
961 val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK100);
962
963 if (rules & BIT(TRIGGER_NETDEV_LINK) ||
964 rules & BIT(TRIGGER_NETDEV_LINK_1000))
965 val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK1000);
966
967 if (rules & BIT(TRIGGER_NETDEV_LINK) ||
968 rules & BIT(TRIGGER_NETDEV_LINK_2500))
969 val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK2500);
970
971 if (rules & BIT(TRIGGER_NETDEV_TX))
972 val |= FIELD_PREP(VSPEC1_LED_PULSE, VSPEC1_LED_TXACT);
973
974 if (rules & BIT(TRIGGER_NETDEV_RX))
975 val |= FIELD_PREP(VSPEC1_LED_PULSE, VSPEC1_LED_RXACT);
976
977 /* allow RX/TX pulse without link indication */
978 if ((rules & BIT(TRIGGER_NETDEV_TX) || rules & BIT(TRIGGER_NETDEV_RX)) &&
979 !(val & VSPEC1_LED_CON))
980 val |= FIELD_PREP(VSPEC1_LED_PULSE, VSPEC1_LED_NO_CON) | VSPEC1_LED_CON;
981
982 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index), val);
983 if (ret)
984 return ret;
985
986 return phy_set_bits(phydev, PHY_LED, PHY_LED_HWCONTROL(index));
987}
988
989static int gpy_led_polarity_set(struct phy_device *phydev, int index,
990 unsigned long modes)
991{
992 bool force_active_low = false, force_active_high = false;
993 u32 mode;
994
995 if (index >= GPY_MAX_LEDS)
996 return -EINVAL;
997
998 for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
999 switch (mode) {
1000 case PHY_LED_ACTIVE_LOW:
1001 force_active_low = true;
1002 break;
1003 case PHY_LED_ACTIVE_HIGH:
1004 force_active_high = true;
1005 break;
1006 default:
1007 return -EINVAL;
1008 }
1009 }
1010
1011 if (force_active_low)
1012 return phy_set_bits(phydev, PHY_LED, PHY_LED_POLARITY(index));
1013
1014 if (force_active_high)
1015 return phy_clear_bits(phydev, PHY_LED, PHY_LED_POLARITY(index));
1016
1017 return -EINVAL;
1018}
1019
1020static struct phy_driver gpy_drivers[] = {
1021 {
1022 PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx),
1023 .name = "Maxlinear Ethernet GPY2xx",
1024 .get_features = genphy_c45_pma_read_abilities,
1025 .config_init = gpy_config_init,
1026 .probe = gpy_probe,
1027 .suspend = genphy_suspend,
1028 .resume = genphy_resume,
1029 .config_aneg = gpy_config_aneg,
1030 .aneg_done = genphy_c45_aneg_done,
1031 .read_status = gpy_read_status,
1032 .config_intr = gpy_config_intr,
1033 .handle_interrupt = gpy_handle_interrupt,
1034 .set_wol = gpy_set_wol,
1035 .get_wol = gpy_get_wol,
1036 .set_loopback = gpy_loopback,
1037 .led_brightness_set = gpy_led_brightness_set,
1038 .led_hw_is_supported = gpy_led_hw_is_supported,
1039 .led_hw_control_get = gpy_led_hw_control_get,
1040 .led_hw_control_set = gpy_led_hw_control_set,
1041 .led_polarity_set = gpy_led_polarity_set,
1042 },
1043 {
1044 .phy_id = PHY_ID_GPY115B,
1045 .phy_id_mask = PHY_ID_GPYx15B_MASK,
1046 .name = "Maxlinear Ethernet GPY115B",
1047 .get_features = genphy_c45_pma_read_abilities,
1048 .config_init = gpy_config_init,
1049 .probe = gpy_probe,
1050 .suspend = genphy_suspend,
1051 .resume = genphy_resume,
1052 .config_aneg = gpy_config_aneg,
1053 .aneg_done = genphy_c45_aneg_done,
1054 .read_status = gpy_read_status,
1055 .config_intr = gpy_config_intr,
1056 .handle_interrupt = gpy_handle_interrupt,
1057 .set_wol = gpy_set_wol,
1058 .get_wol = gpy_get_wol,
1059 .set_loopback = gpy115_loopback,
1060 .led_brightness_set = gpy_led_brightness_set,
1061 .led_hw_is_supported = gpy_led_hw_is_supported,
1062 .led_hw_control_get = gpy_led_hw_control_get,
1063 .led_hw_control_set = gpy_led_hw_control_set,
1064 .led_polarity_set = gpy_led_polarity_set,
1065 },
1066 {
1067 PHY_ID_MATCH_MODEL(PHY_ID_GPY115C),
1068 .name = "Maxlinear Ethernet GPY115C",
1069 .get_features = genphy_c45_pma_read_abilities,
1070 .config_init = gpy_config_init,
1071 .probe = gpy_probe,
1072 .suspend = genphy_suspend,
1073 .resume = genphy_resume,
1074 .config_aneg = gpy_config_aneg,
1075 .aneg_done = genphy_c45_aneg_done,
1076 .read_status = gpy_read_status,
1077 .config_intr = gpy_config_intr,
1078 .handle_interrupt = gpy_handle_interrupt,
1079 .set_wol = gpy_set_wol,
1080 .get_wol = gpy_get_wol,
1081 .set_loopback = gpy115_loopback,
1082 .led_brightness_set = gpy_led_brightness_set,
1083 .led_hw_is_supported = gpy_led_hw_is_supported,
1084 .led_hw_control_get = gpy_led_hw_control_get,
1085 .led_hw_control_set = gpy_led_hw_control_set,
1086 .led_polarity_set = gpy_led_polarity_set,
1087 },
1088 {
1089 .phy_id = PHY_ID_GPY211B,
1090 .phy_id_mask = PHY_ID_GPY21xB_MASK,
1091 .name = "Maxlinear Ethernet GPY211B",
1092 .get_features = genphy_c45_pma_read_abilities,
1093 .config_init = gpy21x_config_init,
1094 .probe = gpy_probe,
1095 .suspend = genphy_suspend,
1096 .resume = genphy_resume,
1097 .config_aneg = gpy_config_aneg,
1098 .aneg_done = genphy_c45_aneg_done,
1099 .read_status = gpy_read_status,
1100 .config_intr = gpy_config_intr,
1101 .handle_interrupt = gpy_handle_interrupt,
1102 .set_wol = gpy_set_wol,
1103 .get_wol = gpy_get_wol,
1104 .set_loopback = gpy_loopback,
1105 .led_brightness_set = gpy_led_brightness_set,
1106 .led_hw_is_supported = gpy_led_hw_is_supported,
1107 .led_hw_control_get = gpy_led_hw_control_get,
1108 .led_hw_control_set = gpy_led_hw_control_set,
1109 .led_polarity_set = gpy_led_polarity_set,
1110 },
1111 {
1112 PHY_ID_MATCH_MODEL(PHY_ID_GPY211C),
1113 .name = "Maxlinear Ethernet GPY211C",
1114 .get_features = genphy_c45_pma_read_abilities,
1115 .config_init = gpy21x_config_init,
1116 .probe = gpy_probe,
1117 .suspend = genphy_suspend,
1118 .resume = genphy_resume,
1119 .config_aneg = gpy_config_aneg,
1120 .aneg_done = genphy_c45_aneg_done,
1121 .read_status = gpy_read_status,
1122 .config_intr = gpy_config_intr,
1123 .handle_interrupt = gpy_handle_interrupt,
1124 .set_wol = gpy_set_wol,
1125 .get_wol = gpy_get_wol,
1126 .set_loopback = gpy_loopback,
1127 .led_brightness_set = gpy_led_brightness_set,
1128 .led_hw_is_supported = gpy_led_hw_is_supported,
1129 .led_hw_control_get = gpy_led_hw_control_get,
1130 .led_hw_control_set = gpy_led_hw_control_set,
1131 .led_polarity_set = gpy_led_polarity_set,
1132 },
1133 {
1134 .phy_id = PHY_ID_GPY212B,
1135 .phy_id_mask = PHY_ID_GPY21xB_MASK,
1136 .name = "Maxlinear Ethernet GPY212B",
1137 .get_features = genphy_c45_pma_read_abilities,
1138 .config_init = gpy21x_config_init,
1139 .probe = gpy_probe,
1140 .suspend = genphy_suspend,
1141 .resume = genphy_resume,
1142 .config_aneg = gpy_config_aneg,
1143 .aneg_done = genphy_c45_aneg_done,
1144 .read_status = gpy_read_status,
1145 .config_intr = gpy_config_intr,
1146 .handle_interrupt = gpy_handle_interrupt,
1147 .set_wol = gpy_set_wol,
1148 .get_wol = gpy_get_wol,
1149 .set_loopback = gpy_loopback,
1150 .led_brightness_set = gpy_led_brightness_set,
1151 .led_hw_is_supported = gpy_led_hw_is_supported,
1152 .led_hw_control_get = gpy_led_hw_control_get,
1153 .led_hw_control_set = gpy_led_hw_control_set,
1154 .led_polarity_set = gpy_led_polarity_set,
1155 },
1156 {
1157 PHY_ID_MATCH_MODEL(PHY_ID_GPY212C),
1158 .name = "Maxlinear Ethernet GPY212C",
1159 .get_features = genphy_c45_pma_read_abilities,
1160 .config_init = gpy21x_config_init,
1161 .probe = gpy_probe,
1162 .suspend = genphy_suspend,
1163 .resume = genphy_resume,
1164 .config_aneg = gpy_config_aneg,
1165 .aneg_done = genphy_c45_aneg_done,
1166 .read_status = gpy_read_status,
1167 .config_intr = gpy_config_intr,
1168 .handle_interrupt = gpy_handle_interrupt,
1169 .set_wol = gpy_set_wol,
1170 .get_wol = gpy_get_wol,
1171 .set_loopback = gpy_loopback,
1172 .led_brightness_set = gpy_led_brightness_set,
1173 .led_hw_is_supported = gpy_led_hw_is_supported,
1174 .led_hw_control_get = gpy_led_hw_control_get,
1175 .led_hw_control_set = gpy_led_hw_control_set,
1176 .led_polarity_set = gpy_led_polarity_set,
1177 },
1178 {
1179 .phy_id = PHY_ID_GPY215B,
1180 .phy_id_mask = PHY_ID_GPYx15B_MASK,
1181 .name = "Maxlinear Ethernet GPY215B",
1182 .get_features = genphy_c45_pma_read_abilities,
1183 .config_init = gpy21x_config_init,
1184 .probe = gpy_probe,
1185 .suspend = genphy_suspend,
1186 .resume = genphy_resume,
1187 .config_aneg = gpy_config_aneg,
1188 .aneg_done = genphy_c45_aneg_done,
1189 .read_status = gpy_read_status,
1190 .config_intr = gpy_config_intr,
1191 .handle_interrupt = gpy_handle_interrupt,
1192 .set_wol = gpy_set_wol,
1193 .get_wol = gpy_get_wol,
1194 .set_loopback = gpy_loopback,
1195 .led_brightness_set = gpy_led_brightness_set,
1196 .led_hw_is_supported = gpy_led_hw_is_supported,
1197 .led_hw_control_get = gpy_led_hw_control_get,
1198 .led_hw_control_set = gpy_led_hw_control_set,
1199 .led_polarity_set = gpy_led_polarity_set,
1200 },
1201 {
1202 PHY_ID_MATCH_MODEL(PHY_ID_GPY215C),
1203 .name = "Maxlinear Ethernet GPY215C",
1204 .get_features = genphy_c45_pma_read_abilities,
1205 .config_init = gpy21x_config_init,
1206 .probe = gpy_probe,
1207 .suspend = genphy_suspend,
1208 .resume = genphy_resume,
1209 .config_aneg = gpy_config_aneg,
1210 .aneg_done = genphy_c45_aneg_done,
1211 .read_status = gpy_read_status,
1212 .config_intr = gpy_config_intr,
1213 .handle_interrupt = gpy_handle_interrupt,
1214 .set_wol = gpy_set_wol,
1215 .get_wol = gpy_get_wol,
1216 .set_loopback = gpy_loopback,
1217 .led_brightness_set = gpy_led_brightness_set,
1218 .led_hw_is_supported = gpy_led_hw_is_supported,
1219 .led_hw_control_get = gpy_led_hw_control_get,
1220 .led_hw_control_set = gpy_led_hw_control_set,
1221 .led_polarity_set = gpy_led_polarity_set,
1222 },
1223 {
1224 PHY_ID_MATCH_MODEL(PHY_ID_GPY241B),
1225 .name = "Maxlinear Ethernet GPY241B",
1226 .get_features = genphy_c45_pma_read_abilities,
1227 .config_init = gpy_config_init,
1228 .probe = gpy_probe,
1229 .suspend = genphy_suspend,
1230 .resume = genphy_resume,
1231 .config_aneg = gpy_config_aneg,
1232 .aneg_done = genphy_c45_aneg_done,
1233 .read_status = gpy_read_status,
1234 .config_intr = gpy_config_intr,
1235 .handle_interrupt = gpy_handle_interrupt,
1236 .set_wol = gpy_set_wol,
1237 .get_wol = gpy_get_wol,
1238 .set_loopback = gpy_loopback,
1239 },
1240 {
1241 PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM),
1242 .name = "Maxlinear Ethernet GPY241BM",
1243 .get_features = genphy_c45_pma_read_abilities,
1244 .config_init = gpy_config_init,
1245 .probe = gpy_probe,
1246 .suspend = genphy_suspend,
1247 .resume = genphy_resume,
1248 .config_aneg = gpy_config_aneg,
1249 .aneg_done = genphy_c45_aneg_done,
1250 .read_status = gpy_read_status,
1251 .config_intr = gpy_config_intr,
1252 .handle_interrupt = gpy_handle_interrupt,
1253 .set_wol = gpy_set_wol,
1254 .get_wol = gpy_get_wol,
1255 .set_loopback = gpy_loopback,
1256 },
1257 {
1258 PHY_ID_MATCH_MODEL(PHY_ID_GPY245B),
1259 .name = "Maxlinear Ethernet GPY245B",
1260 .get_features = genphy_c45_pma_read_abilities,
1261 .config_init = gpy_config_init,
1262 .probe = gpy_probe,
1263 .suspend = genphy_suspend,
1264 .resume = genphy_resume,
1265 .config_aneg = gpy_config_aneg,
1266 .aneg_done = genphy_c45_aneg_done,
1267 .read_status = gpy_read_status,
1268 .config_intr = gpy_config_intr,
1269 .handle_interrupt = gpy_handle_interrupt,
1270 .set_wol = gpy_set_wol,
1271 .get_wol = gpy_get_wol,
1272 .set_loopback = gpy_loopback,
1273 },
1274};
1275module_phy_driver(gpy_drivers);
1276
1277static struct mdio_device_id __maybe_unused gpy_tbl[] = {
1278 {PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx)},
1279 {PHY_ID_GPY115B, PHY_ID_GPYx15B_MASK},
1280 {PHY_ID_MATCH_MODEL(PHY_ID_GPY115C)},
1281 {PHY_ID_GPY211B, PHY_ID_GPY21xB_MASK},
1282 {PHY_ID_MATCH_MODEL(PHY_ID_GPY211C)},
1283 {PHY_ID_GPY212B, PHY_ID_GPY21xB_MASK},
1284 {PHY_ID_MATCH_MODEL(PHY_ID_GPY212C)},
1285 {PHY_ID_GPY215B, PHY_ID_GPYx15B_MASK},
1286 {PHY_ID_MATCH_MODEL(PHY_ID_GPY215C)},
1287 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241B)},
1288 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM)},
1289 {PHY_ID_MATCH_MODEL(PHY_ID_GPY245B)},
1290 { }
1291};
1292MODULE_DEVICE_TABLE(mdio, gpy_tbl);
1293
1294MODULE_DESCRIPTION("Maxlinear Ethernet GPY Driver");
1295MODULE_AUTHOR("Xu Liang");
1296MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0+
2/* Copyright (C) 2021 Maxlinear Corporation
3 * Copyright (C) 2020 Intel Corporation
4 *
5 * Drivers for Maxlinear Ethernet GPY
6 *
7 */
8
9#include <linux/module.h>
10#include <linux/bitfield.h>
11#include <linux/hwmon.h>
12#include <linux/mutex.h>
13#include <linux/phy.h>
14#include <linux/polynomial.h>
15#include <linux/property.h>
16#include <linux/netdevice.h>
17
18/* PHY ID */
19#define PHY_ID_GPYx15B_MASK 0xFFFFFFFC
20#define PHY_ID_GPY21xB_MASK 0xFFFFFFF9
21#define PHY_ID_GPY2xx 0x67C9DC00
22#define PHY_ID_GPY115B 0x67C9DF00
23#define PHY_ID_GPY115C 0x67C9DF10
24#define PHY_ID_GPY211B 0x67C9DE08
25#define PHY_ID_GPY211C 0x67C9DE10
26#define PHY_ID_GPY212B 0x67C9DE09
27#define PHY_ID_GPY212C 0x67C9DE20
28#define PHY_ID_GPY215B 0x67C9DF04
29#define PHY_ID_GPY215C 0x67C9DF20
30#define PHY_ID_GPY241B 0x67C9DE40
31#define PHY_ID_GPY241BM 0x67C9DE80
32#define PHY_ID_GPY245B 0x67C9DEC0
33
34#define PHY_CTL1 0x13
35#define PHY_CTL1_MDICD BIT(3)
36#define PHY_CTL1_MDIAB BIT(2)
37#define PHY_CTL1_AMDIX BIT(0)
38#define PHY_MIISTAT 0x18 /* MII state */
39#define PHY_IMASK 0x19 /* interrupt mask */
40#define PHY_ISTAT 0x1A /* interrupt status */
41#define PHY_FWV 0x1E /* firmware version */
42
43#define PHY_MIISTAT_SPD_MASK GENMASK(2, 0)
44#define PHY_MIISTAT_DPX BIT(3)
45#define PHY_MIISTAT_LS BIT(10)
46
47#define PHY_MIISTAT_SPD_10 0
48#define PHY_MIISTAT_SPD_100 1
49#define PHY_MIISTAT_SPD_1000 2
50#define PHY_MIISTAT_SPD_2500 4
51
52#define PHY_IMASK_WOL BIT(15) /* Wake-on-LAN */
53#define PHY_IMASK_ANC BIT(10) /* Auto-Neg complete */
54#define PHY_IMASK_ADSC BIT(5) /* Link auto-downspeed detect */
55#define PHY_IMASK_DXMC BIT(2) /* Duplex mode change */
56#define PHY_IMASK_LSPC BIT(1) /* Link speed change */
57#define PHY_IMASK_LSTC BIT(0) /* Link state change */
58#define PHY_IMASK_MASK (PHY_IMASK_LSTC | \
59 PHY_IMASK_LSPC | \
60 PHY_IMASK_DXMC | \
61 PHY_IMASK_ADSC | \
62 PHY_IMASK_ANC)
63
64#define PHY_FWV_REL_MASK BIT(15)
65#define PHY_FWV_MAJOR_MASK GENMASK(11, 8)
66#define PHY_FWV_MINOR_MASK GENMASK(7, 0)
67
68#define PHY_PMA_MGBT_POLARITY 0x82
69#define PHY_MDI_MDI_X_MASK GENMASK(1, 0)
70#define PHY_MDI_MDI_X_NORMAL 0x3
71#define PHY_MDI_MDI_X_AB 0x2
72#define PHY_MDI_MDI_X_CD 0x1
73#define PHY_MDI_MDI_X_CROSS 0x0
74
75/* SGMII */
76#define VSPEC1_SGMII_CTRL 0x08
77#define VSPEC1_SGMII_CTRL_ANEN BIT(12) /* Aneg enable */
78#define VSPEC1_SGMII_CTRL_ANRS BIT(9) /* Restart Aneg */
79#define VSPEC1_SGMII_ANEN_ANRS (VSPEC1_SGMII_CTRL_ANEN | \
80 VSPEC1_SGMII_CTRL_ANRS)
81
82/* Temperature sensor */
83#define VSPEC1_TEMP_STA 0x0E
84#define VSPEC1_TEMP_STA_DATA GENMASK(9, 0)
85
86/* Mailbox */
87#define VSPEC1_MBOX_DATA 0x5
88#define VSPEC1_MBOX_ADDRLO 0x6
89#define VSPEC1_MBOX_CMD 0x7
90#define VSPEC1_MBOX_CMD_ADDRHI GENMASK(7, 0)
91#define VSPEC1_MBOX_CMD_RD (0 << 8)
92#define VSPEC1_MBOX_CMD_READY BIT(15)
93
94/* WoL */
95#define VPSPEC2_WOL_CTL 0x0E06
96#define VPSPEC2_WOL_AD01 0x0E08
97#define VPSPEC2_WOL_AD23 0x0E09
98#define VPSPEC2_WOL_AD45 0x0E0A
99#define WOL_EN BIT(0)
100
101/* Internal registers, access via mbox */
102#define REG_GPIO0_OUT 0xd3ce00
103
104struct gpy_priv {
105 /* serialize mailbox acesses */
106 struct mutex mbox_lock;
107
108 u8 fw_major;
109 u8 fw_minor;
110
111 /* It takes 3 seconds to fully switch out of loopback mode before
112 * it can safely re-enter loopback mode. Record the time when
113 * loopback is disabled. Check and wait if necessary before loopback
114 * is enabled.
115 */
116 u64 lb_dis_to;
117};
118
119static const struct {
120 int major;
121 int minor;
122} ver_need_sgmii_reaneg[] = {
123 {7, 0x6D},
124 {8, 0x6D},
125 {9, 0x73},
126};
127
128#if IS_ENABLED(CONFIG_HWMON)
129/* The original translation formulae of the temperature (in degrees of Celsius)
130 * are as follows:
131 *
132 * T = -2.5761e-11*(N^4) + 9.7332e-8*(N^3) + -1.9165e-4*(N^2) +
133 * 3.0762e-1*(N^1) + -5.2156e1
134 *
135 * where [-52.156, 137.961]C and N = [0, 1023].
136 *
137 * They must be accordingly altered to be suitable for the integer arithmetics.
138 * The technique is called 'factor redistribution', which just makes sure the
139 * multiplications and divisions are made so to have a result of the operations
140 * within the integer numbers limit. In addition we need to translate the
141 * formulae to accept millidegrees of Celsius. Here what it looks like after
142 * the alterations:
143 *
144 * T = -25761e-12*(N^4) + 97332e-9*(N^3) + -191650e-6*(N^2) +
145 * 307620e-3*(N^1) + -52156
146 *
147 * where T = [-52156, 137961]mC and N = [0, 1023].
148 */
149static const struct polynomial poly_N_to_temp = {
150 .terms = {
151 {4, -25761, 1000, 1},
152 {3, 97332, 1000, 1},
153 {2, -191650, 1000, 1},
154 {1, 307620, 1000, 1},
155 {0, -52156, 1, 1}
156 }
157};
158
159static int gpy_hwmon_read(struct device *dev,
160 enum hwmon_sensor_types type,
161 u32 attr, int channel, long *value)
162{
163 struct phy_device *phydev = dev_get_drvdata(dev);
164 int ret;
165
166 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_TEMP_STA);
167 if (ret < 0)
168 return ret;
169 if (!ret)
170 return -ENODATA;
171
172 *value = polynomial_calc(&poly_N_to_temp,
173 FIELD_GET(VSPEC1_TEMP_STA_DATA, ret));
174
175 return 0;
176}
177
178static umode_t gpy_hwmon_is_visible(const void *data,
179 enum hwmon_sensor_types type,
180 u32 attr, int channel)
181{
182 return 0444;
183}
184
185static const struct hwmon_channel_info * const gpy_hwmon_info[] = {
186 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT),
187 NULL
188};
189
190static const struct hwmon_ops gpy_hwmon_hwmon_ops = {
191 .is_visible = gpy_hwmon_is_visible,
192 .read = gpy_hwmon_read,
193};
194
195static const struct hwmon_chip_info gpy_hwmon_chip_info = {
196 .ops = &gpy_hwmon_hwmon_ops,
197 .info = gpy_hwmon_info,
198};
199
200static int gpy_hwmon_register(struct phy_device *phydev)
201{
202 struct device *dev = &phydev->mdio.dev;
203 struct device *hwmon_dev;
204 char *hwmon_name;
205
206 hwmon_name = devm_hwmon_sanitize_name(dev, dev_name(dev));
207 if (IS_ERR(hwmon_name))
208 return PTR_ERR(hwmon_name);
209
210 hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name,
211 phydev,
212 &gpy_hwmon_chip_info,
213 NULL);
214
215 return PTR_ERR_OR_ZERO(hwmon_dev);
216}
217#else
218static int gpy_hwmon_register(struct phy_device *phydev)
219{
220 return 0;
221}
222#endif
223
224static int gpy_mbox_read(struct phy_device *phydev, u32 addr)
225{
226 struct gpy_priv *priv = phydev->priv;
227 int val, ret;
228 u16 cmd;
229
230 mutex_lock(&priv->mbox_lock);
231
232 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_ADDRLO,
233 addr);
234 if (ret)
235 goto out;
236
237 cmd = VSPEC1_MBOX_CMD_RD;
238 cmd |= FIELD_PREP(VSPEC1_MBOX_CMD_ADDRHI, addr >> 16);
239
240 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_CMD, cmd);
241 if (ret)
242 goto out;
243
244 /* The mbox read is used in the interrupt workaround. It was observed
245 * that a read might take up to 2.5ms. This is also the time for which
246 * the interrupt line is stuck low. To be on the safe side, poll the
247 * ready bit for 10ms.
248 */
249 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
250 VSPEC1_MBOX_CMD, val,
251 (val & VSPEC1_MBOX_CMD_READY),
252 500, 10000, false);
253 if (ret)
254 goto out;
255
256 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_DATA);
257
258out:
259 mutex_unlock(&priv->mbox_lock);
260 return ret;
261}
262
263static int gpy_config_init(struct phy_device *phydev)
264{
265 int ret;
266
267 /* Mask all interrupts */
268 ret = phy_write(phydev, PHY_IMASK, 0);
269 if (ret)
270 return ret;
271
272 /* Clear all pending interrupts */
273 ret = phy_read(phydev, PHY_ISTAT);
274 return ret < 0 ? ret : 0;
275}
276
277static int gpy21x_config_init(struct phy_device *phydev)
278{
279 __set_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces);
280 __set_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces);
281
282 return gpy_config_init(phydev);
283}
284
285static int gpy_probe(struct phy_device *phydev)
286{
287 struct device *dev = &phydev->mdio.dev;
288 struct gpy_priv *priv;
289 int fw_version;
290 int ret;
291
292 if (!phydev->is_c45) {
293 ret = phy_get_c45_ids(phydev);
294 if (ret < 0)
295 return ret;
296 }
297
298 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
299 if (!priv)
300 return -ENOMEM;
301 phydev->priv = priv;
302 mutex_init(&priv->mbox_lock);
303
304 if (!device_property_present(dev, "maxlinear,use-broken-interrupts"))
305 phydev->dev_flags |= PHY_F_NO_IRQ;
306
307 fw_version = phy_read(phydev, PHY_FWV);
308 if (fw_version < 0)
309 return fw_version;
310 priv->fw_major = FIELD_GET(PHY_FWV_MAJOR_MASK, fw_version);
311 priv->fw_minor = FIELD_GET(PHY_FWV_MINOR_MASK, fw_version);
312
313 ret = gpy_hwmon_register(phydev);
314 if (ret)
315 return ret;
316
317 /* Show GPY PHY FW version in dmesg */
318 phydev_info(phydev, "Firmware Version: %d.%d (0x%04X%s)\n",
319 priv->fw_major, priv->fw_minor, fw_version,
320 fw_version & PHY_FWV_REL_MASK ? "" : " test version");
321
322 return 0;
323}
324
325static bool gpy_sgmii_need_reaneg(struct phy_device *phydev)
326{
327 struct gpy_priv *priv = phydev->priv;
328 size_t i;
329
330 for (i = 0; i < ARRAY_SIZE(ver_need_sgmii_reaneg); i++) {
331 if (priv->fw_major != ver_need_sgmii_reaneg[i].major)
332 continue;
333 if (priv->fw_minor < ver_need_sgmii_reaneg[i].minor)
334 return true;
335 break;
336 }
337
338 return false;
339}
340
341static bool gpy_2500basex_chk(struct phy_device *phydev)
342{
343 int ret;
344
345 ret = phy_read(phydev, PHY_MIISTAT);
346 if (ret < 0) {
347 phydev_err(phydev, "Error: MDIO register access failed: %d\n",
348 ret);
349 return false;
350 }
351
352 if (!(ret & PHY_MIISTAT_LS) ||
353 FIELD_GET(PHY_MIISTAT_SPD_MASK, ret) != PHY_MIISTAT_SPD_2500)
354 return false;
355
356 phydev->speed = SPEED_2500;
357 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
358 phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
359 VSPEC1_SGMII_CTRL_ANEN, 0);
360 return true;
361}
362
363static bool gpy_sgmii_aneg_en(struct phy_device *phydev)
364{
365 int ret;
366
367 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL);
368 if (ret < 0) {
369 phydev_err(phydev, "Error: MMD register access failed: %d\n",
370 ret);
371 return true;
372 }
373
374 return (ret & VSPEC1_SGMII_CTRL_ANEN) ? true : false;
375}
376
377static int gpy_config_mdix(struct phy_device *phydev, u8 ctrl)
378{
379 int ret;
380 u16 val;
381
382 switch (ctrl) {
383 case ETH_TP_MDI_AUTO:
384 val = PHY_CTL1_AMDIX;
385 break;
386 case ETH_TP_MDI_X:
387 val = (PHY_CTL1_MDIAB | PHY_CTL1_MDICD);
388 break;
389 case ETH_TP_MDI:
390 val = 0;
391 break;
392 default:
393 return 0;
394 }
395
396 ret = phy_modify(phydev, PHY_CTL1, PHY_CTL1_AMDIX | PHY_CTL1_MDIAB |
397 PHY_CTL1_MDICD, val);
398 if (ret < 0)
399 return ret;
400
401 return genphy_c45_restart_aneg(phydev);
402}
403
404static int gpy_config_aneg(struct phy_device *phydev)
405{
406 bool changed = false;
407 u32 adv;
408 int ret;
409
410 if (phydev->autoneg == AUTONEG_DISABLE) {
411 /* Configure half duplex with genphy_setup_forced,
412 * because genphy_c45_pma_setup_forced does not support.
413 */
414 return phydev->duplex != DUPLEX_FULL
415 ? genphy_setup_forced(phydev)
416 : genphy_c45_pma_setup_forced(phydev);
417 }
418
419 ret = gpy_config_mdix(phydev, phydev->mdix_ctrl);
420 if (ret < 0)
421 return ret;
422
423 ret = genphy_c45_an_config_aneg(phydev);
424 if (ret < 0)
425 return ret;
426 if (ret > 0)
427 changed = true;
428
429 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
430 ret = phy_modify_changed(phydev, MII_CTRL1000,
431 ADVERTISE_1000FULL | ADVERTISE_1000HALF,
432 adv);
433 if (ret < 0)
434 return ret;
435 if (ret > 0)
436 changed = true;
437
438 ret = genphy_c45_check_and_restart_aneg(phydev, changed);
439 if (ret < 0)
440 return ret;
441
442 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII ||
443 phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
444 return 0;
445
446 /* No need to trigger re-ANEG if link speed is 2.5G or SGMII ANEG is
447 * disabled.
448 */
449 if (!gpy_sgmii_need_reaneg(phydev) || gpy_2500basex_chk(phydev) ||
450 !gpy_sgmii_aneg_en(phydev))
451 return 0;
452
453 /* There is a design constraint in GPY2xx device where SGMII AN is
454 * only triggered when there is change of speed. If, PHY link
455 * partner`s speed is still same even after PHY TPI is down and up
456 * again, SGMII AN is not triggered and hence no new in-band message
457 * from GPY to MAC side SGMII.
458 * This could cause an issue during power up, when PHY is up prior to
459 * MAC. At this condition, once MAC side SGMII is up, MAC side SGMII
460 * wouldn`t receive new in-band message from GPY with correct link
461 * status, speed and duplex info.
462 *
463 * 1) If PHY is already up and TPI link status is still down (such as
464 * hard reboot), TPI link status is polled for 4 seconds before
465 * retriggerring SGMII AN.
466 * 2) If PHY is already up and TPI link status is also up (such as soft
467 * reboot), polling of TPI link status is not needed and SGMII AN is
468 * immediately retriggered.
469 * 3) Other conditions such as PHY is down, speed change etc, skip
470 * retriggering SGMII AN. Note: in case of speed change, GPY FW will
471 * initiate SGMII AN.
472 */
473
474 if (phydev->state != PHY_UP)
475 return 0;
476
477 ret = phy_read_poll_timeout(phydev, MII_BMSR, ret, ret & BMSR_LSTATUS,
478 20000, 4000000, false);
479 if (ret == -ETIMEDOUT)
480 return 0;
481 else if (ret < 0)
482 return ret;
483
484 /* Trigger SGMII AN. */
485 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
486 VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS);
487}
488
489static int gpy_update_mdix(struct phy_device *phydev)
490{
491 int ret;
492
493 ret = phy_read(phydev, PHY_CTL1);
494 if (ret < 0)
495 return ret;
496
497 if (ret & PHY_CTL1_AMDIX)
498 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
499 else
500 if (ret & PHY_CTL1_MDICD || ret & PHY_CTL1_MDIAB)
501 phydev->mdix_ctrl = ETH_TP_MDI_X;
502 else
503 phydev->mdix_ctrl = ETH_TP_MDI;
504
505 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PHY_PMA_MGBT_POLARITY);
506 if (ret < 0)
507 return ret;
508
509 if ((ret & PHY_MDI_MDI_X_MASK) < PHY_MDI_MDI_X_NORMAL)
510 phydev->mdix = ETH_TP_MDI_X;
511 else
512 phydev->mdix = ETH_TP_MDI;
513
514 return 0;
515}
516
517static int gpy_update_interface(struct phy_device *phydev)
518{
519 int ret;
520
521 /* Interface mode is fixed for USXGMII and integrated PHY */
522 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII ||
523 phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
524 return -EINVAL;
525
526 /* Automatically switch SERDES interface between SGMII and 2500-BaseX
527 * according to speed. Disable ANEG in 2500-BaseX mode.
528 */
529 switch (phydev->speed) {
530 case SPEED_2500:
531 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
532 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
533 VSPEC1_SGMII_CTRL_ANEN, 0);
534 if (ret < 0) {
535 phydev_err(phydev,
536 "Error: Disable of SGMII ANEG failed: %d\n",
537 ret);
538 return ret;
539 }
540 break;
541 case SPEED_1000:
542 case SPEED_100:
543 case SPEED_10:
544 phydev->interface = PHY_INTERFACE_MODE_SGMII;
545 if (gpy_sgmii_aneg_en(phydev))
546 break;
547 /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed
548 * if ANEG is disabled (in 2500-BaseX mode).
549 */
550 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
551 VSPEC1_SGMII_ANEN_ANRS,
552 VSPEC1_SGMII_ANEN_ANRS);
553 if (ret < 0) {
554 phydev_err(phydev,
555 "Error: Enable of SGMII ANEG failed: %d\n",
556 ret);
557 return ret;
558 }
559 break;
560 }
561
562 if (phydev->speed == SPEED_2500 || phydev->speed == SPEED_1000) {
563 ret = genphy_read_master_slave(phydev);
564 if (ret < 0)
565 return ret;
566 }
567
568 return gpy_update_mdix(phydev);
569}
570
571static int gpy_read_status(struct phy_device *phydev)
572{
573 int ret;
574
575 ret = genphy_update_link(phydev);
576 if (ret)
577 return ret;
578
579 phydev->speed = SPEED_UNKNOWN;
580 phydev->duplex = DUPLEX_UNKNOWN;
581 phydev->pause = 0;
582 phydev->asym_pause = 0;
583
584 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
585 ret = genphy_c45_read_lpa(phydev);
586 if (ret < 0)
587 return ret;
588
589 /* Read the link partner's 1G advertisement */
590 ret = phy_read(phydev, MII_STAT1000);
591 if (ret < 0)
592 return ret;
593 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
594 } else if (phydev->autoneg == AUTONEG_DISABLE) {
595 linkmode_zero(phydev->lp_advertising);
596 }
597
598 ret = phy_read(phydev, PHY_MIISTAT);
599 if (ret < 0)
600 return ret;
601
602 phydev->link = (ret & PHY_MIISTAT_LS) ? 1 : 0;
603 phydev->duplex = (ret & PHY_MIISTAT_DPX) ? DUPLEX_FULL : DUPLEX_HALF;
604 switch (FIELD_GET(PHY_MIISTAT_SPD_MASK, ret)) {
605 case PHY_MIISTAT_SPD_10:
606 phydev->speed = SPEED_10;
607 break;
608 case PHY_MIISTAT_SPD_100:
609 phydev->speed = SPEED_100;
610 break;
611 case PHY_MIISTAT_SPD_1000:
612 phydev->speed = SPEED_1000;
613 break;
614 case PHY_MIISTAT_SPD_2500:
615 phydev->speed = SPEED_2500;
616 break;
617 }
618
619 if (phydev->link) {
620 ret = gpy_update_interface(phydev);
621 if (ret < 0)
622 return ret;
623 }
624
625 return 0;
626}
627
628static int gpy_config_intr(struct phy_device *phydev)
629{
630 u16 mask = 0;
631
632 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
633 mask = PHY_IMASK_MASK;
634
635 return phy_write(phydev, PHY_IMASK, mask);
636}
637
638static irqreturn_t gpy_handle_interrupt(struct phy_device *phydev)
639{
640 int reg;
641
642 reg = phy_read(phydev, PHY_ISTAT);
643 if (reg < 0) {
644 phy_error(phydev);
645 return IRQ_NONE;
646 }
647
648 if (!(reg & PHY_IMASK_MASK))
649 return IRQ_NONE;
650
651 /* The PHY might leave the interrupt line asserted even after PHY_ISTAT
652 * is read. To avoid interrupt storms, delay the interrupt handling as
653 * long as the PHY drives the interrupt line. An internal bus read will
654 * stall as long as the interrupt line is asserted, thus just read a
655 * random register here.
656 * Because we cannot access the internal bus at all while the interrupt
657 * is driven by the PHY, there is no way to make the interrupt line
658 * unstuck (e.g. by changing the pinmux to GPIO input) during that time
659 * frame. Therefore, polling is the best we can do and won't do any more
660 * harm.
661 * It was observed that this bug happens on link state and link speed
662 * changes independent of the firmware version.
663 */
664 if (reg & (PHY_IMASK_LSTC | PHY_IMASK_LSPC)) {
665 reg = gpy_mbox_read(phydev, REG_GPIO0_OUT);
666 if (reg < 0) {
667 phy_error(phydev);
668 return IRQ_NONE;
669 }
670 }
671
672 phy_trigger_machine(phydev);
673
674 return IRQ_HANDLED;
675}
676
677static int gpy_set_wol(struct phy_device *phydev,
678 struct ethtool_wolinfo *wol)
679{
680 struct net_device *attach_dev = phydev->attached_dev;
681 int ret;
682
683 if (wol->wolopts & WAKE_MAGIC) {
684 /* MAC address - Byte0:Byte1:Byte2:Byte3:Byte4:Byte5
685 * VPSPEC2_WOL_AD45 = Byte0:Byte1
686 * VPSPEC2_WOL_AD23 = Byte2:Byte3
687 * VPSPEC2_WOL_AD01 = Byte4:Byte5
688 */
689 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
690 VPSPEC2_WOL_AD45,
691 ((attach_dev->dev_addr[0] << 8) |
692 attach_dev->dev_addr[1]));
693 if (ret < 0)
694 return ret;
695
696 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
697 VPSPEC2_WOL_AD23,
698 ((attach_dev->dev_addr[2] << 8) |
699 attach_dev->dev_addr[3]));
700 if (ret < 0)
701 return ret;
702
703 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
704 VPSPEC2_WOL_AD01,
705 ((attach_dev->dev_addr[4] << 8) |
706 attach_dev->dev_addr[5]));
707 if (ret < 0)
708 return ret;
709
710 /* Enable the WOL interrupt */
711 ret = phy_write(phydev, PHY_IMASK, PHY_IMASK_WOL);
712 if (ret < 0)
713 return ret;
714
715 /* Enable magic packet matching */
716 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
717 VPSPEC2_WOL_CTL,
718 WOL_EN);
719 if (ret < 0)
720 return ret;
721
722 /* Clear the interrupt status register.
723 * Only WoL is enabled so clear all.
724 */
725 ret = phy_read(phydev, PHY_ISTAT);
726 if (ret < 0)
727 return ret;
728 } else {
729 /* Disable magic packet matching */
730 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
731 VPSPEC2_WOL_CTL,
732 WOL_EN);
733 if (ret < 0)
734 return ret;
735 }
736
737 if (wol->wolopts & WAKE_PHY) {
738 /* Enable the link state change interrupt */
739 ret = phy_set_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC);
740 if (ret < 0)
741 return ret;
742
743 /* Clear the interrupt status register */
744 ret = phy_read(phydev, PHY_ISTAT);
745 if (ret < 0)
746 return ret;
747
748 if (ret & (PHY_IMASK_MASK & ~PHY_IMASK_LSTC))
749 phy_trigger_machine(phydev);
750
751 return 0;
752 }
753
754 /* Disable the link state change interrupt */
755 return phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC);
756}
757
758static void gpy_get_wol(struct phy_device *phydev,
759 struct ethtool_wolinfo *wol)
760{
761 int ret;
762
763 wol->supported = WAKE_MAGIC | WAKE_PHY;
764 wol->wolopts = 0;
765
766 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, VPSPEC2_WOL_CTL);
767 if (ret & WOL_EN)
768 wol->wolopts |= WAKE_MAGIC;
769
770 ret = phy_read(phydev, PHY_IMASK);
771 if (ret & PHY_IMASK_LSTC)
772 wol->wolopts |= WAKE_PHY;
773}
774
775static int gpy_loopback(struct phy_device *phydev, bool enable)
776{
777 struct gpy_priv *priv = phydev->priv;
778 u16 set = 0;
779 int ret;
780
781 if (enable) {
782 u64 now = get_jiffies_64();
783
784 /* wait until 3 seconds from last disable */
785 if (time_before64(now, priv->lb_dis_to))
786 msleep(jiffies64_to_msecs(priv->lb_dis_to - now));
787
788 set = BMCR_LOOPBACK;
789 }
790
791 ret = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, set);
792 if (ret <= 0)
793 return ret;
794
795 if (enable) {
796 /* It takes some time for PHY device to switch into
797 * loopback mode.
798 */
799 msleep(100);
800 } else {
801 priv->lb_dis_to = get_jiffies_64() + HZ * 3;
802 }
803
804 return 0;
805}
806
807static int gpy115_loopback(struct phy_device *phydev, bool enable)
808{
809 struct gpy_priv *priv = phydev->priv;
810
811 if (enable)
812 return gpy_loopback(phydev, enable);
813
814 if (priv->fw_minor > 0x76)
815 return gpy_loopback(phydev, 0);
816
817 return genphy_soft_reset(phydev);
818}
819
820static struct phy_driver gpy_drivers[] = {
821 {
822 PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx),
823 .name = "Maxlinear Ethernet GPY2xx",
824 .get_features = genphy_c45_pma_read_abilities,
825 .config_init = gpy_config_init,
826 .probe = gpy_probe,
827 .suspend = genphy_suspend,
828 .resume = genphy_resume,
829 .config_aneg = gpy_config_aneg,
830 .aneg_done = genphy_c45_aneg_done,
831 .read_status = gpy_read_status,
832 .config_intr = gpy_config_intr,
833 .handle_interrupt = gpy_handle_interrupt,
834 .set_wol = gpy_set_wol,
835 .get_wol = gpy_get_wol,
836 .set_loopback = gpy_loopback,
837 },
838 {
839 .phy_id = PHY_ID_GPY115B,
840 .phy_id_mask = PHY_ID_GPYx15B_MASK,
841 .name = "Maxlinear Ethernet GPY115B",
842 .get_features = genphy_c45_pma_read_abilities,
843 .config_init = gpy_config_init,
844 .probe = gpy_probe,
845 .suspend = genphy_suspend,
846 .resume = genphy_resume,
847 .config_aneg = gpy_config_aneg,
848 .aneg_done = genphy_c45_aneg_done,
849 .read_status = gpy_read_status,
850 .config_intr = gpy_config_intr,
851 .handle_interrupt = gpy_handle_interrupt,
852 .set_wol = gpy_set_wol,
853 .get_wol = gpy_get_wol,
854 .set_loopback = gpy115_loopback,
855 },
856 {
857 PHY_ID_MATCH_MODEL(PHY_ID_GPY115C),
858 .name = "Maxlinear Ethernet GPY115C",
859 .get_features = genphy_c45_pma_read_abilities,
860 .config_init = gpy_config_init,
861 .probe = gpy_probe,
862 .suspend = genphy_suspend,
863 .resume = genphy_resume,
864 .config_aneg = gpy_config_aneg,
865 .aneg_done = genphy_c45_aneg_done,
866 .read_status = gpy_read_status,
867 .config_intr = gpy_config_intr,
868 .handle_interrupt = gpy_handle_interrupt,
869 .set_wol = gpy_set_wol,
870 .get_wol = gpy_get_wol,
871 .set_loopback = gpy115_loopback,
872 },
873 {
874 .phy_id = PHY_ID_GPY211B,
875 .phy_id_mask = PHY_ID_GPY21xB_MASK,
876 .name = "Maxlinear Ethernet GPY211B",
877 .get_features = genphy_c45_pma_read_abilities,
878 .config_init = gpy21x_config_init,
879 .probe = gpy_probe,
880 .suspend = genphy_suspend,
881 .resume = genphy_resume,
882 .config_aneg = gpy_config_aneg,
883 .aneg_done = genphy_c45_aneg_done,
884 .read_status = gpy_read_status,
885 .config_intr = gpy_config_intr,
886 .handle_interrupt = gpy_handle_interrupt,
887 .set_wol = gpy_set_wol,
888 .get_wol = gpy_get_wol,
889 .set_loopback = gpy_loopback,
890 },
891 {
892 PHY_ID_MATCH_MODEL(PHY_ID_GPY211C),
893 .name = "Maxlinear Ethernet GPY211C",
894 .get_features = genphy_c45_pma_read_abilities,
895 .config_init = gpy21x_config_init,
896 .probe = gpy_probe,
897 .suspend = genphy_suspend,
898 .resume = genphy_resume,
899 .config_aneg = gpy_config_aneg,
900 .aneg_done = genphy_c45_aneg_done,
901 .read_status = gpy_read_status,
902 .config_intr = gpy_config_intr,
903 .handle_interrupt = gpy_handle_interrupt,
904 .set_wol = gpy_set_wol,
905 .get_wol = gpy_get_wol,
906 .set_loopback = gpy_loopback,
907 },
908 {
909 .phy_id = PHY_ID_GPY212B,
910 .phy_id_mask = PHY_ID_GPY21xB_MASK,
911 .name = "Maxlinear Ethernet GPY212B",
912 .get_features = genphy_c45_pma_read_abilities,
913 .config_init = gpy21x_config_init,
914 .probe = gpy_probe,
915 .suspend = genphy_suspend,
916 .resume = genphy_resume,
917 .config_aneg = gpy_config_aneg,
918 .aneg_done = genphy_c45_aneg_done,
919 .read_status = gpy_read_status,
920 .config_intr = gpy_config_intr,
921 .handle_interrupt = gpy_handle_interrupt,
922 .set_wol = gpy_set_wol,
923 .get_wol = gpy_get_wol,
924 .set_loopback = gpy_loopback,
925 },
926 {
927 PHY_ID_MATCH_MODEL(PHY_ID_GPY212C),
928 .name = "Maxlinear Ethernet GPY212C",
929 .get_features = genphy_c45_pma_read_abilities,
930 .config_init = gpy21x_config_init,
931 .probe = gpy_probe,
932 .suspend = genphy_suspend,
933 .resume = genphy_resume,
934 .config_aneg = gpy_config_aneg,
935 .aneg_done = genphy_c45_aneg_done,
936 .read_status = gpy_read_status,
937 .config_intr = gpy_config_intr,
938 .handle_interrupt = gpy_handle_interrupt,
939 .set_wol = gpy_set_wol,
940 .get_wol = gpy_get_wol,
941 .set_loopback = gpy_loopback,
942 },
943 {
944 .phy_id = PHY_ID_GPY215B,
945 .phy_id_mask = PHY_ID_GPYx15B_MASK,
946 .name = "Maxlinear Ethernet GPY215B",
947 .get_features = genphy_c45_pma_read_abilities,
948 .config_init = gpy21x_config_init,
949 .probe = gpy_probe,
950 .suspend = genphy_suspend,
951 .resume = genphy_resume,
952 .config_aneg = gpy_config_aneg,
953 .aneg_done = genphy_c45_aneg_done,
954 .read_status = gpy_read_status,
955 .config_intr = gpy_config_intr,
956 .handle_interrupt = gpy_handle_interrupt,
957 .set_wol = gpy_set_wol,
958 .get_wol = gpy_get_wol,
959 .set_loopback = gpy_loopback,
960 },
961 {
962 PHY_ID_MATCH_MODEL(PHY_ID_GPY215C),
963 .name = "Maxlinear Ethernet GPY215C",
964 .get_features = genphy_c45_pma_read_abilities,
965 .config_init = gpy21x_config_init,
966 .probe = gpy_probe,
967 .suspend = genphy_suspend,
968 .resume = genphy_resume,
969 .config_aneg = gpy_config_aneg,
970 .aneg_done = genphy_c45_aneg_done,
971 .read_status = gpy_read_status,
972 .config_intr = gpy_config_intr,
973 .handle_interrupt = gpy_handle_interrupt,
974 .set_wol = gpy_set_wol,
975 .get_wol = gpy_get_wol,
976 .set_loopback = gpy_loopback,
977 },
978 {
979 PHY_ID_MATCH_MODEL(PHY_ID_GPY241B),
980 .name = "Maxlinear Ethernet GPY241B",
981 .get_features = genphy_c45_pma_read_abilities,
982 .config_init = gpy_config_init,
983 .probe = gpy_probe,
984 .suspend = genphy_suspend,
985 .resume = genphy_resume,
986 .config_aneg = gpy_config_aneg,
987 .aneg_done = genphy_c45_aneg_done,
988 .read_status = gpy_read_status,
989 .config_intr = gpy_config_intr,
990 .handle_interrupt = gpy_handle_interrupt,
991 .set_wol = gpy_set_wol,
992 .get_wol = gpy_get_wol,
993 .set_loopback = gpy_loopback,
994 },
995 {
996 PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM),
997 .name = "Maxlinear Ethernet GPY241BM",
998 .get_features = genphy_c45_pma_read_abilities,
999 .config_init = gpy_config_init,
1000 .probe = gpy_probe,
1001 .suspend = genphy_suspend,
1002 .resume = genphy_resume,
1003 .config_aneg = gpy_config_aneg,
1004 .aneg_done = genphy_c45_aneg_done,
1005 .read_status = gpy_read_status,
1006 .config_intr = gpy_config_intr,
1007 .handle_interrupt = gpy_handle_interrupt,
1008 .set_wol = gpy_set_wol,
1009 .get_wol = gpy_get_wol,
1010 .set_loopback = gpy_loopback,
1011 },
1012 {
1013 PHY_ID_MATCH_MODEL(PHY_ID_GPY245B),
1014 .name = "Maxlinear Ethernet GPY245B",
1015 .get_features = genphy_c45_pma_read_abilities,
1016 .config_init = gpy_config_init,
1017 .probe = gpy_probe,
1018 .suspend = genphy_suspend,
1019 .resume = genphy_resume,
1020 .config_aneg = gpy_config_aneg,
1021 .aneg_done = genphy_c45_aneg_done,
1022 .read_status = gpy_read_status,
1023 .config_intr = gpy_config_intr,
1024 .handle_interrupt = gpy_handle_interrupt,
1025 .set_wol = gpy_set_wol,
1026 .get_wol = gpy_get_wol,
1027 .set_loopback = gpy_loopback,
1028 },
1029};
1030module_phy_driver(gpy_drivers);
1031
1032static struct mdio_device_id __maybe_unused gpy_tbl[] = {
1033 {PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx)},
1034 {PHY_ID_GPY115B, PHY_ID_GPYx15B_MASK},
1035 {PHY_ID_MATCH_MODEL(PHY_ID_GPY115C)},
1036 {PHY_ID_GPY211B, PHY_ID_GPY21xB_MASK},
1037 {PHY_ID_MATCH_MODEL(PHY_ID_GPY211C)},
1038 {PHY_ID_GPY212B, PHY_ID_GPY21xB_MASK},
1039 {PHY_ID_MATCH_MODEL(PHY_ID_GPY212C)},
1040 {PHY_ID_GPY215B, PHY_ID_GPYx15B_MASK},
1041 {PHY_ID_MATCH_MODEL(PHY_ID_GPY215C)},
1042 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241B)},
1043 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM)},
1044 {PHY_ID_MATCH_MODEL(PHY_ID_GPY245B)},
1045 { }
1046};
1047MODULE_DEVICE_TABLE(mdio, gpy_tbl);
1048
1049MODULE_DESCRIPTION("Maxlinear Ethernet GPY Driver");
1050MODULE_AUTHOR("Xu Liang");
1051MODULE_LICENSE("GPL");