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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2018 Intel Corporation */
3
4#include <linux/pci.h>
5#include <linux/delay.h>
6
7#include "igc_mac.h"
8#include "igc_hw.h"
9
10/**
11 * igc_disable_pcie_master - Disables PCI-express master access
12 * @hw: pointer to the HW structure
13 *
14 * Returns 0 (0) if successful, else returns -10
15 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
16 * the master requests to be disabled.
17 *
18 * Disables PCI-Express master access and verifies there are no pending
19 * requests.
20 */
21s32 igc_disable_pcie_master(struct igc_hw *hw)
22{
23 s32 timeout = MASTER_DISABLE_TIMEOUT;
24 s32 ret_val = 0;
25 u32 ctrl;
26
27 ctrl = rd32(IGC_CTRL);
28 ctrl |= IGC_CTRL_GIO_MASTER_DISABLE;
29 wr32(IGC_CTRL, ctrl);
30
31 while (timeout) {
32 if (!(rd32(IGC_STATUS) &
33 IGC_STATUS_GIO_MASTER_ENABLE))
34 break;
35 usleep_range(2000, 3000);
36 timeout--;
37 }
38
39 if (!timeout) {
40 hw_dbg("Master requests are pending.\n");
41 ret_val = -IGC_ERR_MASTER_REQUESTS_PENDING;
42 goto out;
43 }
44
45out:
46 return ret_val;
47}
48
49/**
50 * igc_init_rx_addrs - Initialize receive addresses
51 * @hw: pointer to the HW structure
52 * @rar_count: receive address registers
53 *
54 * Setup the receive address registers by setting the base receive address
55 * register to the devices MAC address and clearing all the other receive
56 * address registers to 0.
57 */
58void igc_init_rx_addrs(struct igc_hw *hw, u16 rar_count)
59{
60 u8 mac_addr[ETH_ALEN] = {0};
61 u32 i;
62
63 /* Setup the receive address */
64 hw_dbg("Programming MAC Address into RAR[0]\n");
65
66 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
67
68 /* Zero out the other (rar_entry_count - 1) receive addresses */
69 hw_dbg("Clearing RAR[1-%u]\n", rar_count - 1);
70 for (i = 1; i < rar_count; i++)
71 hw->mac.ops.rar_set(hw, mac_addr, i);
72}
73
74/**
75 * igc_set_fc_watermarks - Set flow control high/low watermarks
76 * @hw: pointer to the HW structure
77 *
78 * Sets the flow control high/low threshold (watermark) registers. If
79 * flow control XON frame transmission is enabled, then set XON frame
80 * transmission as well.
81 */
82static s32 igc_set_fc_watermarks(struct igc_hw *hw)
83{
84 u32 fcrtl = 0, fcrth = 0;
85
86 /* Set the flow control receive threshold registers. Normally,
87 * these registers will be set to a default threshold that may be
88 * adjusted later by the driver's runtime code. However, if the
89 * ability to transmit pause frames is not enabled, then these
90 * registers will be set to 0.
91 */
92 if (hw->fc.current_mode & igc_fc_tx_pause) {
93 /* We need to set up the Receive Threshold high and low water
94 * marks as well as (optionally) enabling the transmission of
95 * XON frames.
96 */
97 fcrtl = hw->fc.low_water;
98 if (hw->fc.send_xon)
99 fcrtl |= IGC_FCRTL_XONE;
100
101 fcrth = hw->fc.high_water;
102 }
103 wr32(IGC_FCRTL, fcrtl);
104 wr32(IGC_FCRTH, fcrth);
105
106 return 0;
107}
108
109/**
110 * igc_setup_link - Setup flow control and link settings
111 * @hw: pointer to the HW structure
112 *
113 * Determines which flow control settings to use, then configures flow
114 * control. Calls the appropriate media-specific link configuration
115 * function. Assuming the adapter has a valid link partner, a valid link
116 * should be established. Assumes the hardware has previously been reset
117 * and the transmitter and receiver are not enabled.
118 */
119s32 igc_setup_link(struct igc_hw *hw)
120{
121 s32 ret_val = 0;
122
123 /* In the case of the phy reset being blocked, we already have a link.
124 * We do not need to set it up again.
125 */
126 if (igc_check_reset_block(hw))
127 goto out;
128
129 /* If requested flow control is set to default, set flow control
130 * to the both 'rx' and 'tx' pause frames.
131 */
132 if (hw->fc.requested_mode == igc_fc_default)
133 hw->fc.requested_mode = igc_fc_full;
134
135 /* We want to save off the original Flow Control configuration just
136 * in case we get disconnected and then reconnected into a different
137 * hub or switch with different Flow Control capabilities.
138 */
139 hw->fc.current_mode = hw->fc.requested_mode;
140
141 hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
142
143 /* Call the necessary media_type subroutine to configure the link. */
144 ret_val = hw->mac.ops.setup_physical_interface(hw);
145 if (ret_val)
146 goto out;
147
148 /* Initialize the flow control address, type, and PAUSE timer
149 * registers to their default values. This is done even if flow
150 * control is disabled, because it does not hurt anything to
151 * initialize these registers.
152 */
153 hw_dbg("Initializing the Flow Control address, type and timer regs\n");
154 wr32(IGC_FCT, FLOW_CONTROL_TYPE);
155 wr32(IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
156 wr32(IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW);
157
158 wr32(IGC_FCTTV, hw->fc.pause_time);
159
160 ret_val = igc_set_fc_watermarks(hw);
161
162out:
163 return ret_val;
164}
165
166/**
167 * igc_force_mac_fc - Force the MAC's flow control settings
168 * @hw: pointer to the HW structure
169 *
170 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
171 * device control register to reflect the adapter settings. TFCE and RFCE
172 * need to be explicitly set by software when a copper PHY is used because
173 * autonegotiation is managed by the PHY rather than the MAC. Software must
174 * also configure these bits when link is forced on a fiber connection.
175 */
176s32 igc_force_mac_fc(struct igc_hw *hw)
177{
178 s32 ret_val = 0;
179 u32 ctrl;
180
181 ctrl = rd32(IGC_CTRL);
182
183 /* Because we didn't get link via the internal auto-negotiation
184 * mechanism (we either forced link or we got link via PHY
185 * auto-neg), we have to manually enable/disable transmit an
186 * receive flow control.
187 *
188 * The "Case" statement below enables/disable flow control
189 * according to the "hw->fc.current_mode" parameter.
190 *
191 * The possible values of the "fc" parameter are:
192 * 0: Flow control is completely disabled
193 * 1: Rx flow control is enabled (we can receive pause
194 * frames but not send pause frames).
195 * 2: Tx flow control is enabled (we can send pause frames
196 * but we do not receive pause frames).
197 * 3: Both Rx and TX flow control (symmetric) is enabled.
198 * other: No other values should be possible at this point.
199 */
200 hw_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
201
202 switch (hw->fc.current_mode) {
203 case igc_fc_none:
204 ctrl &= (~(IGC_CTRL_TFCE | IGC_CTRL_RFCE));
205 break;
206 case igc_fc_rx_pause:
207 ctrl &= (~IGC_CTRL_TFCE);
208 ctrl |= IGC_CTRL_RFCE;
209 break;
210 case igc_fc_tx_pause:
211 ctrl &= (~IGC_CTRL_RFCE);
212 ctrl |= IGC_CTRL_TFCE;
213 break;
214 case igc_fc_full:
215 ctrl |= (IGC_CTRL_TFCE | IGC_CTRL_RFCE);
216 break;
217 default:
218 hw_dbg("Flow control param set incorrectly\n");
219 ret_val = -IGC_ERR_CONFIG;
220 goto out;
221 }
222
223 wr32(IGC_CTRL, ctrl);
224
225out:
226 return ret_val;
227}
228
229/**
230 * igc_clear_hw_cntrs_base - Clear base hardware counters
231 * @hw: pointer to the HW structure
232 *
233 * Clears the base hardware counters by reading the counter registers.
234 */
235void igc_clear_hw_cntrs_base(struct igc_hw *hw)
236{
237 rd32(IGC_CRCERRS);
238 rd32(IGC_MPC);
239 rd32(IGC_SCC);
240 rd32(IGC_ECOL);
241 rd32(IGC_MCC);
242 rd32(IGC_LATECOL);
243 rd32(IGC_COLC);
244 rd32(IGC_RERC);
245 rd32(IGC_DC);
246 rd32(IGC_RLEC);
247 rd32(IGC_XONRXC);
248 rd32(IGC_XONTXC);
249 rd32(IGC_XOFFRXC);
250 rd32(IGC_XOFFTXC);
251 rd32(IGC_FCRUC);
252 rd32(IGC_GPRC);
253 rd32(IGC_BPRC);
254 rd32(IGC_MPRC);
255 rd32(IGC_GPTC);
256 rd32(IGC_GORCL);
257 rd32(IGC_GORCH);
258 rd32(IGC_GOTCL);
259 rd32(IGC_GOTCH);
260 rd32(IGC_RNBC);
261 rd32(IGC_RUC);
262 rd32(IGC_RFC);
263 rd32(IGC_ROC);
264 rd32(IGC_RJC);
265 rd32(IGC_TORL);
266 rd32(IGC_TORH);
267 rd32(IGC_TOTL);
268 rd32(IGC_TOTH);
269 rd32(IGC_TPR);
270 rd32(IGC_TPT);
271 rd32(IGC_MPTC);
272 rd32(IGC_BPTC);
273
274 rd32(IGC_PRC64);
275 rd32(IGC_PRC127);
276 rd32(IGC_PRC255);
277 rd32(IGC_PRC511);
278 rd32(IGC_PRC1023);
279 rd32(IGC_PRC1522);
280 rd32(IGC_PTC64);
281 rd32(IGC_PTC127);
282 rd32(IGC_PTC255);
283 rd32(IGC_PTC511);
284 rd32(IGC_PTC1023);
285 rd32(IGC_PTC1522);
286
287 rd32(IGC_ALGNERRC);
288 rd32(IGC_RXERRC);
289 rd32(IGC_TNCRS);
290 rd32(IGC_HTDPMC);
291 rd32(IGC_TSCTC);
292
293 rd32(IGC_MGTPRC);
294 rd32(IGC_MGTPDC);
295 rd32(IGC_MGTPTC);
296
297 rd32(IGC_IAC);
298
299 rd32(IGC_RPTHC);
300 rd32(IGC_TLPIC);
301 rd32(IGC_RLPIC);
302 rd32(IGC_HGPTC);
303 rd32(IGC_RXDMTC);
304 rd32(IGC_HGORCL);
305 rd32(IGC_HGORCH);
306 rd32(IGC_HGOTCL);
307 rd32(IGC_HGOTCH);
308 rd32(IGC_LENERRS);
309}
310
311/**
312 * igc_rar_set - Set receive address register
313 * @hw: pointer to the HW structure
314 * @addr: pointer to the receive address
315 * @index: receive address array register
316 *
317 * Sets the receive address array register at index to the address passed
318 * in by addr.
319 */
320void igc_rar_set(struct igc_hw *hw, u8 *addr, u32 index)
321{
322 u32 rar_low, rar_high;
323
324 /* HW expects these in little endian so we reverse the byte order
325 * from network order (big endian) to little endian
326 */
327 rar_low = ((u32)addr[0] |
328 ((u32)addr[1] << 8) |
329 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
330
331 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
332
333 /* If MAC address zero, no need to set the AV bit */
334 if (rar_low || rar_high)
335 rar_high |= IGC_RAH_AV;
336
337 /* Some bridges will combine consecutive 32-bit writes into
338 * a single burst write, which will malfunction on some parts.
339 * The flushes avoid this.
340 */
341 wr32(IGC_RAL(index), rar_low);
342 wrfl();
343 wr32(IGC_RAH(index), rar_high);
344 wrfl();
345}
346
347/**
348 * igc_check_for_copper_link - Check for link (Copper)
349 * @hw: pointer to the HW structure
350 *
351 * Checks to see of the link status of the hardware has changed. If a
352 * change in link status has been detected, then we read the PHY registers
353 * to get the current speed/duplex if link exists.
354 */
355s32 igc_check_for_copper_link(struct igc_hw *hw)
356{
357 struct igc_mac_info *mac = &hw->mac;
358 bool link = false;
359 s32 ret_val;
360
361 /* We only want to go out to the PHY registers to see if Auto-Neg
362 * has completed and/or if our link status has changed. The
363 * get_link_status flag is set upon receiving a Link Status
364 * Change or Rx Sequence Error interrupt.
365 */
366 if (!mac->get_link_status) {
367 ret_val = 0;
368 goto out;
369 }
370
371 /* First we want to see if the MII Status Register reports
372 * link. If so, then we want to get the current speed/duplex
373 * of the PHY.
374 */
375 ret_val = igc_phy_has_link(hw, 1, 0, &link);
376 if (ret_val)
377 goto out;
378
379 if (!link)
380 goto out; /* No link detected */
381
382 mac->get_link_status = false;
383
384 /* Check if there was DownShift, must be checked
385 * immediately after link-up
386 */
387 igc_check_downshift(hw);
388
389 /* Auto-Neg is enabled. Auto Speed Detection takes care
390 * of MAC speed/duplex configuration. So we only need to
391 * configure Collision Distance in the MAC.
392 */
393 igc_config_collision_dist(hw);
394
395 /* Configure Flow Control now that Auto-Neg has completed.
396 * First, we need to restore the desired flow control
397 * settings because we may have had to re-autoneg with a
398 * different link partner.
399 */
400 ret_val = igc_config_fc_after_link_up(hw);
401 if (ret_val)
402 hw_dbg("Error configuring flow control\n");
403
404out:
405 /* Now that we are aware of our link settings, we can set the LTR
406 * thresholds.
407 */
408 ret_val = igc_set_ltr_i225(hw, link);
409
410 return ret_val;
411}
412
413/**
414 * igc_config_collision_dist - Configure collision distance
415 * @hw: pointer to the HW structure
416 *
417 * Configures the collision distance to the default value and is used
418 * during link setup. Currently no func pointer exists and all
419 * implementations are handled in the generic version of this function.
420 */
421void igc_config_collision_dist(struct igc_hw *hw)
422{
423 u32 tctl;
424
425 tctl = rd32(IGC_TCTL);
426
427 tctl &= ~IGC_TCTL_COLD;
428 tctl |= IGC_COLLISION_DISTANCE << IGC_COLD_SHIFT;
429
430 wr32(IGC_TCTL, tctl);
431 wrfl();
432}
433
434/**
435 * igc_config_fc_after_link_up - Configures flow control after link
436 * @hw: pointer to the HW structure
437 *
438 * Checks the status of auto-negotiation after link up to ensure that the
439 * speed and duplex were not forced. If the link needed to be forced, then
440 * flow control needs to be forced also. If auto-negotiation is enabled
441 * and did not fail, then we configure flow control based on our link
442 * partner.
443 */
444s32 igc_config_fc_after_link_up(struct igc_hw *hw)
445{
446 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
447 struct igc_mac_info *mac = &hw->mac;
448 u16 speed, duplex;
449 s32 ret_val = 0;
450
451 /* Check for the case where we have fiber media and auto-neg failed
452 * so we had to force link. In this case, we need to force the
453 * configuration of the MAC to match the "fc" parameter.
454 */
455 if (mac->autoneg_failed)
456 ret_val = igc_force_mac_fc(hw);
457
458 if (ret_val) {
459 hw_dbg("Error forcing flow control settings\n");
460 goto out;
461 }
462
463 /* In auto-neg, we need to check and see if Auto-Neg has completed,
464 * and if so, how the PHY and link partner has flow control
465 * configured.
466 */
467
468 /* Read the MII Status Register and check to see if AutoNeg
469 * has completed. We read this twice because this reg has
470 * some "sticky" (latched) bits.
471 */
472 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
473 &mii_status_reg);
474 if (ret_val)
475 goto out;
476 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
477 &mii_status_reg);
478 if (ret_val)
479 goto out;
480
481 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
482 hw_dbg("Copper PHY and Auto Neg has not completed.\n");
483 goto out;
484 }
485
486 /* The AutoNeg process has completed, so we now need to
487 * read both the Auto Negotiation Advertisement
488 * Register (Address 4) and the Auto_Negotiation Base
489 * Page Ability Register (Address 5) to determine how
490 * flow control was negotiated.
491 */
492 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
493 &mii_nway_adv_reg);
494 if (ret_val)
495 goto out;
496 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
497 &mii_nway_lp_ability_reg);
498 if (ret_val)
499 goto out;
500 /* Two bits in the Auto Negotiation Advertisement Register
501 * (Address 4) and two bits in the Auto Negotiation Base
502 * Page Ability Register (Address 5) determine flow control
503 * for both the PHY and the link partner. The following
504 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
505 * 1999, describes these PAUSE resolution bits and how flow
506 * control is determined based upon these settings.
507 * NOTE: DC = Don't Care
508 *
509 * LOCAL DEVICE | LINK PARTNER
510 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
511 *-------|---------|-------|---------|--------------------
512 * 0 | 0 | DC | DC | igc_fc_none
513 * 0 | 1 | 0 | DC | igc_fc_none
514 * 0 | 1 | 1 | 0 | igc_fc_none
515 * 0 | 1 | 1 | 1 | igc_fc_tx_pause
516 * 1 | 0 | 0 | DC | igc_fc_none
517 * 1 | DC | 1 | DC | igc_fc_full
518 * 1 | 1 | 0 | 0 | igc_fc_none
519 * 1 | 1 | 0 | 1 | igc_fc_rx_pause
520 *
521 * Are both PAUSE bits set to 1? If so, this implies
522 * Symmetric Flow Control is enabled at both ends. The
523 * ASM_DIR bits are irrelevant per the spec.
524 *
525 * For Symmetric Flow Control:
526 *
527 * LOCAL DEVICE | LINK PARTNER
528 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
529 *-------|---------|-------|---------|--------------------
530 * 1 | DC | 1 | DC | IGC_fc_full
531 *
532 */
533 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
534 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
535 /* Now we need to check if the user selected RX ONLY
536 * of pause frames. In this case, we had to advertise
537 * FULL flow control because we could not advertise RX
538 * ONLY. Hence, we must now check to see if we need to
539 * turn OFF the TRANSMISSION of PAUSE frames.
540 */
541 if (hw->fc.requested_mode == igc_fc_full) {
542 hw->fc.current_mode = igc_fc_full;
543 hw_dbg("Flow Control = FULL.\n");
544 } else {
545 hw->fc.current_mode = igc_fc_rx_pause;
546 hw_dbg("Flow Control = RX PAUSE frames only.\n");
547 }
548 }
549
550 /* For receiving PAUSE frames ONLY.
551 *
552 * LOCAL DEVICE | LINK PARTNER
553 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
554 *-------|---------|-------|---------|--------------------
555 * 0 | 1 | 1 | 1 | igc_fc_tx_pause
556 */
557 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
558 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
559 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
560 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
561 hw->fc.current_mode = igc_fc_tx_pause;
562 hw_dbg("Flow Control = TX PAUSE frames only.\n");
563 }
564 /* For transmitting PAUSE frames ONLY.
565 *
566 * LOCAL DEVICE | LINK PARTNER
567 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
568 *-------|---------|-------|---------|--------------------
569 * 1 | 1 | 0 | 1 | igc_fc_rx_pause
570 */
571 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
572 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
573 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
574 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
575 hw->fc.current_mode = igc_fc_rx_pause;
576 hw_dbg("Flow Control = RX PAUSE frames only.\n");
577 }
578 /* Per the IEEE spec, at this point flow control should be
579 * disabled. However, we want to consider that we could
580 * be connected to a legacy switch that doesn't advertise
581 * desired flow control, but can be forced on the link
582 * partner. So if we advertised no flow control, that is
583 * what we will resolve to. If we advertised some kind of
584 * receive capability (Rx Pause Only or Full Flow Control)
585 * and the link partner advertised none, we will configure
586 * ourselves to enable Rx Flow Control only. We can do
587 * this safely for two reasons: If the link partner really
588 * didn't want flow control enabled, and we enable Rx, no
589 * harm done since we won't be receiving any PAUSE frames
590 * anyway. If the intent on the link partner was to have
591 * flow control enabled, then by us enabling RX only, we
592 * can at least receive pause frames and process them.
593 * This is a good idea because in most cases, since we are
594 * predominantly a server NIC, more times than not we will
595 * be asked to delay transmission of packets than asking
596 * our link partner to pause transmission of frames.
597 */
598 else if ((hw->fc.requested_mode == igc_fc_none) ||
599 (hw->fc.requested_mode == igc_fc_tx_pause) ||
600 (hw->fc.strict_ieee)) {
601 hw->fc.current_mode = igc_fc_none;
602 hw_dbg("Flow Control = NONE.\n");
603 } else {
604 hw->fc.current_mode = igc_fc_rx_pause;
605 hw_dbg("Flow Control = RX PAUSE frames only.\n");
606 }
607
608 /* Now we need to do one last check... If we auto-
609 * negotiated to HALF DUPLEX, flow control should not be
610 * enabled per IEEE 802.3 spec.
611 */
612 ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex);
613 if (ret_val) {
614 hw_dbg("Error getting link speed and duplex\n");
615 goto out;
616 }
617
618 if (duplex == HALF_DUPLEX)
619 hw->fc.current_mode = igc_fc_none;
620
621 /* Now we call a subroutine to actually force the MAC
622 * controller to use the correct flow control settings.
623 */
624 ret_val = igc_force_mac_fc(hw);
625 if (ret_val) {
626 hw_dbg("Error forcing flow control settings\n");
627 goto out;
628 }
629
630out:
631 return ret_val;
632}
633
634/**
635 * igc_get_auto_rd_done - Check for auto read completion
636 * @hw: pointer to the HW structure
637 *
638 * Check EEPROM for Auto Read done bit.
639 */
640s32 igc_get_auto_rd_done(struct igc_hw *hw)
641{
642 s32 ret_val = 0;
643 s32 i = 0;
644
645 while (i < AUTO_READ_DONE_TIMEOUT) {
646 if (rd32(IGC_EECD) & IGC_EECD_AUTO_RD)
647 break;
648 usleep_range(1000, 2000);
649 i++;
650 }
651
652 if (i == AUTO_READ_DONE_TIMEOUT) {
653 hw_dbg("Auto read by HW from NVM has not completed.\n");
654 ret_val = -IGC_ERR_RESET;
655 goto out;
656 }
657
658out:
659 return ret_val;
660}
661
662/**
663 * igc_get_speed_and_duplex_copper - Retrieve current speed/duplex
664 * @hw: pointer to the HW structure
665 * @speed: stores the current speed
666 * @duplex: stores the current duplex
667 *
668 * Read the status register for the current speed/duplex and store the current
669 * speed and duplex for copper connections.
670 */
671s32 igc_get_speed_and_duplex_copper(struct igc_hw *hw, u16 *speed,
672 u16 *duplex)
673{
674 u32 status;
675
676 status = rd32(IGC_STATUS);
677 if (status & IGC_STATUS_SPEED_1000) {
678 /* For I225, STATUS will indicate 1G speed in both 1 Gbps
679 * and 2.5 Gbps link modes. An additional bit is used
680 * to differentiate between 1 Gbps and 2.5 Gbps.
681 */
682 if (hw->mac.type == igc_i225 &&
683 (status & IGC_STATUS_SPEED_2500)) {
684 *speed = SPEED_2500;
685 hw_dbg("2500 Mbs, ");
686 } else {
687 *speed = SPEED_1000;
688 hw_dbg("1000 Mbs, ");
689 }
690 } else if (status & IGC_STATUS_SPEED_100) {
691 *speed = SPEED_100;
692 hw_dbg("100 Mbs, ");
693 } else {
694 *speed = SPEED_10;
695 hw_dbg("10 Mbs, ");
696 }
697
698 if (status & IGC_STATUS_FD) {
699 *duplex = FULL_DUPLEX;
700 hw_dbg("Full Duplex\n");
701 } else {
702 *duplex = HALF_DUPLEX;
703 hw_dbg("Half Duplex\n");
704 }
705
706 return 0;
707}
708
709/**
710 * igc_put_hw_semaphore - Release hardware semaphore
711 * @hw: pointer to the HW structure
712 *
713 * Release hardware semaphore used to access the PHY or NVM
714 */
715void igc_put_hw_semaphore(struct igc_hw *hw)
716{
717 u32 swsm;
718
719 swsm = rd32(IGC_SWSM);
720
721 swsm &= ~(IGC_SWSM_SMBI | IGC_SWSM_SWESMBI);
722
723 wr32(IGC_SWSM, swsm);
724}
725
726/**
727 * igc_enable_mng_pass_thru - Enable processing of ARP's
728 * @hw: pointer to the HW structure
729 *
730 * Verifies the hardware needs to leave interface enabled so that frames can
731 * be directed to and from the management interface.
732 */
733bool igc_enable_mng_pass_thru(struct igc_hw *hw)
734{
735 bool ret_val = false;
736 u32 fwsm, factps;
737 u32 manc;
738
739 if (!hw->mac.asf_firmware_present)
740 goto out;
741
742 manc = rd32(IGC_MANC);
743
744 if (!(manc & IGC_MANC_RCV_TCO_EN))
745 goto out;
746
747 if (hw->mac.arc_subsystem_valid) {
748 fwsm = rd32(IGC_FWSM);
749 factps = rd32(IGC_FACTPS);
750
751 if (!(factps & IGC_FACTPS_MNGCG) &&
752 ((fwsm & IGC_FWSM_MODE_MASK) ==
753 (igc_mng_mode_pt << IGC_FWSM_MODE_SHIFT))) {
754 ret_val = true;
755 goto out;
756 }
757 } else {
758 if ((manc & IGC_MANC_SMBUS_EN) &&
759 !(manc & IGC_MANC_ASF_EN)) {
760 ret_val = true;
761 goto out;
762 }
763 }
764
765out:
766 return ret_val;
767}
768
769/**
770 * igc_hash_mc_addr - Generate a multicast hash value
771 * @hw: pointer to the HW structure
772 * @mc_addr: pointer to a multicast address
773 *
774 * Generates a multicast address hash value which is used to determine
775 * the multicast filter table array address and new table value. See
776 * igc_mta_set()
777 **/
778static u32 igc_hash_mc_addr(struct igc_hw *hw, u8 *mc_addr)
779{
780 u32 hash_value, hash_mask;
781 u8 bit_shift = 0;
782
783 /* Register count multiplied by bits per register */
784 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
785
786 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
787 * where 0xFF would still fall within the hash mask.
788 */
789 while (hash_mask >> bit_shift != 0xFF)
790 bit_shift++;
791
792 /* The portion of the address that is used for the hash table
793 * is determined by the mc_filter_type setting.
794 * The algorithm is such that there is a total of 8 bits of shifting.
795 * The bit_shift for a mc_filter_type of 0 represents the number of
796 * left-shifts where the MSB of mc_addr[5] would still fall within
797 * the hash_mask. Case 0 does this exactly. Since there are a total
798 * of 8 bits of shifting, then mc_addr[4] will shift right the
799 * remaining number of bits. Thus 8 - bit_shift. The rest of the
800 * cases are a variation of this algorithm...essentially raising the
801 * number of bits to shift mc_addr[5] left, while still keeping the
802 * 8-bit shifting total.
803 *
804 * For example, given the following Destination MAC Address and an
805 * MTA register count of 128 (thus a 4096-bit vector and 0xFFF mask),
806 * we can see that the bit_shift for case 0 is 4. These are the hash
807 * values resulting from each mc_filter_type...
808 * [0] [1] [2] [3] [4] [5]
809 * 01 AA 00 12 34 56
810 * LSB MSB
811 *
812 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
813 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
814 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
815 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
816 */
817 switch (hw->mac.mc_filter_type) {
818 default:
819 case 0:
820 break;
821 case 1:
822 bit_shift += 1;
823 break;
824 case 2:
825 bit_shift += 2;
826 break;
827 case 3:
828 bit_shift += 4;
829 break;
830 }
831
832 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
833 (((u16)mc_addr[5]) << bit_shift)));
834
835 return hash_value;
836}
837
838/**
839 * igc_update_mc_addr_list - Update Multicast addresses
840 * @hw: pointer to the HW structure
841 * @mc_addr_list: array of multicast addresses to program
842 * @mc_addr_count: number of multicast addresses to program
843 *
844 * Updates entire Multicast Table Array.
845 * The caller must have a packed mc_addr_list of multicast addresses.
846 **/
847void igc_update_mc_addr_list(struct igc_hw *hw,
848 u8 *mc_addr_list, u32 mc_addr_count)
849{
850 u32 hash_value, hash_bit, hash_reg;
851 int i;
852
853 /* clear mta_shadow */
854 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
855
856 /* update mta_shadow from mc_addr_list */
857 for (i = 0; (u32)i < mc_addr_count; i++) {
858 hash_value = igc_hash_mc_addr(hw, mc_addr_list);
859
860 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
861 hash_bit = hash_value & 0x1F;
862
863 hw->mac.mta_shadow[hash_reg] |= BIT(hash_bit);
864 mc_addr_list += ETH_ALEN;
865 }
866
867 /* replace the entire MTA table */
868 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
869 array_wr32(IGC_MTA, i, hw->mac.mta_shadow[i]);
870 wrfl();
871}
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2018 Intel Corporation */
3
4#include <linux/pci.h>
5#include <linux/delay.h>
6
7#include "igc_mac.h"
8#include "igc_hw.h"
9
10/**
11 * igc_disable_pcie_master - Disables PCI-express master access
12 * @hw: pointer to the HW structure
13 *
14 * Returns 0 (0) if successful, else returns -10
15 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
16 * the master requests to be disabled.
17 *
18 * Disables PCI-Express master access and verifies there are no pending
19 * requests.
20 */
21s32 igc_disable_pcie_master(struct igc_hw *hw)
22{
23 s32 timeout = MASTER_DISABLE_TIMEOUT;
24 s32 ret_val = 0;
25 u32 ctrl;
26
27 ctrl = rd32(IGC_CTRL);
28 ctrl |= IGC_CTRL_GIO_MASTER_DISABLE;
29 wr32(IGC_CTRL, ctrl);
30
31 while (timeout) {
32 if (!(rd32(IGC_STATUS) &
33 IGC_STATUS_GIO_MASTER_ENABLE))
34 break;
35 usleep_range(2000, 3000);
36 timeout--;
37 }
38
39 if (!timeout) {
40 hw_dbg("Master requests are pending.\n");
41 ret_val = -IGC_ERR_MASTER_REQUESTS_PENDING;
42 goto out;
43 }
44
45out:
46 return ret_val;
47}
48
49/**
50 * igc_init_rx_addrs - Initialize receive addresses
51 * @hw: pointer to the HW structure
52 * @rar_count: receive address registers
53 *
54 * Setup the receive address registers by setting the base receive address
55 * register to the devices MAC address and clearing all the other receive
56 * address registers to 0.
57 */
58void igc_init_rx_addrs(struct igc_hw *hw, u16 rar_count)
59{
60 u8 mac_addr[ETH_ALEN] = {0};
61 u32 i;
62
63 /* Setup the receive address */
64 hw_dbg("Programming MAC Address into RAR[0]\n");
65
66 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
67
68 /* Zero out the other (rar_entry_count - 1) receive addresses */
69 hw_dbg("Clearing RAR[1-%u]\n", rar_count - 1);
70 for (i = 1; i < rar_count; i++)
71 hw->mac.ops.rar_set(hw, mac_addr, i);
72}
73
74/**
75 * igc_set_fc_watermarks - Set flow control high/low watermarks
76 * @hw: pointer to the HW structure
77 *
78 * Sets the flow control high/low threshold (watermark) registers. If
79 * flow control XON frame transmission is enabled, then set XON frame
80 * transmission as well.
81 */
82static s32 igc_set_fc_watermarks(struct igc_hw *hw)
83{
84 u32 fcrtl = 0, fcrth = 0;
85
86 /* Set the flow control receive threshold registers. Normally,
87 * these registers will be set to a default threshold that may be
88 * adjusted later by the driver's runtime code. However, if the
89 * ability to transmit pause frames is not enabled, then these
90 * registers will be set to 0.
91 */
92 if (hw->fc.current_mode & igc_fc_tx_pause) {
93 /* We need to set up the Receive Threshold high and low water
94 * marks as well as (optionally) enabling the transmission of
95 * XON frames.
96 */
97 fcrtl = hw->fc.low_water;
98 if (hw->fc.send_xon)
99 fcrtl |= IGC_FCRTL_XONE;
100
101 fcrth = hw->fc.high_water;
102 }
103 wr32(IGC_FCRTL, fcrtl);
104 wr32(IGC_FCRTH, fcrth);
105
106 return 0;
107}
108
109/**
110 * igc_setup_link - Setup flow control and link settings
111 * @hw: pointer to the HW structure
112 *
113 * Determines which flow control settings to use, then configures flow
114 * control. Calls the appropriate media-specific link configuration
115 * function. Assuming the adapter has a valid link partner, a valid link
116 * should be established. Assumes the hardware has previously been reset
117 * and the transmitter and receiver are not enabled.
118 */
119s32 igc_setup_link(struct igc_hw *hw)
120{
121 s32 ret_val = 0;
122
123 /* In the case of the phy reset being blocked, we already have a link.
124 * We do not need to set it up again.
125 */
126 if (igc_check_reset_block(hw))
127 goto out;
128
129 /* If requested flow control is set to default, set flow control
130 * to the both 'rx' and 'tx' pause frames.
131 */
132 if (hw->fc.requested_mode == igc_fc_default)
133 hw->fc.requested_mode = igc_fc_full;
134
135 /* We want to save off the original Flow Control configuration just
136 * in case we get disconnected and then reconnected into a different
137 * hub or switch with different Flow Control capabilities.
138 */
139 hw->fc.current_mode = hw->fc.requested_mode;
140
141 hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
142
143 /* Call the necessary media_type subroutine to configure the link. */
144 ret_val = hw->mac.ops.setup_physical_interface(hw);
145 if (ret_val)
146 goto out;
147
148 /* Initialize the flow control address, type, and PAUSE timer
149 * registers to their default values. This is done even if flow
150 * control is disabled, because it does not hurt anything to
151 * initialize these registers.
152 */
153 hw_dbg("Initializing the Flow Control address, type and timer regs\n");
154 wr32(IGC_FCT, FLOW_CONTROL_TYPE);
155 wr32(IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
156 wr32(IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW);
157
158 wr32(IGC_FCTTV, hw->fc.pause_time);
159
160 ret_val = igc_set_fc_watermarks(hw);
161
162out:
163 return ret_val;
164}
165
166/**
167 * igc_force_mac_fc - Force the MAC's flow control settings
168 * @hw: pointer to the HW structure
169 *
170 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
171 * device control register to reflect the adapter settings. TFCE and RFCE
172 * need to be explicitly set by software when a copper PHY is used because
173 * autonegotiation is managed by the PHY rather than the MAC. Software must
174 * also configure these bits when link is forced on a fiber connection.
175 */
176s32 igc_force_mac_fc(struct igc_hw *hw)
177{
178 s32 ret_val = 0;
179 u32 ctrl;
180
181 ctrl = rd32(IGC_CTRL);
182
183 /* Because we didn't get link via the internal auto-negotiation
184 * mechanism (we either forced link or we got link via PHY
185 * auto-neg), we have to manually enable/disable transmit an
186 * receive flow control.
187 *
188 * The "Case" statement below enables/disable flow control
189 * according to the "hw->fc.current_mode" parameter.
190 *
191 * The possible values of the "fc" parameter are:
192 * 0: Flow control is completely disabled
193 * 1: Rx flow control is enabled (we can receive pause
194 * frames but not send pause frames).
195 * 2: Tx flow control is enabled (we can send pause frames
196 * but we do not receive pause frames).
197 * 3: Both Rx and TX flow control (symmetric) is enabled.
198 * other: No other values should be possible at this point.
199 */
200 hw_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
201
202 switch (hw->fc.current_mode) {
203 case igc_fc_none:
204 ctrl &= (~(IGC_CTRL_TFCE | IGC_CTRL_RFCE));
205 break;
206 case igc_fc_rx_pause:
207 ctrl &= (~IGC_CTRL_TFCE);
208 ctrl |= IGC_CTRL_RFCE;
209 break;
210 case igc_fc_tx_pause:
211 ctrl &= (~IGC_CTRL_RFCE);
212 ctrl |= IGC_CTRL_TFCE;
213 break;
214 case igc_fc_full:
215 ctrl |= (IGC_CTRL_TFCE | IGC_CTRL_RFCE);
216 break;
217 default:
218 hw_dbg("Flow control param set incorrectly\n");
219 ret_val = -IGC_ERR_CONFIG;
220 goto out;
221 }
222
223 wr32(IGC_CTRL, ctrl);
224
225out:
226 return ret_val;
227}
228
229/**
230 * igc_clear_hw_cntrs_base - Clear base hardware counters
231 * @hw: pointer to the HW structure
232 *
233 * Clears the base hardware counters by reading the counter registers.
234 */
235void igc_clear_hw_cntrs_base(struct igc_hw *hw)
236{
237 rd32(IGC_CRCERRS);
238 rd32(IGC_MPC);
239 rd32(IGC_SCC);
240 rd32(IGC_ECOL);
241 rd32(IGC_MCC);
242 rd32(IGC_LATECOL);
243 rd32(IGC_COLC);
244 rd32(IGC_RERC);
245 rd32(IGC_DC);
246 rd32(IGC_RLEC);
247 rd32(IGC_XONRXC);
248 rd32(IGC_XONTXC);
249 rd32(IGC_XOFFRXC);
250 rd32(IGC_XOFFTXC);
251 rd32(IGC_FCRUC);
252 rd32(IGC_GPRC);
253 rd32(IGC_BPRC);
254 rd32(IGC_MPRC);
255 rd32(IGC_GPTC);
256 rd32(IGC_GORCL);
257 rd32(IGC_GORCH);
258 rd32(IGC_GOTCL);
259 rd32(IGC_GOTCH);
260 rd32(IGC_RNBC);
261 rd32(IGC_RUC);
262 rd32(IGC_RFC);
263 rd32(IGC_ROC);
264 rd32(IGC_RJC);
265 rd32(IGC_TORL);
266 rd32(IGC_TORH);
267 rd32(IGC_TOTL);
268 rd32(IGC_TOTH);
269 rd32(IGC_TPR);
270 rd32(IGC_TPT);
271 rd32(IGC_MPTC);
272 rd32(IGC_BPTC);
273
274 rd32(IGC_PRC64);
275 rd32(IGC_PRC127);
276 rd32(IGC_PRC255);
277 rd32(IGC_PRC511);
278 rd32(IGC_PRC1023);
279 rd32(IGC_PRC1522);
280 rd32(IGC_PTC64);
281 rd32(IGC_PTC127);
282 rd32(IGC_PTC255);
283 rd32(IGC_PTC511);
284 rd32(IGC_PTC1023);
285 rd32(IGC_PTC1522);
286
287 rd32(IGC_ALGNERRC);
288 rd32(IGC_RXERRC);
289 rd32(IGC_TNCRS);
290 rd32(IGC_HTDPMC);
291 rd32(IGC_TSCTC);
292
293 rd32(IGC_MGTPRC);
294 rd32(IGC_MGTPDC);
295 rd32(IGC_MGTPTC);
296
297 rd32(IGC_IAC);
298
299 rd32(IGC_RPTHC);
300 rd32(IGC_TLPIC);
301 rd32(IGC_RLPIC);
302 rd32(IGC_HGPTC);
303 rd32(IGC_RXDMTC);
304 rd32(IGC_HGORCL);
305 rd32(IGC_HGORCH);
306 rd32(IGC_HGOTCL);
307 rd32(IGC_HGOTCH);
308 rd32(IGC_LENERRS);
309}
310
311/**
312 * igc_rar_set - Set receive address register
313 * @hw: pointer to the HW structure
314 * @addr: pointer to the receive address
315 * @index: receive address array register
316 *
317 * Sets the receive address array register at index to the address passed
318 * in by addr.
319 */
320void igc_rar_set(struct igc_hw *hw, u8 *addr, u32 index)
321{
322 u32 rar_low, rar_high;
323
324 /* HW expects these in little endian so we reverse the byte order
325 * from network order (big endian) to little endian
326 */
327 rar_low = ((u32)addr[0] |
328 ((u32)addr[1] << 8) |
329 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
330
331 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
332
333 /* If MAC address zero, no need to set the AV bit */
334 if (rar_low || rar_high)
335 rar_high |= IGC_RAH_AV;
336
337 /* Some bridges will combine consecutive 32-bit writes into
338 * a single burst write, which will malfunction on some parts.
339 * The flushes avoid this.
340 */
341 wr32(IGC_RAL(index), rar_low);
342 wrfl();
343 wr32(IGC_RAH(index), rar_high);
344 wrfl();
345}
346
347/**
348 * igc_check_for_copper_link - Check for link (Copper)
349 * @hw: pointer to the HW structure
350 *
351 * Checks to see of the link status of the hardware has changed. If a
352 * change in link status has been detected, then we read the PHY registers
353 * to get the current speed/duplex if link exists.
354 */
355s32 igc_check_for_copper_link(struct igc_hw *hw)
356{
357 struct igc_mac_info *mac = &hw->mac;
358 bool link = false;
359 s32 ret_val;
360
361 /* We only want to go out to the PHY registers to see if Auto-Neg
362 * has completed and/or if our link status has changed. The
363 * get_link_status flag is set upon receiving a Link Status
364 * Change or Rx Sequence Error interrupt.
365 */
366 if (!mac->get_link_status) {
367 ret_val = 0;
368 goto out;
369 }
370
371 /* First we want to see if the MII Status Register reports
372 * link. If so, then we want to get the current speed/duplex
373 * of the PHY.
374 */
375 ret_val = igc_phy_has_link(hw, 1, 0, &link);
376 if (ret_val)
377 goto out;
378
379 if (!link)
380 goto out; /* No link detected */
381
382 mac->get_link_status = false;
383
384 /* Check if there was DownShift, must be checked
385 * immediately after link-up
386 */
387 igc_check_downshift(hw);
388
389 /* If we are forcing speed/duplex, then we simply return since
390 * we have already determined whether we have link or not.
391 */
392 if (!mac->autoneg) {
393 ret_val = -IGC_ERR_CONFIG;
394 goto out;
395 }
396
397 /* Auto-Neg is enabled. Auto Speed Detection takes care
398 * of MAC speed/duplex configuration. So we only need to
399 * configure Collision Distance in the MAC.
400 */
401 igc_config_collision_dist(hw);
402
403 /* Configure Flow Control now that Auto-Neg has completed.
404 * First, we need to restore the desired flow control
405 * settings because we may have had to re-autoneg with a
406 * different link partner.
407 */
408 ret_val = igc_config_fc_after_link_up(hw);
409 if (ret_val)
410 hw_dbg("Error configuring flow control\n");
411
412out:
413 /* Now that we are aware of our link settings, we can set the LTR
414 * thresholds.
415 */
416 ret_val = igc_set_ltr_i225(hw, link);
417
418 return ret_val;
419}
420
421/**
422 * igc_config_collision_dist - Configure collision distance
423 * @hw: pointer to the HW structure
424 *
425 * Configures the collision distance to the default value and is used
426 * during link setup. Currently no func pointer exists and all
427 * implementations are handled in the generic version of this function.
428 */
429void igc_config_collision_dist(struct igc_hw *hw)
430{
431 u32 tctl;
432
433 tctl = rd32(IGC_TCTL);
434
435 tctl &= ~IGC_TCTL_COLD;
436 tctl |= IGC_COLLISION_DISTANCE << IGC_COLD_SHIFT;
437
438 wr32(IGC_TCTL, tctl);
439 wrfl();
440}
441
442/**
443 * igc_config_fc_after_link_up - Configures flow control after link
444 * @hw: pointer to the HW structure
445 *
446 * Checks the status of auto-negotiation after link up to ensure that the
447 * speed and duplex were not forced. If the link needed to be forced, then
448 * flow control needs to be forced also. If auto-negotiation is enabled
449 * and did not fail, then we configure flow control based on our link
450 * partner.
451 */
452s32 igc_config_fc_after_link_up(struct igc_hw *hw)
453{
454 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
455 struct igc_mac_info *mac = &hw->mac;
456 u16 speed, duplex;
457 s32 ret_val = 0;
458
459 /* Check for the case where we have fiber media and auto-neg failed
460 * so we had to force link. In this case, we need to force the
461 * configuration of the MAC to match the "fc" parameter.
462 */
463 if (mac->autoneg_failed)
464 ret_val = igc_force_mac_fc(hw);
465
466 if (ret_val) {
467 hw_dbg("Error forcing flow control settings\n");
468 goto out;
469 }
470
471 /* Check for the case where we have copper media and auto-neg is
472 * enabled. In this case, we need to check and see if Auto-Neg
473 * has completed, and if so, how the PHY and link partner has
474 * flow control configured.
475 */
476 if (mac->autoneg) {
477 /* Read the MII Status Register and check to see if AutoNeg
478 * has completed. We read this twice because this reg has
479 * some "sticky" (latched) bits.
480 */
481 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
482 &mii_status_reg);
483 if (ret_val)
484 goto out;
485 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
486 &mii_status_reg);
487 if (ret_val)
488 goto out;
489
490 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
491 hw_dbg("Copper PHY and Auto Neg has not completed.\n");
492 goto out;
493 }
494
495 /* The AutoNeg process has completed, so we now need to
496 * read both the Auto Negotiation Advertisement
497 * Register (Address 4) and the Auto_Negotiation Base
498 * Page Ability Register (Address 5) to determine how
499 * flow control was negotiated.
500 */
501 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
502 &mii_nway_adv_reg);
503 if (ret_val)
504 goto out;
505 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
506 &mii_nway_lp_ability_reg);
507 if (ret_val)
508 goto out;
509 /* Two bits in the Auto Negotiation Advertisement Register
510 * (Address 4) and two bits in the Auto Negotiation Base
511 * Page Ability Register (Address 5) determine flow control
512 * for both the PHY and the link partner. The following
513 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
514 * 1999, describes these PAUSE resolution bits and how flow
515 * control is determined based upon these settings.
516 * NOTE: DC = Don't Care
517 *
518 * LOCAL DEVICE | LINK PARTNER
519 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
520 *-------|---------|-------|---------|--------------------
521 * 0 | 0 | DC | DC | igc_fc_none
522 * 0 | 1 | 0 | DC | igc_fc_none
523 * 0 | 1 | 1 | 0 | igc_fc_none
524 * 0 | 1 | 1 | 1 | igc_fc_tx_pause
525 * 1 | 0 | 0 | DC | igc_fc_none
526 * 1 | DC | 1 | DC | igc_fc_full
527 * 1 | 1 | 0 | 0 | igc_fc_none
528 * 1 | 1 | 0 | 1 | igc_fc_rx_pause
529 *
530 * Are both PAUSE bits set to 1? If so, this implies
531 * Symmetric Flow Control is enabled at both ends. The
532 * ASM_DIR bits are irrelevant per the spec.
533 *
534 * For Symmetric Flow Control:
535 *
536 * LOCAL DEVICE | LINK PARTNER
537 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
538 *-------|---------|-------|---------|--------------------
539 * 1 | DC | 1 | DC | IGC_fc_full
540 *
541 */
542 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
543 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
544 /* Now we need to check if the user selected RX ONLY
545 * of pause frames. In this case, we had to advertise
546 * FULL flow control because we could not advertise RX
547 * ONLY. Hence, we must now check to see if we need to
548 * turn OFF the TRANSMISSION of PAUSE frames.
549 */
550 if (hw->fc.requested_mode == igc_fc_full) {
551 hw->fc.current_mode = igc_fc_full;
552 hw_dbg("Flow Control = FULL.\n");
553 } else {
554 hw->fc.current_mode = igc_fc_rx_pause;
555 hw_dbg("Flow Control = RX PAUSE frames only.\n");
556 }
557 }
558
559 /* For receiving PAUSE frames ONLY.
560 *
561 * LOCAL DEVICE | LINK PARTNER
562 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
563 *-------|---------|-------|---------|--------------------
564 * 0 | 1 | 1 | 1 | igc_fc_tx_pause
565 */
566 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
567 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
568 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
569 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
570 hw->fc.current_mode = igc_fc_tx_pause;
571 hw_dbg("Flow Control = TX PAUSE frames only.\n");
572 }
573 /* For transmitting PAUSE frames ONLY.
574 *
575 * LOCAL DEVICE | LINK PARTNER
576 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
577 *-------|---------|-------|---------|--------------------
578 * 1 | 1 | 0 | 1 | igc_fc_rx_pause
579 */
580 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
581 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
582 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
583 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
584 hw->fc.current_mode = igc_fc_rx_pause;
585 hw_dbg("Flow Control = RX PAUSE frames only.\n");
586 }
587 /* Per the IEEE spec, at this point flow control should be
588 * disabled. However, we want to consider that we could
589 * be connected to a legacy switch that doesn't advertise
590 * desired flow control, but can be forced on the link
591 * partner. So if we advertised no flow control, that is
592 * what we will resolve to. If we advertised some kind of
593 * receive capability (Rx Pause Only or Full Flow Control)
594 * and the link partner advertised none, we will configure
595 * ourselves to enable Rx Flow Control only. We can do
596 * this safely for two reasons: If the link partner really
597 * didn't want flow control enabled, and we enable Rx, no
598 * harm done since we won't be receiving any PAUSE frames
599 * anyway. If the intent on the link partner was to have
600 * flow control enabled, then by us enabling RX only, we
601 * can at least receive pause frames and process them.
602 * This is a good idea because in most cases, since we are
603 * predominantly a server NIC, more times than not we will
604 * be asked to delay transmission of packets than asking
605 * our link partner to pause transmission of frames.
606 */
607 else if ((hw->fc.requested_mode == igc_fc_none) ||
608 (hw->fc.requested_mode == igc_fc_tx_pause) ||
609 (hw->fc.strict_ieee)) {
610 hw->fc.current_mode = igc_fc_none;
611 hw_dbg("Flow Control = NONE.\n");
612 } else {
613 hw->fc.current_mode = igc_fc_rx_pause;
614 hw_dbg("Flow Control = RX PAUSE frames only.\n");
615 }
616
617 /* Now we need to do one last check... If we auto-
618 * negotiated to HALF DUPLEX, flow control should not be
619 * enabled per IEEE 802.3 spec.
620 */
621 ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex);
622 if (ret_val) {
623 hw_dbg("Error getting link speed and duplex\n");
624 goto out;
625 }
626
627 if (duplex == HALF_DUPLEX)
628 hw->fc.current_mode = igc_fc_none;
629
630 /* Now we call a subroutine to actually force the MAC
631 * controller to use the correct flow control settings.
632 */
633 ret_val = igc_force_mac_fc(hw);
634 if (ret_val) {
635 hw_dbg("Error forcing flow control settings\n");
636 goto out;
637 }
638 }
639
640out:
641 return ret_val;
642}
643
644/**
645 * igc_get_auto_rd_done - Check for auto read completion
646 * @hw: pointer to the HW structure
647 *
648 * Check EEPROM for Auto Read done bit.
649 */
650s32 igc_get_auto_rd_done(struct igc_hw *hw)
651{
652 s32 ret_val = 0;
653 s32 i = 0;
654
655 while (i < AUTO_READ_DONE_TIMEOUT) {
656 if (rd32(IGC_EECD) & IGC_EECD_AUTO_RD)
657 break;
658 usleep_range(1000, 2000);
659 i++;
660 }
661
662 if (i == AUTO_READ_DONE_TIMEOUT) {
663 hw_dbg("Auto read by HW from NVM has not completed.\n");
664 ret_val = -IGC_ERR_RESET;
665 goto out;
666 }
667
668out:
669 return ret_val;
670}
671
672/**
673 * igc_get_speed_and_duplex_copper - Retrieve current speed/duplex
674 * @hw: pointer to the HW structure
675 * @speed: stores the current speed
676 * @duplex: stores the current duplex
677 *
678 * Read the status register for the current speed/duplex and store the current
679 * speed and duplex for copper connections.
680 */
681s32 igc_get_speed_and_duplex_copper(struct igc_hw *hw, u16 *speed,
682 u16 *duplex)
683{
684 u32 status;
685
686 status = rd32(IGC_STATUS);
687 if (status & IGC_STATUS_SPEED_1000) {
688 /* For I225, STATUS will indicate 1G speed in both 1 Gbps
689 * and 2.5 Gbps link modes. An additional bit is used
690 * to differentiate between 1 Gbps and 2.5 Gbps.
691 */
692 if (hw->mac.type == igc_i225 &&
693 (status & IGC_STATUS_SPEED_2500)) {
694 *speed = SPEED_2500;
695 hw_dbg("2500 Mbs, ");
696 } else {
697 *speed = SPEED_1000;
698 hw_dbg("1000 Mbs, ");
699 }
700 } else if (status & IGC_STATUS_SPEED_100) {
701 *speed = SPEED_100;
702 hw_dbg("100 Mbs, ");
703 } else {
704 *speed = SPEED_10;
705 hw_dbg("10 Mbs, ");
706 }
707
708 if (status & IGC_STATUS_FD) {
709 *duplex = FULL_DUPLEX;
710 hw_dbg("Full Duplex\n");
711 } else {
712 *duplex = HALF_DUPLEX;
713 hw_dbg("Half Duplex\n");
714 }
715
716 return 0;
717}
718
719/**
720 * igc_put_hw_semaphore - Release hardware semaphore
721 * @hw: pointer to the HW structure
722 *
723 * Release hardware semaphore used to access the PHY or NVM
724 */
725void igc_put_hw_semaphore(struct igc_hw *hw)
726{
727 u32 swsm;
728
729 swsm = rd32(IGC_SWSM);
730
731 swsm &= ~(IGC_SWSM_SMBI | IGC_SWSM_SWESMBI);
732
733 wr32(IGC_SWSM, swsm);
734}
735
736/**
737 * igc_enable_mng_pass_thru - Enable processing of ARP's
738 * @hw: pointer to the HW structure
739 *
740 * Verifies the hardware needs to leave interface enabled so that frames can
741 * be directed to and from the management interface.
742 */
743bool igc_enable_mng_pass_thru(struct igc_hw *hw)
744{
745 bool ret_val = false;
746 u32 fwsm, factps;
747 u32 manc;
748
749 if (!hw->mac.asf_firmware_present)
750 goto out;
751
752 manc = rd32(IGC_MANC);
753
754 if (!(manc & IGC_MANC_RCV_TCO_EN))
755 goto out;
756
757 if (hw->mac.arc_subsystem_valid) {
758 fwsm = rd32(IGC_FWSM);
759 factps = rd32(IGC_FACTPS);
760
761 if (!(factps & IGC_FACTPS_MNGCG) &&
762 ((fwsm & IGC_FWSM_MODE_MASK) ==
763 (igc_mng_mode_pt << IGC_FWSM_MODE_SHIFT))) {
764 ret_val = true;
765 goto out;
766 }
767 } else {
768 if ((manc & IGC_MANC_SMBUS_EN) &&
769 !(manc & IGC_MANC_ASF_EN)) {
770 ret_val = true;
771 goto out;
772 }
773 }
774
775out:
776 return ret_val;
777}
778
779/**
780 * igc_hash_mc_addr - Generate a multicast hash value
781 * @hw: pointer to the HW structure
782 * @mc_addr: pointer to a multicast address
783 *
784 * Generates a multicast address hash value which is used to determine
785 * the multicast filter table array address and new table value. See
786 * igc_mta_set()
787 **/
788static u32 igc_hash_mc_addr(struct igc_hw *hw, u8 *mc_addr)
789{
790 u32 hash_value, hash_mask;
791 u8 bit_shift = 0;
792
793 /* Register count multiplied by bits per register */
794 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
795
796 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
797 * where 0xFF would still fall within the hash mask.
798 */
799 while (hash_mask >> bit_shift != 0xFF)
800 bit_shift++;
801
802 /* The portion of the address that is used for the hash table
803 * is determined by the mc_filter_type setting.
804 * The algorithm is such that there is a total of 8 bits of shifting.
805 * The bit_shift for a mc_filter_type of 0 represents the number of
806 * left-shifts where the MSB of mc_addr[5] would still fall within
807 * the hash_mask. Case 0 does this exactly. Since there are a total
808 * of 8 bits of shifting, then mc_addr[4] will shift right the
809 * remaining number of bits. Thus 8 - bit_shift. The rest of the
810 * cases are a variation of this algorithm...essentially raising the
811 * number of bits to shift mc_addr[5] left, while still keeping the
812 * 8-bit shifting total.
813 *
814 * For example, given the following Destination MAC Address and an
815 * MTA register count of 128 (thus a 4096-bit vector and 0xFFF mask),
816 * we can see that the bit_shift for case 0 is 4. These are the hash
817 * values resulting from each mc_filter_type...
818 * [0] [1] [2] [3] [4] [5]
819 * 01 AA 00 12 34 56
820 * LSB MSB
821 *
822 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
823 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
824 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
825 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
826 */
827 switch (hw->mac.mc_filter_type) {
828 default:
829 case 0:
830 break;
831 case 1:
832 bit_shift += 1;
833 break;
834 case 2:
835 bit_shift += 2;
836 break;
837 case 3:
838 bit_shift += 4;
839 break;
840 }
841
842 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
843 (((u16)mc_addr[5]) << bit_shift)));
844
845 return hash_value;
846}
847
848/**
849 * igc_update_mc_addr_list - Update Multicast addresses
850 * @hw: pointer to the HW structure
851 * @mc_addr_list: array of multicast addresses to program
852 * @mc_addr_count: number of multicast addresses to program
853 *
854 * Updates entire Multicast Table Array.
855 * The caller must have a packed mc_addr_list of multicast addresses.
856 **/
857void igc_update_mc_addr_list(struct igc_hw *hw,
858 u8 *mc_addr_list, u32 mc_addr_count)
859{
860 u32 hash_value, hash_bit, hash_reg;
861 int i;
862
863 /* clear mta_shadow */
864 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
865
866 /* update mta_shadow from mc_addr_list */
867 for (i = 0; (u32)i < mc_addr_count; i++) {
868 hash_value = igc_hash_mc_addr(hw, mc_addr_list);
869
870 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
871 hash_bit = hash_value & 0x1F;
872
873 hw->mac.mta_shadow[hash_reg] |= BIT(hash_bit);
874 mc_addr_list += ETH_ALEN;
875 }
876
877 /* replace the entire MTA table */
878 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
879 array_wr32(IGC_MTA, i, hw->mac.mta_shadow[i]);
880 wrfl();
881}