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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2018, Intel Corporation. */
3
4#include <linux/vmalloc.h>
5
6#include "ice_common.h"
7
8/**
9 * ice_aq_read_nvm
10 * @hw: pointer to the HW struct
11 * @module_typeid: module pointer location in words from the NVM beginning
12 * @offset: byte offset from the module beginning
13 * @length: length of the section to be read (in bytes from the offset)
14 * @data: command buffer (size [bytes] = length)
15 * @last_command: tells if this is the last command in a series
16 * @read_shadow_ram: tell if this is a shadow RAM read
17 * @cd: pointer to command details structure or NULL
18 *
19 * Read the NVM using the admin queue commands (0x0701)
20 */
21int ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset,
22 u16 length, void *data, bool last_command,
23 bool read_shadow_ram, struct ice_sq_cd *cd)
24{
25 struct ice_aq_desc desc;
26 struct ice_aqc_nvm *cmd;
27
28 cmd = &desc.params.nvm;
29
30 if (offset > ICE_AQC_NVM_MAX_OFFSET)
31 return -EINVAL;
32
33 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);
34
35 if (!read_shadow_ram && module_typeid == ICE_AQC_NVM_START_POINT)
36 cmd->cmd_flags |= ICE_AQC_NVM_FLASH_ONLY;
37
38 /* If this is the last command in a series, set the proper flag. */
39 if (last_command)
40 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
41 cmd->module_typeid = cpu_to_le16(module_typeid);
42 cmd->offset_low = cpu_to_le16(offset & 0xFFFF);
43 cmd->offset_high = (offset >> 16) & 0xFF;
44 cmd->length = cpu_to_le16(length);
45
46 return ice_aq_send_cmd(hw, &desc, data, length, cd);
47}
48
49/**
50 * ice_read_flat_nvm - Read portion of NVM by flat offset
51 * @hw: pointer to the HW struct
52 * @offset: offset from beginning of NVM
53 * @length: (in) number of bytes to read; (out) number of bytes actually read
54 * @data: buffer to return data in (sized to fit the specified length)
55 * @read_shadow_ram: if true, read from shadow RAM instead of NVM
56 *
57 * Reads a portion of the NVM, as a flat memory space. This function correctly
58 * breaks read requests across Shadow RAM sectors and ensures that no single
59 * read request exceeds the maximum 4KB read for a single AdminQ command.
60 *
61 * Returns a status code on failure. Note that the data pointer may be
62 * partially updated if some reads succeed before a failure.
63 */
64int
65ice_read_flat_nvm(struct ice_hw *hw, u32 offset, u32 *length, u8 *data,
66 bool read_shadow_ram)
67{
68 u32 inlen = *length;
69 u32 bytes_read = 0;
70 bool last_cmd;
71 int status;
72
73 *length = 0;
74
75 /* Verify the length of the read if this is for the Shadow RAM */
76 if (read_shadow_ram && ((offset + inlen) > (hw->flash.sr_words * 2u))) {
77 ice_debug(hw, ICE_DBG_NVM, "NVM error: requested offset is beyond Shadow RAM limit\n");
78 return -EINVAL;
79 }
80
81 do {
82 u32 read_size, sector_offset;
83
84 /* ice_aq_read_nvm cannot read more than 4KB at a time.
85 * Additionally, a read from the Shadow RAM may not cross over
86 * a sector boundary. Conveniently, the sector size is also
87 * 4KB.
88 */
89 sector_offset = offset % ICE_AQ_MAX_BUF_LEN;
90 read_size = min_t(u32, ICE_AQ_MAX_BUF_LEN - sector_offset,
91 inlen - bytes_read);
92
93 last_cmd = !(bytes_read + read_size < inlen);
94
95 status = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT,
96 offset, read_size,
97 data + bytes_read, last_cmd,
98 read_shadow_ram, NULL);
99 if (status)
100 break;
101
102 bytes_read += read_size;
103 offset += read_size;
104 } while (!last_cmd);
105
106 *length = bytes_read;
107 return status;
108}
109
110/**
111 * ice_aq_update_nvm
112 * @hw: pointer to the HW struct
113 * @module_typeid: module pointer location in words from the NVM beginning
114 * @offset: byte offset from the module beginning
115 * @length: length of the section to be written (in bytes from the offset)
116 * @data: command buffer (size [bytes] = length)
117 * @last_command: tells if this is the last command in a series
118 * @command_flags: command parameters
119 * @cd: pointer to command details structure or NULL
120 *
121 * Update the NVM using the admin queue commands (0x0703)
122 */
123int
124ice_aq_update_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset,
125 u16 length, void *data, bool last_command, u8 command_flags,
126 struct ice_sq_cd *cd)
127{
128 struct ice_aq_desc desc;
129 struct ice_aqc_nvm *cmd;
130
131 cmd = &desc.params.nvm;
132
133 /* In offset the highest byte must be zeroed. */
134 if (offset & 0xFF000000)
135 return -EINVAL;
136
137 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_write);
138
139 cmd->cmd_flags |= command_flags;
140
141 /* If this is the last command in a series, set the proper flag. */
142 if (last_command)
143 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
144 cmd->module_typeid = cpu_to_le16(module_typeid);
145 cmd->offset_low = cpu_to_le16(offset & 0xFFFF);
146 cmd->offset_high = (offset >> 16) & 0xFF;
147 cmd->length = cpu_to_le16(length);
148
149 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
150
151 return ice_aq_send_cmd(hw, &desc, data, length, cd);
152}
153
154/**
155 * ice_aq_erase_nvm
156 * @hw: pointer to the HW struct
157 * @module_typeid: module pointer location in words from the NVM beginning
158 * @cd: pointer to command details structure or NULL
159 *
160 * Erase the NVM sector using the admin queue commands (0x0702)
161 */
162int ice_aq_erase_nvm(struct ice_hw *hw, u16 module_typeid, struct ice_sq_cd *cd)
163{
164 struct ice_aq_desc desc;
165 struct ice_aqc_nvm *cmd;
166
167 cmd = &desc.params.nvm;
168
169 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_erase);
170
171 cmd->module_typeid = cpu_to_le16(module_typeid);
172 cmd->length = cpu_to_le16(ICE_AQC_NVM_ERASE_LEN);
173 cmd->offset_low = 0;
174 cmd->offset_high = 0;
175
176 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
177}
178
179/**
180 * ice_read_sr_word_aq - Reads Shadow RAM via AQ
181 * @hw: pointer to the HW structure
182 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
183 * @data: word read from the Shadow RAM
184 *
185 * Reads one 16 bit word from the Shadow RAM using ice_read_flat_nvm.
186 */
187static int ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)
188{
189 u32 bytes = sizeof(u16);
190 __le16 data_local;
191 int status;
192
193 /* Note that ice_read_flat_nvm takes into account the 4Kb AdminQ and
194 * Shadow RAM sector restrictions necessary when reading from the NVM.
195 */
196 status = ice_read_flat_nvm(hw, offset * sizeof(u16), &bytes,
197 (__force u8 *)&data_local, true);
198 if (status)
199 return status;
200
201 *data = le16_to_cpu(data_local);
202 return 0;
203}
204
205/**
206 * ice_acquire_nvm - Generic request for acquiring the NVM ownership
207 * @hw: pointer to the HW structure
208 * @access: NVM access type (read or write)
209 *
210 * This function will request NVM ownership.
211 */
212int ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access)
213{
214 if (hw->flash.blank_nvm_mode)
215 return 0;
216
217 return ice_acquire_res(hw, ICE_NVM_RES_ID, access, ICE_NVM_TIMEOUT);
218}
219
220/**
221 * ice_release_nvm - Generic request for releasing the NVM ownership
222 * @hw: pointer to the HW structure
223 *
224 * This function will release NVM ownership.
225 */
226void ice_release_nvm(struct ice_hw *hw)
227{
228 if (hw->flash.blank_nvm_mode)
229 return;
230
231 ice_release_res(hw, ICE_NVM_RES_ID);
232}
233
234/**
235 * ice_get_flash_bank_offset - Get offset into requested flash bank
236 * @hw: pointer to the HW structure
237 * @bank: whether to read from the active or inactive flash bank
238 * @module: the module to read from
239 *
240 * Based on the module, lookup the module offset from the beginning of the
241 * flash.
242 *
243 * Returns the flash offset. Note that a value of zero is invalid and must be
244 * treated as an error.
245 */
246static u32 ice_get_flash_bank_offset(struct ice_hw *hw, enum ice_bank_select bank, u16 module)
247{
248 struct ice_bank_info *banks = &hw->flash.banks;
249 enum ice_flash_bank active_bank;
250 bool second_bank_active;
251 u32 offset, size;
252
253 switch (module) {
254 case ICE_SR_1ST_NVM_BANK_PTR:
255 offset = banks->nvm_ptr;
256 size = banks->nvm_size;
257 active_bank = banks->nvm_bank;
258 break;
259 case ICE_SR_1ST_OROM_BANK_PTR:
260 offset = banks->orom_ptr;
261 size = banks->orom_size;
262 active_bank = banks->orom_bank;
263 break;
264 case ICE_SR_NETLIST_BANK_PTR:
265 offset = banks->netlist_ptr;
266 size = banks->netlist_size;
267 active_bank = banks->netlist_bank;
268 break;
269 default:
270 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash module: 0x%04x\n", module);
271 return 0;
272 }
273
274 switch (active_bank) {
275 case ICE_1ST_FLASH_BANK:
276 second_bank_active = false;
277 break;
278 case ICE_2ND_FLASH_BANK:
279 second_bank_active = true;
280 break;
281 default:
282 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for active flash bank: %u\n",
283 active_bank);
284 return 0;
285 }
286
287 /* The second flash bank is stored immediately following the first
288 * bank. Based on whether the 1st or 2nd bank is active, and whether
289 * we want the active or inactive bank, calculate the desired offset.
290 */
291 switch (bank) {
292 case ICE_ACTIVE_FLASH_BANK:
293 return offset + (second_bank_active ? size : 0);
294 case ICE_INACTIVE_FLASH_BANK:
295 return offset + (second_bank_active ? 0 : size);
296 }
297
298 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash bank selection: %u\n", bank);
299 return 0;
300}
301
302/**
303 * ice_read_flash_module - Read a word from one of the main NVM modules
304 * @hw: pointer to the HW structure
305 * @bank: which bank of the module to read
306 * @module: the module to read
307 * @offset: the offset into the module in bytes
308 * @data: storage for the word read from the flash
309 * @length: bytes of data to read
310 *
311 * Read data from the specified flash module. The bank parameter indicates
312 * whether or not to read from the active bank or the inactive bank of that
313 * module.
314 *
315 * The word will be read using flat NVM access, and relies on the
316 * hw->flash.banks data being setup by ice_determine_active_flash_banks()
317 * during initialization.
318 */
319static int
320ice_read_flash_module(struct ice_hw *hw, enum ice_bank_select bank, u16 module,
321 u32 offset, u8 *data, u32 length)
322{
323 int status;
324 u32 start;
325
326 start = ice_get_flash_bank_offset(hw, bank, module);
327 if (!start) {
328 ice_debug(hw, ICE_DBG_NVM, "Unable to calculate flash bank offset for module 0x%04x\n",
329 module);
330 return -EINVAL;
331 }
332
333 status = ice_acquire_nvm(hw, ICE_RES_READ);
334 if (status)
335 return status;
336
337 status = ice_read_flat_nvm(hw, start + offset, &length, data, false);
338
339 ice_release_nvm(hw);
340
341 return status;
342}
343
344/**
345 * ice_read_nvm_module - Read from the active main NVM module
346 * @hw: pointer to the HW structure
347 * @bank: whether to read from active or inactive NVM module
348 * @offset: offset into the NVM module to read, in words
349 * @data: storage for returned word value
350 *
351 * Read the specified word from the active NVM module. This includes the CSS
352 * header at the start of the NVM module.
353 */
354static int
355ice_read_nvm_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
356{
357 __le16 data_local;
358 int status;
359
360 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_NVM_BANK_PTR, offset * sizeof(u16),
361 (__force u8 *)&data_local, sizeof(u16));
362 if (!status)
363 *data = le16_to_cpu(data_local);
364
365 return status;
366}
367
368/**
369 * ice_read_nvm_sr_copy - Read a word from the Shadow RAM copy in the NVM bank
370 * @hw: pointer to the HW structure
371 * @bank: whether to read from the active or inactive NVM module
372 * @offset: offset into the Shadow RAM copy to read, in words
373 * @data: storage for returned word value
374 *
375 * Read the specified word from the copy of the Shadow RAM found in the
376 * specified NVM module.
377 *
378 * Note that the Shadow RAM copy is always located after the CSS header, and
379 * is aligned to 64-byte (32-word) offsets.
380 */
381static int
382ice_read_nvm_sr_copy(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
383{
384 u32 sr_copy;
385
386 switch (bank) {
387 case ICE_ACTIVE_FLASH_BANK:
388 sr_copy = roundup(hw->flash.banks.active_css_hdr_len, 32);
389 break;
390 case ICE_INACTIVE_FLASH_BANK:
391 sr_copy = roundup(hw->flash.banks.inactive_css_hdr_len, 32);
392 break;
393 }
394
395 return ice_read_nvm_module(hw, bank, sr_copy + offset, data);
396}
397
398/**
399 * ice_read_netlist_module - Read data from the netlist module area
400 * @hw: pointer to the HW structure
401 * @bank: whether to read from the active or inactive module
402 * @offset: offset into the netlist to read from
403 * @data: storage for returned word value
404 *
405 * Read a word from the specified netlist bank.
406 */
407static int
408ice_read_netlist_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
409{
410 __le16 data_local;
411 int status;
412
413 status = ice_read_flash_module(hw, bank, ICE_SR_NETLIST_BANK_PTR, offset * sizeof(u16),
414 (__force u8 *)&data_local, sizeof(u16));
415 if (!status)
416 *data = le16_to_cpu(data_local);
417
418 return status;
419}
420
421/**
422 * ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary
423 * @hw: pointer to the HW structure
424 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
425 * @data: word read from the Shadow RAM
426 *
427 * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_word_aq.
428 */
429int ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
430{
431 int status;
432
433 status = ice_acquire_nvm(hw, ICE_RES_READ);
434 if (!status) {
435 status = ice_read_sr_word_aq(hw, offset, data);
436 ice_release_nvm(hw);
437 }
438
439 return status;
440}
441
442/**
443 * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA
444 * @hw: pointer to hardware structure
445 * @module_tlv: pointer to module TLV to return
446 * @module_tlv_len: pointer to module TLV length to return
447 * @module_type: module type requested
448 *
449 * Finds the requested sub module TLV type from the Preserved Field
450 * Area (PFA) and returns the TLV pointer and length. The caller can
451 * use these to read the variable length TLV value.
452 */
453int
454ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
455 u16 module_type)
456{
457 u16 pfa_len, pfa_ptr, next_tlv, max_tlv;
458 int status;
459
460 status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr);
461 if (status) {
462 ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n");
463 return status;
464 }
465 status = ice_read_sr_word(hw, pfa_ptr, &pfa_len);
466 if (status) {
467 ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n");
468 return status;
469 }
470
471 /* The Preserved Fields Area contains a sequence of Type-Length-Value
472 * structures which define its contents. The PFA length includes all
473 * of the TLVs, plus the initial length word itself, *and* one final
474 * word at the end after all of the TLVs.
475 */
476 if (check_add_overflow(pfa_ptr, pfa_len - 1, &max_tlv)) {
477 dev_warn(ice_hw_to_dev(hw), "PFA starts at offset %u. PFA length of %u caused 16-bit arithmetic overflow.\n",
478 pfa_ptr, pfa_len);
479 return -EINVAL;
480 }
481
482 /* Starting with first TLV after PFA length, iterate through the list
483 * of TLVs to find the requested one.
484 */
485 next_tlv = pfa_ptr + 1;
486 while (next_tlv < max_tlv) {
487 u16 tlv_sub_module_type;
488 u16 tlv_len;
489
490 /* Read TLV type */
491 status = ice_read_sr_word(hw, next_tlv, &tlv_sub_module_type);
492 if (status) {
493 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV type.\n");
494 break;
495 }
496 /* Read TLV length */
497 status = ice_read_sr_word(hw, next_tlv + 1, &tlv_len);
498 if (status) {
499 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n");
500 break;
501 }
502 if (tlv_sub_module_type == module_type) {
503 if (tlv_len) {
504 *module_tlv = next_tlv;
505 *module_tlv_len = tlv_len;
506 return 0;
507 }
508 return -EINVAL;
509 }
510
511 if (check_add_overflow(next_tlv, 2, &next_tlv) ||
512 check_add_overflow(next_tlv, tlv_len, &next_tlv)) {
513 dev_warn(ice_hw_to_dev(hw), "TLV of type %u and length 0x%04x caused 16-bit arithmetic overflow. The PFA starts at 0x%04x and has length of 0x%04x\n",
514 tlv_sub_module_type, tlv_len, pfa_ptr, pfa_len);
515 return -EINVAL;
516 }
517 }
518 /* Module does not exist */
519 return -ENOENT;
520}
521
522/**
523 * ice_read_pba_string - Reads part number string from NVM
524 * @hw: pointer to hardware structure
525 * @pba_num: stores the part number string from the NVM
526 * @pba_num_size: part number string buffer length
527 *
528 * Reads the part number string from the NVM.
529 */
530int ice_read_pba_string(struct ice_hw *hw, u8 *pba_num, u32 pba_num_size)
531{
532 u16 pba_tlv, pba_tlv_len;
533 u16 pba_word, pba_size;
534 int status;
535 u16 i;
536
537 status = ice_get_pfa_module_tlv(hw, &pba_tlv, &pba_tlv_len,
538 ICE_SR_PBA_BLOCK_PTR);
539 if (status) {
540 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block TLV.\n");
541 return status;
542 }
543
544 /* pba_size is the next word */
545 status = ice_read_sr_word(hw, (pba_tlv + 2), &pba_size);
546 if (status) {
547 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Section size.\n");
548 return status;
549 }
550
551 if (pba_tlv_len < pba_size) {
552 ice_debug(hw, ICE_DBG_INIT, "Invalid PBA Block TLV size.\n");
553 return -EINVAL;
554 }
555
556 /* Subtract one to get PBA word count (PBA Size word is included in
557 * total size)
558 */
559 pba_size--;
560 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
561 ice_debug(hw, ICE_DBG_INIT, "Buffer too small for PBA data.\n");
562 return -EINVAL;
563 }
564
565 for (i = 0; i < pba_size; i++) {
566 status = ice_read_sr_word(hw, (pba_tlv + 2 + 1) + i, &pba_word);
567 if (status) {
568 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block word %d.\n", i);
569 return status;
570 }
571
572 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
573 pba_num[(i * 2) + 1] = pba_word & 0xFF;
574 }
575 pba_num[(pba_size * 2)] = '\0';
576
577 return status;
578}
579
580/**
581 * ice_get_nvm_ver_info - Read NVM version information
582 * @hw: pointer to the HW struct
583 * @bank: whether to read from the active or inactive flash bank
584 * @nvm: pointer to NVM info structure
585 *
586 * Read the NVM EETRACK ID and map version of the main NVM image bank, filling
587 * in the NVM info structure.
588 */
589static int
590ice_get_nvm_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_nvm_info *nvm)
591{
592 u16 eetrack_lo, eetrack_hi, ver;
593 int status;
594
595 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_DEV_STARTER_VER, &ver);
596 if (status) {
597 ice_debug(hw, ICE_DBG_NVM, "Failed to read DEV starter version.\n");
598 return status;
599 }
600
601 nvm->major = FIELD_GET(ICE_NVM_VER_HI_MASK, ver);
602 nvm->minor = FIELD_GET(ICE_NVM_VER_LO_MASK, ver);
603
604 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);
605 if (status) {
606 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK lo.\n");
607 return status;
608 }
609 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);
610 if (status) {
611 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK hi.\n");
612 return status;
613 }
614
615 nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
616
617 return 0;
618}
619
620/**
621 * ice_get_inactive_nvm_ver - Read Option ROM version from the inactive bank
622 * @hw: pointer to the HW structure
623 * @nvm: storage for Option ROM version information
624 *
625 * Reads the NVM EETRACK ID, Map version, and security revision of the
626 * inactive NVM bank. Used to access version data for a pending update that
627 * has not yet been activated.
628 */
629int ice_get_inactive_nvm_ver(struct ice_hw *hw, struct ice_nvm_info *nvm)
630{
631 return ice_get_nvm_ver_info(hw, ICE_INACTIVE_FLASH_BANK, nvm);
632}
633
634/**
635 * ice_get_orom_civd_data - Get the combo version information from Option ROM
636 * @hw: pointer to the HW struct
637 * @bank: whether to read from the active or inactive flash module
638 * @civd: storage for the Option ROM CIVD data.
639 *
640 * Searches through the Option ROM flash contents to locate the CIVD data for
641 * the image.
642 */
643static int
644ice_get_orom_civd_data(struct ice_hw *hw, enum ice_bank_select bank,
645 struct ice_orom_civd_info *civd)
646{
647 u8 *orom_data;
648 int status;
649 u32 offset;
650
651 /* The CIVD section is located in the Option ROM aligned to 512 bytes.
652 * The first 4 bytes must contain the ASCII characters "$CIV".
653 * A simple modulo 256 sum of all of the bytes of the structure must
654 * equal 0.
655 *
656 * The exact location is unknown and varies between images but is
657 * usually somewhere in the middle of the bank. We need to scan the
658 * Option ROM bank to locate it.
659 *
660 * It's significantly faster to read the entire Option ROM up front
661 * using the maximum page size, than to read each possible location
662 * with a separate firmware command.
663 */
664 orom_data = vzalloc(hw->flash.banks.orom_size);
665 if (!orom_data)
666 return -ENOMEM;
667
668 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR, 0,
669 orom_data, hw->flash.banks.orom_size);
670 if (status) {
671 vfree(orom_data);
672 ice_debug(hw, ICE_DBG_NVM, "Unable to read Option ROM data\n");
673 return status;
674 }
675
676 /* Scan the memory buffer to locate the CIVD data section */
677 for (offset = 0; (offset + 512) <= hw->flash.banks.orom_size; offset += 512) {
678 struct ice_orom_civd_info *tmp;
679 u8 sum = 0, i;
680
681 tmp = (struct ice_orom_civd_info *)&orom_data[offset];
682
683 /* Skip forward until we find a matching signature */
684 if (memcmp("$CIV", tmp->signature, sizeof(tmp->signature)) != 0)
685 continue;
686
687 ice_debug(hw, ICE_DBG_NVM, "Found CIVD section at offset %u\n",
688 offset);
689
690 /* Verify that the simple checksum is zero */
691 for (i = 0; i < sizeof(*tmp); i++)
692 sum += ((u8 *)tmp)[i];
693
694 if (sum) {
695 ice_debug(hw, ICE_DBG_NVM, "Found CIVD data with invalid checksum of %u\n",
696 sum);
697 goto err_invalid_checksum;
698 }
699
700 *civd = *tmp;
701 vfree(orom_data);
702 return 0;
703 }
704
705 ice_debug(hw, ICE_DBG_NVM, "Unable to locate CIVD data within the Option ROM\n");
706
707err_invalid_checksum:
708 vfree(orom_data);
709 return -EIO;
710}
711
712/**
713 * ice_get_orom_ver_info - Read Option ROM version information
714 * @hw: pointer to the HW struct
715 * @bank: whether to read from the active or inactive flash module
716 * @orom: pointer to Option ROM info structure
717 *
718 * Read Option ROM version and security revision from the Option ROM flash
719 * section.
720 */
721static int
722ice_get_orom_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_orom_info *orom)
723{
724 struct ice_orom_civd_info civd;
725 u32 combo_ver;
726 int status;
727
728 status = ice_get_orom_civd_data(hw, bank, &civd);
729 if (status) {
730 ice_debug(hw, ICE_DBG_NVM, "Failed to locate valid Option ROM CIVD data\n");
731 return status;
732 }
733
734 combo_ver = le32_to_cpu(civd.combo_ver);
735
736 orom->major = FIELD_GET(ICE_OROM_VER_MASK, combo_ver);
737 orom->patch = FIELD_GET(ICE_OROM_VER_PATCH_MASK, combo_ver);
738 orom->build = FIELD_GET(ICE_OROM_VER_BUILD_MASK, combo_ver);
739
740 return 0;
741}
742
743/**
744 * ice_get_inactive_orom_ver - Read Option ROM version from the inactive bank
745 * @hw: pointer to the HW structure
746 * @orom: storage for Option ROM version information
747 *
748 * Reads the Option ROM version and security revision data for the inactive
749 * section of flash. Used to access version data for a pending update that has
750 * not yet been activated.
751 */
752int ice_get_inactive_orom_ver(struct ice_hw *hw, struct ice_orom_info *orom)
753{
754 return ice_get_orom_ver_info(hw, ICE_INACTIVE_FLASH_BANK, orom);
755}
756
757/**
758 * ice_get_netlist_info
759 * @hw: pointer to the HW struct
760 * @bank: whether to read from the active or inactive flash bank
761 * @netlist: pointer to netlist version info structure
762 *
763 * Get the netlist version information from the requested bank. Reads the Link
764 * Topology section to find the Netlist ID block and extract the relevant
765 * information into the netlist version structure.
766 */
767static int
768ice_get_netlist_info(struct ice_hw *hw, enum ice_bank_select bank,
769 struct ice_netlist_info *netlist)
770{
771 u16 module_id, length, node_count, i;
772 u16 *id_blk;
773 int status;
774
775 status = ice_read_netlist_module(hw, bank, ICE_NETLIST_TYPE_OFFSET, &module_id);
776 if (status)
777 return status;
778
779 if (module_id != ICE_NETLIST_LINK_TOPO_MOD_ID) {
780 ice_debug(hw, ICE_DBG_NVM, "Expected netlist module_id ID of 0x%04x, but got 0x%04x\n",
781 ICE_NETLIST_LINK_TOPO_MOD_ID, module_id);
782 return -EIO;
783 }
784
785 status = ice_read_netlist_module(hw, bank, ICE_LINK_TOPO_MODULE_LEN, &length);
786 if (status)
787 return status;
788
789 /* sanity check that we have at least enough words to store the netlist ID block */
790 if (length < ICE_NETLIST_ID_BLK_SIZE) {
791 ice_debug(hw, ICE_DBG_NVM, "Netlist Link Topology module too small. Expected at least %u words, but got %u words.\n",
792 ICE_NETLIST_ID_BLK_SIZE, length);
793 return -EIO;
794 }
795
796 status = ice_read_netlist_module(hw, bank, ICE_LINK_TOPO_NODE_COUNT, &node_count);
797 if (status)
798 return status;
799 node_count &= ICE_LINK_TOPO_NODE_COUNT_M;
800
801 id_blk = kcalloc(ICE_NETLIST_ID_BLK_SIZE, sizeof(*id_blk), GFP_KERNEL);
802 if (!id_blk)
803 return -ENOMEM;
804
805 /* Read out the entire Netlist ID Block at once. */
806 status = ice_read_flash_module(hw, bank, ICE_SR_NETLIST_BANK_PTR,
807 ICE_NETLIST_ID_BLK_OFFSET(node_count) * sizeof(u16),
808 (u8 *)id_blk, ICE_NETLIST_ID_BLK_SIZE * sizeof(u16));
809 if (status)
810 goto exit_error;
811
812 for (i = 0; i < ICE_NETLIST_ID_BLK_SIZE; i++)
813 id_blk[i] = le16_to_cpu(((__force __le16 *)id_blk)[i]);
814
815 netlist->major = id_blk[ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH] << 16 |
816 id_blk[ICE_NETLIST_ID_BLK_MAJOR_VER_LOW];
817 netlist->minor = id_blk[ICE_NETLIST_ID_BLK_MINOR_VER_HIGH] << 16 |
818 id_blk[ICE_NETLIST_ID_BLK_MINOR_VER_LOW];
819 netlist->type = id_blk[ICE_NETLIST_ID_BLK_TYPE_HIGH] << 16 |
820 id_blk[ICE_NETLIST_ID_BLK_TYPE_LOW];
821 netlist->rev = id_blk[ICE_NETLIST_ID_BLK_REV_HIGH] << 16 |
822 id_blk[ICE_NETLIST_ID_BLK_REV_LOW];
823 netlist->cust_ver = id_blk[ICE_NETLIST_ID_BLK_CUST_VER];
824 /* Read the left most 4 bytes of SHA */
825 netlist->hash = id_blk[ICE_NETLIST_ID_BLK_SHA_HASH_WORD(15)] << 16 |
826 id_blk[ICE_NETLIST_ID_BLK_SHA_HASH_WORD(14)];
827
828exit_error:
829 kfree(id_blk);
830
831 return status;
832}
833
834/**
835 * ice_get_inactive_netlist_ver
836 * @hw: pointer to the HW struct
837 * @netlist: pointer to netlist version info structure
838 *
839 * Read the netlist version data from the inactive netlist bank. Used to
840 * extract version data of a pending flash update in order to display the
841 * version data.
842 */
843int ice_get_inactive_netlist_ver(struct ice_hw *hw, struct ice_netlist_info *netlist)
844{
845 return ice_get_netlist_info(hw, ICE_INACTIVE_FLASH_BANK, netlist);
846}
847
848/**
849 * ice_discover_flash_size - Discover the available flash size.
850 * @hw: pointer to the HW struct
851 *
852 * The device flash could be up to 16MB in size. However, it is possible that
853 * the actual size is smaller. Use bisection to determine the accessible size
854 * of flash memory.
855 */
856static int ice_discover_flash_size(struct ice_hw *hw)
857{
858 u32 min_size = 0, max_size = ICE_AQC_NVM_MAX_OFFSET + 1;
859 int status;
860
861 status = ice_acquire_nvm(hw, ICE_RES_READ);
862 if (status)
863 return status;
864
865 while ((max_size - min_size) > 1) {
866 u32 offset = (max_size + min_size) / 2;
867 u32 len = 1;
868 u8 data;
869
870 status = ice_read_flat_nvm(hw, offset, &len, &data, false);
871 if (status == -EIO &&
872 hw->adminq.sq_last_status == ICE_AQ_RC_EINVAL) {
873 ice_debug(hw, ICE_DBG_NVM, "%s: New upper bound of %u bytes\n",
874 __func__, offset);
875 status = 0;
876 max_size = offset;
877 } else if (!status) {
878 ice_debug(hw, ICE_DBG_NVM, "%s: New lower bound of %u bytes\n",
879 __func__, offset);
880 min_size = offset;
881 } else {
882 /* an unexpected error occurred */
883 goto err_read_flat_nvm;
884 }
885 }
886
887 ice_debug(hw, ICE_DBG_NVM, "Predicted flash size is %u bytes\n", max_size);
888
889 hw->flash.flash_size = max_size;
890
891err_read_flat_nvm:
892 ice_release_nvm(hw);
893
894 return status;
895}
896
897/**
898 * ice_read_sr_pointer - Read the value of a Shadow RAM pointer word
899 * @hw: pointer to the HW structure
900 * @offset: the word offset of the Shadow RAM word to read
901 * @pointer: pointer value read from Shadow RAM
902 *
903 * Read the given Shadow RAM word, and convert it to a pointer value specified
904 * in bytes. This function assumes the specified offset is a valid pointer
905 * word.
906 *
907 * Each pointer word specifies whether it is stored in word size or 4KB
908 * sector size by using the highest bit. The reported pointer value will be in
909 * bytes, intended for flat NVM reads.
910 */
911static int ice_read_sr_pointer(struct ice_hw *hw, u16 offset, u32 *pointer)
912{
913 int status;
914 u16 value;
915
916 status = ice_read_sr_word(hw, offset, &value);
917 if (status)
918 return status;
919
920 /* Determine if the pointer is in 4KB or word units */
921 if (value & ICE_SR_NVM_PTR_4KB_UNITS)
922 *pointer = (value & ~ICE_SR_NVM_PTR_4KB_UNITS) * 4 * 1024;
923 else
924 *pointer = value * 2;
925
926 return 0;
927}
928
929/**
930 * ice_read_sr_area_size - Read an area size from a Shadow RAM word
931 * @hw: pointer to the HW structure
932 * @offset: the word offset of the Shadow RAM to read
933 * @size: size value read from the Shadow RAM
934 *
935 * Read the given Shadow RAM word, and convert it to an area size value
936 * specified in bytes. This function assumes the specified offset is a valid
937 * area size word.
938 *
939 * Each area size word is specified in 4KB sector units. This function reports
940 * the size in bytes, intended for flat NVM reads.
941 */
942static int ice_read_sr_area_size(struct ice_hw *hw, u16 offset, u32 *size)
943{
944 int status;
945 u16 value;
946
947 status = ice_read_sr_word(hw, offset, &value);
948 if (status)
949 return status;
950
951 /* Area sizes are always specified in 4KB units */
952 *size = value * 4 * 1024;
953
954 return 0;
955}
956
957/**
958 * ice_determine_active_flash_banks - Discover active bank for each module
959 * @hw: pointer to the HW struct
960 *
961 * Read the Shadow RAM control word and determine which banks are active for
962 * the NVM, OROM, and Netlist modules. Also read and calculate the associated
963 * pointer and size. These values are then cached into the ice_flash_info
964 * structure for later use in order to calculate the correct offset to read
965 * from the active module.
966 */
967static int ice_determine_active_flash_banks(struct ice_hw *hw)
968{
969 struct ice_bank_info *banks = &hw->flash.banks;
970 u16 ctrl_word;
971 int status;
972
973 status = ice_read_sr_word(hw, ICE_SR_NVM_CTRL_WORD, &ctrl_word);
974 if (status) {
975 ice_debug(hw, ICE_DBG_NVM, "Failed to read the Shadow RAM control word\n");
976 return status;
977 }
978
979 /* Check that the control word indicates validity */
980 if (FIELD_GET(ICE_SR_CTRL_WORD_1_M, ctrl_word) !=
981 ICE_SR_CTRL_WORD_VALID) {
982 ice_debug(hw, ICE_DBG_NVM, "Shadow RAM control word is invalid\n");
983 return -EIO;
984 }
985
986 if (!(ctrl_word & ICE_SR_CTRL_WORD_NVM_BANK))
987 banks->nvm_bank = ICE_1ST_FLASH_BANK;
988 else
989 banks->nvm_bank = ICE_2ND_FLASH_BANK;
990
991 if (!(ctrl_word & ICE_SR_CTRL_WORD_OROM_BANK))
992 banks->orom_bank = ICE_1ST_FLASH_BANK;
993 else
994 banks->orom_bank = ICE_2ND_FLASH_BANK;
995
996 if (!(ctrl_word & ICE_SR_CTRL_WORD_NETLIST_BANK))
997 banks->netlist_bank = ICE_1ST_FLASH_BANK;
998 else
999 banks->netlist_bank = ICE_2ND_FLASH_BANK;
1000
1001 status = ice_read_sr_pointer(hw, ICE_SR_1ST_NVM_BANK_PTR, &banks->nvm_ptr);
1002 if (status) {
1003 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank pointer\n");
1004 return status;
1005 }
1006
1007 status = ice_read_sr_area_size(hw, ICE_SR_NVM_BANK_SIZE, &banks->nvm_size);
1008 if (status) {
1009 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank area size\n");
1010 return status;
1011 }
1012
1013 status = ice_read_sr_pointer(hw, ICE_SR_1ST_OROM_BANK_PTR, &banks->orom_ptr);
1014 if (status) {
1015 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank pointer\n");
1016 return status;
1017 }
1018
1019 status = ice_read_sr_area_size(hw, ICE_SR_OROM_BANK_SIZE, &banks->orom_size);
1020 if (status) {
1021 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank area size\n");
1022 return status;
1023 }
1024
1025 status = ice_read_sr_pointer(hw, ICE_SR_NETLIST_BANK_PTR, &banks->netlist_ptr);
1026 if (status) {
1027 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank pointer\n");
1028 return status;
1029 }
1030
1031 status = ice_read_sr_area_size(hw, ICE_SR_NETLIST_BANK_SIZE, &banks->netlist_size);
1032 if (status) {
1033 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank area size\n");
1034 return status;
1035 }
1036
1037 return 0;
1038}
1039
1040/**
1041 * ice_get_nvm_css_hdr_len - Read the CSS header length from the NVM CSS header
1042 * @hw: pointer to the HW struct
1043 * @bank: whether to read from the active or inactive flash bank
1044 * @hdr_len: storage for header length in words
1045 *
1046 * Read the CSS header length from the NVM CSS header and add the Authentication
1047 * header size, and then convert to words.
1048 *
1049 * Return: zero on success, or a negative error code on failure.
1050 */
1051static int
1052ice_get_nvm_css_hdr_len(struct ice_hw *hw, enum ice_bank_select bank,
1053 u32 *hdr_len)
1054{
1055 u16 hdr_len_l, hdr_len_h;
1056 u32 hdr_len_dword;
1057 int status;
1058
1059 status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_HDR_LEN_L,
1060 &hdr_len_l);
1061 if (status)
1062 return status;
1063
1064 status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_HDR_LEN_H,
1065 &hdr_len_h);
1066 if (status)
1067 return status;
1068
1069 /* CSS header length is in DWORD, so convert to words and add
1070 * authentication header size
1071 */
1072 hdr_len_dword = hdr_len_h << 16 | hdr_len_l;
1073 *hdr_len = (hdr_len_dword * 2) + ICE_NVM_AUTH_HEADER_LEN;
1074
1075 return 0;
1076}
1077
1078/**
1079 * ice_determine_css_hdr_len - Discover CSS header length for the device
1080 * @hw: pointer to the HW struct
1081 *
1082 * Determine the size of the CSS header at the start of the NVM module. This
1083 * is useful for locating the Shadow RAM copy in the NVM, as the Shadow RAM is
1084 * always located just after the CSS header.
1085 *
1086 * Return: zero on success, or a negative error code on failure.
1087 */
1088static int ice_determine_css_hdr_len(struct ice_hw *hw)
1089{
1090 struct ice_bank_info *banks = &hw->flash.banks;
1091 int status;
1092
1093 status = ice_get_nvm_css_hdr_len(hw, ICE_ACTIVE_FLASH_BANK,
1094 &banks->active_css_hdr_len);
1095 if (status)
1096 return status;
1097
1098 status = ice_get_nvm_css_hdr_len(hw, ICE_INACTIVE_FLASH_BANK,
1099 &banks->inactive_css_hdr_len);
1100 if (status)
1101 return status;
1102
1103 return 0;
1104}
1105
1106/**
1107 * ice_init_nvm - initializes NVM setting
1108 * @hw: pointer to the HW struct
1109 *
1110 * This function reads and populates NVM settings such as Shadow RAM size,
1111 * max_timeout, and blank_nvm_mode
1112 */
1113int ice_init_nvm(struct ice_hw *hw)
1114{
1115 struct ice_flash_info *flash = &hw->flash;
1116 u32 fla, gens_stat;
1117 u8 sr_size;
1118 int status;
1119
1120 /* The SR size is stored regardless of the NVM programming mode
1121 * as the blank mode may be used in the factory line.
1122 */
1123 gens_stat = rd32(hw, GLNVM_GENS);
1124 sr_size = FIELD_GET(GLNVM_GENS_SR_SIZE_M, gens_stat);
1125
1126 /* Switching to words (sr_size contains power of 2) */
1127 flash->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;
1128
1129 /* Check if we are in the normal or blank NVM programming mode */
1130 fla = rd32(hw, GLNVM_FLA);
1131 if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */
1132 flash->blank_nvm_mode = false;
1133 } else {
1134 /* Blank programming mode */
1135 flash->blank_nvm_mode = true;
1136 ice_debug(hw, ICE_DBG_NVM, "NVM init error: unsupported blank mode.\n");
1137 return -EIO;
1138 }
1139
1140 status = ice_discover_flash_size(hw);
1141 if (status) {
1142 ice_debug(hw, ICE_DBG_NVM, "NVM init error: failed to discover flash size.\n");
1143 return status;
1144 }
1145
1146 status = ice_determine_active_flash_banks(hw);
1147 if (status) {
1148 ice_debug(hw, ICE_DBG_NVM, "Failed to determine active flash banks.\n");
1149 return status;
1150 }
1151
1152 status = ice_determine_css_hdr_len(hw);
1153 if (status) {
1154 ice_debug(hw, ICE_DBG_NVM, "Failed to determine Shadow RAM copy offsets.\n");
1155 return status;
1156 }
1157
1158 status = ice_get_nvm_ver_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->nvm);
1159 if (status) {
1160 ice_debug(hw, ICE_DBG_INIT, "Failed to read NVM info.\n");
1161 return status;
1162 }
1163
1164 status = ice_get_orom_ver_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->orom);
1165 if (status)
1166 ice_debug(hw, ICE_DBG_INIT, "Failed to read Option ROM info.\n");
1167
1168 /* read the netlist version information */
1169 status = ice_get_netlist_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->netlist);
1170 if (status)
1171 ice_debug(hw, ICE_DBG_INIT, "Failed to read netlist info.\n");
1172
1173 return 0;
1174}
1175
1176/**
1177 * ice_nvm_validate_checksum
1178 * @hw: pointer to the HW struct
1179 *
1180 * Verify NVM PFA checksum validity (0x0706)
1181 */
1182int ice_nvm_validate_checksum(struct ice_hw *hw)
1183{
1184 struct ice_aqc_nvm_checksum *cmd;
1185 struct ice_aq_desc desc;
1186 int status;
1187
1188 status = ice_acquire_nvm(hw, ICE_RES_READ);
1189 if (status)
1190 return status;
1191
1192 cmd = &desc.params.nvm_checksum;
1193
1194 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);
1195 cmd->flags = ICE_AQC_NVM_CHECKSUM_VERIFY;
1196
1197 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1198 ice_release_nvm(hw);
1199
1200 if (!status)
1201 if (le16_to_cpu(cmd->checksum) != ICE_AQC_NVM_CHECKSUM_CORRECT)
1202 status = -EIO;
1203
1204 return status;
1205}
1206
1207/**
1208 * ice_nvm_write_activate
1209 * @hw: pointer to the HW struct
1210 * @cmd_flags: flags for write activate command
1211 * @response_flags: response indicators from firmware
1212 *
1213 * Update the control word with the required banks' validity bits
1214 * and dumps the Shadow RAM to flash (0x0707)
1215 *
1216 * cmd_flags controls which banks to activate, the preservation level to use
1217 * when activating the NVM bank, and whether an EMP reset is required for
1218 * activation.
1219 *
1220 * Note that the 16bit cmd_flags value is split between two separate 1 byte
1221 * flag values in the descriptor.
1222 *
1223 * On successful return of the firmware command, the response_flags variable
1224 * is updated with the flags reported by firmware indicating certain status,
1225 * such as whether EMP reset is enabled.
1226 */
1227int ice_nvm_write_activate(struct ice_hw *hw, u16 cmd_flags, u8 *response_flags)
1228{
1229 struct ice_aqc_nvm *cmd;
1230 struct ice_aq_desc desc;
1231 int err;
1232
1233 cmd = &desc.params.nvm;
1234 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_write_activate);
1235
1236 cmd->cmd_flags = (u8)(cmd_flags & 0xFF);
1237 cmd->offset_high = (u8)((cmd_flags >> 8) & 0xFF);
1238
1239 err = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1240 if (!err && response_flags)
1241 *response_flags = cmd->cmd_flags;
1242
1243 return err;
1244}
1245
1246/**
1247 * ice_aq_nvm_update_empr
1248 * @hw: pointer to the HW struct
1249 *
1250 * Update empr (0x0709). This command allows SW to
1251 * request an EMPR to activate new FW.
1252 */
1253int ice_aq_nvm_update_empr(struct ice_hw *hw)
1254{
1255 struct ice_aq_desc desc;
1256
1257 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_update_empr);
1258
1259 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1260}
1261
1262/* ice_nvm_set_pkg_data
1263 * @hw: pointer to the HW struct
1264 * @del_pkg_data_flag: If is set then the current pkg_data store by FW
1265 * is deleted.
1266 * If bit is set to 1, then buffer should be size 0.
1267 * @data: pointer to buffer
1268 * @length: length of the buffer
1269 * @cd: pointer to command details structure or NULL
1270 *
1271 * Set package data (0x070A). This command is equivalent to the reception
1272 * of a PLDM FW Update GetPackageData cmd. This command should be sent
1273 * as part of the NVM update as the first cmd in the flow.
1274 */
1275
1276int
1277ice_nvm_set_pkg_data(struct ice_hw *hw, bool del_pkg_data_flag, u8 *data,
1278 u16 length, struct ice_sq_cd *cd)
1279{
1280 struct ice_aqc_nvm_pkg_data *cmd;
1281 struct ice_aq_desc desc;
1282
1283 if (length != 0 && !data)
1284 return -EINVAL;
1285
1286 cmd = &desc.params.pkg_data;
1287
1288 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_pkg_data);
1289 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1290
1291 if (del_pkg_data_flag)
1292 cmd->cmd_flags |= ICE_AQC_NVM_PKG_DELETE;
1293
1294 return ice_aq_send_cmd(hw, &desc, data, length, cd);
1295}
1296
1297/* ice_nvm_pass_component_tbl
1298 * @hw: pointer to the HW struct
1299 * @data: pointer to buffer
1300 * @length: length of the buffer
1301 * @transfer_flag: parameter for determining stage of the update
1302 * @comp_response: a pointer to the response from the 0x070B AQC.
1303 * @comp_response_code: a pointer to the response code from the 0x070B AQC.
1304 * @cd: pointer to command details structure or NULL
1305 *
1306 * Pass component table (0x070B). This command is equivalent to the reception
1307 * of a PLDM FW Update PassComponentTable cmd. This command should be sent once
1308 * per component. It can be only sent after Set Package Data cmd and before
1309 * actual update. FW will assume these commands are going to be sent until
1310 * the TransferFlag is set to End or StartAndEnd.
1311 */
1312
1313int
1314ice_nvm_pass_component_tbl(struct ice_hw *hw, u8 *data, u16 length,
1315 u8 transfer_flag, u8 *comp_response,
1316 u8 *comp_response_code, struct ice_sq_cd *cd)
1317{
1318 struct ice_aqc_nvm_pass_comp_tbl *cmd;
1319 struct ice_aq_desc desc;
1320 int status;
1321
1322 if (!data || !comp_response || !comp_response_code)
1323 return -EINVAL;
1324
1325 cmd = &desc.params.pass_comp_tbl;
1326
1327 ice_fill_dflt_direct_cmd_desc(&desc,
1328 ice_aqc_opc_nvm_pass_component_tbl);
1329 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1330
1331 cmd->transfer_flag = transfer_flag;
1332 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
1333
1334 if (!status) {
1335 *comp_response = cmd->component_response;
1336 *comp_response_code = cmd->component_response_code;
1337 }
1338 return status;
1339}
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2018, Intel Corporation. */
3
4#include <linux/vmalloc.h>
5
6#include "ice_common.h"
7
8/**
9 * ice_aq_read_nvm
10 * @hw: pointer to the HW struct
11 * @module_typeid: module pointer location in words from the NVM beginning
12 * @offset: byte offset from the module beginning
13 * @length: length of the section to be read (in bytes from the offset)
14 * @data: command buffer (size [bytes] = length)
15 * @last_command: tells if this is the last command in a series
16 * @read_shadow_ram: tell if this is a shadow RAM read
17 * @cd: pointer to command details structure or NULL
18 *
19 * Read the NVM using the admin queue commands (0x0701)
20 */
21static int
22ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,
23 void *data, bool last_command, bool read_shadow_ram,
24 struct ice_sq_cd *cd)
25{
26 struct ice_aq_desc desc;
27 struct ice_aqc_nvm *cmd;
28
29 cmd = &desc.params.nvm;
30
31 if (offset > ICE_AQC_NVM_MAX_OFFSET)
32 return -EINVAL;
33
34 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);
35
36 if (!read_shadow_ram && module_typeid == ICE_AQC_NVM_START_POINT)
37 cmd->cmd_flags |= ICE_AQC_NVM_FLASH_ONLY;
38
39 /* If this is the last command in a series, set the proper flag. */
40 if (last_command)
41 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
42 cmd->module_typeid = cpu_to_le16(module_typeid);
43 cmd->offset_low = cpu_to_le16(offset & 0xFFFF);
44 cmd->offset_high = (offset >> 16) & 0xFF;
45 cmd->length = cpu_to_le16(length);
46
47 return ice_aq_send_cmd(hw, &desc, data, length, cd);
48}
49
50/**
51 * ice_read_flat_nvm - Read portion of NVM by flat offset
52 * @hw: pointer to the HW struct
53 * @offset: offset from beginning of NVM
54 * @length: (in) number of bytes to read; (out) number of bytes actually read
55 * @data: buffer to return data in (sized to fit the specified length)
56 * @read_shadow_ram: if true, read from shadow RAM instead of NVM
57 *
58 * Reads a portion of the NVM, as a flat memory space. This function correctly
59 * breaks read requests across Shadow RAM sectors and ensures that no single
60 * read request exceeds the maximum 4KB read for a single AdminQ command.
61 *
62 * Returns a status code on failure. Note that the data pointer may be
63 * partially updated if some reads succeed before a failure.
64 */
65int
66ice_read_flat_nvm(struct ice_hw *hw, u32 offset, u32 *length, u8 *data,
67 bool read_shadow_ram)
68{
69 u32 inlen = *length;
70 u32 bytes_read = 0;
71 bool last_cmd;
72 int status;
73
74 *length = 0;
75
76 /* Verify the length of the read if this is for the Shadow RAM */
77 if (read_shadow_ram && ((offset + inlen) > (hw->flash.sr_words * 2u))) {
78 ice_debug(hw, ICE_DBG_NVM, "NVM error: requested offset is beyond Shadow RAM limit\n");
79 return -EINVAL;
80 }
81
82 do {
83 u32 read_size, sector_offset;
84
85 /* ice_aq_read_nvm cannot read more than 4KB at a time.
86 * Additionally, a read from the Shadow RAM may not cross over
87 * a sector boundary. Conveniently, the sector size is also
88 * 4KB.
89 */
90 sector_offset = offset % ICE_AQ_MAX_BUF_LEN;
91 read_size = min_t(u32, ICE_AQ_MAX_BUF_LEN - sector_offset,
92 inlen - bytes_read);
93
94 last_cmd = !(bytes_read + read_size < inlen);
95
96 status = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT,
97 offset, read_size,
98 data + bytes_read, last_cmd,
99 read_shadow_ram, NULL);
100 if (status)
101 break;
102
103 bytes_read += read_size;
104 offset += read_size;
105 } while (!last_cmd);
106
107 *length = bytes_read;
108 return status;
109}
110
111/**
112 * ice_aq_update_nvm
113 * @hw: pointer to the HW struct
114 * @module_typeid: module pointer location in words from the NVM beginning
115 * @offset: byte offset from the module beginning
116 * @length: length of the section to be written (in bytes from the offset)
117 * @data: command buffer (size [bytes] = length)
118 * @last_command: tells if this is the last command in a series
119 * @command_flags: command parameters
120 * @cd: pointer to command details structure or NULL
121 *
122 * Update the NVM using the admin queue commands (0x0703)
123 */
124int
125ice_aq_update_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset,
126 u16 length, void *data, bool last_command, u8 command_flags,
127 struct ice_sq_cd *cd)
128{
129 struct ice_aq_desc desc;
130 struct ice_aqc_nvm *cmd;
131
132 cmd = &desc.params.nvm;
133
134 /* In offset the highest byte must be zeroed. */
135 if (offset & 0xFF000000)
136 return -EINVAL;
137
138 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_write);
139
140 cmd->cmd_flags |= command_flags;
141
142 /* If this is the last command in a series, set the proper flag. */
143 if (last_command)
144 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
145 cmd->module_typeid = cpu_to_le16(module_typeid);
146 cmd->offset_low = cpu_to_le16(offset & 0xFFFF);
147 cmd->offset_high = (offset >> 16) & 0xFF;
148 cmd->length = cpu_to_le16(length);
149
150 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
151
152 return ice_aq_send_cmd(hw, &desc, data, length, cd);
153}
154
155/**
156 * ice_aq_erase_nvm
157 * @hw: pointer to the HW struct
158 * @module_typeid: module pointer location in words from the NVM beginning
159 * @cd: pointer to command details structure or NULL
160 *
161 * Erase the NVM sector using the admin queue commands (0x0702)
162 */
163int ice_aq_erase_nvm(struct ice_hw *hw, u16 module_typeid, struct ice_sq_cd *cd)
164{
165 struct ice_aq_desc desc;
166 struct ice_aqc_nvm *cmd;
167
168 cmd = &desc.params.nvm;
169
170 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_erase);
171
172 cmd->module_typeid = cpu_to_le16(module_typeid);
173 cmd->length = cpu_to_le16(ICE_AQC_NVM_ERASE_LEN);
174 cmd->offset_low = 0;
175 cmd->offset_high = 0;
176
177 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
178}
179
180/**
181 * ice_read_sr_word_aq - Reads Shadow RAM via AQ
182 * @hw: pointer to the HW structure
183 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
184 * @data: word read from the Shadow RAM
185 *
186 * Reads one 16 bit word from the Shadow RAM using ice_read_flat_nvm.
187 */
188static int ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)
189{
190 u32 bytes = sizeof(u16);
191 __le16 data_local;
192 int status;
193
194 /* Note that ice_read_flat_nvm takes into account the 4Kb AdminQ and
195 * Shadow RAM sector restrictions necessary when reading from the NVM.
196 */
197 status = ice_read_flat_nvm(hw, offset * sizeof(u16), &bytes,
198 (__force u8 *)&data_local, true);
199 if (status)
200 return status;
201
202 *data = le16_to_cpu(data_local);
203 return 0;
204}
205
206/**
207 * ice_acquire_nvm - Generic request for acquiring the NVM ownership
208 * @hw: pointer to the HW structure
209 * @access: NVM access type (read or write)
210 *
211 * This function will request NVM ownership.
212 */
213int ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access)
214{
215 if (hw->flash.blank_nvm_mode)
216 return 0;
217
218 return ice_acquire_res(hw, ICE_NVM_RES_ID, access, ICE_NVM_TIMEOUT);
219}
220
221/**
222 * ice_release_nvm - Generic request for releasing the NVM ownership
223 * @hw: pointer to the HW structure
224 *
225 * This function will release NVM ownership.
226 */
227void ice_release_nvm(struct ice_hw *hw)
228{
229 if (hw->flash.blank_nvm_mode)
230 return;
231
232 ice_release_res(hw, ICE_NVM_RES_ID);
233}
234
235/**
236 * ice_get_flash_bank_offset - Get offset into requested flash bank
237 * @hw: pointer to the HW structure
238 * @bank: whether to read from the active or inactive flash bank
239 * @module: the module to read from
240 *
241 * Based on the module, lookup the module offset from the beginning of the
242 * flash.
243 *
244 * Returns the flash offset. Note that a value of zero is invalid and must be
245 * treated as an error.
246 */
247static u32 ice_get_flash_bank_offset(struct ice_hw *hw, enum ice_bank_select bank, u16 module)
248{
249 struct ice_bank_info *banks = &hw->flash.banks;
250 enum ice_flash_bank active_bank;
251 bool second_bank_active;
252 u32 offset, size;
253
254 switch (module) {
255 case ICE_SR_1ST_NVM_BANK_PTR:
256 offset = banks->nvm_ptr;
257 size = banks->nvm_size;
258 active_bank = banks->nvm_bank;
259 break;
260 case ICE_SR_1ST_OROM_BANK_PTR:
261 offset = banks->orom_ptr;
262 size = banks->orom_size;
263 active_bank = banks->orom_bank;
264 break;
265 case ICE_SR_NETLIST_BANK_PTR:
266 offset = banks->netlist_ptr;
267 size = banks->netlist_size;
268 active_bank = banks->netlist_bank;
269 break;
270 default:
271 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash module: 0x%04x\n", module);
272 return 0;
273 }
274
275 switch (active_bank) {
276 case ICE_1ST_FLASH_BANK:
277 second_bank_active = false;
278 break;
279 case ICE_2ND_FLASH_BANK:
280 second_bank_active = true;
281 break;
282 default:
283 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for active flash bank: %u\n",
284 active_bank);
285 return 0;
286 }
287
288 /* The second flash bank is stored immediately following the first
289 * bank. Based on whether the 1st or 2nd bank is active, and whether
290 * we want the active or inactive bank, calculate the desired offset.
291 */
292 switch (bank) {
293 case ICE_ACTIVE_FLASH_BANK:
294 return offset + (second_bank_active ? size : 0);
295 case ICE_INACTIVE_FLASH_BANK:
296 return offset + (second_bank_active ? 0 : size);
297 }
298
299 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash bank selection: %u\n", bank);
300 return 0;
301}
302
303/**
304 * ice_read_flash_module - Read a word from one of the main NVM modules
305 * @hw: pointer to the HW structure
306 * @bank: which bank of the module to read
307 * @module: the module to read
308 * @offset: the offset into the module in bytes
309 * @data: storage for the word read from the flash
310 * @length: bytes of data to read
311 *
312 * Read data from the specified flash module. The bank parameter indicates
313 * whether or not to read from the active bank or the inactive bank of that
314 * module.
315 *
316 * The word will be read using flat NVM access, and relies on the
317 * hw->flash.banks data being setup by ice_determine_active_flash_banks()
318 * during initialization.
319 */
320static int
321ice_read_flash_module(struct ice_hw *hw, enum ice_bank_select bank, u16 module,
322 u32 offset, u8 *data, u32 length)
323{
324 int status;
325 u32 start;
326
327 start = ice_get_flash_bank_offset(hw, bank, module);
328 if (!start) {
329 ice_debug(hw, ICE_DBG_NVM, "Unable to calculate flash bank offset for module 0x%04x\n",
330 module);
331 return -EINVAL;
332 }
333
334 status = ice_acquire_nvm(hw, ICE_RES_READ);
335 if (status)
336 return status;
337
338 status = ice_read_flat_nvm(hw, start + offset, &length, data, false);
339
340 ice_release_nvm(hw);
341
342 return status;
343}
344
345/**
346 * ice_read_nvm_module - Read from the active main NVM module
347 * @hw: pointer to the HW structure
348 * @bank: whether to read from active or inactive NVM module
349 * @offset: offset into the NVM module to read, in words
350 * @data: storage for returned word value
351 *
352 * Read the specified word from the active NVM module. This includes the CSS
353 * header at the start of the NVM module.
354 */
355static int
356ice_read_nvm_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
357{
358 __le16 data_local;
359 int status;
360
361 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_NVM_BANK_PTR, offset * sizeof(u16),
362 (__force u8 *)&data_local, sizeof(u16));
363 if (!status)
364 *data = le16_to_cpu(data_local);
365
366 return status;
367}
368
369/**
370 * ice_read_nvm_sr_copy - Read a word from the Shadow RAM copy in the NVM bank
371 * @hw: pointer to the HW structure
372 * @bank: whether to read from the active or inactive NVM module
373 * @offset: offset into the Shadow RAM copy to read, in words
374 * @data: storage for returned word value
375 *
376 * Read the specified word from the copy of the Shadow RAM found in the
377 * specified NVM module.
378 */
379static int
380ice_read_nvm_sr_copy(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
381{
382 return ice_read_nvm_module(hw, bank, ICE_NVM_SR_COPY_WORD_OFFSET + offset, data);
383}
384
385/**
386 * ice_read_netlist_module - Read data from the netlist module area
387 * @hw: pointer to the HW structure
388 * @bank: whether to read from the active or inactive module
389 * @offset: offset into the netlist to read from
390 * @data: storage for returned word value
391 *
392 * Read a word from the specified netlist bank.
393 */
394static int
395ice_read_netlist_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
396{
397 __le16 data_local;
398 int status;
399
400 status = ice_read_flash_module(hw, bank, ICE_SR_NETLIST_BANK_PTR, offset * sizeof(u16),
401 (__force u8 *)&data_local, sizeof(u16));
402 if (!status)
403 *data = le16_to_cpu(data_local);
404
405 return status;
406}
407
408/**
409 * ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary
410 * @hw: pointer to the HW structure
411 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
412 * @data: word read from the Shadow RAM
413 *
414 * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_word_aq.
415 */
416int ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
417{
418 int status;
419
420 status = ice_acquire_nvm(hw, ICE_RES_READ);
421 if (!status) {
422 status = ice_read_sr_word_aq(hw, offset, data);
423 ice_release_nvm(hw);
424 }
425
426 return status;
427}
428
429/**
430 * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA
431 * @hw: pointer to hardware structure
432 * @module_tlv: pointer to module TLV to return
433 * @module_tlv_len: pointer to module TLV length to return
434 * @module_type: module type requested
435 *
436 * Finds the requested sub module TLV type from the Preserved Field
437 * Area (PFA) and returns the TLV pointer and length. The caller can
438 * use these to read the variable length TLV value.
439 */
440int
441ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
442 u16 module_type)
443{
444 u16 pfa_len, pfa_ptr;
445 u16 next_tlv;
446 int status;
447
448 status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr);
449 if (status) {
450 ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n");
451 return status;
452 }
453 status = ice_read_sr_word(hw, pfa_ptr, &pfa_len);
454 if (status) {
455 ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n");
456 return status;
457 }
458 /* Starting with first TLV after PFA length, iterate through the list
459 * of TLVs to find the requested one.
460 */
461 next_tlv = pfa_ptr + 1;
462 while (next_tlv < pfa_ptr + pfa_len) {
463 u16 tlv_sub_module_type;
464 u16 tlv_len;
465
466 /* Read TLV type */
467 status = ice_read_sr_word(hw, next_tlv, &tlv_sub_module_type);
468 if (status) {
469 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV type.\n");
470 break;
471 }
472 /* Read TLV length */
473 status = ice_read_sr_word(hw, next_tlv + 1, &tlv_len);
474 if (status) {
475 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n");
476 break;
477 }
478 if (tlv_sub_module_type == module_type) {
479 if (tlv_len) {
480 *module_tlv = next_tlv;
481 *module_tlv_len = tlv_len;
482 return 0;
483 }
484 return -EINVAL;
485 }
486 /* Check next TLV, i.e. current TLV pointer + length + 2 words
487 * (for current TLV's type and length)
488 */
489 next_tlv = next_tlv + tlv_len + 2;
490 }
491 /* Module does not exist */
492 return -ENOENT;
493}
494
495/**
496 * ice_read_pba_string - Reads part number string from NVM
497 * @hw: pointer to hardware structure
498 * @pba_num: stores the part number string from the NVM
499 * @pba_num_size: part number string buffer length
500 *
501 * Reads the part number string from the NVM.
502 */
503int ice_read_pba_string(struct ice_hw *hw, u8 *pba_num, u32 pba_num_size)
504{
505 u16 pba_tlv, pba_tlv_len;
506 u16 pba_word, pba_size;
507 int status;
508 u16 i;
509
510 status = ice_get_pfa_module_tlv(hw, &pba_tlv, &pba_tlv_len,
511 ICE_SR_PBA_BLOCK_PTR);
512 if (status) {
513 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block TLV.\n");
514 return status;
515 }
516
517 /* pba_size is the next word */
518 status = ice_read_sr_word(hw, (pba_tlv + 2), &pba_size);
519 if (status) {
520 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Section size.\n");
521 return status;
522 }
523
524 if (pba_tlv_len < pba_size) {
525 ice_debug(hw, ICE_DBG_INIT, "Invalid PBA Block TLV size.\n");
526 return -EINVAL;
527 }
528
529 /* Subtract one to get PBA word count (PBA Size word is included in
530 * total size)
531 */
532 pba_size--;
533 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
534 ice_debug(hw, ICE_DBG_INIT, "Buffer too small for PBA data.\n");
535 return -EINVAL;
536 }
537
538 for (i = 0; i < pba_size; i++) {
539 status = ice_read_sr_word(hw, (pba_tlv + 2 + 1) + i, &pba_word);
540 if (status) {
541 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block word %d.\n", i);
542 return status;
543 }
544
545 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
546 pba_num[(i * 2) + 1] = pba_word & 0xFF;
547 }
548 pba_num[(pba_size * 2)] = '\0';
549
550 return status;
551}
552
553/**
554 * ice_get_nvm_ver_info - Read NVM version information
555 * @hw: pointer to the HW struct
556 * @bank: whether to read from the active or inactive flash bank
557 * @nvm: pointer to NVM info structure
558 *
559 * Read the NVM EETRACK ID and map version of the main NVM image bank, filling
560 * in the NVM info structure.
561 */
562static int
563ice_get_nvm_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_nvm_info *nvm)
564{
565 u16 eetrack_lo, eetrack_hi, ver;
566 int status;
567
568 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_DEV_STARTER_VER, &ver);
569 if (status) {
570 ice_debug(hw, ICE_DBG_NVM, "Failed to read DEV starter version.\n");
571 return status;
572 }
573
574 nvm->major = FIELD_GET(ICE_NVM_VER_HI_MASK, ver);
575 nvm->minor = FIELD_GET(ICE_NVM_VER_LO_MASK, ver);
576
577 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);
578 if (status) {
579 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK lo.\n");
580 return status;
581 }
582 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);
583 if (status) {
584 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK hi.\n");
585 return status;
586 }
587
588 nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
589
590 return 0;
591}
592
593/**
594 * ice_get_inactive_nvm_ver - Read Option ROM version from the inactive bank
595 * @hw: pointer to the HW structure
596 * @nvm: storage for Option ROM version information
597 *
598 * Reads the NVM EETRACK ID, Map version, and security revision of the
599 * inactive NVM bank. Used to access version data for a pending update that
600 * has not yet been activated.
601 */
602int ice_get_inactive_nvm_ver(struct ice_hw *hw, struct ice_nvm_info *nvm)
603{
604 return ice_get_nvm_ver_info(hw, ICE_INACTIVE_FLASH_BANK, nvm);
605}
606
607/**
608 * ice_get_orom_civd_data - Get the combo version information from Option ROM
609 * @hw: pointer to the HW struct
610 * @bank: whether to read from the active or inactive flash module
611 * @civd: storage for the Option ROM CIVD data.
612 *
613 * Searches through the Option ROM flash contents to locate the CIVD data for
614 * the image.
615 */
616static int
617ice_get_orom_civd_data(struct ice_hw *hw, enum ice_bank_select bank,
618 struct ice_orom_civd_info *civd)
619{
620 u8 *orom_data;
621 int status;
622 u32 offset;
623
624 /* The CIVD section is located in the Option ROM aligned to 512 bytes.
625 * The first 4 bytes must contain the ASCII characters "$CIV".
626 * A simple modulo 256 sum of all of the bytes of the structure must
627 * equal 0.
628 *
629 * The exact location is unknown and varies between images but is
630 * usually somewhere in the middle of the bank. We need to scan the
631 * Option ROM bank to locate it.
632 *
633 * It's significantly faster to read the entire Option ROM up front
634 * using the maximum page size, than to read each possible location
635 * with a separate firmware command.
636 */
637 orom_data = vzalloc(hw->flash.banks.orom_size);
638 if (!orom_data)
639 return -ENOMEM;
640
641 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR, 0,
642 orom_data, hw->flash.banks.orom_size);
643 if (status) {
644 vfree(orom_data);
645 ice_debug(hw, ICE_DBG_NVM, "Unable to read Option ROM data\n");
646 return status;
647 }
648
649 /* Scan the memory buffer to locate the CIVD data section */
650 for (offset = 0; (offset + 512) <= hw->flash.banks.orom_size; offset += 512) {
651 struct ice_orom_civd_info *tmp;
652 u8 sum = 0, i;
653
654 tmp = (struct ice_orom_civd_info *)&orom_data[offset];
655
656 /* Skip forward until we find a matching signature */
657 if (memcmp("$CIV", tmp->signature, sizeof(tmp->signature)) != 0)
658 continue;
659
660 ice_debug(hw, ICE_DBG_NVM, "Found CIVD section at offset %u\n",
661 offset);
662
663 /* Verify that the simple checksum is zero */
664 for (i = 0; i < sizeof(*tmp); i++)
665 sum += ((u8 *)tmp)[i];
666
667 if (sum) {
668 ice_debug(hw, ICE_DBG_NVM, "Found CIVD data with invalid checksum of %u\n",
669 sum);
670 goto err_invalid_checksum;
671 }
672
673 *civd = *tmp;
674 vfree(orom_data);
675 return 0;
676 }
677
678 ice_debug(hw, ICE_DBG_NVM, "Unable to locate CIVD data within the Option ROM\n");
679
680err_invalid_checksum:
681 vfree(orom_data);
682 return -EIO;
683}
684
685/**
686 * ice_get_orom_ver_info - Read Option ROM version information
687 * @hw: pointer to the HW struct
688 * @bank: whether to read from the active or inactive flash module
689 * @orom: pointer to Option ROM info structure
690 *
691 * Read Option ROM version and security revision from the Option ROM flash
692 * section.
693 */
694static int
695ice_get_orom_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_orom_info *orom)
696{
697 struct ice_orom_civd_info civd;
698 u32 combo_ver;
699 int status;
700
701 status = ice_get_orom_civd_data(hw, bank, &civd);
702 if (status) {
703 ice_debug(hw, ICE_DBG_NVM, "Failed to locate valid Option ROM CIVD data\n");
704 return status;
705 }
706
707 combo_ver = le32_to_cpu(civd.combo_ver);
708
709 orom->major = FIELD_GET(ICE_OROM_VER_MASK, combo_ver);
710 orom->patch = FIELD_GET(ICE_OROM_VER_PATCH_MASK, combo_ver);
711 orom->build = FIELD_GET(ICE_OROM_VER_BUILD_MASK, combo_ver);
712
713 return 0;
714}
715
716/**
717 * ice_get_inactive_orom_ver - Read Option ROM version from the inactive bank
718 * @hw: pointer to the HW structure
719 * @orom: storage for Option ROM version information
720 *
721 * Reads the Option ROM version and security revision data for the inactive
722 * section of flash. Used to access version data for a pending update that has
723 * not yet been activated.
724 */
725int ice_get_inactive_orom_ver(struct ice_hw *hw, struct ice_orom_info *orom)
726{
727 return ice_get_orom_ver_info(hw, ICE_INACTIVE_FLASH_BANK, orom);
728}
729
730/**
731 * ice_get_netlist_info
732 * @hw: pointer to the HW struct
733 * @bank: whether to read from the active or inactive flash bank
734 * @netlist: pointer to netlist version info structure
735 *
736 * Get the netlist version information from the requested bank. Reads the Link
737 * Topology section to find the Netlist ID block and extract the relevant
738 * information into the netlist version structure.
739 */
740static int
741ice_get_netlist_info(struct ice_hw *hw, enum ice_bank_select bank,
742 struct ice_netlist_info *netlist)
743{
744 u16 module_id, length, node_count, i;
745 u16 *id_blk;
746 int status;
747
748 status = ice_read_netlist_module(hw, bank, ICE_NETLIST_TYPE_OFFSET, &module_id);
749 if (status)
750 return status;
751
752 if (module_id != ICE_NETLIST_LINK_TOPO_MOD_ID) {
753 ice_debug(hw, ICE_DBG_NVM, "Expected netlist module_id ID of 0x%04x, but got 0x%04x\n",
754 ICE_NETLIST_LINK_TOPO_MOD_ID, module_id);
755 return -EIO;
756 }
757
758 status = ice_read_netlist_module(hw, bank, ICE_LINK_TOPO_MODULE_LEN, &length);
759 if (status)
760 return status;
761
762 /* sanity check that we have at least enough words to store the netlist ID block */
763 if (length < ICE_NETLIST_ID_BLK_SIZE) {
764 ice_debug(hw, ICE_DBG_NVM, "Netlist Link Topology module too small. Expected at least %u words, but got %u words.\n",
765 ICE_NETLIST_ID_BLK_SIZE, length);
766 return -EIO;
767 }
768
769 status = ice_read_netlist_module(hw, bank, ICE_LINK_TOPO_NODE_COUNT, &node_count);
770 if (status)
771 return status;
772 node_count &= ICE_LINK_TOPO_NODE_COUNT_M;
773
774 id_blk = kcalloc(ICE_NETLIST_ID_BLK_SIZE, sizeof(*id_blk), GFP_KERNEL);
775 if (!id_blk)
776 return -ENOMEM;
777
778 /* Read out the entire Netlist ID Block at once. */
779 status = ice_read_flash_module(hw, bank, ICE_SR_NETLIST_BANK_PTR,
780 ICE_NETLIST_ID_BLK_OFFSET(node_count) * sizeof(u16),
781 (u8 *)id_blk, ICE_NETLIST_ID_BLK_SIZE * sizeof(u16));
782 if (status)
783 goto exit_error;
784
785 for (i = 0; i < ICE_NETLIST_ID_BLK_SIZE; i++)
786 id_blk[i] = le16_to_cpu(((__force __le16 *)id_blk)[i]);
787
788 netlist->major = id_blk[ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH] << 16 |
789 id_blk[ICE_NETLIST_ID_BLK_MAJOR_VER_LOW];
790 netlist->minor = id_blk[ICE_NETLIST_ID_BLK_MINOR_VER_HIGH] << 16 |
791 id_blk[ICE_NETLIST_ID_BLK_MINOR_VER_LOW];
792 netlist->type = id_blk[ICE_NETLIST_ID_BLK_TYPE_HIGH] << 16 |
793 id_blk[ICE_NETLIST_ID_BLK_TYPE_LOW];
794 netlist->rev = id_blk[ICE_NETLIST_ID_BLK_REV_HIGH] << 16 |
795 id_blk[ICE_NETLIST_ID_BLK_REV_LOW];
796 netlist->cust_ver = id_blk[ICE_NETLIST_ID_BLK_CUST_VER];
797 /* Read the left most 4 bytes of SHA */
798 netlist->hash = id_blk[ICE_NETLIST_ID_BLK_SHA_HASH_WORD(15)] << 16 |
799 id_blk[ICE_NETLIST_ID_BLK_SHA_HASH_WORD(14)];
800
801exit_error:
802 kfree(id_blk);
803
804 return status;
805}
806
807/**
808 * ice_get_inactive_netlist_ver
809 * @hw: pointer to the HW struct
810 * @netlist: pointer to netlist version info structure
811 *
812 * Read the netlist version data from the inactive netlist bank. Used to
813 * extract version data of a pending flash update in order to display the
814 * version data.
815 */
816int ice_get_inactive_netlist_ver(struct ice_hw *hw, struct ice_netlist_info *netlist)
817{
818 return ice_get_netlist_info(hw, ICE_INACTIVE_FLASH_BANK, netlist);
819}
820
821/**
822 * ice_discover_flash_size - Discover the available flash size.
823 * @hw: pointer to the HW struct
824 *
825 * The device flash could be up to 16MB in size. However, it is possible that
826 * the actual size is smaller. Use bisection to determine the accessible size
827 * of flash memory.
828 */
829static int ice_discover_flash_size(struct ice_hw *hw)
830{
831 u32 min_size = 0, max_size = ICE_AQC_NVM_MAX_OFFSET + 1;
832 int status;
833
834 status = ice_acquire_nvm(hw, ICE_RES_READ);
835 if (status)
836 return status;
837
838 while ((max_size - min_size) > 1) {
839 u32 offset = (max_size + min_size) / 2;
840 u32 len = 1;
841 u8 data;
842
843 status = ice_read_flat_nvm(hw, offset, &len, &data, false);
844 if (status == -EIO &&
845 hw->adminq.sq_last_status == ICE_AQ_RC_EINVAL) {
846 ice_debug(hw, ICE_DBG_NVM, "%s: New upper bound of %u bytes\n",
847 __func__, offset);
848 status = 0;
849 max_size = offset;
850 } else if (!status) {
851 ice_debug(hw, ICE_DBG_NVM, "%s: New lower bound of %u bytes\n",
852 __func__, offset);
853 min_size = offset;
854 } else {
855 /* an unexpected error occurred */
856 goto err_read_flat_nvm;
857 }
858 }
859
860 ice_debug(hw, ICE_DBG_NVM, "Predicted flash size is %u bytes\n", max_size);
861
862 hw->flash.flash_size = max_size;
863
864err_read_flat_nvm:
865 ice_release_nvm(hw);
866
867 return status;
868}
869
870/**
871 * ice_read_sr_pointer - Read the value of a Shadow RAM pointer word
872 * @hw: pointer to the HW structure
873 * @offset: the word offset of the Shadow RAM word to read
874 * @pointer: pointer value read from Shadow RAM
875 *
876 * Read the given Shadow RAM word, and convert it to a pointer value specified
877 * in bytes. This function assumes the specified offset is a valid pointer
878 * word.
879 *
880 * Each pointer word specifies whether it is stored in word size or 4KB
881 * sector size by using the highest bit. The reported pointer value will be in
882 * bytes, intended for flat NVM reads.
883 */
884static int ice_read_sr_pointer(struct ice_hw *hw, u16 offset, u32 *pointer)
885{
886 int status;
887 u16 value;
888
889 status = ice_read_sr_word(hw, offset, &value);
890 if (status)
891 return status;
892
893 /* Determine if the pointer is in 4KB or word units */
894 if (value & ICE_SR_NVM_PTR_4KB_UNITS)
895 *pointer = (value & ~ICE_SR_NVM_PTR_4KB_UNITS) * 4 * 1024;
896 else
897 *pointer = value * 2;
898
899 return 0;
900}
901
902/**
903 * ice_read_sr_area_size - Read an area size from a Shadow RAM word
904 * @hw: pointer to the HW structure
905 * @offset: the word offset of the Shadow RAM to read
906 * @size: size value read from the Shadow RAM
907 *
908 * Read the given Shadow RAM word, and convert it to an area size value
909 * specified in bytes. This function assumes the specified offset is a valid
910 * area size word.
911 *
912 * Each area size word is specified in 4KB sector units. This function reports
913 * the size in bytes, intended for flat NVM reads.
914 */
915static int ice_read_sr_area_size(struct ice_hw *hw, u16 offset, u32 *size)
916{
917 int status;
918 u16 value;
919
920 status = ice_read_sr_word(hw, offset, &value);
921 if (status)
922 return status;
923
924 /* Area sizes are always specified in 4KB units */
925 *size = value * 4 * 1024;
926
927 return 0;
928}
929
930/**
931 * ice_determine_active_flash_banks - Discover active bank for each module
932 * @hw: pointer to the HW struct
933 *
934 * Read the Shadow RAM control word and determine which banks are active for
935 * the NVM, OROM, and Netlist modules. Also read and calculate the associated
936 * pointer and size. These values are then cached into the ice_flash_info
937 * structure for later use in order to calculate the correct offset to read
938 * from the active module.
939 */
940static int ice_determine_active_flash_banks(struct ice_hw *hw)
941{
942 struct ice_bank_info *banks = &hw->flash.banks;
943 u16 ctrl_word;
944 int status;
945
946 status = ice_read_sr_word(hw, ICE_SR_NVM_CTRL_WORD, &ctrl_word);
947 if (status) {
948 ice_debug(hw, ICE_DBG_NVM, "Failed to read the Shadow RAM control word\n");
949 return status;
950 }
951
952 /* Check that the control word indicates validity */
953 if (FIELD_GET(ICE_SR_CTRL_WORD_1_M, ctrl_word) !=
954 ICE_SR_CTRL_WORD_VALID) {
955 ice_debug(hw, ICE_DBG_NVM, "Shadow RAM control word is invalid\n");
956 return -EIO;
957 }
958
959 if (!(ctrl_word & ICE_SR_CTRL_WORD_NVM_BANK))
960 banks->nvm_bank = ICE_1ST_FLASH_BANK;
961 else
962 banks->nvm_bank = ICE_2ND_FLASH_BANK;
963
964 if (!(ctrl_word & ICE_SR_CTRL_WORD_OROM_BANK))
965 banks->orom_bank = ICE_1ST_FLASH_BANK;
966 else
967 banks->orom_bank = ICE_2ND_FLASH_BANK;
968
969 if (!(ctrl_word & ICE_SR_CTRL_WORD_NETLIST_BANK))
970 banks->netlist_bank = ICE_1ST_FLASH_BANK;
971 else
972 banks->netlist_bank = ICE_2ND_FLASH_BANK;
973
974 status = ice_read_sr_pointer(hw, ICE_SR_1ST_NVM_BANK_PTR, &banks->nvm_ptr);
975 if (status) {
976 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank pointer\n");
977 return status;
978 }
979
980 status = ice_read_sr_area_size(hw, ICE_SR_NVM_BANK_SIZE, &banks->nvm_size);
981 if (status) {
982 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank area size\n");
983 return status;
984 }
985
986 status = ice_read_sr_pointer(hw, ICE_SR_1ST_OROM_BANK_PTR, &banks->orom_ptr);
987 if (status) {
988 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank pointer\n");
989 return status;
990 }
991
992 status = ice_read_sr_area_size(hw, ICE_SR_OROM_BANK_SIZE, &banks->orom_size);
993 if (status) {
994 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank area size\n");
995 return status;
996 }
997
998 status = ice_read_sr_pointer(hw, ICE_SR_NETLIST_BANK_PTR, &banks->netlist_ptr);
999 if (status) {
1000 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank pointer\n");
1001 return status;
1002 }
1003
1004 status = ice_read_sr_area_size(hw, ICE_SR_NETLIST_BANK_SIZE, &banks->netlist_size);
1005 if (status) {
1006 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank area size\n");
1007 return status;
1008 }
1009
1010 return 0;
1011}
1012
1013/**
1014 * ice_init_nvm - initializes NVM setting
1015 * @hw: pointer to the HW struct
1016 *
1017 * This function reads and populates NVM settings such as Shadow RAM size,
1018 * max_timeout, and blank_nvm_mode
1019 */
1020int ice_init_nvm(struct ice_hw *hw)
1021{
1022 struct ice_flash_info *flash = &hw->flash;
1023 u32 fla, gens_stat;
1024 u8 sr_size;
1025 int status;
1026
1027 /* The SR size is stored regardless of the NVM programming mode
1028 * as the blank mode may be used in the factory line.
1029 */
1030 gens_stat = rd32(hw, GLNVM_GENS);
1031 sr_size = FIELD_GET(GLNVM_GENS_SR_SIZE_M, gens_stat);
1032
1033 /* Switching to words (sr_size contains power of 2) */
1034 flash->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;
1035
1036 /* Check if we are in the normal or blank NVM programming mode */
1037 fla = rd32(hw, GLNVM_FLA);
1038 if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */
1039 flash->blank_nvm_mode = false;
1040 } else {
1041 /* Blank programming mode */
1042 flash->blank_nvm_mode = true;
1043 ice_debug(hw, ICE_DBG_NVM, "NVM init error: unsupported blank mode.\n");
1044 return -EIO;
1045 }
1046
1047 status = ice_discover_flash_size(hw);
1048 if (status) {
1049 ice_debug(hw, ICE_DBG_NVM, "NVM init error: failed to discover flash size.\n");
1050 return status;
1051 }
1052
1053 status = ice_determine_active_flash_banks(hw);
1054 if (status) {
1055 ice_debug(hw, ICE_DBG_NVM, "Failed to determine active flash banks.\n");
1056 return status;
1057 }
1058
1059 status = ice_get_nvm_ver_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->nvm);
1060 if (status) {
1061 ice_debug(hw, ICE_DBG_INIT, "Failed to read NVM info.\n");
1062 return status;
1063 }
1064
1065 status = ice_get_orom_ver_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->orom);
1066 if (status)
1067 ice_debug(hw, ICE_DBG_INIT, "Failed to read Option ROM info.\n");
1068
1069 /* read the netlist version information */
1070 status = ice_get_netlist_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->netlist);
1071 if (status)
1072 ice_debug(hw, ICE_DBG_INIT, "Failed to read netlist info.\n");
1073
1074 return 0;
1075}
1076
1077/**
1078 * ice_nvm_validate_checksum
1079 * @hw: pointer to the HW struct
1080 *
1081 * Verify NVM PFA checksum validity (0x0706)
1082 */
1083int ice_nvm_validate_checksum(struct ice_hw *hw)
1084{
1085 struct ice_aqc_nvm_checksum *cmd;
1086 struct ice_aq_desc desc;
1087 int status;
1088
1089 status = ice_acquire_nvm(hw, ICE_RES_READ);
1090 if (status)
1091 return status;
1092
1093 cmd = &desc.params.nvm_checksum;
1094
1095 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);
1096 cmd->flags = ICE_AQC_NVM_CHECKSUM_VERIFY;
1097
1098 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1099 ice_release_nvm(hw);
1100
1101 if (!status)
1102 if (le16_to_cpu(cmd->checksum) != ICE_AQC_NVM_CHECKSUM_CORRECT)
1103 status = -EIO;
1104
1105 return status;
1106}
1107
1108/**
1109 * ice_nvm_write_activate
1110 * @hw: pointer to the HW struct
1111 * @cmd_flags: flags for write activate command
1112 * @response_flags: response indicators from firmware
1113 *
1114 * Update the control word with the required banks' validity bits
1115 * and dumps the Shadow RAM to flash (0x0707)
1116 *
1117 * cmd_flags controls which banks to activate, the preservation level to use
1118 * when activating the NVM bank, and whether an EMP reset is required for
1119 * activation.
1120 *
1121 * Note that the 16bit cmd_flags value is split between two separate 1 byte
1122 * flag values in the descriptor.
1123 *
1124 * On successful return of the firmware command, the response_flags variable
1125 * is updated with the flags reported by firmware indicating certain status,
1126 * such as whether EMP reset is enabled.
1127 */
1128int ice_nvm_write_activate(struct ice_hw *hw, u16 cmd_flags, u8 *response_flags)
1129{
1130 struct ice_aqc_nvm *cmd;
1131 struct ice_aq_desc desc;
1132 int err;
1133
1134 cmd = &desc.params.nvm;
1135 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_write_activate);
1136
1137 cmd->cmd_flags = (u8)(cmd_flags & 0xFF);
1138 cmd->offset_high = (u8)((cmd_flags >> 8) & 0xFF);
1139
1140 err = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1141 if (!err && response_flags)
1142 *response_flags = cmd->cmd_flags;
1143
1144 return err;
1145}
1146
1147/**
1148 * ice_aq_nvm_update_empr
1149 * @hw: pointer to the HW struct
1150 *
1151 * Update empr (0x0709). This command allows SW to
1152 * request an EMPR to activate new FW.
1153 */
1154int ice_aq_nvm_update_empr(struct ice_hw *hw)
1155{
1156 struct ice_aq_desc desc;
1157
1158 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_update_empr);
1159
1160 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1161}
1162
1163/* ice_nvm_set_pkg_data
1164 * @hw: pointer to the HW struct
1165 * @del_pkg_data_flag: If is set then the current pkg_data store by FW
1166 * is deleted.
1167 * If bit is set to 1, then buffer should be size 0.
1168 * @data: pointer to buffer
1169 * @length: length of the buffer
1170 * @cd: pointer to command details structure or NULL
1171 *
1172 * Set package data (0x070A). This command is equivalent to the reception
1173 * of a PLDM FW Update GetPackageData cmd. This command should be sent
1174 * as part of the NVM update as the first cmd in the flow.
1175 */
1176
1177int
1178ice_nvm_set_pkg_data(struct ice_hw *hw, bool del_pkg_data_flag, u8 *data,
1179 u16 length, struct ice_sq_cd *cd)
1180{
1181 struct ice_aqc_nvm_pkg_data *cmd;
1182 struct ice_aq_desc desc;
1183
1184 if (length != 0 && !data)
1185 return -EINVAL;
1186
1187 cmd = &desc.params.pkg_data;
1188
1189 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_pkg_data);
1190 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1191
1192 if (del_pkg_data_flag)
1193 cmd->cmd_flags |= ICE_AQC_NVM_PKG_DELETE;
1194
1195 return ice_aq_send_cmd(hw, &desc, data, length, cd);
1196}
1197
1198/* ice_nvm_pass_component_tbl
1199 * @hw: pointer to the HW struct
1200 * @data: pointer to buffer
1201 * @length: length of the buffer
1202 * @transfer_flag: parameter for determining stage of the update
1203 * @comp_response: a pointer to the response from the 0x070B AQC.
1204 * @comp_response_code: a pointer to the response code from the 0x070B AQC.
1205 * @cd: pointer to command details structure or NULL
1206 *
1207 * Pass component table (0x070B). This command is equivalent to the reception
1208 * of a PLDM FW Update PassComponentTable cmd. This command should be sent once
1209 * per component. It can be only sent after Set Package Data cmd and before
1210 * actual update. FW will assume these commands are going to be sent until
1211 * the TransferFlag is set to End or StartAndEnd.
1212 */
1213
1214int
1215ice_nvm_pass_component_tbl(struct ice_hw *hw, u8 *data, u16 length,
1216 u8 transfer_flag, u8 *comp_response,
1217 u8 *comp_response_code, struct ice_sq_cd *cd)
1218{
1219 struct ice_aqc_nvm_pass_comp_tbl *cmd;
1220 struct ice_aq_desc desc;
1221 int status;
1222
1223 if (!data || !comp_response || !comp_response_code)
1224 return -EINVAL;
1225
1226 cmd = &desc.params.pass_comp_tbl;
1227
1228 ice_fill_dflt_direct_cmd_desc(&desc,
1229 ice_aqc_opc_nvm_pass_component_tbl);
1230 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1231
1232 cmd->transfer_flag = transfer_flag;
1233 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
1234
1235 if (!status) {
1236 *comp_response = cmd->component_response;
1237 *comp_response_code = cmd->component_response_code;
1238 }
1239 return status;
1240}