1/* SPDX-License-Identifier: MIT */
 2/*
 3 * Copyright(c) 2023, Intel Corporation. All rights reserved.
 4 */
 5#ifndef __XE_HECI_GSC_DEV_H__
 6#define __XE_HECI_GSC_DEV_H__
 7
 8#include <linux/types.h>
 9
10struct xe_device;
11struct mei_aux_device;
12
13/*
14 * GSC HECI1 bit corresponds to bit15 and HECI2 to bit14.
15 * The reason for this is to allow growth for more interfaces in the future.
16 */
17#define GSC_IRQ_INTF(_x) BIT(15 - (_x))
18
19/*
20 * CSC HECI1 bit corresponds to bit9 and HECI2 to bit10.
21 */
22#define CSC_IRQ_INTF(_x) BIT(9 + (_x))
23
24/**
25 * struct xe_heci_gsc - graphics security controller for xe, HECI interface
26 *
27 * @adev : pointer to mei auxiliary device structure
28 * @irq : irq number
29 *
30 */
31struct xe_heci_gsc {
32	struct mei_aux_device *adev;
33	int irq;
34};
35
36void xe_heci_gsc_init(struct xe_device *xe);
37void xe_heci_gsc_fini(struct xe_device *xe);
38void xe_heci_gsc_irq_handler(struct xe_device *xe, u32 iir);
39void xe_heci_csc_irq_handler(struct xe_device *xe, u32 iir);
40
41#endif /* __XE_HECI_GSC_DEV_H__ */

 1/* SPDX-License-Identifier: MIT */
 2/*
 3 * Copyright(c) 2023, Intel Corporation. All rights reserved.
 4 */
 5#ifndef __XE_HECI_GSC_DEV_H__
 6#define __XE_HECI_GSC_DEV_H__
 7
 8#include <linux/types.h>
 9
10struct xe_device;
11struct mei_aux_device;
12
13/*
14 * The HECI1 bit corresponds to bit15 and HECI2 to bit14.
15 * The reason for this is to allow growth for more interfaces in the future.
16 */
17#define GSC_IRQ_INTF(_x)  BIT(15 - (_x))
 
 
 
 
 
18
19/**
20 * struct xe_heci_gsc - graphics security controller for xe, HECI interface
21 *
22 * @adev : pointer to mei auxiliary device structure
23 * @irq : irq number
24 *
25 */
26struct xe_heci_gsc {
27	struct mei_aux_device *adev;
28	int irq;
29};
30
31void xe_heci_gsc_init(struct xe_device *xe);
32void xe_heci_gsc_fini(struct xe_device *xe);
33void xe_heci_gsc_irq_handler(struct xe_device *xe, u32 iir);
 
34
35#endif /* __XE_HECI_GSC_DEV_H__ */