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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2022 Intel Corporation
4 */
5
6#include "xe_guc_hwconfig.h"
7
8#include <drm/drm_managed.h>
9#include <drm/drm_print.h>
10
11#include "abi/guc_actions_abi.h"
12#include "xe_bo.h"
13#include "xe_device.h"
14#include "xe_gt.h"
15#include "xe_guc.h"
16#include "xe_map.h"
17
18static int send_get_hwconfig(struct xe_guc *guc, u64 ggtt_addr, u32 size)
19{
20 u32 action[] = {
21 XE_GUC_ACTION_GET_HWCONFIG,
22 lower_32_bits(ggtt_addr),
23 upper_32_bits(ggtt_addr),
24 size,
25 };
26
27 return xe_guc_mmio_send(guc, action, ARRAY_SIZE(action));
28}
29
30static int guc_hwconfig_size(struct xe_guc *guc, u32 *size)
31{
32 int ret = send_get_hwconfig(guc, 0, 0);
33
34 if (ret < 0)
35 return ret;
36
37 *size = ret;
38 return 0;
39}
40
41static int guc_hwconfig_copy(struct xe_guc *guc)
42{
43 int ret = send_get_hwconfig(guc, xe_bo_ggtt_addr(guc->hwconfig.bo),
44 guc->hwconfig.size);
45
46 if (ret < 0)
47 return ret;
48
49 return 0;
50}
51
52int xe_guc_hwconfig_init(struct xe_guc *guc)
53{
54 struct xe_device *xe = guc_to_xe(guc);
55 struct xe_gt *gt = guc_to_gt(guc);
56 struct xe_tile *tile = gt_to_tile(gt);
57 struct xe_bo *bo;
58 u32 size;
59 int err;
60
61 /* Initialization already done */
62 if (guc->hwconfig.bo)
63 return 0;
64
65 /*
66 * All hwconfig the same across GTs so only GT0 needs to be configured
67 */
68 if (gt->info.id != XE_GT0)
69 return 0;
70
71 /* ADL_P, DG2+ supports hwconfig table */
72 if (GRAPHICS_VERx100(xe) < 1255 && xe->info.platform != XE_ALDERLAKE_P)
73 return 0;
74
75 err = guc_hwconfig_size(guc, &size);
76 if (err)
77 return err;
78 if (!size)
79 return -EINVAL;
80
81 bo = xe_managed_bo_create_pin_map(xe, tile, PAGE_ALIGN(size),
82 XE_BO_FLAG_SYSTEM |
83 XE_BO_FLAG_GGTT |
84 XE_BO_FLAG_GGTT_INVALIDATE);
85 if (IS_ERR(bo))
86 return PTR_ERR(bo);
87 guc->hwconfig.bo = bo;
88 guc->hwconfig.size = size;
89
90 return guc_hwconfig_copy(guc);
91}
92
93u32 xe_guc_hwconfig_size(struct xe_guc *guc)
94{
95 return !guc->hwconfig.bo ? 0 : guc->hwconfig.size;
96}
97
98void xe_guc_hwconfig_copy(struct xe_guc *guc, void *dst)
99{
100 struct xe_device *xe = guc_to_xe(guc);
101
102 XE_WARN_ON(!guc->hwconfig.bo);
103
104 xe_map_memcpy_from(xe, dst, &guc->hwconfig.bo->vmap, 0,
105 guc->hwconfig.size);
106}
107
108void xe_guc_hwconfig_dump(struct xe_guc *guc, struct drm_printer *p)
109{
110 size_t size = xe_guc_hwconfig_size(guc);
111 u32 *hwconfig;
112 u64 num_dw;
113 u32 extra_bytes;
114 int i = 0;
115
116 if (size == 0) {
117 drm_printf(p, "No hwconfig available\n");
118 return;
119 }
120
121 num_dw = div_u64_rem(size, sizeof(u32), &extra_bytes);
122
123 hwconfig = kzalloc(size, GFP_KERNEL);
124 if (!hwconfig) {
125 drm_printf(p, "Error: could not allocate hwconfig memory\n");
126 return;
127 }
128
129 xe_guc_hwconfig_copy(guc, hwconfig);
130
131 /* An entry requires at least three dwords for key, length, value */
132 while (i + 3 <= num_dw) {
133 u32 attribute = hwconfig[i++];
134 u32 len_dw = hwconfig[i++];
135
136 if (i + len_dw > num_dw) {
137 drm_printf(p, "Error: Attribute %u is %u dwords, but only %llu remain\n",
138 attribute, len_dw, num_dw - i);
139 len_dw = num_dw - i;
140 }
141
142 /*
143 * If it's a single dword (as most hwconfig attributes are),
144 * then it's probably a number that makes sense to display
145 * in decimal form. In the rare cases where it's more than
146 * one dword, just print it in hex form and let the user
147 * figure out how to interpret it.
148 */
149 if (len_dw == 1)
150 drm_printf(p, "[%2u] = %u\n", attribute, hwconfig[i]);
151 else
152 drm_printf(p, "[%2u] = { %*ph }\n", attribute,
153 (int)(len_dw * sizeof(u32)), &hwconfig[i]);
154 i += len_dw;
155 }
156
157 if (i < num_dw || extra_bytes)
158 drm_printf(p, "Error: %llu extra bytes at end of hwconfig\n",
159 (num_dw - i) * sizeof(u32) + extra_bytes);
160
161 kfree(hwconfig);
162}
163
164/*
165 * Lookup a specific 32-bit attribute value in the GuC's hwconfig table.
166 */
167int xe_guc_hwconfig_lookup_u32(struct xe_guc *guc, u32 attribute, u32 *val)
168{
169 size_t size = xe_guc_hwconfig_size(guc);
170 u64 num_dw = div_u64(size, sizeof(u32));
171 u32 *hwconfig;
172 bool found = false;
173 int i = 0;
174
175 if (num_dw == 0)
176 return -EINVAL;
177
178 hwconfig = kzalloc(size, GFP_KERNEL);
179 if (!hwconfig)
180 return -ENOMEM;
181
182 xe_guc_hwconfig_copy(guc, hwconfig);
183
184 /* An entry requires at least three dwords for key, length, value */
185 while (i + 3 <= num_dw) {
186 u32 key = hwconfig[i++];
187 u32 len_dw = hwconfig[i++];
188
189 if (key != attribute) {
190 i += len_dw;
191 continue;
192 }
193
194 *val = hwconfig[i];
195 found = true;
196 break;
197 }
198
199 kfree(hwconfig);
200
201 return found ? 0 : -ENOENT;
202}
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2022 Intel Corporation
4 */
5
6#include "xe_guc_hwconfig.h"
7
8#include <drm/drm_managed.h>
9
10#include "abi/guc_actions_abi.h"
11#include "xe_bo.h"
12#include "xe_device.h"
13#include "xe_gt.h"
14#include "xe_guc.h"
15#include "xe_map.h"
16
17static int send_get_hwconfig(struct xe_guc *guc, u32 ggtt_addr, u32 size)
18{
19 u32 action[] = {
20 XE_GUC_ACTION_GET_HWCONFIG,
21 lower_32_bits(ggtt_addr),
22 upper_32_bits(ggtt_addr),
23 size,
24 };
25
26 return xe_guc_mmio_send(guc, action, ARRAY_SIZE(action));
27}
28
29static int guc_hwconfig_size(struct xe_guc *guc, u32 *size)
30{
31 int ret = send_get_hwconfig(guc, 0, 0);
32
33 if (ret < 0)
34 return ret;
35
36 *size = ret;
37 return 0;
38}
39
40static int guc_hwconfig_copy(struct xe_guc *guc)
41{
42 int ret = send_get_hwconfig(guc, xe_bo_ggtt_addr(guc->hwconfig.bo),
43 guc->hwconfig.size);
44
45 if (ret < 0)
46 return ret;
47
48 return 0;
49}
50
51int xe_guc_hwconfig_init(struct xe_guc *guc)
52{
53 struct xe_device *xe = guc_to_xe(guc);
54 struct xe_gt *gt = guc_to_gt(guc);
55 struct xe_tile *tile = gt_to_tile(gt);
56 struct xe_bo *bo;
57 u32 size;
58 int err;
59
60 /* Initialization already done */
61 if (guc->hwconfig.bo)
62 return 0;
63
64 /*
65 * All hwconfig the same across GTs so only GT0 needs to be configured
66 */
67 if (gt->info.id != XE_GT0)
68 return 0;
69
70 /* ADL_P, DG2+ supports hwconfig table */
71 if (GRAPHICS_VERx100(xe) < 1255 && xe->info.platform != XE_ALDERLAKE_P)
72 return 0;
73
74 err = guc_hwconfig_size(guc, &size);
75 if (err)
76 return err;
77 if (!size)
78 return -EINVAL;
79
80 bo = xe_managed_bo_create_pin_map(xe, tile, PAGE_ALIGN(size),
81 XE_BO_CREATE_SYSTEM_BIT |
82 XE_BO_CREATE_GGTT_BIT);
83 if (IS_ERR(bo))
84 return PTR_ERR(bo);
85 guc->hwconfig.bo = bo;
86 guc->hwconfig.size = size;
87
88 return guc_hwconfig_copy(guc);
89}
90
91u32 xe_guc_hwconfig_size(struct xe_guc *guc)
92{
93 return !guc->hwconfig.bo ? 0 : guc->hwconfig.size;
94}
95
96void xe_guc_hwconfig_copy(struct xe_guc *guc, void *dst)
97{
98 struct xe_device *xe = guc_to_xe(guc);
99
100 XE_WARN_ON(!guc->hwconfig.bo);
101
102 xe_map_memcpy_from(xe, dst, &guc->hwconfig.bo->vmap, 0,
103 guc->hwconfig.size);
104}