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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
4 */
5
6#include <linux/clk.h>
7#include <linux/mfd/syscon.h>
8#include <linux/module.h>
9#include <linux/platform_device.h>
10#include <linux/phy/phy.h>
11#include <linux/regmap.h>
12#include <linux/regulator/consumer.h>
13
14#include <drm/bridge/dw_hdmi.h>
15#include <drm/drm_edid.h>
16#include <drm/drm_of.h>
17#include <drm/drm_probe_helper.h>
18#include <drm/drm_simple_kms_helper.h>
19
20#include "rockchip_drm_drv.h"
21
22#define RK3228_GRF_SOC_CON2 0x0408
23#define RK3228_HDMI_SDAIN_MSK BIT(14)
24#define RK3228_HDMI_SCLIN_MSK BIT(13)
25#define RK3228_GRF_SOC_CON6 0x0418
26#define RK3228_HDMI_HPD_VSEL BIT(6)
27#define RK3228_HDMI_SDA_VSEL BIT(5)
28#define RK3228_HDMI_SCL_VSEL BIT(4)
29
30#define RK3288_GRF_SOC_CON6 0x025C
31#define RK3288_HDMI_LCDC_SEL BIT(4)
32#define RK3328_GRF_SOC_CON2 0x0408
33
34#define RK3328_HDMI_SDAIN_MSK BIT(11)
35#define RK3328_HDMI_SCLIN_MSK BIT(10)
36#define RK3328_HDMI_HPD_IOE BIT(2)
37#define RK3328_GRF_SOC_CON3 0x040c
38/* need to be unset if hdmi or i2c should control voltage */
39#define RK3328_HDMI_SDA5V_GRF BIT(15)
40#define RK3328_HDMI_SCL5V_GRF BIT(14)
41#define RK3328_HDMI_HPD5V_GRF BIT(13)
42#define RK3328_HDMI_CEC5V_GRF BIT(12)
43#define RK3328_GRF_SOC_CON4 0x0410
44#define RK3328_HDMI_HPD_SARADC BIT(13)
45#define RK3328_HDMI_CEC_5V BIT(11)
46#define RK3328_HDMI_SDA_5V BIT(10)
47#define RK3328_HDMI_SCL_5V BIT(9)
48#define RK3328_HDMI_HPD_5V BIT(8)
49
50#define RK3399_GRF_SOC_CON20 0x6250
51#define RK3399_HDMI_LCDC_SEL BIT(6)
52
53#define RK3568_GRF_VO_CON1 0x0364
54#define RK3568_HDMI_SDAIN_MSK BIT(15)
55#define RK3568_HDMI_SCLIN_MSK BIT(14)
56
57#define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
58
59/**
60 * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips
61 * @lcdsel_grf_reg: grf register offset of lcdc select
62 * @lcdsel_big: reg value of selecting vop big for HDMI
63 * @lcdsel_lit: reg value of selecting vop little for HDMI
64 * @max_tmds_clock: maximum TMDS clock rate supported
65 */
66struct rockchip_hdmi_chip_data {
67 int lcdsel_grf_reg;
68 u32 lcdsel_big;
69 u32 lcdsel_lit;
70 int max_tmds_clock;
71};
72
73struct rockchip_hdmi {
74 struct device *dev;
75 struct regmap *regmap;
76 struct rockchip_encoder encoder;
77 const struct rockchip_hdmi_chip_data *chip_data;
78 const struct dw_hdmi_plat_data *plat_data;
79 struct clk *hdmiphy_clk;
80 struct clk *ref_clk;
81 struct clk *grf_clk;
82 struct dw_hdmi *hdmi;
83 struct phy *phy;
84};
85
86static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder)
87{
88 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
89
90 return container_of(rkencoder, struct rockchip_hdmi, encoder);
91}
92
93static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
94 {
95 30666000, {
96 { 0x00b3, 0x0000 },
97 { 0x2153, 0x0000 },
98 { 0x40f3, 0x0000 },
99 },
100 }, {
101 36800000, {
102 { 0x00b3, 0x0000 },
103 { 0x2153, 0x0000 },
104 { 0x40a2, 0x0001 },
105 },
106 }, {
107 46000000, {
108 { 0x00b3, 0x0000 },
109 { 0x2142, 0x0001 },
110 { 0x40a2, 0x0001 },
111 },
112 }, {
113 61333000, {
114 { 0x0072, 0x0001 },
115 { 0x2142, 0x0001 },
116 { 0x40a2, 0x0001 },
117 },
118 }, {
119 73600000, {
120 { 0x0072, 0x0001 },
121 { 0x2142, 0x0001 },
122 { 0x4061, 0x0002 },
123 },
124 }, {
125 92000000, {
126 { 0x0072, 0x0001 },
127 { 0x2145, 0x0002 },
128 { 0x4061, 0x0002 },
129 },
130 }, {
131 122666000, {
132 { 0x0051, 0x0002 },
133 { 0x2145, 0x0002 },
134 { 0x4061, 0x0002 },
135 },
136 }, {
137 147200000, {
138 { 0x0051, 0x0002 },
139 { 0x2145, 0x0002 },
140 { 0x4064, 0x0003 },
141 },
142 }, {
143 184000000, {
144 { 0x0051, 0x0002 },
145 { 0x214c, 0x0003 },
146 { 0x4064, 0x0003 },
147 },
148 }, {
149 226666000, {
150 { 0x0040, 0x0003 },
151 { 0x214c, 0x0003 },
152 { 0x4064, 0x0003 },
153 },
154 }, {
155 272000000, {
156 { 0x0040, 0x0003 },
157 { 0x214c, 0x0003 },
158 { 0x5a64, 0x0003 },
159 },
160 }, {
161 340000000, {
162 { 0x0040, 0x0003 },
163 { 0x3b4c, 0x0003 },
164 { 0x5a64, 0x0003 },
165 },
166 }, {
167 600000000, {
168 { 0x1a40, 0x0003 },
169 { 0x3b4c, 0x0003 },
170 { 0x5a64, 0x0003 },
171 },
172 }, {
173 ~0UL, {
174 { 0x0000, 0x0000 },
175 { 0x0000, 0x0000 },
176 { 0x0000, 0x0000 },
177 },
178 }
179};
180
181static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
182 /* pixelclk bpp8 bpp10 bpp12 */
183 {
184 600000000, { 0x0000, 0x0000, 0x0000 },
185 }, {
186 ~0UL, { 0x0000, 0x0000, 0x0000 },
187 }
188};
189
190static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
191 /*pixelclk symbol term vlev*/
192 { 74250000, 0x8009, 0x0004, 0x0272},
193 { 165000000, 0x802b, 0x0004, 0x0209},
194 { 297000000, 0x8039, 0x0005, 0x028d},
195 { 594000000, 0x8039, 0x0000, 0x019d},
196 { ~0UL, 0x0000, 0x0000, 0x0000}
197};
198
199static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
200{
201 struct device_node *np = hdmi->dev->of_node;
202 int ret;
203
204 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
205 if (IS_ERR(hdmi->regmap)) {
206 drm_err(hdmi, "Unable to get rockchip,grf\n");
207 return PTR_ERR(hdmi->regmap);
208 }
209
210 hdmi->ref_clk = devm_clk_get_optional_enabled(hdmi->dev, "ref");
211 if (!hdmi->ref_clk)
212 hdmi->ref_clk = devm_clk_get_optional_enabled(hdmi->dev, "vpll");
213
214 if (IS_ERR(hdmi->ref_clk)) {
215 ret = PTR_ERR(hdmi->ref_clk);
216 if (ret != -EPROBE_DEFER)
217 drm_err(hdmi, "failed to get reference clock\n");
218 return ret;
219 }
220
221 hdmi->grf_clk = devm_clk_get_optional(hdmi->dev, "grf");
222 if (IS_ERR(hdmi->grf_clk)) {
223 ret = PTR_ERR(hdmi->grf_clk);
224 if (ret != -EPROBE_DEFER)
225 drm_err(hdmi, "failed to get grf clock\n");
226 return ret;
227 }
228
229 ret = devm_regulator_get_enable(hdmi->dev, "avdd-0v9");
230 if (ret)
231 return ret;
232
233 ret = devm_regulator_get_enable(hdmi->dev, "avdd-1v8");
234
235 return ret;
236}
237
238static enum drm_mode_status
239dw_hdmi_rockchip_mode_valid(struct dw_hdmi *dw_hdmi, void *data,
240 const struct drm_display_info *info,
241 const struct drm_display_mode *mode)
242{
243 struct rockchip_hdmi *hdmi = data;
244 int pclk = mode->clock * 1000;
245
246 if (hdmi->chip_data->max_tmds_clock &&
247 mode->clock > hdmi->chip_data->max_tmds_clock)
248 return MODE_CLOCK_HIGH;
249
250 if (hdmi->ref_clk) {
251 int rpclk = clk_round_rate(hdmi->ref_clk, pclk);
252
253 if (rpclk < 0 || abs(rpclk - pclk) > pclk / 1000)
254 return MODE_NOCLOCK;
255 }
256
257 if (hdmi->hdmiphy_clk) {
258 int rpclk = clk_round_rate(hdmi->hdmiphy_clk, pclk);
259
260 if (rpclk < 0 || abs(rpclk - pclk) > pclk / 1000)
261 return MODE_NOCLOCK;
262 }
263
264 return MODE_OK;
265}
266
267static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
268{
269}
270
271static bool
272dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
273 const struct drm_display_mode *mode,
274 struct drm_display_mode *adj_mode)
275{
276 return true;
277}
278
279static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
280 struct drm_display_mode *mode,
281 struct drm_display_mode *adj_mode)
282{
283 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
284
285 clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000);
286}
287
288static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
289{
290 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
291 u32 val;
292 int ret;
293
294 if (hdmi->chip_data->lcdsel_grf_reg < 0)
295 return;
296
297 ret = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
298 if (ret)
299 val = hdmi->chip_data->lcdsel_lit;
300 else
301 val = hdmi->chip_data->lcdsel_big;
302
303 ret = clk_prepare_enable(hdmi->grf_clk);
304 if (ret < 0) {
305 drm_err(hdmi, "failed to enable grfclk %d\n", ret);
306 return;
307 }
308
309 ret = regmap_write(hdmi->regmap, hdmi->chip_data->lcdsel_grf_reg, val);
310 if (ret != 0)
311 drm_err(hdmi, "Could not write to GRF: %d\n", ret);
312
313 clk_disable_unprepare(hdmi->grf_clk);
314 drm_dbg(hdmi, "vop %s output to hdmi\n", ret ? "LIT" : "BIG");
315}
316
317static int
318dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
319 struct drm_crtc_state *crtc_state,
320 struct drm_connector_state *conn_state)
321{
322 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
323
324 s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
325 s->output_type = DRM_MODE_CONNECTOR_HDMIA;
326
327 return 0;
328}
329
330static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
331 .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
332 .mode_set = dw_hdmi_rockchip_encoder_mode_set,
333 .enable = dw_hdmi_rockchip_encoder_enable,
334 .disable = dw_hdmi_rockchip_encoder_disable,
335 .atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
336};
337
338static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data,
339 const struct drm_display_info *display,
340 const struct drm_display_mode *mode)
341{
342 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
343
344 dw_hdmi_set_high_tmds_clock_ratio(dw_hdmi, display);
345
346 return phy_power_on(hdmi->phy);
347}
348
349static void dw_hdmi_rockchip_genphy_disable(struct dw_hdmi *dw_hdmi, void *data)
350{
351 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
352
353 phy_power_off(hdmi->phy);
354}
355
356static void dw_hdmi_rk3228_setup_hpd(struct dw_hdmi *dw_hdmi, void *data)
357{
358 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
359
360 dw_hdmi_phy_setup_hpd(dw_hdmi, data);
361
362 regmap_write(hdmi->regmap,
363 RK3228_GRF_SOC_CON6,
364 HIWORD_UPDATE(RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL |
365 RK3228_HDMI_SCL_VSEL,
366 RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL |
367 RK3228_HDMI_SCL_VSEL));
368
369 regmap_write(hdmi->regmap,
370 RK3228_GRF_SOC_CON2,
371 HIWORD_UPDATE(RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK,
372 RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK));
373}
374
375static enum drm_connector_status
376dw_hdmi_rk3328_read_hpd(struct dw_hdmi *dw_hdmi, void *data)
377{
378 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
379 enum drm_connector_status status;
380
381 status = dw_hdmi_phy_read_hpd(dw_hdmi, data);
382
383 if (status == connector_status_connected)
384 regmap_write(hdmi->regmap,
385 RK3328_GRF_SOC_CON4,
386 HIWORD_UPDATE(RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V,
387 RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V));
388 else
389 regmap_write(hdmi->regmap,
390 RK3328_GRF_SOC_CON4,
391 HIWORD_UPDATE(0, RK3328_HDMI_SDA_5V |
392 RK3328_HDMI_SCL_5V));
393 return status;
394}
395
396static void dw_hdmi_rk3328_setup_hpd(struct dw_hdmi *dw_hdmi, void *data)
397{
398 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
399
400 dw_hdmi_phy_setup_hpd(dw_hdmi, data);
401
402 /* Enable and map pins to 3V grf-controlled io-voltage */
403 regmap_write(hdmi->regmap,
404 RK3328_GRF_SOC_CON4,
405 HIWORD_UPDATE(0, RK3328_HDMI_HPD_SARADC | RK3328_HDMI_CEC_5V |
406 RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V |
407 RK3328_HDMI_HPD_5V));
408 regmap_write(hdmi->regmap,
409 RK3328_GRF_SOC_CON3,
410 HIWORD_UPDATE(0, RK3328_HDMI_SDA5V_GRF | RK3328_HDMI_SCL5V_GRF |
411 RK3328_HDMI_HPD5V_GRF |
412 RK3328_HDMI_CEC5V_GRF));
413 regmap_write(hdmi->regmap,
414 RK3328_GRF_SOC_CON2,
415 HIWORD_UPDATE(RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK,
416 RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK |
417 RK3328_HDMI_HPD_IOE));
418
419 dw_hdmi_rk3328_read_hpd(dw_hdmi, data);
420}
421
422static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops = {
423 .init = dw_hdmi_rockchip_genphy_init,
424 .disable = dw_hdmi_rockchip_genphy_disable,
425 .read_hpd = dw_hdmi_phy_read_hpd,
426 .update_hpd = dw_hdmi_phy_update_hpd,
427 .setup_hpd = dw_hdmi_rk3228_setup_hpd,
428};
429
430static struct rockchip_hdmi_chip_data rk3228_chip_data = {
431 .lcdsel_grf_reg = -1,
432 .max_tmds_clock = 594000,
433};
434
435static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
436 .mode_valid = dw_hdmi_rockchip_mode_valid,
437 .phy_data = &rk3228_chip_data,
438 .phy_ops = &rk3228_hdmi_phy_ops,
439 .phy_name = "inno_dw_hdmi_phy2",
440 .phy_force_vendor = true,
441};
442
443static struct rockchip_hdmi_chip_data rk3288_chip_data = {
444 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
445 .lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL),
446 .lcdsel_lit = HIWORD_UPDATE(RK3288_HDMI_LCDC_SEL, RK3288_HDMI_LCDC_SEL),
447 .max_tmds_clock = 340000,
448};
449
450static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
451 .mode_valid = dw_hdmi_rockchip_mode_valid,
452 .mpll_cfg = rockchip_mpll_cfg,
453 .cur_ctr = rockchip_cur_ctr,
454 .phy_config = rockchip_phy_config,
455 .phy_data = &rk3288_chip_data,
456};
457
458static const struct dw_hdmi_phy_ops rk3328_hdmi_phy_ops = {
459 .init = dw_hdmi_rockchip_genphy_init,
460 .disable = dw_hdmi_rockchip_genphy_disable,
461 .read_hpd = dw_hdmi_rk3328_read_hpd,
462 .update_hpd = dw_hdmi_phy_update_hpd,
463 .setup_hpd = dw_hdmi_rk3328_setup_hpd,
464};
465
466static struct rockchip_hdmi_chip_data rk3328_chip_data = {
467 .lcdsel_grf_reg = -1,
468 .max_tmds_clock = 594000,
469};
470
471static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
472 .mode_valid = dw_hdmi_rockchip_mode_valid,
473 .phy_data = &rk3328_chip_data,
474 .phy_ops = &rk3328_hdmi_phy_ops,
475 .phy_name = "inno_dw_hdmi_phy2",
476 .phy_force_vendor = true,
477 .use_drm_infoframe = true,
478};
479
480static struct rockchip_hdmi_chip_data rk3399_chip_data = {
481 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
482 .lcdsel_big = HIWORD_UPDATE(0, RK3399_HDMI_LCDC_SEL),
483 .lcdsel_lit = HIWORD_UPDATE(RK3399_HDMI_LCDC_SEL, RK3399_HDMI_LCDC_SEL),
484 .max_tmds_clock = 594000,
485};
486
487static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
488 .mode_valid = dw_hdmi_rockchip_mode_valid,
489 .mpll_cfg = rockchip_mpll_cfg,
490 .cur_ctr = rockchip_cur_ctr,
491 .phy_config = rockchip_phy_config,
492 .phy_data = &rk3399_chip_data,
493 .use_drm_infoframe = true,
494};
495
496static struct rockchip_hdmi_chip_data rk3568_chip_data = {
497 .lcdsel_grf_reg = -1,
498 .max_tmds_clock = 594000,
499};
500
501static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = {
502 .mode_valid = dw_hdmi_rockchip_mode_valid,
503 .mpll_cfg = rockchip_mpll_cfg,
504 .cur_ctr = rockchip_cur_ctr,
505 .phy_config = rockchip_phy_config,
506 .phy_data = &rk3568_chip_data,
507 .use_drm_infoframe = true,
508};
509
510static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
511 { .compatible = "rockchip,rk3228-dw-hdmi",
512 .data = &rk3228_hdmi_drv_data
513 },
514 { .compatible = "rockchip,rk3288-dw-hdmi",
515 .data = &rk3288_hdmi_drv_data
516 },
517 { .compatible = "rockchip,rk3328-dw-hdmi",
518 .data = &rk3328_hdmi_drv_data
519 },
520 { .compatible = "rockchip,rk3399-dw-hdmi",
521 .data = &rk3399_hdmi_drv_data
522 },
523 { .compatible = "rockchip,rk3568-dw-hdmi",
524 .data = &rk3568_hdmi_drv_data
525 },
526 {},
527};
528MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
529
530static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
531 void *data)
532{
533 struct platform_device *pdev = to_platform_device(dev);
534 struct dw_hdmi_plat_data *plat_data;
535 const struct of_device_id *match;
536 struct drm_device *drm = data;
537 struct drm_encoder *encoder;
538 struct rockchip_hdmi *hdmi;
539 int ret;
540
541 if (!pdev->dev.of_node)
542 return -ENODEV;
543
544 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
545 if (!hdmi)
546 return -ENOMEM;
547
548 match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
549 plat_data = devm_kmemdup(&pdev->dev, match->data,
550 sizeof(*plat_data), GFP_KERNEL);
551 if (!plat_data)
552 return -ENOMEM;
553
554 hdmi->dev = &pdev->dev;
555 hdmi->plat_data = plat_data;
556 hdmi->chip_data = plat_data->phy_data;
557 plat_data->phy_data = hdmi;
558 plat_data->priv_data = hdmi;
559 encoder = &hdmi->encoder.encoder;
560
561 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
562 rockchip_drm_encoder_set_crtc_endpoint_id(&hdmi->encoder,
563 dev->of_node, 0, 0);
564
565 /*
566 * If we failed to find the CRTC(s) which this encoder is
567 * supposed to be connected to, it's because the CRTC has
568 * not been registered yet. Defer probing, and hope that
569 * the required CRTC is added later.
570 */
571 if (encoder->possible_crtcs == 0)
572 return -EPROBE_DEFER;
573
574 ret = rockchip_hdmi_parse_dt(hdmi);
575 if (ret) {
576 if (ret != -EPROBE_DEFER)
577 drm_err(hdmi, "Unable to parse OF data\n");
578 return ret;
579 }
580
581 hdmi->phy = devm_phy_optional_get(dev, "hdmi");
582 if (IS_ERR(hdmi->phy)) {
583 ret = PTR_ERR(hdmi->phy);
584 if (ret != -EPROBE_DEFER)
585 drm_err(hdmi, "failed to get phy\n");
586 return ret;
587 }
588
589 if (hdmi->phy) {
590 struct of_phandle_args clkspec;
591
592 clkspec.np = hdmi->phy->dev.of_node;
593 hdmi->hdmiphy_clk = of_clk_get_from_provider(&clkspec);
594 if (IS_ERR(hdmi->hdmiphy_clk))
595 hdmi->hdmiphy_clk = NULL;
596 }
597
598 if (hdmi->chip_data == &rk3568_chip_data) {
599 regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1,
600 HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK |
601 RK3568_HDMI_SCLIN_MSK,
602 RK3568_HDMI_SDAIN_MSK |
603 RK3568_HDMI_SCLIN_MSK));
604 }
605
606 drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
607 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
608
609 platform_set_drvdata(pdev, hdmi);
610
611 hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data);
612
613 /*
614 * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
615 * which would have called the encoder cleanup. Do it manually.
616 */
617 if (IS_ERR(hdmi->hdmi)) {
618 ret = PTR_ERR(hdmi->hdmi);
619 goto err_bind;
620 }
621
622 return 0;
623
624err_bind:
625 drm_encoder_cleanup(encoder);
626
627 return ret;
628}
629
630static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
631 void *data)
632{
633 struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
634
635 dw_hdmi_unbind(hdmi->hdmi);
636 drm_encoder_cleanup(&hdmi->encoder.encoder);
637}
638
639static const struct component_ops dw_hdmi_rockchip_ops = {
640 .bind = dw_hdmi_rockchip_bind,
641 .unbind = dw_hdmi_rockchip_unbind,
642};
643
644static int dw_hdmi_rockchip_probe(struct platform_device *pdev)
645{
646 return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
647}
648
649static void dw_hdmi_rockchip_remove(struct platform_device *pdev)
650{
651 component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
652}
653
654static int __maybe_unused dw_hdmi_rockchip_resume(struct device *dev)
655{
656 struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
657
658 dw_hdmi_resume(hdmi->hdmi);
659
660 return 0;
661}
662
663static const struct dev_pm_ops dw_hdmi_rockchip_pm = {
664 SET_SYSTEM_SLEEP_PM_OPS(NULL, dw_hdmi_rockchip_resume)
665};
666
667struct platform_driver dw_hdmi_rockchip_pltfm_driver = {
668 .probe = dw_hdmi_rockchip_probe,
669 .remove = dw_hdmi_rockchip_remove,
670 .driver = {
671 .name = "dwhdmi-rockchip",
672 .pm = &dw_hdmi_rockchip_pm,
673 .of_match_table = dw_hdmi_rockchip_dt_ids,
674 },
675};
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
4 */
5
6#include <linux/clk.h>
7#include <linux/mfd/syscon.h>
8#include <linux/module.h>
9#include <linux/platform_device.h>
10#include <linux/phy/phy.h>
11#include <linux/regmap.h>
12#include <linux/regulator/consumer.h>
13
14#include <drm/bridge/dw_hdmi.h>
15#include <drm/drm_edid.h>
16#include <drm/drm_of.h>
17#include <drm/drm_probe_helper.h>
18#include <drm/drm_simple_kms_helper.h>
19
20#include "rockchip_drm_drv.h"
21
22#define RK3228_GRF_SOC_CON2 0x0408
23#define RK3228_HDMI_SDAIN_MSK BIT(14)
24#define RK3228_HDMI_SCLIN_MSK BIT(13)
25#define RK3228_GRF_SOC_CON6 0x0418
26#define RK3228_HDMI_HPD_VSEL BIT(6)
27#define RK3228_HDMI_SDA_VSEL BIT(5)
28#define RK3228_HDMI_SCL_VSEL BIT(4)
29
30#define RK3288_GRF_SOC_CON6 0x025C
31#define RK3288_HDMI_LCDC_SEL BIT(4)
32#define RK3328_GRF_SOC_CON2 0x0408
33
34#define RK3328_HDMI_SDAIN_MSK BIT(11)
35#define RK3328_HDMI_SCLIN_MSK BIT(10)
36#define RK3328_HDMI_HPD_IOE BIT(2)
37#define RK3328_GRF_SOC_CON3 0x040c
38/* need to be unset if hdmi or i2c should control voltage */
39#define RK3328_HDMI_SDA5V_GRF BIT(15)
40#define RK3328_HDMI_SCL5V_GRF BIT(14)
41#define RK3328_HDMI_HPD5V_GRF BIT(13)
42#define RK3328_HDMI_CEC5V_GRF BIT(12)
43#define RK3328_GRF_SOC_CON4 0x0410
44#define RK3328_HDMI_HPD_SARADC BIT(13)
45#define RK3328_HDMI_CEC_5V BIT(11)
46#define RK3328_HDMI_SDA_5V BIT(10)
47#define RK3328_HDMI_SCL_5V BIT(9)
48#define RK3328_HDMI_HPD_5V BIT(8)
49
50#define RK3399_GRF_SOC_CON20 0x6250
51#define RK3399_HDMI_LCDC_SEL BIT(6)
52
53#define RK3568_GRF_VO_CON1 0x0364
54#define RK3568_HDMI_SDAIN_MSK BIT(15)
55#define RK3568_HDMI_SCLIN_MSK BIT(14)
56
57#define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
58
59/**
60 * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips
61 * @lcdsel_grf_reg: grf register offset of lcdc select
62 * @lcdsel_big: reg value of selecting vop big for HDMI
63 * @lcdsel_lit: reg value of selecting vop little for HDMI
64 */
65struct rockchip_hdmi_chip_data {
66 int lcdsel_grf_reg;
67 u32 lcdsel_big;
68 u32 lcdsel_lit;
69};
70
71struct rockchip_hdmi {
72 struct device *dev;
73 struct regmap *regmap;
74 struct rockchip_encoder encoder;
75 const struct rockchip_hdmi_chip_data *chip_data;
76 const struct dw_hdmi_plat_data *plat_data;
77 struct clk *ref_clk;
78 struct clk *grf_clk;
79 struct dw_hdmi *hdmi;
80 struct regulator *avdd_0v9;
81 struct regulator *avdd_1v8;
82 struct phy *phy;
83};
84
85static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder)
86{
87 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
88
89 return container_of(rkencoder, struct rockchip_hdmi, encoder);
90}
91
92static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
93 {
94 27000000, {
95 { 0x00b3, 0x0000},
96 { 0x2153, 0x0000},
97 { 0x40f3, 0x0000}
98 },
99 }, {
100 36000000, {
101 { 0x00b3, 0x0000},
102 { 0x2153, 0x0000},
103 { 0x40f3, 0x0000}
104 },
105 }, {
106 40000000, {
107 { 0x00b3, 0x0000},
108 { 0x2153, 0x0000},
109 { 0x40f3, 0x0000}
110 },
111 }, {
112 54000000, {
113 { 0x0072, 0x0001},
114 { 0x2142, 0x0001},
115 { 0x40a2, 0x0001},
116 },
117 }, {
118 65000000, {
119 { 0x0072, 0x0001},
120 { 0x2142, 0x0001},
121 { 0x40a2, 0x0001},
122 },
123 }, {
124 66000000, {
125 { 0x013e, 0x0003},
126 { 0x217e, 0x0002},
127 { 0x4061, 0x0002}
128 },
129 }, {
130 74250000, {
131 { 0x0072, 0x0001},
132 { 0x2145, 0x0002},
133 { 0x4061, 0x0002}
134 },
135 }, {
136 83500000, {
137 { 0x0072, 0x0001},
138 },
139 }, {
140 108000000, {
141 { 0x0051, 0x0002},
142 { 0x2145, 0x0002},
143 { 0x4061, 0x0002}
144 },
145 }, {
146 106500000, {
147 { 0x0051, 0x0002},
148 { 0x2145, 0x0002},
149 { 0x4061, 0x0002}
150 },
151 }, {
152 146250000, {
153 { 0x0051, 0x0002},
154 { 0x2145, 0x0002},
155 { 0x4061, 0x0002}
156 },
157 }, {
158 148500000, {
159 { 0x0051, 0x0003},
160 { 0x214c, 0x0003},
161 { 0x4064, 0x0003}
162 },
163 }, {
164 340000000, {
165 { 0x0040, 0x0003 },
166 { 0x3b4c, 0x0003 },
167 { 0x5a64, 0x0003 },
168 },
169 }, {
170 ~0UL, {
171 { 0x00a0, 0x000a },
172 { 0x2001, 0x000f },
173 { 0x4002, 0x000f },
174 },
175 }
176};
177
178static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
179 /* pixelclk bpp8 bpp10 bpp12 */
180 {
181 40000000, { 0x0018, 0x0018, 0x0018 },
182 }, {
183 65000000, { 0x0028, 0x0028, 0x0028 },
184 }, {
185 66000000, { 0x0038, 0x0038, 0x0038 },
186 }, {
187 74250000, { 0x0028, 0x0038, 0x0038 },
188 }, {
189 83500000, { 0x0028, 0x0038, 0x0038 },
190 }, {
191 146250000, { 0x0038, 0x0038, 0x0038 },
192 }, {
193 148500000, { 0x0000, 0x0038, 0x0038 },
194 }, {
195 600000000, { 0x0000, 0x0000, 0x0000 },
196 }, {
197 ~0UL, { 0x0000, 0x0000, 0x0000},
198 }
199};
200
201static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
202 /*pixelclk symbol term vlev*/
203 { 74250000, 0x8009, 0x0004, 0x0272},
204 { 148500000, 0x802b, 0x0004, 0x028d},
205 { 297000000, 0x8039, 0x0005, 0x028d},
206 { ~0UL, 0x0000, 0x0000, 0x0000}
207};
208
209static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
210{
211 struct device_node *np = hdmi->dev->of_node;
212
213 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
214 if (IS_ERR(hdmi->regmap)) {
215 DRM_DEV_ERROR(hdmi->dev, "Unable to get rockchip,grf\n");
216 return PTR_ERR(hdmi->regmap);
217 }
218
219 hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "ref");
220 if (!hdmi->ref_clk)
221 hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "vpll");
222
223 if (PTR_ERR(hdmi->ref_clk) == -EPROBE_DEFER) {
224 return -EPROBE_DEFER;
225 } else if (IS_ERR(hdmi->ref_clk)) {
226 DRM_DEV_ERROR(hdmi->dev, "failed to get reference clock\n");
227 return PTR_ERR(hdmi->ref_clk);
228 }
229
230 hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");
231 if (PTR_ERR(hdmi->grf_clk) == -ENOENT) {
232 hdmi->grf_clk = NULL;
233 } else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) {
234 return -EPROBE_DEFER;
235 } else if (IS_ERR(hdmi->grf_clk)) {
236 DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n");
237 return PTR_ERR(hdmi->grf_clk);
238 }
239
240 hdmi->avdd_0v9 = devm_regulator_get(hdmi->dev, "avdd-0v9");
241 if (IS_ERR(hdmi->avdd_0v9))
242 return PTR_ERR(hdmi->avdd_0v9);
243
244 hdmi->avdd_1v8 = devm_regulator_get(hdmi->dev, "avdd-1v8");
245 if (IS_ERR(hdmi->avdd_1v8))
246 return PTR_ERR(hdmi->avdd_1v8);
247
248 return 0;
249}
250
251static enum drm_mode_status
252dw_hdmi_rockchip_mode_valid(struct dw_hdmi *dw_hdmi, void *data,
253 const struct drm_display_info *info,
254 const struct drm_display_mode *mode)
255{
256 struct rockchip_hdmi *hdmi = data;
257 const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
258 int pclk = mode->clock * 1000;
259 bool exact_match = hdmi->plat_data->phy_force_vendor;
260 int i;
261
262 if (hdmi->ref_clk) {
263 int rpclk = clk_round_rate(hdmi->ref_clk, pclk);
264
265 if (abs(rpclk - pclk) > pclk / 1000)
266 return MODE_NOCLOCK;
267 }
268
269 for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
270 /*
271 * For vendor specific phys force an exact match of the pixelclock
272 * to preserve the original behaviour of the driver.
273 */
274 if (exact_match && pclk == mpll_cfg[i].mpixelclock)
275 return MODE_OK;
276 /*
277 * The Synopsys phy can work with pixelclocks up to the value given
278 * in the corresponding mpll_cfg entry.
279 */
280 if (!exact_match && pclk <= mpll_cfg[i].mpixelclock)
281 return MODE_OK;
282 }
283
284 return MODE_BAD;
285}
286
287static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
288{
289}
290
291static bool
292dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
293 const struct drm_display_mode *mode,
294 struct drm_display_mode *adj_mode)
295{
296 return true;
297}
298
299static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
300 struct drm_display_mode *mode,
301 struct drm_display_mode *adj_mode)
302{
303 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
304
305 clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000);
306}
307
308static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
309{
310 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
311 u32 val;
312 int ret;
313
314 if (hdmi->chip_data->lcdsel_grf_reg < 0)
315 return;
316
317 ret = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
318 if (ret)
319 val = hdmi->chip_data->lcdsel_lit;
320 else
321 val = hdmi->chip_data->lcdsel_big;
322
323 ret = clk_prepare_enable(hdmi->grf_clk);
324 if (ret < 0) {
325 DRM_DEV_ERROR(hdmi->dev, "failed to enable grfclk %d\n", ret);
326 return;
327 }
328
329 ret = regmap_write(hdmi->regmap, hdmi->chip_data->lcdsel_grf_reg, val);
330 if (ret != 0)
331 DRM_DEV_ERROR(hdmi->dev, "Could not write to GRF: %d\n", ret);
332
333 clk_disable_unprepare(hdmi->grf_clk);
334 DRM_DEV_DEBUG(hdmi->dev, "vop %s output to hdmi\n",
335 ret ? "LIT" : "BIG");
336}
337
338static int
339dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
340 struct drm_crtc_state *crtc_state,
341 struct drm_connector_state *conn_state)
342{
343 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
344
345 s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
346 s->output_type = DRM_MODE_CONNECTOR_HDMIA;
347
348 return 0;
349}
350
351static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
352 .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
353 .mode_set = dw_hdmi_rockchip_encoder_mode_set,
354 .enable = dw_hdmi_rockchip_encoder_enable,
355 .disable = dw_hdmi_rockchip_encoder_disable,
356 .atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
357};
358
359static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data,
360 const struct drm_display_info *display,
361 const struct drm_display_mode *mode)
362{
363 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
364
365 return phy_power_on(hdmi->phy);
366}
367
368static void dw_hdmi_rockchip_genphy_disable(struct dw_hdmi *dw_hdmi, void *data)
369{
370 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
371
372 phy_power_off(hdmi->phy);
373}
374
375static void dw_hdmi_rk3228_setup_hpd(struct dw_hdmi *dw_hdmi, void *data)
376{
377 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
378
379 dw_hdmi_phy_setup_hpd(dw_hdmi, data);
380
381 regmap_write(hdmi->regmap,
382 RK3228_GRF_SOC_CON6,
383 HIWORD_UPDATE(RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL |
384 RK3228_HDMI_SCL_VSEL,
385 RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL |
386 RK3228_HDMI_SCL_VSEL));
387
388 regmap_write(hdmi->regmap,
389 RK3228_GRF_SOC_CON2,
390 HIWORD_UPDATE(RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK,
391 RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK));
392}
393
394static enum drm_connector_status
395dw_hdmi_rk3328_read_hpd(struct dw_hdmi *dw_hdmi, void *data)
396{
397 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
398 enum drm_connector_status status;
399
400 status = dw_hdmi_phy_read_hpd(dw_hdmi, data);
401
402 if (status == connector_status_connected)
403 regmap_write(hdmi->regmap,
404 RK3328_GRF_SOC_CON4,
405 HIWORD_UPDATE(RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V,
406 RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V));
407 else
408 regmap_write(hdmi->regmap,
409 RK3328_GRF_SOC_CON4,
410 HIWORD_UPDATE(0, RK3328_HDMI_SDA_5V |
411 RK3328_HDMI_SCL_5V));
412 return status;
413}
414
415static void dw_hdmi_rk3328_setup_hpd(struct dw_hdmi *dw_hdmi, void *data)
416{
417 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
418
419 dw_hdmi_phy_setup_hpd(dw_hdmi, data);
420
421 /* Enable and map pins to 3V grf-controlled io-voltage */
422 regmap_write(hdmi->regmap,
423 RK3328_GRF_SOC_CON4,
424 HIWORD_UPDATE(0, RK3328_HDMI_HPD_SARADC | RK3328_HDMI_CEC_5V |
425 RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V |
426 RK3328_HDMI_HPD_5V));
427 regmap_write(hdmi->regmap,
428 RK3328_GRF_SOC_CON3,
429 HIWORD_UPDATE(0, RK3328_HDMI_SDA5V_GRF | RK3328_HDMI_SCL5V_GRF |
430 RK3328_HDMI_HPD5V_GRF |
431 RK3328_HDMI_CEC5V_GRF));
432 regmap_write(hdmi->regmap,
433 RK3328_GRF_SOC_CON2,
434 HIWORD_UPDATE(RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK,
435 RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK |
436 RK3328_HDMI_HPD_IOE));
437}
438
439static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops = {
440 .init = dw_hdmi_rockchip_genphy_init,
441 .disable = dw_hdmi_rockchip_genphy_disable,
442 .read_hpd = dw_hdmi_phy_read_hpd,
443 .update_hpd = dw_hdmi_phy_update_hpd,
444 .setup_hpd = dw_hdmi_rk3228_setup_hpd,
445};
446
447static struct rockchip_hdmi_chip_data rk3228_chip_data = {
448 .lcdsel_grf_reg = -1,
449};
450
451static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
452 .mode_valid = dw_hdmi_rockchip_mode_valid,
453 .mpll_cfg = rockchip_mpll_cfg,
454 .cur_ctr = rockchip_cur_ctr,
455 .phy_config = rockchip_phy_config,
456 .phy_data = &rk3228_chip_data,
457 .phy_ops = &rk3228_hdmi_phy_ops,
458 .phy_name = "inno_dw_hdmi_phy2",
459 .phy_force_vendor = true,
460};
461
462static struct rockchip_hdmi_chip_data rk3288_chip_data = {
463 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
464 .lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL),
465 .lcdsel_lit = HIWORD_UPDATE(RK3288_HDMI_LCDC_SEL, RK3288_HDMI_LCDC_SEL),
466};
467
468static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
469 .mode_valid = dw_hdmi_rockchip_mode_valid,
470 .mpll_cfg = rockchip_mpll_cfg,
471 .cur_ctr = rockchip_cur_ctr,
472 .phy_config = rockchip_phy_config,
473 .phy_data = &rk3288_chip_data,
474};
475
476static const struct dw_hdmi_phy_ops rk3328_hdmi_phy_ops = {
477 .init = dw_hdmi_rockchip_genphy_init,
478 .disable = dw_hdmi_rockchip_genphy_disable,
479 .read_hpd = dw_hdmi_rk3328_read_hpd,
480 .update_hpd = dw_hdmi_phy_update_hpd,
481 .setup_hpd = dw_hdmi_rk3328_setup_hpd,
482};
483
484static struct rockchip_hdmi_chip_data rk3328_chip_data = {
485 .lcdsel_grf_reg = -1,
486};
487
488static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
489 .mode_valid = dw_hdmi_rockchip_mode_valid,
490 .mpll_cfg = rockchip_mpll_cfg,
491 .cur_ctr = rockchip_cur_ctr,
492 .phy_config = rockchip_phy_config,
493 .phy_data = &rk3328_chip_data,
494 .phy_ops = &rk3328_hdmi_phy_ops,
495 .phy_name = "inno_dw_hdmi_phy2",
496 .phy_force_vendor = true,
497 .use_drm_infoframe = true,
498};
499
500static struct rockchip_hdmi_chip_data rk3399_chip_data = {
501 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
502 .lcdsel_big = HIWORD_UPDATE(0, RK3399_HDMI_LCDC_SEL),
503 .lcdsel_lit = HIWORD_UPDATE(RK3399_HDMI_LCDC_SEL, RK3399_HDMI_LCDC_SEL),
504};
505
506static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
507 .mode_valid = dw_hdmi_rockchip_mode_valid,
508 .mpll_cfg = rockchip_mpll_cfg,
509 .cur_ctr = rockchip_cur_ctr,
510 .phy_config = rockchip_phy_config,
511 .phy_data = &rk3399_chip_data,
512 .use_drm_infoframe = true,
513};
514
515static struct rockchip_hdmi_chip_data rk3568_chip_data = {
516 .lcdsel_grf_reg = -1,
517};
518
519static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = {
520 .mode_valid = dw_hdmi_rockchip_mode_valid,
521 .mpll_cfg = rockchip_mpll_cfg,
522 .cur_ctr = rockchip_cur_ctr,
523 .phy_config = rockchip_phy_config,
524 .phy_data = &rk3568_chip_data,
525 .use_drm_infoframe = true,
526};
527
528static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
529 { .compatible = "rockchip,rk3228-dw-hdmi",
530 .data = &rk3228_hdmi_drv_data
531 },
532 { .compatible = "rockchip,rk3288-dw-hdmi",
533 .data = &rk3288_hdmi_drv_data
534 },
535 { .compatible = "rockchip,rk3328-dw-hdmi",
536 .data = &rk3328_hdmi_drv_data
537 },
538 { .compatible = "rockchip,rk3399-dw-hdmi",
539 .data = &rk3399_hdmi_drv_data
540 },
541 { .compatible = "rockchip,rk3568-dw-hdmi",
542 .data = &rk3568_hdmi_drv_data
543 },
544 {},
545};
546MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
547
548static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
549 void *data)
550{
551 struct platform_device *pdev = to_platform_device(dev);
552 struct dw_hdmi_plat_data *plat_data;
553 const struct of_device_id *match;
554 struct drm_device *drm = data;
555 struct drm_encoder *encoder;
556 struct rockchip_hdmi *hdmi;
557 int ret;
558
559 if (!pdev->dev.of_node)
560 return -ENODEV;
561
562 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
563 if (!hdmi)
564 return -ENOMEM;
565
566 match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
567 plat_data = devm_kmemdup(&pdev->dev, match->data,
568 sizeof(*plat_data), GFP_KERNEL);
569 if (!plat_data)
570 return -ENOMEM;
571
572 hdmi->dev = &pdev->dev;
573 hdmi->plat_data = plat_data;
574 hdmi->chip_data = plat_data->phy_data;
575 plat_data->phy_data = hdmi;
576 plat_data->priv_data = hdmi;
577 encoder = &hdmi->encoder.encoder;
578
579 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
580 rockchip_drm_encoder_set_crtc_endpoint_id(&hdmi->encoder,
581 dev->of_node, 0, 0);
582
583 /*
584 * If we failed to find the CRTC(s) which this encoder is
585 * supposed to be connected to, it's because the CRTC has
586 * not been registered yet. Defer probing, and hope that
587 * the required CRTC is added later.
588 */
589 if (encoder->possible_crtcs == 0)
590 return -EPROBE_DEFER;
591
592 ret = rockchip_hdmi_parse_dt(hdmi);
593 if (ret) {
594 if (ret != -EPROBE_DEFER)
595 DRM_DEV_ERROR(hdmi->dev, "Unable to parse OF data\n");
596 return ret;
597 }
598
599 hdmi->phy = devm_phy_optional_get(dev, "hdmi");
600 if (IS_ERR(hdmi->phy)) {
601 ret = PTR_ERR(hdmi->phy);
602 if (ret != -EPROBE_DEFER)
603 DRM_DEV_ERROR(hdmi->dev, "failed to get phy\n");
604 return ret;
605 }
606
607 ret = regulator_enable(hdmi->avdd_0v9);
608 if (ret) {
609 DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd0v9: %d\n", ret);
610 goto err_avdd_0v9;
611 }
612
613 ret = regulator_enable(hdmi->avdd_1v8);
614 if (ret) {
615 DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd1v8: %d\n", ret);
616 goto err_avdd_1v8;
617 }
618
619 ret = clk_prepare_enable(hdmi->ref_clk);
620 if (ret) {
621 DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n",
622 ret);
623 goto err_clk;
624 }
625
626 if (hdmi->chip_data == &rk3568_chip_data) {
627 regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1,
628 HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK |
629 RK3568_HDMI_SCLIN_MSK,
630 RK3568_HDMI_SDAIN_MSK |
631 RK3568_HDMI_SCLIN_MSK));
632 }
633
634 drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
635 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
636
637 platform_set_drvdata(pdev, hdmi);
638
639 hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data);
640
641 /*
642 * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
643 * which would have called the encoder cleanup. Do it manually.
644 */
645 if (IS_ERR(hdmi->hdmi)) {
646 ret = PTR_ERR(hdmi->hdmi);
647 goto err_bind;
648 }
649
650 return 0;
651
652err_bind:
653 drm_encoder_cleanup(encoder);
654 clk_disable_unprepare(hdmi->ref_clk);
655err_clk:
656 regulator_disable(hdmi->avdd_1v8);
657err_avdd_1v8:
658 regulator_disable(hdmi->avdd_0v9);
659err_avdd_0v9:
660 return ret;
661}
662
663static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
664 void *data)
665{
666 struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
667
668 dw_hdmi_unbind(hdmi->hdmi);
669 drm_encoder_cleanup(&hdmi->encoder.encoder);
670 clk_disable_unprepare(hdmi->ref_clk);
671
672 regulator_disable(hdmi->avdd_1v8);
673 regulator_disable(hdmi->avdd_0v9);
674}
675
676static const struct component_ops dw_hdmi_rockchip_ops = {
677 .bind = dw_hdmi_rockchip_bind,
678 .unbind = dw_hdmi_rockchip_unbind,
679};
680
681static int dw_hdmi_rockchip_probe(struct platform_device *pdev)
682{
683 return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
684}
685
686static void dw_hdmi_rockchip_remove(struct platform_device *pdev)
687{
688 component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
689}
690
691static int __maybe_unused dw_hdmi_rockchip_resume(struct device *dev)
692{
693 struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
694
695 dw_hdmi_resume(hdmi->hdmi);
696
697 return 0;
698}
699
700static const struct dev_pm_ops dw_hdmi_rockchip_pm = {
701 SET_SYSTEM_SLEEP_PM_OPS(NULL, dw_hdmi_rockchip_resume)
702};
703
704struct platform_driver dw_hdmi_rockchip_pltfm_driver = {
705 .probe = dw_hdmi_rockchip_probe,
706 .remove_new = dw_hdmi_rockchip_remove,
707 .driver = {
708 .name = "dwhdmi-rockchip",
709 .pm = &dw_hdmi_rockchip_pm,
710 .of_match_table = dw_hdmi_rockchip_dt_ids,
711 },
712};