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1/*
2 * Copyright © 2006-2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/math.h>
25#include <linux/string_helpers.h>
26
27#include "bxt_dpio_phy_regs.h"
28#include "i915_reg.h"
29#include "intel_de.h"
30#include "intel_display_types.h"
31#include "intel_dkl_phy.h"
32#include "intel_dkl_phy_regs.h"
33#include "intel_dpio_phy.h"
34#include "intel_dpll.h"
35#include "intel_dpll_mgr.h"
36#include "intel_hti.h"
37#include "intel_mg_phy_regs.h"
38#include "intel_pch_refclk.h"
39#include "intel_tc.h"
40
41/**
42 * DOC: Display PLLs
43 *
44 * Display PLLs used for driving outputs vary by platform. While some have
45 * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
46 * from a pool. In the latter scenario, it is possible that multiple pipes
47 * share a PLL if their configurations match.
48 *
49 * This file provides an abstraction over display PLLs. The function
50 * intel_shared_dpll_init() initializes the PLLs for the given platform. The
51 * users of a PLL are tracked and that tracking is integrated with the atomic
52 * modset interface. During an atomic operation, required PLLs can be reserved
53 * for a given CRTC and encoder configuration by calling
54 * intel_reserve_shared_dplls() and previously reserved PLLs can be released
55 * with intel_release_shared_dplls().
56 * Changes to the users are first staged in the atomic state, and then made
57 * effective by calling intel_shared_dpll_swap_state() during the atomic
58 * commit phase.
59 */
60
61/* platform specific hooks for managing DPLLs */
62struct intel_shared_dpll_funcs {
63 /*
64 * Hook for enabling the pll, called from intel_enable_shared_dpll() if
65 * the pll is not already enabled.
66 */
67 void (*enable)(struct drm_i915_private *i915,
68 struct intel_shared_dpll *pll,
69 const struct intel_dpll_hw_state *dpll_hw_state);
70
71 /*
72 * Hook for disabling the pll, called from intel_disable_shared_dpll()
73 * only when it is safe to disable the pll, i.e., there are no more
74 * tracked users for it.
75 */
76 void (*disable)(struct drm_i915_private *i915,
77 struct intel_shared_dpll *pll);
78
79 /*
80 * Hook for reading the values currently programmed to the DPLL
81 * registers. This is used for initial hw state readout and state
82 * verification after a mode set.
83 */
84 bool (*get_hw_state)(struct drm_i915_private *i915,
85 struct intel_shared_dpll *pll,
86 struct intel_dpll_hw_state *dpll_hw_state);
87
88 /*
89 * Hook for calculating the pll's output frequency based on its passed
90 * in state.
91 */
92 int (*get_freq)(struct drm_i915_private *i915,
93 const struct intel_shared_dpll *pll,
94 const struct intel_dpll_hw_state *dpll_hw_state);
95};
96
97struct intel_dpll_mgr {
98 const struct dpll_info *dpll_info;
99
100 int (*compute_dplls)(struct intel_atomic_state *state,
101 struct intel_crtc *crtc,
102 struct intel_encoder *encoder);
103 int (*get_dplls)(struct intel_atomic_state *state,
104 struct intel_crtc *crtc,
105 struct intel_encoder *encoder);
106 void (*put_dplls)(struct intel_atomic_state *state,
107 struct intel_crtc *crtc);
108 void (*update_active_dpll)(struct intel_atomic_state *state,
109 struct intel_crtc *crtc,
110 struct intel_encoder *encoder);
111 void (*update_ref_clks)(struct drm_i915_private *i915);
112 void (*dump_hw_state)(struct drm_printer *p,
113 const struct intel_dpll_hw_state *dpll_hw_state);
114 bool (*compare_hw_state)(const struct intel_dpll_hw_state *a,
115 const struct intel_dpll_hw_state *b);
116};
117
118static void
119intel_atomic_duplicate_dpll_state(struct drm_i915_private *i915,
120 struct intel_shared_dpll_state *shared_dpll)
121{
122 struct intel_shared_dpll *pll;
123 int i;
124
125 /* Copy shared dpll state */
126 for_each_shared_dpll(i915, pll, i)
127 shared_dpll[pll->index] = pll->state;
128}
129
130static struct intel_shared_dpll_state *
131intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
132{
133 struct intel_atomic_state *state = to_intel_atomic_state(s);
134
135 drm_WARN_ON(s->dev, !drm_modeset_is_locked(&s->dev->mode_config.connection_mutex));
136
137 if (!state->dpll_set) {
138 state->dpll_set = true;
139
140 intel_atomic_duplicate_dpll_state(to_i915(s->dev),
141 state->shared_dpll);
142 }
143
144 return state->shared_dpll;
145}
146
147/**
148 * intel_get_shared_dpll_by_id - get a DPLL given its id
149 * @i915: i915 device instance
150 * @id: pll id
151 *
152 * Returns:
153 * A pointer to the DPLL with @id
154 */
155struct intel_shared_dpll *
156intel_get_shared_dpll_by_id(struct drm_i915_private *i915,
157 enum intel_dpll_id id)
158{
159 struct intel_shared_dpll *pll;
160 int i;
161
162 for_each_shared_dpll(i915, pll, i) {
163 if (pll->info->id == id)
164 return pll;
165 }
166
167 MISSING_CASE(id);
168 return NULL;
169}
170
171/* For ILK+ */
172void assert_shared_dpll(struct drm_i915_private *i915,
173 struct intel_shared_dpll *pll,
174 bool state)
175{
176 struct intel_display *display = &i915->display;
177 bool cur_state;
178 struct intel_dpll_hw_state hw_state;
179
180 if (drm_WARN(display->drm, !pll,
181 "asserting DPLL %s with no DPLL\n", str_on_off(state)))
182 return;
183
184 cur_state = intel_dpll_get_hw_state(i915, pll, &hw_state);
185 INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
186 "%s assertion failure (expected %s, current %s)\n",
187 pll->info->name, str_on_off(state),
188 str_on_off(cur_state));
189}
190
191static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)
192{
193 return TC_PORT_1 + id - DPLL_ID_ICL_MGPLL1;
194}
195
196enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
197{
198 return tc_port - TC_PORT_1 + DPLL_ID_ICL_MGPLL1;
199}
200
201static i915_reg_t
202intel_combo_pll_enable_reg(struct drm_i915_private *i915,
203 struct intel_shared_dpll *pll)
204{
205 if (IS_DG1(i915))
206 return DG1_DPLL_ENABLE(pll->info->id);
207 else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
208 (pll->info->id == DPLL_ID_EHL_DPLL4))
209 return MG_PLL_ENABLE(0);
210
211 return ICL_DPLL_ENABLE(pll->info->id);
212}
213
214static i915_reg_t
215intel_tc_pll_enable_reg(struct drm_i915_private *i915,
216 struct intel_shared_dpll *pll)
217{
218 const enum intel_dpll_id id = pll->info->id;
219 enum tc_port tc_port = icl_pll_id_to_tc_port(id);
220
221 if (IS_ALDERLAKE_P(i915))
222 return ADLP_PORTTC_PLL_ENABLE(tc_port);
223
224 return MG_PLL_ENABLE(tc_port);
225}
226
227static void _intel_enable_shared_dpll(struct drm_i915_private *i915,
228 struct intel_shared_dpll *pll)
229{
230 if (pll->info->power_domain)
231 pll->wakeref = intel_display_power_get(i915, pll->info->power_domain);
232
233 pll->info->funcs->enable(i915, pll, &pll->state.hw_state);
234 pll->on = true;
235}
236
237static void _intel_disable_shared_dpll(struct drm_i915_private *i915,
238 struct intel_shared_dpll *pll)
239{
240 pll->info->funcs->disable(i915, pll);
241 pll->on = false;
242
243 if (pll->info->power_domain)
244 intel_display_power_put(i915, pll->info->power_domain, pll->wakeref);
245}
246
247/**
248 * intel_enable_shared_dpll - enable a CRTC's shared DPLL
249 * @crtc_state: CRTC, and its state, which has a shared DPLL
250 *
251 * Enable the shared DPLL used by @crtc.
252 */
253void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
254{
255 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
256 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
257 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
258 unsigned int pipe_mask = BIT(crtc->pipe);
259 unsigned int old_mask;
260
261 if (drm_WARN_ON(&i915->drm, pll == NULL))
262 return;
263
264 mutex_lock(&i915->display.dpll.lock);
265 old_mask = pll->active_mask;
266
267 if (drm_WARN_ON(&i915->drm, !(pll->state.pipe_mask & pipe_mask)) ||
268 drm_WARN_ON(&i915->drm, pll->active_mask & pipe_mask))
269 goto out;
270
271 pll->active_mask |= pipe_mask;
272
273 drm_dbg_kms(&i915->drm,
274 "enable %s (active 0x%x, on? %d) for [CRTC:%d:%s]\n",
275 pll->info->name, pll->active_mask, pll->on,
276 crtc->base.base.id, crtc->base.name);
277
278 if (old_mask) {
279 drm_WARN_ON(&i915->drm, !pll->on);
280 assert_shared_dpll_enabled(i915, pll);
281 goto out;
282 }
283 drm_WARN_ON(&i915->drm, pll->on);
284
285 drm_dbg_kms(&i915->drm, "enabling %s\n", pll->info->name);
286
287 _intel_enable_shared_dpll(i915, pll);
288
289out:
290 mutex_unlock(&i915->display.dpll.lock);
291}
292
293/**
294 * intel_disable_shared_dpll - disable a CRTC's shared DPLL
295 * @crtc_state: CRTC, and its state, which has a shared DPLL
296 *
297 * Disable the shared DPLL used by @crtc.
298 */
299void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
300{
301 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
302 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
303 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
304 unsigned int pipe_mask = BIT(crtc->pipe);
305
306 /* PCH only available on ILK+ */
307 if (DISPLAY_VER(i915) < 5)
308 return;
309
310 if (pll == NULL)
311 return;
312
313 mutex_lock(&i915->display.dpll.lock);
314 if (drm_WARN(&i915->drm, !(pll->active_mask & pipe_mask),
315 "%s not used by [CRTC:%d:%s]\n", pll->info->name,
316 crtc->base.base.id, crtc->base.name))
317 goto out;
318
319 drm_dbg_kms(&i915->drm,
320 "disable %s (active 0x%x, on? %d) for [CRTC:%d:%s]\n",
321 pll->info->name, pll->active_mask, pll->on,
322 crtc->base.base.id, crtc->base.name);
323
324 assert_shared_dpll_enabled(i915, pll);
325 drm_WARN_ON(&i915->drm, !pll->on);
326
327 pll->active_mask &= ~pipe_mask;
328 if (pll->active_mask)
329 goto out;
330
331 drm_dbg_kms(&i915->drm, "disabling %s\n", pll->info->name);
332
333 _intel_disable_shared_dpll(i915, pll);
334
335out:
336 mutex_unlock(&i915->display.dpll.lock);
337}
338
339static unsigned long
340intel_dpll_mask_all(struct drm_i915_private *i915)
341{
342 struct intel_shared_dpll *pll;
343 unsigned long dpll_mask = 0;
344 int i;
345
346 for_each_shared_dpll(i915, pll, i) {
347 drm_WARN_ON(&i915->drm, dpll_mask & BIT(pll->info->id));
348
349 dpll_mask |= BIT(pll->info->id);
350 }
351
352 return dpll_mask;
353}
354
355static struct intel_shared_dpll *
356intel_find_shared_dpll(struct intel_atomic_state *state,
357 const struct intel_crtc *crtc,
358 const struct intel_dpll_hw_state *dpll_hw_state,
359 unsigned long dpll_mask)
360{
361 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
362 unsigned long dpll_mask_all = intel_dpll_mask_all(i915);
363 struct intel_shared_dpll_state *shared_dpll;
364 struct intel_shared_dpll *unused_pll = NULL;
365 enum intel_dpll_id id;
366
367 shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
368
369 drm_WARN_ON(&i915->drm, dpll_mask & ~dpll_mask_all);
370
371 for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
372 struct intel_shared_dpll *pll;
373
374 pll = intel_get_shared_dpll_by_id(i915, id);
375 if (!pll)
376 continue;
377
378 /* Only want to check enabled timings first */
379 if (shared_dpll[pll->index].pipe_mask == 0) {
380 if (!unused_pll)
381 unused_pll = pll;
382 continue;
383 }
384
385 if (memcmp(dpll_hw_state,
386 &shared_dpll[pll->index].hw_state,
387 sizeof(*dpll_hw_state)) == 0) {
388 drm_dbg_kms(&i915->drm,
389 "[CRTC:%d:%s] sharing existing %s (pipe mask 0x%x, active 0x%x)\n",
390 crtc->base.base.id, crtc->base.name,
391 pll->info->name,
392 shared_dpll[pll->index].pipe_mask,
393 pll->active_mask);
394 return pll;
395 }
396 }
397
398 /* Ok no matching timings, maybe there's a free one? */
399 if (unused_pll) {
400 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] allocated %s\n",
401 crtc->base.base.id, crtc->base.name,
402 unused_pll->info->name);
403 return unused_pll;
404 }
405
406 return NULL;
407}
408
409/**
410 * intel_reference_shared_dpll_crtc - Get a DPLL reference for a CRTC
411 * @crtc: CRTC on which behalf the reference is taken
412 * @pll: DPLL for which the reference is taken
413 * @shared_dpll_state: the DPLL atomic state in which the reference is tracked
414 *
415 * Take a reference for @pll tracking the use of it by @crtc.
416 */
417static void
418intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
419 const struct intel_shared_dpll *pll,
420 struct intel_shared_dpll_state *shared_dpll_state)
421{
422 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
423
424 drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);
425
426 shared_dpll_state->pipe_mask |= BIT(crtc->pipe);
427
428 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] reserving %s\n",
429 crtc->base.base.id, crtc->base.name, pll->info->name);
430}
431
432static void
433intel_reference_shared_dpll(struct intel_atomic_state *state,
434 const struct intel_crtc *crtc,
435 const struct intel_shared_dpll *pll,
436 const struct intel_dpll_hw_state *dpll_hw_state)
437{
438 struct intel_shared_dpll_state *shared_dpll;
439
440 shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
441
442 if (shared_dpll[pll->index].pipe_mask == 0)
443 shared_dpll[pll->index].hw_state = *dpll_hw_state;
444
445 intel_reference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]);
446}
447
448/**
449 * intel_unreference_shared_dpll_crtc - Drop a DPLL reference for a CRTC
450 * @crtc: CRTC on which behalf the reference is dropped
451 * @pll: DPLL for which the reference is dropped
452 * @shared_dpll_state: the DPLL atomic state in which the reference is tracked
453 *
454 * Drop a reference for @pll tracking the end of use of it by @crtc.
455 */
456void
457intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
458 const struct intel_shared_dpll *pll,
459 struct intel_shared_dpll_state *shared_dpll_state)
460{
461 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
462
463 drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);
464
465 shared_dpll_state->pipe_mask &= ~BIT(crtc->pipe);
466
467 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] releasing %s\n",
468 crtc->base.base.id, crtc->base.name, pll->info->name);
469}
470
471static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
472 const struct intel_crtc *crtc,
473 const struct intel_shared_dpll *pll)
474{
475 struct intel_shared_dpll_state *shared_dpll;
476
477 shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
478
479 intel_unreference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]);
480}
481
482static void intel_put_dpll(struct intel_atomic_state *state,
483 struct intel_crtc *crtc)
484{
485 const struct intel_crtc_state *old_crtc_state =
486 intel_atomic_get_old_crtc_state(state, crtc);
487 struct intel_crtc_state *new_crtc_state =
488 intel_atomic_get_new_crtc_state(state, crtc);
489
490 new_crtc_state->shared_dpll = NULL;
491
492 if (!old_crtc_state->shared_dpll)
493 return;
494
495 intel_unreference_shared_dpll(state, crtc, old_crtc_state->shared_dpll);
496}
497
498/**
499 * intel_shared_dpll_swap_state - make atomic DPLL configuration effective
500 * @state: atomic state
501 *
502 * This is the dpll version of drm_atomic_helper_swap_state() since the
503 * helper does not handle driver-specific global state.
504 *
505 * For consistency with atomic helpers this function does a complete swap,
506 * i.e. it also puts the current state into @state, even though there is no
507 * need for that at this moment.
508 */
509void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
510{
511 struct drm_i915_private *i915 = to_i915(state->base.dev);
512 struct intel_shared_dpll_state *shared_dpll = state->shared_dpll;
513 struct intel_shared_dpll *pll;
514 int i;
515
516 if (!state->dpll_set)
517 return;
518
519 for_each_shared_dpll(i915, pll, i)
520 swap(pll->state, shared_dpll[pll->index]);
521}
522
523static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *i915,
524 struct intel_shared_dpll *pll,
525 struct intel_dpll_hw_state *dpll_hw_state)
526{
527 struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
528 const enum intel_dpll_id id = pll->info->id;
529 intel_wakeref_t wakeref;
530 u32 val;
531
532 wakeref = intel_display_power_get_if_enabled(i915,
533 POWER_DOMAIN_DISPLAY_CORE);
534 if (!wakeref)
535 return false;
536
537 val = intel_de_read(i915, PCH_DPLL(id));
538 hw_state->dpll = val;
539 hw_state->fp0 = intel_de_read(i915, PCH_FP0(id));
540 hw_state->fp1 = intel_de_read(i915, PCH_FP1(id));
541
542 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref);
543
544 return val & DPLL_VCO_ENABLE;
545}
546
547static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *i915)
548{
549 struct intel_display *display = &i915->display;
550 u32 val;
551 bool enabled;
552
553 val = intel_de_read(display, PCH_DREF_CONTROL);
554 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
555 DREF_SUPERSPREAD_SOURCE_MASK));
556 INTEL_DISPLAY_STATE_WARN(display, !enabled,
557 "PCH refclk assertion failure, should be active but is disabled\n");
558}
559
560static void ibx_pch_dpll_enable(struct drm_i915_private *i915,
561 struct intel_shared_dpll *pll,
562 const struct intel_dpll_hw_state *dpll_hw_state)
563{
564 const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
565 const enum intel_dpll_id id = pll->info->id;
566
567 /* PCH refclock must be enabled first */
568 ibx_assert_pch_refclk_enabled(i915);
569
570 intel_de_write(i915, PCH_FP0(id), hw_state->fp0);
571 intel_de_write(i915, PCH_FP1(id), hw_state->fp1);
572
573 intel_de_write(i915, PCH_DPLL(id), hw_state->dpll);
574
575 /* Wait for the clocks to stabilize. */
576 intel_de_posting_read(i915, PCH_DPLL(id));
577 udelay(150);
578
579 /* The pixel multiplier can only be updated once the
580 * DPLL is enabled and the clocks are stable.
581 *
582 * So write it again.
583 */
584 intel_de_write(i915, PCH_DPLL(id), hw_state->dpll);
585 intel_de_posting_read(i915, PCH_DPLL(id));
586 udelay(200);
587}
588
589static void ibx_pch_dpll_disable(struct drm_i915_private *i915,
590 struct intel_shared_dpll *pll)
591{
592 const enum intel_dpll_id id = pll->info->id;
593
594 intel_de_write(i915, PCH_DPLL(id), 0);
595 intel_de_posting_read(i915, PCH_DPLL(id));
596 udelay(200);
597}
598
599static int ibx_compute_dpll(struct intel_atomic_state *state,
600 struct intel_crtc *crtc,
601 struct intel_encoder *encoder)
602{
603 return 0;
604}
605
606static int ibx_get_dpll(struct intel_atomic_state *state,
607 struct intel_crtc *crtc,
608 struct intel_encoder *encoder)
609{
610 struct intel_crtc_state *crtc_state =
611 intel_atomic_get_new_crtc_state(state, crtc);
612 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
613 struct intel_shared_dpll *pll;
614 enum intel_dpll_id id;
615
616 if (HAS_PCH_IBX(i915)) {
617 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
618 id = (enum intel_dpll_id) crtc->pipe;
619 pll = intel_get_shared_dpll_by_id(i915, id);
620
621 drm_dbg_kms(&i915->drm,
622 "[CRTC:%d:%s] using pre-allocated %s\n",
623 crtc->base.base.id, crtc->base.name,
624 pll->info->name);
625 } else {
626 pll = intel_find_shared_dpll(state, crtc,
627 &crtc_state->dpll_hw_state,
628 BIT(DPLL_ID_PCH_PLL_B) |
629 BIT(DPLL_ID_PCH_PLL_A));
630 }
631
632 if (!pll)
633 return -EINVAL;
634
635 /* reference the pll */
636 intel_reference_shared_dpll(state, crtc,
637 pll, &crtc_state->dpll_hw_state);
638
639 crtc_state->shared_dpll = pll;
640
641 return 0;
642}
643
644static void ibx_dump_hw_state(struct drm_printer *p,
645 const struct intel_dpll_hw_state *dpll_hw_state)
646{
647 const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
648
649 drm_printf(p, "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
650 "fp0: 0x%x, fp1: 0x%x\n",
651 hw_state->dpll,
652 hw_state->dpll_md,
653 hw_state->fp0,
654 hw_state->fp1);
655}
656
657static bool ibx_compare_hw_state(const struct intel_dpll_hw_state *_a,
658 const struct intel_dpll_hw_state *_b)
659{
660 const struct i9xx_dpll_hw_state *a = &_a->i9xx;
661 const struct i9xx_dpll_hw_state *b = &_b->i9xx;
662
663 return a->dpll == b->dpll &&
664 a->dpll_md == b->dpll_md &&
665 a->fp0 == b->fp0 &&
666 a->fp1 == b->fp1;
667}
668
669static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
670 .enable = ibx_pch_dpll_enable,
671 .disable = ibx_pch_dpll_disable,
672 .get_hw_state = ibx_pch_dpll_get_hw_state,
673};
674
675static const struct dpll_info pch_plls[] = {
676 { .name = "PCH DPLL A", .funcs = &ibx_pch_dpll_funcs, .id = DPLL_ID_PCH_PLL_A, },
677 { .name = "PCH DPLL B", .funcs = &ibx_pch_dpll_funcs, .id = DPLL_ID_PCH_PLL_B, },
678 {}
679};
680
681static const struct intel_dpll_mgr pch_pll_mgr = {
682 .dpll_info = pch_plls,
683 .compute_dplls = ibx_compute_dpll,
684 .get_dplls = ibx_get_dpll,
685 .put_dplls = intel_put_dpll,
686 .dump_hw_state = ibx_dump_hw_state,
687 .compare_hw_state = ibx_compare_hw_state,
688};
689
690static void hsw_ddi_wrpll_enable(struct drm_i915_private *i915,
691 struct intel_shared_dpll *pll,
692 const struct intel_dpll_hw_state *dpll_hw_state)
693{
694 const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
695 const enum intel_dpll_id id = pll->info->id;
696
697 intel_de_write(i915, WRPLL_CTL(id), hw_state->wrpll);
698 intel_de_posting_read(i915, WRPLL_CTL(id));
699 udelay(20);
700}
701
702static void hsw_ddi_spll_enable(struct drm_i915_private *i915,
703 struct intel_shared_dpll *pll,
704 const struct intel_dpll_hw_state *dpll_hw_state)
705{
706 const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
707
708 intel_de_write(i915, SPLL_CTL, hw_state->spll);
709 intel_de_posting_read(i915, SPLL_CTL);
710 udelay(20);
711}
712
713static void hsw_ddi_wrpll_disable(struct drm_i915_private *i915,
714 struct intel_shared_dpll *pll)
715{
716 const enum intel_dpll_id id = pll->info->id;
717
718 intel_de_rmw(i915, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0);
719 intel_de_posting_read(i915, WRPLL_CTL(id));
720
721 /*
722 * Try to set up the PCH reference clock once all DPLLs
723 * that depend on it have been shut down.
724 */
725 if (i915->display.dpll.pch_ssc_use & BIT(id))
726 intel_init_pch_refclk(i915);
727}
728
729static void hsw_ddi_spll_disable(struct drm_i915_private *i915,
730 struct intel_shared_dpll *pll)
731{
732 enum intel_dpll_id id = pll->info->id;
733
734 intel_de_rmw(i915, SPLL_CTL, SPLL_PLL_ENABLE, 0);
735 intel_de_posting_read(i915, SPLL_CTL);
736
737 /*
738 * Try to set up the PCH reference clock once all DPLLs
739 * that depend on it have been shut down.
740 */
741 if (i915->display.dpll.pch_ssc_use & BIT(id))
742 intel_init_pch_refclk(i915);
743}
744
745static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915,
746 struct intel_shared_dpll *pll,
747 struct intel_dpll_hw_state *dpll_hw_state)
748{
749 struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
750 const enum intel_dpll_id id = pll->info->id;
751 intel_wakeref_t wakeref;
752 u32 val;
753
754 wakeref = intel_display_power_get_if_enabled(i915,
755 POWER_DOMAIN_DISPLAY_CORE);
756 if (!wakeref)
757 return false;
758
759 val = intel_de_read(i915, WRPLL_CTL(id));
760 hw_state->wrpll = val;
761
762 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref);
763
764 return val & WRPLL_PLL_ENABLE;
765}
766
767static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *i915,
768 struct intel_shared_dpll *pll,
769 struct intel_dpll_hw_state *dpll_hw_state)
770{
771 struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
772 intel_wakeref_t wakeref;
773 u32 val;
774
775 wakeref = intel_display_power_get_if_enabled(i915,
776 POWER_DOMAIN_DISPLAY_CORE);
777 if (!wakeref)
778 return false;
779
780 val = intel_de_read(i915, SPLL_CTL);
781 hw_state->spll = val;
782
783 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref);
784
785 return val & SPLL_PLL_ENABLE;
786}
787
788#define LC_FREQ 2700
789#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
790
791#define P_MIN 2
792#define P_MAX 64
793#define P_INC 2
794
795/* Constraints for PLL good behavior */
796#define REF_MIN 48
797#define REF_MAX 400
798#define VCO_MIN 2400
799#define VCO_MAX 4800
800
801struct hsw_wrpll_rnp {
802 unsigned p, n2, r2;
803};
804
805static unsigned hsw_wrpll_get_budget_for_freq(int clock)
806{
807 switch (clock) {
808 case 25175000:
809 case 25200000:
810 case 27000000:
811 case 27027000:
812 case 37762500:
813 case 37800000:
814 case 40500000:
815 case 40541000:
816 case 54000000:
817 case 54054000:
818 case 59341000:
819 case 59400000:
820 case 72000000:
821 case 74176000:
822 case 74250000:
823 case 81000000:
824 case 81081000:
825 case 89012000:
826 case 89100000:
827 case 108000000:
828 case 108108000:
829 case 111264000:
830 case 111375000:
831 case 148352000:
832 case 148500000:
833 case 162000000:
834 case 162162000:
835 case 222525000:
836 case 222750000:
837 case 296703000:
838 case 297000000:
839 return 0;
840 case 233500000:
841 case 245250000:
842 case 247750000:
843 case 253250000:
844 case 298000000:
845 return 1500;
846 case 169128000:
847 case 169500000:
848 case 179500000:
849 case 202000000:
850 return 2000;
851 case 256250000:
852 case 262500000:
853 case 270000000:
854 case 272500000:
855 case 273750000:
856 case 280750000:
857 case 281250000:
858 case 286000000:
859 case 291750000:
860 return 4000;
861 case 267250000:
862 case 268500000:
863 return 5000;
864 default:
865 return 1000;
866 }
867}
868
869static void hsw_wrpll_update_rnp(u64 freq2k, unsigned int budget,
870 unsigned int r2, unsigned int n2,
871 unsigned int p,
872 struct hsw_wrpll_rnp *best)
873{
874 u64 a, b, c, d, diff, diff_best;
875
876 /* No best (r,n,p) yet */
877 if (best->p == 0) {
878 best->p = p;
879 best->n2 = n2;
880 best->r2 = r2;
881 return;
882 }
883
884 /*
885 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
886 * freq2k.
887 *
888 * delta = 1e6 *
889 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
890 * freq2k;
891 *
892 * and we would like delta <= budget.
893 *
894 * If the discrepancy is above the PPM-based budget, always prefer to
895 * improve upon the previous solution. However, if you're within the
896 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
897 */
898 a = freq2k * budget * p * r2;
899 b = freq2k * budget * best->p * best->r2;
900 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
901 diff_best = abs_diff(freq2k * best->p * best->r2,
902 LC_FREQ_2K * best->n2);
903 c = 1000000 * diff;
904 d = 1000000 * diff_best;
905
906 if (a < c && b < d) {
907 /* If both are above the budget, pick the closer */
908 if (best->p * best->r2 * diff < p * r2 * diff_best) {
909 best->p = p;
910 best->n2 = n2;
911 best->r2 = r2;
912 }
913 } else if (a >= c && b < d) {
914 /* If A is below the threshold but B is above it? Update. */
915 best->p = p;
916 best->n2 = n2;
917 best->r2 = r2;
918 } else if (a >= c && b >= d) {
919 /* Both are below the limit, so pick the higher n2/(r2*r2) */
920 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
921 best->p = p;
922 best->n2 = n2;
923 best->r2 = r2;
924 }
925 }
926 /* Otherwise a < c && b >= d, do nothing */
927}
928
929static void
930hsw_ddi_calculate_wrpll(int clock /* in Hz */,
931 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
932{
933 u64 freq2k;
934 unsigned p, n2, r2;
935 struct hsw_wrpll_rnp best = {};
936 unsigned budget;
937
938 freq2k = clock / 100;
939
940 budget = hsw_wrpll_get_budget_for_freq(clock);
941
942 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
943 * and directly pass the LC PLL to it. */
944 if (freq2k == 5400000) {
945 *n2_out = 2;
946 *p_out = 1;
947 *r2_out = 2;
948 return;
949 }
950
951 /*
952 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
953 * the WR PLL.
954 *
955 * We want R so that REF_MIN <= Ref <= REF_MAX.
956 * Injecting R2 = 2 * R gives:
957 * REF_MAX * r2 > LC_FREQ * 2 and
958 * REF_MIN * r2 < LC_FREQ * 2
959 *
960 * Which means the desired boundaries for r2 are:
961 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
962 *
963 */
964 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
965 r2 <= LC_FREQ * 2 / REF_MIN;
966 r2++) {
967
968 /*
969 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
970 *
971 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
972 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
973 * VCO_MAX * r2 > n2 * LC_FREQ and
974 * VCO_MIN * r2 < n2 * LC_FREQ)
975 *
976 * Which means the desired boundaries for n2 are:
977 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
978 */
979 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
980 n2 <= VCO_MAX * r2 / LC_FREQ;
981 n2++) {
982
983 for (p = P_MIN; p <= P_MAX; p += P_INC)
984 hsw_wrpll_update_rnp(freq2k, budget,
985 r2, n2, p, &best);
986 }
987 }
988
989 *n2_out = best.n2;
990 *p_out = best.p;
991 *r2_out = best.r2;
992}
993
994static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915,
995 const struct intel_shared_dpll *pll,
996 const struct intel_dpll_hw_state *dpll_hw_state)
997{
998 const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
999 int refclk;
1000 int n, p, r;
1001 u32 wrpll = hw_state->wrpll;
1002
1003 switch (wrpll & WRPLL_REF_MASK) {
1004 case WRPLL_REF_SPECIAL_HSW:
1005 /* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */
1006 if (IS_HASWELL(i915) && !IS_HASWELL_ULT(i915)) {
1007 refclk = i915->display.dpll.ref_clks.nssc;
1008 break;
1009 }
1010 fallthrough;
1011 case WRPLL_REF_PCH_SSC:
1012 /*
1013 * We could calculate spread here, but our checking
1014 * code only cares about 5% accuracy, and spread is a max of
1015 * 0.5% downspread.
1016 */
1017 refclk = i915->display.dpll.ref_clks.ssc;
1018 break;
1019 case WRPLL_REF_LCPLL:
1020 refclk = 2700000;
1021 break;
1022 default:
1023 MISSING_CASE(wrpll);
1024 return 0;
1025 }
1026
1027 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1028 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1029 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1030
1031 /* Convert to KHz, p & r have a fixed point portion */
1032 return (refclk * n / 10) / (p * r) * 2;
1033}
1034
1035static int
1036hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
1037 struct intel_crtc *crtc)
1038{
1039 struct drm_i915_private *i915 = to_i915(state->base.dev);
1040 struct intel_crtc_state *crtc_state =
1041 intel_atomic_get_new_crtc_state(state, crtc);
1042 struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
1043 unsigned int p, n2, r2;
1044
1045 hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p);
1046
1047 hw_state->wrpll =
1048 WRPLL_PLL_ENABLE | WRPLL_REF_LCPLL |
1049 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1050 WRPLL_DIVIDER_POST(p);
1051
1052 crtc_state->port_clock = hsw_ddi_wrpll_get_freq(i915, NULL,
1053 &crtc_state->dpll_hw_state);
1054
1055 return 0;
1056}
1057
1058static struct intel_shared_dpll *
1059hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
1060 struct intel_crtc *crtc)
1061{
1062 struct intel_crtc_state *crtc_state =
1063 intel_atomic_get_new_crtc_state(state, crtc);
1064
1065 return intel_find_shared_dpll(state, crtc,
1066 &crtc_state->dpll_hw_state,
1067 BIT(DPLL_ID_WRPLL2) |
1068 BIT(DPLL_ID_WRPLL1));
1069}
1070
1071static int
1072hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
1073{
1074 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1075 int clock = crtc_state->port_clock;
1076
1077 switch (clock / 2) {
1078 case 81000:
1079 case 135000:
1080 case 270000:
1081 return 0;
1082 default:
1083 drm_dbg_kms(&i915->drm, "Invalid clock for DP: %d\n",
1084 clock);
1085 return -EINVAL;
1086 }
1087}
1088
1089static struct intel_shared_dpll *
1090hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
1091{
1092 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1093 struct intel_shared_dpll *pll;
1094 enum intel_dpll_id pll_id;
1095 int clock = crtc_state->port_clock;
1096
1097 switch (clock / 2) {
1098 case 81000:
1099 pll_id = DPLL_ID_LCPLL_810;
1100 break;
1101 case 135000:
1102 pll_id = DPLL_ID_LCPLL_1350;
1103 break;
1104 case 270000:
1105 pll_id = DPLL_ID_LCPLL_2700;
1106 break;
1107 default:
1108 MISSING_CASE(clock / 2);
1109 return NULL;
1110 }
1111
1112 pll = intel_get_shared_dpll_by_id(i915, pll_id);
1113
1114 if (!pll)
1115 return NULL;
1116
1117 return pll;
1118}
1119
1120static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915,
1121 const struct intel_shared_dpll *pll,
1122 const struct intel_dpll_hw_state *dpll_hw_state)
1123{
1124 int link_clock = 0;
1125
1126 switch (pll->info->id) {
1127 case DPLL_ID_LCPLL_810:
1128 link_clock = 81000;
1129 break;
1130 case DPLL_ID_LCPLL_1350:
1131 link_clock = 135000;
1132 break;
1133 case DPLL_ID_LCPLL_2700:
1134 link_clock = 270000;
1135 break;
1136 default:
1137 drm_WARN(&i915->drm, 1, "bad port clock sel\n");
1138 break;
1139 }
1140
1141 return link_clock * 2;
1142}
1143
1144static int
1145hsw_ddi_spll_compute_dpll(struct intel_atomic_state *state,
1146 struct intel_crtc *crtc)
1147{
1148 struct intel_crtc_state *crtc_state =
1149 intel_atomic_get_new_crtc_state(state, crtc);
1150 struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
1151
1152 if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000))
1153 return -EINVAL;
1154
1155 hw_state->spll =
1156 SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;
1157
1158 return 0;
1159}
1160
1161static struct intel_shared_dpll *
1162hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
1163 struct intel_crtc *crtc)
1164{
1165 struct intel_crtc_state *crtc_state =
1166 intel_atomic_get_new_crtc_state(state, crtc);
1167
1168 return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state,
1169 BIT(DPLL_ID_SPLL));
1170}
1171
1172static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
1173 const struct intel_shared_dpll *pll,
1174 const struct intel_dpll_hw_state *dpll_hw_state)
1175{
1176 const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
1177 int link_clock = 0;
1178
1179 switch (hw_state->spll & SPLL_FREQ_MASK) {
1180 case SPLL_FREQ_810MHz:
1181 link_clock = 81000;
1182 break;
1183 case SPLL_FREQ_1350MHz:
1184 link_clock = 135000;
1185 break;
1186 case SPLL_FREQ_2700MHz:
1187 link_clock = 270000;
1188 break;
1189 default:
1190 drm_WARN(&i915->drm, 1, "bad spll freq\n");
1191 break;
1192 }
1193
1194 return link_clock * 2;
1195}
1196
1197static int hsw_compute_dpll(struct intel_atomic_state *state,
1198 struct intel_crtc *crtc,
1199 struct intel_encoder *encoder)
1200{
1201 struct intel_crtc_state *crtc_state =
1202 intel_atomic_get_new_crtc_state(state, crtc);
1203
1204 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1205 return hsw_ddi_wrpll_compute_dpll(state, crtc);
1206 else if (intel_crtc_has_dp_encoder(crtc_state))
1207 return hsw_ddi_lcpll_compute_dpll(crtc_state);
1208 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1209 return hsw_ddi_spll_compute_dpll(state, crtc);
1210 else
1211 return -EINVAL;
1212}
1213
1214static int hsw_get_dpll(struct intel_atomic_state *state,
1215 struct intel_crtc *crtc,
1216 struct intel_encoder *encoder)
1217{
1218 struct intel_crtc_state *crtc_state =
1219 intel_atomic_get_new_crtc_state(state, crtc);
1220 struct intel_shared_dpll *pll = NULL;
1221
1222 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1223 pll = hsw_ddi_wrpll_get_dpll(state, crtc);
1224 else if (intel_crtc_has_dp_encoder(crtc_state))
1225 pll = hsw_ddi_lcpll_get_dpll(crtc_state);
1226 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1227 pll = hsw_ddi_spll_get_dpll(state, crtc);
1228
1229 if (!pll)
1230 return -EINVAL;
1231
1232 intel_reference_shared_dpll(state, crtc,
1233 pll, &crtc_state->dpll_hw_state);
1234
1235 crtc_state->shared_dpll = pll;
1236
1237 return 0;
1238}
1239
1240static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915)
1241{
1242 i915->display.dpll.ref_clks.ssc = 135000;
1243 /* Non-SSC is only used on non-ULT HSW. */
1244 if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
1245 i915->display.dpll.ref_clks.nssc = 24000;
1246 else
1247 i915->display.dpll.ref_clks.nssc = 135000;
1248}
1249
1250static void hsw_dump_hw_state(struct drm_printer *p,
1251 const struct intel_dpll_hw_state *dpll_hw_state)
1252{
1253 const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
1254
1255 drm_printf(p, "dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
1256 hw_state->wrpll, hw_state->spll);
1257}
1258
1259static bool hsw_compare_hw_state(const struct intel_dpll_hw_state *_a,
1260 const struct intel_dpll_hw_state *_b)
1261{
1262 const struct hsw_dpll_hw_state *a = &_a->hsw;
1263 const struct hsw_dpll_hw_state *b = &_b->hsw;
1264
1265 return a->wrpll == b->wrpll &&
1266 a->spll == b->spll;
1267}
1268
1269static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
1270 .enable = hsw_ddi_wrpll_enable,
1271 .disable = hsw_ddi_wrpll_disable,
1272 .get_hw_state = hsw_ddi_wrpll_get_hw_state,
1273 .get_freq = hsw_ddi_wrpll_get_freq,
1274};
1275
1276static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
1277 .enable = hsw_ddi_spll_enable,
1278 .disable = hsw_ddi_spll_disable,
1279 .get_hw_state = hsw_ddi_spll_get_hw_state,
1280 .get_freq = hsw_ddi_spll_get_freq,
1281};
1282
1283static void hsw_ddi_lcpll_enable(struct drm_i915_private *i915,
1284 struct intel_shared_dpll *pll,
1285 const struct intel_dpll_hw_state *hw_state)
1286{
1287}
1288
1289static void hsw_ddi_lcpll_disable(struct drm_i915_private *i915,
1290 struct intel_shared_dpll *pll)
1291{
1292}
1293
1294static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *i915,
1295 struct intel_shared_dpll *pll,
1296 struct intel_dpll_hw_state *dpll_hw_state)
1297{
1298 return true;
1299}
1300
1301static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
1302 .enable = hsw_ddi_lcpll_enable,
1303 .disable = hsw_ddi_lcpll_disable,
1304 .get_hw_state = hsw_ddi_lcpll_get_hw_state,
1305 .get_freq = hsw_ddi_lcpll_get_freq,
1306};
1307
1308static const struct dpll_info hsw_plls[] = {
1309 { .name = "WRPLL 1", .funcs = &hsw_ddi_wrpll_funcs, .id = DPLL_ID_WRPLL1, },
1310 { .name = "WRPLL 2", .funcs = &hsw_ddi_wrpll_funcs, .id = DPLL_ID_WRPLL2, },
1311 { .name = "SPLL", .funcs = &hsw_ddi_spll_funcs, .id = DPLL_ID_SPLL, },
1312 { .name = "LCPLL 810", .funcs = &hsw_ddi_lcpll_funcs, .id = DPLL_ID_LCPLL_810,
1313 .always_on = true, },
1314 { .name = "LCPLL 1350", .funcs = &hsw_ddi_lcpll_funcs, .id = DPLL_ID_LCPLL_1350,
1315 .always_on = true, },
1316 { .name = "LCPLL 2700", .funcs = &hsw_ddi_lcpll_funcs, .id = DPLL_ID_LCPLL_2700,
1317 .always_on = true, },
1318 {}
1319};
1320
1321static const struct intel_dpll_mgr hsw_pll_mgr = {
1322 .dpll_info = hsw_plls,
1323 .compute_dplls = hsw_compute_dpll,
1324 .get_dplls = hsw_get_dpll,
1325 .put_dplls = intel_put_dpll,
1326 .update_ref_clks = hsw_update_dpll_ref_clks,
1327 .dump_hw_state = hsw_dump_hw_state,
1328 .compare_hw_state = hsw_compare_hw_state,
1329};
1330
1331struct skl_dpll_regs {
1332 i915_reg_t ctl, cfgcr1, cfgcr2;
1333};
1334
1335/* this array is indexed by the *shared* pll id */
1336static const struct skl_dpll_regs skl_dpll_regs[4] = {
1337 {
1338 /* DPLL 0 */
1339 .ctl = LCPLL1_CTL,
1340 /* DPLL 0 doesn't support HDMI mode */
1341 },
1342 {
1343 /* DPLL 1 */
1344 .ctl = LCPLL2_CTL,
1345 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
1346 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
1347 },
1348 {
1349 /* DPLL 2 */
1350 .ctl = WRPLL_CTL(0),
1351 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
1352 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
1353 },
1354 {
1355 /* DPLL 3 */
1356 .ctl = WRPLL_CTL(1),
1357 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
1358 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
1359 },
1360};
1361
1362static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *i915,
1363 struct intel_shared_dpll *pll,
1364 const struct skl_dpll_hw_state *hw_state)
1365{
1366 const enum intel_dpll_id id = pll->info->id;
1367
1368 intel_de_rmw(i915, DPLL_CTRL1,
1369 DPLL_CTRL1_HDMI_MODE(id) |
1370 DPLL_CTRL1_SSC(id) |
1371 DPLL_CTRL1_LINK_RATE_MASK(id),
1372 hw_state->ctrl1 << (id * 6));
1373 intel_de_posting_read(i915, DPLL_CTRL1);
1374}
1375
1376static void skl_ddi_pll_enable(struct drm_i915_private *i915,
1377 struct intel_shared_dpll *pll,
1378 const struct intel_dpll_hw_state *dpll_hw_state)
1379{
1380 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
1381 const struct skl_dpll_regs *regs = skl_dpll_regs;
1382 const enum intel_dpll_id id = pll->info->id;
1383
1384 skl_ddi_pll_write_ctrl1(i915, pll, hw_state);
1385
1386 intel_de_write(i915, regs[id].cfgcr1, hw_state->cfgcr1);
1387 intel_de_write(i915, regs[id].cfgcr2, hw_state->cfgcr2);
1388 intel_de_posting_read(i915, regs[id].cfgcr1);
1389 intel_de_posting_read(i915, regs[id].cfgcr2);
1390
1391 /* the enable bit is always bit 31 */
1392 intel_de_rmw(i915, regs[id].ctl, 0, LCPLL_PLL_ENABLE);
1393
1394 if (intel_de_wait_for_set(i915, DPLL_STATUS, DPLL_LOCK(id), 5))
1395 drm_err(&i915->drm, "DPLL %d not locked\n", id);
1396}
1397
1398static void skl_ddi_dpll0_enable(struct drm_i915_private *i915,
1399 struct intel_shared_dpll *pll,
1400 const struct intel_dpll_hw_state *dpll_hw_state)
1401{
1402 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
1403
1404 skl_ddi_pll_write_ctrl1(i915, pll, hw_state);
1405}
1406
1407static void skl_ddi_pll_disable(struct drm_i915_private *i915,
1408 struct intel_shared_dpll *pll)
1409{
1410 const struct skl_dpll_regs *regs = skl_dpll_regs;
1411 const enum intel_dpll_id id = pll->info->id;
1412
1413 /* the enable bit is always bit 31 */
1414 intel_de_rmw(i915, regs[id].ctl, LCPLL_PLL_ENABLE, 0);
1415 intel_de_posting_read(i915, regs[id].ctl);
1416}
1417
1418static void skl_ddi_dpll0_disable(struct drm_i915_private *i915,
1419 struct intel_shared_dpll *pll)
1420{
1421}
1422
1423static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915,
1424 struct intel_shared_dpll *pll,
1425 struct intel_dpll_hw_state *dpll_hw_state)
1426{
1427 struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
1428 const struct skl_dpll_regs *regs = skl_dpll_regs;
1429 const enum intel_dpll_id id = pll->info->id;
1430 intel_wakeref_t wakeref;
1431 bool ret;
1432 u32 val;
1433
1434 wakeref = intel_display_power_get_if_enabled(i915,
1435 POWER_DOMAIN_DISPLAY_CORE);
1436 if (!wakeref)
1437 return false;
1438
1439 ret = false;
1440
1441 val = intel_de_read(i915, regs[id].ctl);
1442 if (!(val & LCPLL_PLL_ENABLE))
1443 goto out;
1444
1445 val = intel_de_read(i915, DPLL_CTRL1);
1446 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
1447
1448 /* avoid reading back stale values if HDMI mode is not enabled */
1449 if (val & DPLL_CTRL1_HDMI_MODE(id)) {
1450 hw_state->cfgcr1 = intel_de_read(i915, regs[id].cfgcr1);
1451 hw_state->cfgcr2 = intel_de_read(i915, regs[id].cfgcr2);
1452 }
1453 ret = true;
1454
1455out:
1456 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref);
1457
1458 return ret;
1459}
1460
1461static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *i915,
1462 struct intel_shared_dpll *pll,
1463 struct intel_dpll_hw_state *dpll_hw_state)
1464{
1465 struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
1466 const struct skl_dpll_regs *regs = skl_dpll_regs;
1467 const enum intel_dpll_id id = pll->info->id;
1468 intel_wakeref_t wakeref;
1469 u32 val;
1470 bool ret;
1471
1472 wakeref = intel_display_power_get_if_enabled(i915,
1473 POWER_DOMAIN_DISPLAY_CORE);
1474 if (!wakeref)
1475 return false;
1476
1477 ret = false;
1478
1479 /* DPLL0 is always enabled since it drives CDCLK */
1480 val = intel_de_read(i915, regs[id].ctl);
1481 if (drm_WARN_ON(&i915->drm, !(val & LCPLL_PLL_ENABLE)))
1482 goto out;
1483
1484 val = intel_de_read(i915, DPLL_CTRL1);
1485 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
1486
1487 ret = true;
1488
1489out:
1490 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref);
1491
1492 return ret;
1493}
1494
1495struct skl_wrpll_context {
1496 u64 min_deviation; /* current minimal deviation */
1497 u64 central_freq; /* chosen central freq */
1498 u64 dco_freq; /* chosen dco freq */
1499 unsigned int p; /* chosen divider */
1500};
1501
1502/* DCO freq must be within +1%/-6% of the DCO central freq */
1503#define SKL_DCO_MAX_PDEVIATION 100
1504#define SKL_DCO_MAX_NDEVIATION 600
1505
1506static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1507 u64 central_freq,
1508 u64 dco_freq,
1509 unsigned int divider)
1510{
1511 u64 deviation;
1512
1513 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1514 central_freq);
1515
1516 /* positive deviation */
1517 if (dco_freq >= central_freq) {
1518 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1519 deviation < ctx->min_deviation) {
1520 ctx->min_deviation = deviation;
1521 ctx->central_freq = central_freq;
1522 ctx->dco_freq = dco_freq;
1523 ctx->p = divider;
1524 }
1525 /* negative deviation */
1526 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1527 deviation < ctx->min_deviation) {
1528 ctx->min_deviation = deviation;
1529 ctx->central_freq = central_freq;
1530 ctx->dco_freq = dco_freq;
1531 ctx->p = divider;
1532 }
1533}
1534
1535static void skl_wrpll_get_multipliers(unsigned int p,
1536 unsigned int *p0 /* out */,
1537 unsigned int *p1 /* out */,
1538 unsigned int *p2 /* out */)
1539{
1540 /* even dividers */
1541 if (p % 2 == 0) {
1542 unsigned int half = p / 2;
1543
1544 if (half == 1 || half == 2 || half == 3 || half == 5) {
1545 *p0 = 2;
1546 *p1 = 1;
1547 *p2 = half;
1548 } else if (half % 2 == 0) {
1549 *p0 = 2;
1550 *p1 = half / 2;
1551 *p2 = 2;
1552 } else if (half % 3 == 0) {
1553 *p0 = 3;
1554 *p1 = half / 3;
1555 *p2 = 2;
1556 } else if (half % 7 == 0) {
1557 *p0 = 7;
1558 *p1 = half / 7;
1559 *p2 = 2;
1560 }
1561 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1562 *p0 = 3;
1563 *p1 = 1;
1564 *p2 = p / 3;
1565 } else if (p == 5 || p == 7) {
1566 *p0 = p;
1567 *p1 = 1;
1568 *p2 = 1;
1569 } else if (p == 15) {
1570 *p0 = 3;
1571 *p1 = 1;
1572 *p2 = 5;
1573 } else if (p == 21) {
1574 *p0 = 7;
1575 *p1 = 1;
1576 *p2 = 3;
1577 } else if (p == 35) {
1578 *p0 = 7;
1579 *p1 = 1;
1580 *p2 = 5;
1581 }
1582}
1583
1584struct skl_wrpll_params {
1585 u32 dco_fraction;
1586 u32 dco_integer;
1587 u32 qdiv_ratio;
1588 u32 qdiv_mode;
1589 u32 kdiv;
1590 u32 pdiv;
1591 u32 central_freq;
1592};
1593
1594static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1595 u64 afe_clock,
1596 int ref_clock,
1597 u64 central_freq,
1598 u32 p0, u32 p1, u32 p2)
1599{
1600 u64 dco_freq;
1601
1602 switch (central_freq) {
1603 case 9600000000ULL:
1604 params->central_freq = 0;
1605 break;
1606 case 9000000000ULL:
1607 params->central_freq = 1;
1608 break;
1609 case 8400000000ULL:
1610 params->central_freq = 3;
1611 }
1612
1613 switch (p0) {
1614 case 1:
1615 params->pdiv = 0;
1616 break;
1617 case 2:
1618 params->pdiv = 1;
1619 break;
1620 case 3:
1621 params->pdiv = 2;
1622 break;
1623 case 7:
1624 params->pdiv = 4;
1625 break;
1626 default:
1627 WARN(1, "Incorrect PDiv\n");
1628 }
1629
1630 switch (p2) {
1631 case 5:
1632 params->kdiv = 0;
1633 break;
1634 case 2:
1635 params->kdiv = 1;
1636 break;
1637 case 3:
1638 params->kdiv = 2;
1639 break;
1640 case 1:
1641 params->kdiv = 3;
1642 break;
1643 default:
1644 WARN(1, "Incorrect KDiv\n");
1645 }
1646
1647 params->qdiv_ratio = p1;
1648 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1649
1650 dco_freq = p0 * p1 * p2 * afe_clock;
1651
1652 /*
1653 * Intermediate values are in Hz.
1654 * Divide by MHz to match bsepc
1655 */
1656 params->dco_integer = div_u64(dco_freq, ref_clock * KHz(1));
1657 params->dco_fraction =
1658 div_u64((div_u64(dco_freq, ref_clock / KHz(1)) -
1659 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
1660}
1661
1662static int
1663skl_ddi_calculate_wrpll(int clock,
1664 int ref_clock,
1665 struct skl_wrpll_params *wrpll_params)
1666{
1667 static const u64 dco_central_freq[3] = { 8400000000ULL,
1668 9000000000ULL,
1669 9600000000ULL };
1670 static const u8 even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1671 24, 28, 30, 32, 36, 40, 42, 44,
1672 48, 52, 54, 56, 60, 64, 66, 68,
1673 70, 72, 76, 78, 80, 84, 88, 90,
1674 92, 96, 98 };
1675 static const u8 odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1676 static const struct {
1677 const u8 *list;
1678 int n_dividers;
1679 } dividers[] = {
1680 { even_dividers, ARRAY_SIZE(even_dividers) },
1681 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1682 };
1683 struct skl_wrpll_context ctx = {
1684 .min_deviation = U64_MAX,
1685 };
1686 unsigned int dco, d, i;
1687 unsigned int p0, p1, p2;
1688 u64 afe_clock = (u64)clock * 1000 * 5; /* AFE Clock is 5x Pixel clock, in Hz */
1689
1690 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1691 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1692 for (i = 0; i < dividers[d].n_dividers; i++) {
1693 unsigned int p = dividers[d].list[i];
1694 u64 dco_freq = p * afe_clock;
1695
1696 skl_wrpll_try_divider(&ctx,
1697 dco_central_freq[dco],
1698 dco_freq,
1699 p);
1700 /*
1701 * Skip the remaining dividers if we're sure to
1702 * have found the definitive divider, we can't
1703 * improve a 0 deviation.
1704 */
1705 if (ctx.min_deviation == 0)
1706 goto skip_remaining_dividers;
1707 }
1708 }
1709
1710skip_remaining_dividers:
1711 /*
1712 * If a solution is found with an even divider, prefer
1713 * this one.
1714 */
1715 if (d == 0 && ctx.p)
1716 break;
1717 }
1718
1719 if (!ctx.p)
1720 return -EINVAL;
1721
1722 /*
1723 * gcc incorrectly analyses that these can be used without being
1724 * initialized. To be fair, it's hard to guess.
1725 */
1726 p0 = p1 = p2 = 0;
1727 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1728 skl_wrpll_params_populate(wrpll_params, afe_clock, ref_clock,
1729 ctx.central_freq, p0, p1, p2);
1730
1731 return 0;
1732}
1733
1734static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
1735 const struct intel_shared_dpll *pll,
1736 const struct intel_dpll_hw_state *dpll_hw_state)
1737{
1738 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
1739 int ref_clock = i915->display.dpll.ref_clks.nssc;
1740 u32 p0, p1, p2, dco_freq;
1741
1742 p0 = hw_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1743 p2 = hw_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
1744
1745 if (hw_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1))
1746 p1 = (hw_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1747 else
1748 p1 = 1;
1749
1750
1751 switch (p0) {
1752 case DPLL_CFGCR2_PDIV_1:
1753 p0 = 1;
1754 break;
1755 case DPLL_CFGCR2_PDIV_2:
1756 p0 = 2;
1757 break;
1758 case DPLL_CFGCR2_PDIV_3:
1759 p0 = 3;
1760 break;
1761 case DPLL_CFGCR2_PDIV_7_INVALID:
1762 /*
1763 * Incorrect ASUS-Z170M BIOS setting, the HW seems to ignore bit#0,
1764 * handling it the same way as PDIV_7.
1765 */
1766 drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");
1767 fallthrough;
1768 case DPLL_CFGCR2_PDIV_7:
1769 p0 = 7;
1770 break;
1771 default:
1772 MISSING_CASE(p0);
1773 return 0;
1774 }
1775
1776 switch (p2) {
1777 case DPLL_CFGCR2_KDIV_5:
1778 p2 = 5;
1779 break;
1780 case DPLL_CFGCR2_KDIV_2:
1781 p2 = 2;
1782 break;
1783 case DPLL_CFGCR2_KDIV_3:
1784 p2 = 3;
1785 break;
1786 case DPLL_CFGCR2_KDIV_1:
1787 p2 = 1;
1788 break;
1789 default:
1790 MISSING_CASE(p2);
1791 return 0;
1792 }
1793
1794 dco_freq = (hw_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) *
1795 ref_clock;
1796
1797 dco_freq += ((hw_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) *
1798 ref_clock / 0x8000;
1799
1800 if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0))
1801 return 0;
1802
1803 return dco_freq / (p0 * p1 * p2 * 5);
1804}
1805
1806static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
1807{
1808 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1809 struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;
1810 struct skl_wrpll_params wrpll_params = {};
1811 int ret;
1812
1813 ret = skl_ddi_calculate_wrpll(crtc_state->port_clock,
1814 i915->display.dpll.ref_clks.nssc, &wrpll_params);
1815 if (ret)
1816 return ret;
1817
1818 /*
1819 * See comment in intel_dpll_hw_state to understand why we always use 0
1820 * as the DPLL id in this function.
1821 */
1822 hw_state->ctrl1 =
1823 DPLL_CTRL1_OVERRIDE(0) |
1824 DPLL_CTRL1_HDMI_MODE(0);
1825
1826 hw_state->cfgcr1 =
1827 DPLL_CFGCR1_FREQ_ENABLE |
1828 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1829 wrpll_params.dco_integer;
1830
1831 hw_state->cfgcr2 =
1832 DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1833 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1834 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1835 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1836 wrpll_params.central_freq;
1837
1838 crtc_state->port_clock = skl_ddi_wrpll_get_freq(i915, NULL,
1839 &crtc_state->dpll_hw_state);
1840
1841 return 0;
1842}
1843
1844static int
1845skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
1846{
1847 struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;
1848 u32 ctrl1;
1849
1850 /*
1851 * See comment in intel_dpll_hw_state to understand why we always use 0
1852 * as the DPLL id in this function.
1853 */
1854 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1855 switch (crtc_state->port_clock / 2) {
1856 case 81000:
1857 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
1858 break;
1859 case 135000:
1860 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
1861 break;
1862 case 270000:
1863 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
1864 break;
1865 /* eDP 1.4 rates */
1866 case 162000:
1867 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0);
1868 break;
1869 case 108000:
1870 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
1871 break;
1872 case 216000:
1873 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
1874 break;
1875 }
1876
1877 hw_state->ctrl1 = ctrl1;
1878
1879 return 0;
1880}
1881
1882static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
1883 const struct intel_shared_dpll *pll,
1884 const struct intel_dpll_hw_state *dpll_hw_state)
1885{
1886 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
1887 int link_clock = 0;
1888
1889 switch ((hw_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0)) >>
1890 DPLL_CTRL1_LINK_RATE_SHIFT(0)) {
1891 case DPLL_CTRL1_LINK_RATE_810:
1892 link_clock = 81000;
1893 break;
1894 case DPLL_CTRL1_LINK_RATE_1080:
1895 link_clock = 108000;
1896 break;
1897 case DPLL_CTRL1_LINK_RATE_1350:
1898 link_clock = 135000;
1899 break;
1900 case DPLL_CTRL1_LINK_RATE_1620:
1901 link_clock = 162000;
1902 break;
1903 case DPLL_CTRL1_LINK_RATE_2160:
1904 link_clock = 216000;
1905 break;
1906 case DPLL_CTRL1_LINK_RATE_2700:
1907 link_clock = 270000;
1908 break;
1909 default:
1910 drm_WARN(&i915->drm, 1, "Unsupported link rate\n");
1911 break;
1912 }
1913
1914 return link_clock * 2;
1915}
1916
1917static int skl_compute_dpll(struct intel_atomic_state *state,
1918 struct intel_crtc *crtc,
1919 struct intel_encoder *encoder)
1920{
1921 struct intel_crtc_state *crtc_state =
1922 intel_atomic_get_new_crtc_state(state, crtc);
1923
1924 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1925 return skl_ddi_hdmi_pll_dividers(crtc_state);
1926 else if (intel_crtc_has_dp_encoder(crtc_state))
1927 return skl_ddi_dp_set_dpll_hw_state(crtc_state);
1928 else
1929 return -EINVAL;
1930}
1931
1932static int skl_get_dpll(struct intel_atomic_state *state,
1933 struct intel_crtc *crtc,
1934 struct intel_encoder *encoder)
1935{
1936 struct intel_crtc_state *crtc_state =
1937 intel_atomic_get_new_crtc_state(state, crtc);
1938 struct intel_shared_dpll *pll;
1939
1940 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1941 pll = intel_find_shared_dpll(state, crtc,
1942 &crtc_state->dpll_hw_state,
1943 BIT(DPLL_ID_SKL_DPLL0));
1944 else
1945 pll = intel_find_shared_dpll(state, crtc,
1946 &crtc_state->dpll_hw_state,
1947 BIT(DPLL_ID_SKL_DPLL3) |
1948 BIT(DPLL_ID_SKL_DPLL2) |
1949 BIT(DPLL_ID_SKL_DPLL1));
1950 if (!pll)
1951 return -EINVAL;
1952
1953 intel_reference_shared_dpll(state, crtc,
1954 pll, &crtc_state->dpll_hw_state);
1955
1956 crtc_state->shared_dpll = pll;
1957
1958 return 0;
1959}
1960
1961static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
1962 const struct intel_shared_dpll *pll,
1963 const struct intel_dpll_hw_state *dpll_hw_state)
1964{
1965 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
1966
1967 /*
1968 * ctrl1 register is already shifted for each pll, just use 0 to get
1969 * the internal shift for each field
1970 */
1971 if (hw_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0))
1972 return skl_ddi_wrpll_get_freq(i915, pll, dpll_hw_state);
1973 else
1974 return skl_ddi_lcpll_get_freq(i915, pll, dpll_hw_state);
1975}
1976
1977static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
1978{
1979 /* No SSC ref */
1980 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref;
1981}
1982
1983static void skl_dump_hw_state(struct drm_printer *p,
1984 const struct intel_dpll_hw_state *dpll_hw_state)
1985{
1986 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
1987
1988 drm_printf(p, "dpll_hw_state: ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
1989 hw_state->ctrl1, hw_state->cfgcr1, hw_state->cfgcr2);
1990}
1991
1992static bool skl_compare_hw_state(const struct intel_dpll_hw_state *_a,
1993 const struct intel_dpll_hw_state *_b)
1994{
1995 const struct skl_dpll_hw_state *a = &_a->skl;
1996 const struct skl_dpll_hw_state *b = &_b->skl;
1997
1998 return a->ctrl1 == b->ctrl1 &&
1999 a->cfgcr1 == b->cfgcr1 &&
2000 a->cfgcr2 == b->cfgcr2;
2001}
2002
2003static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
2004 .enable = skl_ddi_pll_enable,
2005 .disable = skl_ddi_pll_disable,
2006 .get_hw_state = skl_ddi_pll_get_hw_state,
2007 .get_freq = skl_ddi_pll_get_freq,
2008};
2009
2010static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
2011 .enable = skl_ddi_dpll0_enable,
2012 .disable = skl_ddi_dpll0_disable,
2013 .get_hw_state = skl_ddi_dpll0_get_hw_state,
2014 .get_freq = skl_ddi_pll_get_freq,
2015};
2016
2017static const struct dpll_info skl_plls[] = {
2018 { .name = "DPLL 0", .funcs = &skl_ddi_dpll0_funcs, .id = DPLL_ID_SKL_DPLL0,
2019 .always_on = true, },
2020 { .name = "DPLL 1", .funcs = &skl_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL1, },
2021 { .name = "DPLL 2", .funcs = &skl_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL2, },
2022 { .name = "DPLL 3", .funcs = &skl_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL3, },
2023 {}
2024};
2025
2026static const struct intel_dpll_mgr skl_pll_mgr = {
2027 .dpll_info = skl_plls,
2028 .compute_dplls = skl_compute_dpll,
2029 .get_dplls = skl_get_dpll,
2030 .put_dplls = intel_put_dpll,
2031 .update_ref_clks = skl_update_dpll_ref_clks,
2032 .dump_hw_state = skl_dump_hw_state,
2033 .compare_hw_state = skl_compare_hw_state,
2034};
2035
2036static void bxt_ddi_pll_enable(struct drm_i915_private *i915,
2037 struct intel_shared_dpll *pll,
2038 const struct intel_dpll_hw_state *dpll_hw_state)
2039{
2040 struct intel_display *display = &i915->display;
2041 const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
2042 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
2043 enum dpio_phy phy;
2044 enum dpio_channel ch;
2045 u32 temp;
2046
2047 bxt_port_to_phy_channel(display, port, &phy, &ch);
2048
2049 /* Non-SSC reference */
2050 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL);
2051
2052 if (IS_GEMINILAKE(i915)) {
2053 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port),
2054 0, PORT_PLL_POWER_ENABLE);
2055
2056 if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) &
2057 PORT_PLL_POWER_STATE), 200))
2058 drm_err(&i915->drm,
2059 "Power state not set for PLL:%d\n", port);
2060 }
2061
2062 /* Disable 10 bit clock */
2063 intel_de_rmw(i915, BXT_PORT_PLL_EBB_4(phy, ch),
2064 PORT_PLL_10BIT_CLK_ENABLE, 0);
2065
2066 /* Write P1 & P2 */
2067 intel_de_rmw(i915, BXT_PORT_PLL_EBB_0(phy, ch),
2068 PORT_PLL_P1_MASK | PORT_PLL_P2_MASK, hw_state->ebb0);
2069
2070 /* Write M2 integer */
2071 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 0),
2072 PORT_PLL_M2_INT_MASK, hw_state->pll0);
2073
2074 /* Write N */
2075 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 1),
2076 PORT_PLL_N_MASK, hw_state->pll1);
2077
2078 /* Write M2 fraction */
2079 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 2),
2080 PORT_PLL_M2_FRAC_MASK, hw_state->pll2);
2081
2082 /* Write M2 fraction enable */
2083 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 3),
2084 PORT_PLL_M2_FRAC_ENABLE, hw_state->pll3);
2085
2086 /* Write coeff */
2087 temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6));
2088 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2089 temp &= ~PORT_PLL_INT_COEFF_MASK;
2090 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2091 temp |= hw_state->pll6;
2092 intel_de_write(i915, BXT_PORT_PLL(phy, ch, 6), temp);
2093
2094 /* Write calibration val */
2095 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 8),
2096 PORT_PLL_TARGET_CNT_MASK, hw_state->pll8);
2097
2098 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 9),
2099 PORT_PLL_LOCK_THRESHOLD_MASK, hw_state->pll9);
2100
2101 temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10));
2102 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2103 temp &= ~PORT_PLL_DCO_AMP_MASK;
2104 temp |= hw_state->pll10;
2105 intel_de_write(i915, BXT_PORT_PLL(phy, ch, 10), temp);
2106
2107 /* Recalibrate with new settings */
2108 temp = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch));
2109 temp |= PORT_PLL_RECALIBRATE;
2110 intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp);
2111 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2112 temp |= hw_state->ebb4;
2113 intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp);
2114
2115 /* Enable PLL */
2116 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE);
2117 intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port));
2118
2119 if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),
2120 200))
2121 drm_err(&i915->drm, "PLL %d not locked\n", port);
2122
2123 if (IS_GEMINILAKE(i915)) {
2124 temp = intel_de_read(i915, BXT_PORT_TX_DW5_LN(phy, ch, 0));
2125 temp |= DCC_DELAY_RANGE_2;
2126 intel_de_write(i915, BXT_PORT_TX_DW5_GRP(phy, ch), temp);
2127 }
2128
2129 /*
2130 * While we write to the group register to program all lanes at once we
2131 * can read only lane registers and we pick lanes 0/1 for that.
2132 */
2133 temp = intel_de_read(i915, BXT_PORT_PCS_DW12_LN01(phy, ch));
2134 temp &= ~LANE_STAGGER_MASK;
2135 temp &= ~LANESTAGGER_STRAP_OVRD;
2136 temp |= hw_state->pcsdw12;
2137 intel_de_write(i915, BXT_PORT_PCS_DW12_GRP(phy, ch), temp);
2138}
2139
2140static void bxt_ddi_pll_disable(struct drm_i915_private *i915,
2141 struct intel_shared_dpll *pll)
2142{
2143 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
2144
2145 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0);
2146 intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port));
2147
2148 if (IS_GEMINILAKE(i915)) {
2149 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port),
2150 PORT_PLL_POWER_ENABLE, 0);
2151
2152 if (wait_for_us(!(intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) &
2153 PORT_PLL_POWER_STATE), 200))
2154 drm_err(&i915->drm,
2155 "Power state not reset for PLL:%d\n", port);
2156 }
2157}
2158
2159static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915,
2160 struct intel_shared_dpll *pll,
2161 struct intel_dpll_hw_state *dpll_hw_state)
2162{
2163 struct intel_display *display = &i915->display;
2164 struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
2165 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
2166 intel_wakeref_t wakeref;
2167 enum dpio_phy phy;
2168 enum dpio_channel ch;
2169 u32 val;
2170 bool ret;
2171
2172 bxt_port_to_phy_channel(display, port, &phy, &ch);
2173
2174 wakeref = intel_display_power_get_if_enabled(i915,
2175 POWER_DOMAIN_DISPLAY_CORE);
2176 if (!wakeref)
2177 return false;
2178
2179 ret = false;
2180
2181 val = intel_de_read(i915, BXT_PORT_PLL_ENABLE(port));
2182 if (!(val & PORT_PLL_ENABLE))
2183 goto out;
2184
2185 hw_state->ebb0 = intel_de_read(i915, BXT_PORT_PLL_EBB_0(phy, ch));
2186 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
2187
2188 hw_state->ebb4 = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch));
2189 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
2190
2191 hw_state->pll0 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 0));
2192 hw_state->pll0 &= PORT_PLL_M2_INT_MASK;
2193
2194 hw_state->pll1 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 1));
2195 hw_state->pll1 &= PORT_PLL_N_MASK;
2196
2197 hw_state->pll2 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 2));
2198 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
2199
2200 hw_state->pll3 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 3));
2201 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
2202
2203 hw_state->pll6 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6));
2204 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
2205 PORT_PLL_INT_COEFF_MASK |
2206 PORT_PLL_GAIN_CTL_MASK;
2207
2208 hw_state->pll8 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 8));
2209 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
2210
2211 hw_state->pll9 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 9));
2212 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
2213
2214 hw_state->pll10 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10));
2215 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
2216 PORT_PLL_DCO_AMP_MASK;
2217
2218 /*
2219 * While we write to the group register to program all lanes at once we
2220 * can read only lane registers. We configure all lanes the same way, so
2221 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2222 */
2223 hw_state->pcsdw12 = intel_de_read(i915,
2224 BXT_PORT_PCS_DW12_LN01(phy, ch));
2225 if (intel_de_read(i915, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)
2226 drm_dbg(&i915->drm,
2227 "lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2228 hw_state->pcsdw12,
2229 intel_de_read(i915,
2230 BXT_PORT_PCS_DW12_LN23(phy, ch)));
2231 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
2232
2233 ret = true;
2234
2235out:
2236 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref);
2237
2238 return ret;
2239}
2240
2241/* pre-calculated values for DP linkrates */
2242static const struct dpll bxt_dp_clk_val[] = {
2243 /* m2 is .22 binary fixed point */
2244 { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
2245 { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },
2246 { .dot = 540000, .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },
2247 { .dot = 216000, .p1 = 3, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
2248 { .dot = 243000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6133333 /* 24.3 */ },
2249 { .dot = 324000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
2250 { .dot = 432000, .p1 = 3, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
2251};
2252
2253static int
2254bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
2255 struct dpll *clk_div)
2256{
2257 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2258
2259 /* Calculate HDMI div */
2260 /*
2261 * FIXME: tie the following calculation into
2262 * i9xx_crtc_compute_clock
2263 */
2264 if (!bxt_find_best_dpll(crtc_state, clk_div))
2265 return -EINVAL;
2266
2267 drm_WARN_ON(&i915->drm, clk_div->m1 != 2);
2268
2269 return 0;
2270}
2271
2272static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
2273 struct dpll *clk_div)
2274{
2275 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2276 int i;
2277
2278 *clk_div = bxt_dp_clk_val[0];
2279 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
2280 if (crtc_state->port_clock == bxt_dp_clk_val[i].dot) {
2281 *clk_div = bxt_dp_clk_val[i];
2282 break;
2283 }
2284 }
2285
2286 chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, clk_div);
2287
2288 drm_WARN_ON(&i915->drm, clk_div->vco == 0 ||
2289 clk_div->dot != crtc_state->port_clock);
2290}
2291
2292static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
2293 const struct dpll *clk_div)
2294{
2295 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2296 struct bxt_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.bxt;
2297 int clock = crtc_state->port_clock;
2298 int vco = clk_div->vco;
2299 u32 prop_coef, int_coef, gain_ctl, targ_cnt;
2300 u32 lanestagger;
2301
2302 if (vco >= 6200000 && vco <= 6700000) {
2303 prop_coef = 4;
2304 int_coef = 9;
2305 gain_ctl = 3;
2306 targ_cnt = 8;
2307 } else if ((vco > 5400000 && vco < 6200000) ||
2308 (vco >= 4800000 && vco < 5400000)) {
2309 prop_coef = 5;
2310 int_coef = 11;
2311 gain_ctl = 3;
2312 targ_cnt = 9;
2313 } else if (vco == 5400000) {
2314 prop_coef = 3;
2315 int_coef = 8;
2316 gain_ctl = 1;
2317 targ_cnt = 9;
2318 } else {
2319 drm_err(&i915->drm, "Invalid VCO\n");
2320 return -EINVAL;
2321 }
2322
2323 if (clock > 270000)
2324 lanestagger = 0x18;
2325 else if (clock > 135000)
2326 lanestagger = 0x0d;
2327 else if (clock > 67000)
2328 lanestagger = 0x07;
2329 else if (clock > 33000)
2330 lanestagger = 0x04;
2331 else
2332 lanestagger = 0x02;
2333
2334 hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2);
2335 hw_state->pll0 = PORT_PLL_M2_INT(clk_div->m2 >> 22);
2336 hw_state->pll1 = PORT_PLL_N(clk_div->n);
2337 hw_state->pll2 = PORT_PLL_M2_FRAC(clk_div->m2 & 0x3fffff);
2338
2339 if (clk_div->m2 & 0x3fffff)
2340 hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE;
2341
2342 hw_state->pll6 = PORT_PLL_PROP_COEFF(prop_coef) |
2343 PORT_PLL_INT_COEFF(int_coef) |
2344 PORT_PLL_GAIN_CTL(gain_ctl);
2345
2346 hw_state->pll8 = PORT_PLL_TARGET_CNT(targ_cnt);
2347
2348 hw_state->pll9 = PORT_PLL_LOCK_THRESHOLD(5);
2349
2350 hw_state->pll10 = PORT_PLL_DCO_AMP(15) |
2351 PORT_PLL_DCO_AMP_OVR_EN_H;
2352
2353 hw_state->ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
2354
2355 hw_state->pcsdw12 = LANESTAGGER_STRAP_OVRD | lanestagger;
2356
2357 return 0;
2358}
2359
2360static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
2361 const struct intel_shared_dpll *pll,
2362 const struct intel_dpll_hw_state *dpll_hw_state)
2363{
2364 const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
2365 struct dpll clock;
2366
2367 clock.m1 = 2;
2368 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, hw_state->pll0) << 22;
2369 if (hw_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
2370 clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK,
2371 hw_state->pll2);
2372 clock.n = REG_FIELD_GET(PORT_PLL_N_MASK, hw_state->pll1);
2373 clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, hw_state->ebb0);
2374 clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, hw_state->ebb0);
2375
2376 return chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, &clock);
2377}
2378
2379static int
2380bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
2381{
2382 struct dpll clk_div = {};
2383
2384 bxt_ddi_dp_pll_dividers(crtc_state, &clk_div);
2385
2386 return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
2387}
2388
2389static int
2390bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
2391{
2392 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2393 struct dpll clk_div = {};
2394 int ret;
2395
2396 bxt_ddi_hdmi_pll_dividers(crtc_state, &clk_div);
2397
2398 ret = bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
2399 if (ret)
2400 return ret;
2401
2402 crtc_state->port_clock = bxt_ddi_pll_get_freq(i915, NULL,
2403 &crtc_state->dpll_hw_state);
2404
2405 return 0;
2406}
2407
2408static int bxt_compute_dpll(struct intel_atomic_state *state,
2409 struct intel_crtc *crtc,
2410 struct intel_encoder *encoder)
2411{
2412 struct intel_crtc_state *crtc_state =
2413 intel_atomic_get_new_crtc_state(state, crtc);
2414
2415 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2416 return bxt_ddi_hdmi_set_dpll_hw_state(crtc_state);
2417 else if (intel_crtc_has_dp_encoder(crtc_state))
2418 return bxt_ddi_dp_set_dpll_hw_state(crtc_state);
2419 else
2420 return -EINVAL;
2421}
2422
2423static int bxt_get_dpll(struct intel_atomic_state *state,
2424 struct intel_crtc *crtc,
2425 struct intel_encoder *encoder)
2426{
2427 struct intel_crtc_state *crtc_state =
2428 intel_atomic_get_new_crtc_state(state, crtc);
2429 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2430 struct intel_shared_dpll *pll;
2431 enum intel_dpll_id id;
2432
2433 /* 1:1 mapping between ports and PLLs */
2434 id = (enum intel_dpll_id) encoder->port;
2435 pll = intel_get_shared_dpll_by_id(i915, id);
2436
2437 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] using pre-allocated %s\n",
2438 crtc->base.base.id, crtc->base.name, pll->info->name);
2439
2440 intel_reference_shared_dpll(state, crtc,
2441 pll, &crtc_state->dpll_hw_state);
2442
2443 crtc_state->shared_dpll = pll;
2444
2445 return 0;
2446}
2447
2448static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915)
2449{
2450 i915->display.dpll.ref_clks.ssc = 100000;
2451 i915->display.dpll.ref_clks.nssc = 100000;
2452 /* DSI non-SSC ref 19.2MHz */
2453}
2454
2455static void bxt_dump_hw_state(struct drm_printer *p,
2456 const struct intel_dpll_hw_state *dpll_hw_state)
2457{
2458 const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
2459
2460 drm_printf(p, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
2461 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
2462 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
2463 hw_state->ebb0, hw_state->ebb4,
2464 hw_state->pll0, hw_state->pll1, hw_state->pll2, hw_state->pll3,
2465 hw_state->pll6, hw_state->pll8, hw_state->pll9, hw_state->pll10,
2466 hw_state->pcsdw12);
2467}
2468
2469static bool bxt_compare_hw_state(const struct intel_dpll_hw_state *_a,
2470 const struct intel_dpll_hw_state *_b)
2471{
2472 const struct bxt_dpll_hw_state *a = &_a->bxt;
2473 const struct bxt_dpll_hw_state *b = &_b->bxt;
2474
2475 return a->ebb0 == b->ebb0 &&
2476 a->ebb4 == b->ebb4 &&
2477 a->pll0 == b->pll0 &&
2478 a->pll1 == b->pll1 &&
2479 a->pll2 == b->pll2 &&
2480 a->pll3 == b->pll3 &&
2481 a->pll6 == b->pll6 &&
2482 a->pll8 == b->pll8 &&
2483 a->pll10 == b->pll10 &&
2484 a->pcsdw12 == b->pcsdw12;
2485}
2486
2487static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
2488 .enable = bxt_ddi_pll_enable,
2489 .disable = bxt_ddi_pll_disable,
2490 .get_hw_state = bxt_ddi_pll_get_hw_state,
2491 .get_freq = bxt_ddi_pll_get_freq,
2492};
2493
2494static const struct dpll_info bxt_plls[] = {
2495 { .name = "PORT PLL A", .funcs = &bxt_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL0, },
2496 { .name = "PORT PLL B", .funcs = &bxt_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL1, },
2497 { .name = "PORT PLL C", .funcs = &bxt_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL2, },
2498 {}
2499};
2500
2501static const struct intel_dpll_mgr bxt_pll_mgr = {
2502 .dpll_info = bxt_plls,
2503 .compute_dplls = bxt_compute_dpll,
2504 .get_dplls = bxt_get_dpll,
2505 .put_dplls = intel_put_dpll,
2506 .update_ref_clks = bxt_update_dpll_ref_clks,
2507 .dump_hw_state = bxt_dump_hw_state,
2508 .compare_hw_state = bxt_compare_hw_state,
2509};
2510
2511static void icl_wrpll_get_multipliers(int bestdiv, int *pdiv,
2512 int *qdiv, int *kdiv)
2513{
2514 /* even dividers */
2515 if (bestdiv % 2 == 0) {
2516 if (bestdiv == 2) {
2517 *pdiv = 2;
2518 *qdiv = 1;
2519 *kdiv = 1;
2520 } else if (bestdiv % 4 == 0) {
2521 *pdiv = 2;
2522 *qdiv = bestdiv / 4;
2523 *kdiv = 2;
2524 } else if (bestdiv % 6 == 0) {
2525 *pdiv = 3;
2526 *qdiv = bestdiv / 6;
2527 *kdiv = 2;
2528 } else if (bestdiv % 5 == 0) {
2529 *pdiv = 5;
2530 *qdiv = bestdiv / 10;
2531 *kdiv = 2;
2532 } else if (bestdiv % 14 == 0) {
2533 *pdiv = 7;
2534 *qdiv = bestdiv / 14;
2535 *kdiv = 2;
2536 }
2537 } else {
2538 if (bestdiv == 3 || bestdiv == 5 || bestdiv == 7) {
2539 *pdiv = bestdiv;
2540 *qdiv = 1;
2541 *kdiv = 1;
2542 } else { /* 9, 15, 21 */
2543 *pdiv = bestdiv / 3;
2544 *qdiv = 1;
2545 *kdiv = 3;
2546 }
2547 }
2548}
2549
2550static void icl_wrpll_params_populate(struct skl_wrpll_params *params,
2551 u32 dco_freq, u32 ref_freq,
2552 int pdiv, int qdiv, int kdiv)
2553{
2554 u32 dco;
2555
2556 switch (kdiv) {
2557 case 1:
2558 params->kdiv = 1;
2559 break;
2560 case 2:
2561 params->kdiv = 2;
2562 break;
2563 case 3:
2564 params->kdiv = 4;
2565 break;
2566 default:
2567 WARN(1, "Incorrect KDiv\n");
2568 }
2569
2570 switch (pdiv) {
2571 case 2:
2572 params->pdiv = 1;
2573 break;
2574 case 3:
2575 params->pdiv = 2;
2576 break;
2577 case 5:
2578 params->pdiv = 4;
2579 break;
2580 case 7:
2581 params->pdiv = 8;
2582 break;
2583 default:
2584 WARN(1, "Incorrect PDiv\n");
2585 }
2586
2587 WARN_ON(kdiv != 2 && qdiv != 1);
2588
2589 params->qdiv_ratio = qdiv;
2590 params->qdiv_mode = (qdiv == 1) ? 0 : 1;
2591
2592 dco = div_u64((u64)dco_freq << 15, ref_freq);
2593
2594 params->dco_integer = dco >> 15;
2595 params->dco_fraction = dco & 0x7fff;
2596}
2597
2598/*
2599 * Display WA #22010492432: ehl, tgl, adl-s, adl-p
2600 * Program half of the nominal DCO divider fraction value.
2601 */
2602static bool
2603ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
2604{
2605 return ((IS_ELKHARTLAKE(i915) &&
2606 IS_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
2607 IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) &&
2608 i915->display.dpll.ref_clks.nssc == 38400;
2609}
2610
2611struct icl_combo_pll_params {
2612 int clock;
2613 struct skl_wrpll_params wrpll;
2614};
2615
2616/*
2617 * These values alrea already adjusted: they're the bits we write to the
2618 * registers, not the logical values.
2619 */
2620static const struct icl_combo_pll_params icl_dp_combo_pll_24MHz_values[] = {
2621 { 540000,
2622 { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [0]: 5.4 */
2623 .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2624 { 270000,
2625 { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [1]: 2.7 */
2626 .pdiv = 0x2 /* 3 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2627 { 162000,
2628 { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [2]: 1.62 */
2629 .pdiv = 0x4 /* 5 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2630 { 324000,
2631 { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [3]: 3.24 */
2632 .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2633 { 216000,
2634 { .dco_integer = 0x168, .dco_fraction = 0x0000, /* [4]: 2.16 */
2635 .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 1, .qdiv_ratio = 2, }, },
2636 { 432000,
2637 { .dco_integer = 0x168, .dco_fraction = 0x0000, /* [5]: 4.32 */
2638 .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2639 { 648000,
2640 { .dco_integer = 0x195, .dco_fraction = 0x0000, /* [6]: 6.48 */
2641 .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2642 { 810000,
2643 { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [7]: 8.1 */
2644 .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2645};
2646
2647
2648/* Also used for 38.4 MHz values. */
2649static const struct icl_combo_pll_params icl_dp_combo_pll_19_2MHz_values[] = {
2650 { 540000,
2651 { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [0]: 5.4 */
2652 .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2653 { 270000,
2654 { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [1]: 2.7 */
2655 .pdiv = 0x2 /* 3 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2656 { 162000,
2657 { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [2]: 1.62 */
2658 .pdiv = 0x4 /* 5 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2659 { 324000,
2660 { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [3]: 3.24 */
2661 .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2662 { 216000,
2663 { .dco_integer = 0x1C2, .dco_fraction = 0x0000, /* [4]: 2.16 */
2664 .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 1, .qdiv_ratio = 2, }, },
2665 { 432000,
2666 { .dco_integer = 0x1C2, .dco_fraction = 0x0000, /* [5]: 4.32 */
2667 .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2668 { 648000,
2669 { .dco_integer = 0x1FA, .dco_fraction = 0x2000, /* [6]: 6.48 */
2670 .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2671 { 810000,
2672 { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [7]: 8.1 */
2673 .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2674};
2675
2676static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = {
2677 .dco_integer = 0x151, .dco_fraction = 0x4000,
2678 .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0,
2679};
2680
2681static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values = {
2682 .dco_integer = 0x1A5, .dco_fraction = 0x7000,
2683 .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0,
2684};
2685
2686static const struct skl_wrpll_params tgl_tbt_pll_19_2MHz_values = {
2687 .dco_integer = 0x54, .dco_fraction = 0x3000,
2688 /* the following params are unused */
2689 .pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0,
2690};
2691
2692static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = {
2693 .dco_integer = 0x43, .dco_fraction = 0x4000,
2694 /* the following params are unused */
2695};
2696
2697static int icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
2698 struct skl_wrpll_params *pll_params)
2699{
2700 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2701 const struct icl_combo_pll_params *params =
2702 i915->display.dpll.ref_clks.nssc == 24000 ?
2703 icl_dp_combo_pll_24MHz_values :
2704 icl_dp_combo_pll_19_2MHz_values;
2705 int clock = crtc_state->port_clock;
2706 int i;
2707
2708 for (i = 0; i < ARRAY_SIZE(icl_dp_combo_pll_24MHz_values); i++) {
2709 if (clock == params[i].clock) {
2710 *pll_params = params[i].wrpll;
2711 return 0;
2712 }
2713 }
2714
2715 MISSING_CASE(clock);
2716 return -EINVAL;
2717}
2718
2719static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
2720 struct skl_wrpll_params *pll_params)
2721{
2722 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2723
2724 if (DISPLAY_VER(i915) >= 12) {
2725 switch (i915->display.dpll.ref_clks.nssc) {
2726 default:
2727 MISSING_CASE(i915->display.dpll.ref_clks.nssc);
2728 fallthrough;
2729 case 19200:
2730 case 38400:
2731 *pll_params = tgl_tbt_pll_19_2MHz_values;
2732 break;
2733 case 24000:
2734 *pll_params = tgl_tbt_pll_24MHz_values;
2735 break;
2736 }
2737 } else {
2738 switch (i915->display.dpll.ref_clks.nssc) {
2739 default:
2740 MISSING_CASE(i915->display.dpll.ref_clks.nssc);
2741 fallthrough;
2742 case 19200:
2743 case 38400:
2744 *pll_params = icl_tbt_pll_19_2MHz_values;
2745 break;
2746 case 24000:
2747 *pll_params = icl_tbt_pll_24MHz_values;
2748 break;
2749 }
2750 }
2751
2752 return 0;
2753}
2754
2755static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
2756 const struct intel_shared_dpll *pll,
2757 const struct intel_dpll_hw_state *dpll_hw_state)
2758{
2759 /*
2760 * The PLL outputs multiple frequencies at the same time, selection is
2761 * made at DDI clock mux level.
2762 */
2763 drm_WARN_ON(&i915->drm, 1);
2764
2765 return 0;
2766}
2767
2768static int icl_wrpll_ref_clock(struct drm_i915_private *i915)
2769{
2770 int ref_clock = i915->display.dpll.ref_clks.nssc;
2771
2772 /*
2773 * For ICL+, the spec states: if reference frequency is 38.4,
2774 * use 19.2 because the DPLL automatically divides that by 2.
2775 */
2776 if (ref_clock == 38400)
2777 ref_clock = 19200;
2778
2779 return ref_clock;
2780}
2781
2782static int
2783icl_calc_wrpll(struct intel_crtc_state *crtc_state,
2784 struct skl_wrpll_params *wrpll_params)
2785{
2786 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2787 int ref_clock = icl_wrpll_ref_clock(i915);
2788 u32 afe_clock = crtc_state->port_clock * 5;
2789 u32 dco_min = 7998000;
2790 u32 dco_max = 10000000;
2791 u32 dco_mid = (dco_min + dco_max) / 2;
2792 static const int dividers[] = { 2, 4, 6, 8, 10, 12, 14, 16,
2793 18, 20, 24, 28, 30, 32, 36, 40,
2794 42, 44, 48, 50, 52, 54, 56, 60,
2795 64, 66, 68, 70, 72, 76, 78, 80,
2796 84, 88, 90, 92, 96, 98, 100, 102,
2797 3, 5, 7, 9, 15, 21 };
2798 u32 dco, best_dco = 0, dco_centrality = 0;
2799 u32 best_dco_centrality = U32_MAX; /* Spec meaning of 999999 MHz */
2800 int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
2801
2802 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
2803 dco = afe_clock * dividers[d];
2804
2805 if (dco <= dco_max && dco >= dco_min) {
2806 dco_centrality = abs(dco - dco_mid);
2807
2808 if (dco_centrality < best_dco_centrality) {
2809 best_dco_centrality = dco_centrality;
2810 best_div = dividers[d];
2811 best_dco = dco;
2812 }
2813 }
2814 }
2815
2816 if (best_div == 0)
2817 return -EINVAL;
2818
2819 icl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
2820 icl_wrpll_params_populate(wrpll_params, best_dco, ref_clock,
2821 pdiv, qdiv, kdiv);
2822
2823 return 0;
2824}
2825
2826static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
2827 const struct intel_shared_dpll *pll,
2828 const struct intel_dpll_hw_state *dpll_hw_state)
2829{
2830 const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
2831 int ref_clock = icl_wrpll_ref_clock(i915);
2832 u32 dco_fraction;
2833 u32 p0, p1, p2, dco_freq;
2834
2835 p0 = hw_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
2836 p2 = hw_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
2837
2838 if (hw_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
2839 p1 = (hw_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
2840 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
2841 else
2842 p1 = 1;
2843
2844 switch (p0) {
2845 case DPLL_CFGCR1_PDIV_2:
2846 p0 = 2;
2847 break;
2848 case DPLL_CFGCR1_PDIV_3:
2849 p0 = 3;
2850 break;
2851 case DPLL_CFGCR1_PDIV_5:
2852 p0 = 5;
2853 break;
2854 case DPLL_CFGCR1_PDIV_7:
2855 p0 = 7;
2856 break;
2857 }
2858
2859 switch (p2) {
2860 case DPLL_CFGCR1_KDIV_1:
2861 p2 = 1;
2862 break;
2863 case DPLL_CFGCR1_KDIV_2:
2864 p2 = 2;
2865 break;
2866 case DPLL_CFGCR1_KDIV_3:
2867 p2 = 3;
2868 break;
2869 }
2870
2871 dco_freq = (hw_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
2872 ref_clock;
2873
2874 dco_fraction = (hw_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
2875 DPLL_CFGCR0_DCO_FRACTION_SHIFT;
2876
2877 if (ehl_combo_pll_div_frac_wa_needed(i915))
2878 dco_fraction *= 2;
2879
2880 dco_freq += (dco_fraction * ref_clock) / 0x8000;
2881
2882 if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0))
2883 return 0;
2884
2885 return dco_freq / (p0 * p1 * p2 * 5);
2886}
2887
2888static void icl_calc_dpll_state(struct drm_i915_private *i915,
2889 const struct skl_wrpll_params *pll_params,
2890 struct intel_dpll_hw_state *dpll_hw_state)
2891{
2892 struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
2893 u32 dco_fraction = pll_params->dco_fraction;
2894
2895 if (ehl_combo_pll_div_frac_wa_needed(i915))
2896 dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);
2897
2898 hw_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) |
2899 pll_params->dco_integer;
2900
2901 hw_state->cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params->qdiv_ratio) |
2902 DPLL_CFGCR1_QDIV_MODE(pll_params->qdiv_mode) |
2903 DPLL_CFGCR1_KDIV(pll_params->kdiv) |
2904 DPLL_CFGCR1_PDIV(pll_params->pdiv);
2905
2906 if (DISPLAY_VER(i915) >= 12)
2907 hw_state->cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;
2908 else
2909 hw_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
2910
2911 if (i915->display.vbt.override_afc_startup)
2912 hw_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->display.vbt.override_afc_startup_val);
2913}
2914
2915static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
2916 u32 *target_dco_khz,
2917 struct icl_dpll_hw_state *hw_state,
2918 bool is_dkl)
2919{
2920 static const u8 div1_vals[] = { 7, 5, 3, 2 };
2921 u32 dco_min_freq, dco_max_freq;
2922 unsigned int i;
2923 int div2;
2924
2925 dco_min_freq = is_dp ? 8100000 : use_ssc ? 8000000 : 7992000;
2926 dco_max_freq = is_dp ? 8100000 : 10000000;
2927
2928 for (i = 0; i < ARRAY_SIZE(div1_vals); i++) {
2929 int div1 = div1_vals[i];
2930
2931 for (div2 = 10; div2 > 0; div2--) {
2932 int dco = div1 * div2 * clock_khz * 5;
2933 int a_divratio, tlinedrv, inputsel;
2934 u32 hsdiv;
2935
2936 if (dco < dco_min_freq || dco > dco_max_freq)
2937 continue;
2938
2939 if (div2 >= 2) {
2940 /*
2941 * Note: a_divratio not matching TGL BSpec
2942 * algorithm but matching hardcoded values and
2943 * working on HW for DP alt-mode at least
2944 */
2945 a_divratio = is_dp ? 10 : 5;
2946 tlinedrv = is_dkl ? 1 : 2;
2947 } else {
2948 a_divratio = 5;
2949 tlinedrv = 0;
2950 }
2951 inputsel = is_dp ? 0 : 1;
2952
2953 switch (div1) {
2954 default:
2955 MISSING_CASE(div1);
2956 fallthrough;
2957 case 2:
2958 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2;
2959 break;
2960 case 3:
2961 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3;
2962 break;
2963 case 5:
2964 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5;
2965 break;
2966 case 7:
2967 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7;
2968 break;
2969 }
2970
2971 *target_dco_khz = dco;
2972
2973 hw_state->mg_refclkin_ctl = MG_REFCLKIN_CTL_OD_2_MUX(1);
2974
2975 hw_state->mg_clktop2_coreclkctl1 =
2976 MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(a_divratio);
2977
2978 hw_state->mg_clktop2_hsclkctl =
2979 MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(tlinedrv) |
2980 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(inputsel) |
2981 hsdiv |
2982 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(div2);
2983
2984 return 0;
2985 }
2986 }
2987
2988 return -EINVAL;
2989}
2990
2991/*
2992 * The specification for this function uses real numbers, so the math had to be
2993 * adapted to integer-only calculation, that's why it looks so different.
2994 */
2995static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
2996 struct intel_dpll_hw_state *dpll_hw_state)
2997{
2998 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2999 struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
3000 int refclk_khz = i915->display.dpll.ref_clks.nssc;
3001 int clock = crtc_state->port_clock;
3002 u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
3003 u32 iref_ndiv, iref_trim, iref_pulse_w;
3004 u32 prop_coeff, int_coeff;
3005 u32 tdc_targetcnt, feedfwgain;
3006 u64 ssc_stepsize, ssc_steplen, ssc_steplog;
3007 u64 tmp;
3008 bool use_ssc = false;
3009 bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
3010 bool is_dkl = DISPLAY_VER(i915) >= 12;
3011 int ret;
3012
3013 ret = icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
3014 hw_state, is_dkl);
3015 if (ret)
3016 return ret;
3017
3018 m1div = 2;
3019 m2div_int = dco_khz / (refclk_khz * m1div);
3020 if (m2div_int > 255) {
3021 if (!is_dkl) {
3022 m1div = 4;
3023 m2div_int = dco_khz / (refclk_khz * m1div);
3024 }
3025
3026 if (m2div_int > 255)
3027 return -EINVAL;
3028 }
3029 m2div_rem = dco_khz % (refclk_khz * m1div);
3030
3031 tmp = (u64)m2div_rem * (1 << 22);
3032 do_div(tmp, refclk_khz * m1div);
3033 m2div_frac = tmp;
3034
3035 switch (refclk_khz) {
3036 case 19200:
3037 iref_ndiv = 1;
3038 iref_trim = 28;
3039 iref_pulse_w = 1;
3040 break;
3041 case 24000:
3042 iref_ndiv = 1;
3043 iref_trim = 25;
3044 iref_pulse_w = 2;
3045 break;
3046 case 38400:
3047 iref_ndiv = 2;
3048 iref_trim = 28;
3049 iref_pulse_w = 1;
3050 break;
3051 default:
3052 MISSING_CASE(refclk_khz);
3053 return -EINVAL;
3054 }
3055
3056 /*
3057 * tdc_res = 0.000003
3058 * tdc_targetcnt = int(2 / (tdc_res * 8 * 50 * 1.1) / refclk_mhz + 0.5)
3059 *
3060 * The multiplication by 1000 is due to refclk MHz to KHz conversion. It
3061 * was supposed to be a division, but we rearranged the operations of
3062 * the formula to avoid early divisions so we don't multiply the
3063 * rounding errors.
3064 *
3065 * 0.000003 * 8 * 50 * 1.1 = 0.00132, also known as 132 / 100000, which
3066 * we also rearrange to work with integers.
3067 *
3068 * The 0.5 transformed to 5 results in a multiplication by 10 and the
3069 * last division by 10.
3070 */
3071 tdc_targetcnt = (2 * 1000 * 100000 * 10 / (132 * refclk_khz) + 5) / 10;
3072
3073 /*
3074 * Here we divide dco_khz by 10 in order to allow the dividend to fit in
3075 * 32 bits. That's not a problem since we round the division down
3076 * anyway.
3077 */
3078 feedfwgain = (use_ssc || m2div_rem > 0) ?
3079 m1div * 1000000 * 100 / (dco_khz * 3 / 10) : 0;
3080
3081 if (dco_khz >= 9000000) {
3082 prop_coeff = 5;
3083 int_coeff = 10;
3084 } else {
3085 prop_coeff = 4;
3086 int_coeff = 8;
3087 }
3088
3089 if (use_ssc) {
3090 tmp = mul_u32_u32(dco_khz, 47 * 32);
3091 do_div(tmp, refclk_khz * m1div * 10000);
3092 ssc_stepsize = tmp;
3093
3094 tmp = mul_u32_u32(dco_khz, 1000);
3095 ssc_steplen = DIV_ROUND_UP_ULL(tmp, 32 * 2 * 32);
3096 } else {
3097 ssc_stepsize = 0;
3098 ssc_steplen = 0;
3099 }
3100 ssc_steplog = 4;
3101
3102 /* write pll_state calculations */
3103 if (is_dkl) {
3104 hw_state->mg_pll_div0 = DKL_PLL_DIV0_INTEG_COEFF(int_coeff) |
3105 DKL_PLL_DIV0_PROP_COEFF(prop_coeff) |
3106 DKL_PLL_DIV0_FBPREDIV(m1div) |
3107 DKL_PLL_DIV0_FBDIV_INT(m2div_int);
3108 if (i915->display.vbt.override_afc_startup) {
3109 u8 val = i915->display.vbt.override_afc_startup_val;
3110
3111 hw_state->mg_pll_div0 |= DKL_PLL_DIV0_AFC_STARTUP(val);
3112 }
3113
3114 hw_state->mg_pll_div1 = DKL_PLL_DIV1_IREF_TRIM(iref_trim) |
3115 DKL_PLL_DIV1_TDC_TARGET_CNT(tdc_targetcnt);
3116
3117 hw_state->mg_pll_ssc = DKL_PLL_SSC_IREF_NDIV_RATIO(iref_ndiv) |
3118 DKL_PLL_SSC_STEP_LEN(ssc_steplen) |
3119 DKL_PLL_SSC_STEP_NUM(ssc_steplog) |
3120 (use_ssc ? DKL_PLL_SSC_EN : 0);
3121
3122 hw_state->mg_pll_bias = (m2div_frac ? DKL_PLL_BIAS_FRAC_EN_H : 0) |
3123 DKL_PLL_BIAS_FBDIV_FRAC(m2div_frac);
3124
3125 hw_state->mg_pll_tdc_coldst_bias =
3126 DKL_PLL_TDC_SSC_STEP_SIZE(ssc_stepsize) |
3127 DKL_PLL_TDC_FEED_FWD_GAIN(feedfwgain);
3128
3129 } else {
3130 hw_state->mg_pll_div0 =
3131 (m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H : 0) |
3132 MG_PLL_DIV0_FBDIV_FRAC(m2div_frac) |
3133 MG_PLL_DIV0_FBDIV_INT(m2div_int);
3134
3135 hw_state->mg_pll_div1 =
3136 MG_PLL_DIV1_IREF_NDIVRATIO(iref_ndiv) |
3137 MG_PLL_DIV1_DITHER_DIV_2 |
3138 MG_PLL_DIV1_NDIVRATIO(1) |
3139 MG_PLL_DIV1_FBPREDIV(m1div);
3140
3141 hw_state->mg_pll_lf =
3142 MG_PLL_LF_TDCTARGETCNT(tdc_targetcnt) |
3143 MG_PLL_LF_AFCCNTSEL_512 |
3144 MG_PLL_LF_GAINCTRL(1) |
3145 MG_PLL_LF_INT_COEFF(int_coeff) |
3146 MG_PLL_LF_PROP_COEFF(prop_coeff);
3147
3148 hw_state->mg_pll_frac_lock =
3149 MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 |
3150 MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 |
3151 MG_PLL_FRAC_LOCK_LOCKTHRESH(10) |
3152 MG_PLL_FRAC_LOCK_DCODITHEREN |
3153 MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(feedfwgain);
3154 if (use_ssc || m2div_rem > 0)
3155 hw_state->mg_pll_frac_lock |=
3156 MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN;
3157
3158 hw_state->mg_pll_ssc =
3159 (use_ssc ? MG_PLL_SSC_EN : 0) |
3160 MG_PLL_SSC_TYPE(2) |
3161 MG_PLL_SSC_STEPLENGTH(ssc_steplen) |
3162 MG_PLL_SSC_STEPNUM(ssc_steplog) |
3163 MG_PLL_SSC_FLLEN |
3164 MG_PLL_SSC_STEPSIZE(ssc_stepsize);
3165
3166 hw_state->mg_pll_tdc_coldst_bias =
3167 MG_PLL_TDC_COLDST_COLDSTART |
3168 MG_PLL_TDC_COLDST_IREFINT_EN |
3169 MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(iref_pulse_w) |
3170 MG_PLL_TDC_TDCOVCCORR_EN |
3171 MG_PLL_TDC_TDCSEL(3);
3172
3173 hw_state->mg_pll_bias =
3174 MG_PLL_BIAS_BIAS_GB_SEL(3) |
3175 MG_PLL_BIAS_INIT_DCOAMP(0x3F) |
3176 MG_PLL_BIAS_BIAS_BONUS(10) |
3177 MG_PLL_BIAS_BIASCAL_EN |
3178 MG_PLL_BIAS_CTRIM(12) |
3179 MG_PLL_BIAS_VREF_RDAC(4) |
3180 MG_PLL_BIAS_IREFTRIM(iref_trim);
3181
3182 if (refclk_khz == 38400) {
3183 hw_state->mg_pll_tdc_coldst_bias_mask =
3184 MG_PLL_TDC_COLDST_COLDSTART;
3185 hw_state->mg_pll_bias_mask = 0;
3186 } else {
3187 hw_state->mg_pll_tdc_coldst_bias_mask = -1U;
3188 hw_state->mg_pll_bias_mask = -1U;
3189 }
3190
3191 hw_state->mg_pll_tdc_coldst_bias &=
3192 hw_state->mg_pll_tdc_coldst_bias_mask;
3193 hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask;
3194 }
3195
3196 return 0;
3197}
3198
3199static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *i915,
3200 const struct intel_shared_dpll *pll,
3201 const struct intel_dpll_hw_state *dpll_hw_state)
3202{
3203 const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
3204 u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
3205 u64 tmp;
3206
3207 ref_clock = i915->display.dpll.ref_clks.nssc;
3208
3209 if (DISPLAY_VER(i915) >= 12) {
3210 m1 = hw_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
3211 m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT;
3212 m2_int = hw_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK;
3213
3214 if (hw_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) {
3215 m2_frac = hw_state->mg_pll_bias &
3216 DKL_PLL_BIAS_FBDIV_FRAC_MASK;
3217 m2_frac = m2_frac >> DKL_PLL_BIAS_FBDIV_SHIFT;
3218 } else {
3219 m2_frac = 0;
3220 }
3221 } else {
3222 m1 = hw_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
3223 m2_int = hw_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
3224
3225 if (hw_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) {
3226 m2_frac = hw_state->mg_pll_div0 &
3227 MG_PLL_DIV0_FBDIV_FRAC_MASK;
3228 m2_frac = m2_frac >> MG_PLL_DIV0_FBDIV_FRAC_SHIFT;
3229 } else {
3230 m2_frac = 0;
3231 }
3232 }
3233
3234 switch (hw_state->mg_clktop2_hsclkctl &
3235 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
3236 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
3237 div1 = 2;
3238 break;
3239 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
3240 div1 = 3;
3241 break;
3242 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
3243 div1 = 5;
3244 break;
3245 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
3246 div1 = 7;
3247 break;
3248 default:
3249 MISSING_CASE(hw_state->mg_clktop2_hsclkctl);
3250 return 0;
3251 }
3252
3253 div2 = (hw_state->mg_clktop2_hsclkctl &
3254 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
3255 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
3256
3257 /* div2 value of 0 is same as 1 means no div */
3258 if (div2 == 0)
3259 div2 = 1;
3260
3261 /*
3262 * Adjust the original formula to delay the division by 2^22 in order to
3263 * minimize possible rounding errors.
3264 */
3265 tmp = (u64)m1 * m2_int * ref_clock +
3266 (((u64)m1 * m2_frac * ref_clock) >> 22);
3267 tmp = div_u64(tmp, 5 * div1 * div2);
3268
3269 return tmp;
3270}
3271
3272/**
3273 * icl_set_active_port_dpll - select the active port DPLL for a given CRTC
3274 * @crtc_state: state for the CRTC to select the DPLL for
3275 * @port_dpll_id: the active @port_dpll_id to select
3276 *
3277 * Select the given @port_dpll_id instance from the DPLLs reserved for the
3278 * CRTC.
3279 */
3280void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
3281 enum icl_port_dpll_id port_dpll_id)
3282{
3283 struct icl_port_dpll *port_dpll =
3284 &crtc_state->icl_port_dplls[port_dpll_id];
3285
3286 crtc_state->shared_dpll = port_dpll->pll;
3287 crtc_state->dpll_hw_state = port_dpll->hw_state;
3288}
3289
3290static void icl_update_active_dpll(struct intel_atomic_state *state,
3291 struct intel_crtc *crtc,
3292 struct intel_encoder *encoder)
3293{
3294 struct intel_crtc_state *crtc_state =
3295 intel_atomic_get_new_crtc_state(state, crtc);
3296 struct intel_digital_port *primary_port;
3297 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
3298
3299 primary_port = encoder->type == INTEL_OUTPUT_DP_MST ?
3300 enc_to_mst(encoder)->primary :
3301 enc_to_dig_port(encoder);
3302
3303 if (primary_port &&
3304 (intel_tc_port_in_dp_alt_mode(primary_port) ||
3305 intel_tc_port_in_legacy_mode(primary_port)))
3306 port_dpll_id = ICL_PORT_DPLL_MG_PHY;
3307
3308 icl_set_active_port_dpll(crtc_state, port_dpll_id);
3309}
3310
3311static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
3312 struct intel_crtc *crtc)
3313{
3314 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3315 struct intel_crtc_state *crtc_state =
3316 intel_atomic_get_new_crtc_state(state, crtc);
3317 struct icl_port_dpll *port_dpll =
3318 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
3319 struct skl_wrpll_params pll_params = {};
3320 int ret;
3321
3322 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
3323 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
3324 ret = icl_calc_wrpll(crtc_state, &pll_params);
3325 else
3326 ret = icl_calc_dp_combo_pll(crtc_state, &pll_params);
3327
3328 if (ret)
3329 return ret;
3330
3331 icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state);
3332
3333 /* this is mainly for the fastset check */
3334 icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
3335
3336 crtc_state->port_clock = icl_ddi_combo_pll_get_freq(i915, NULL,
3337 &port_dpll->hw_state);
3338
3339 return 0;
3340}
3341
3342static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
3343 struct intel_crtc *crtc,
3344 struct intel_encoder *encoder)
3345{
3346 struct intel_display *display = to_intel_display(crtc);
3347 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3348 struct intel_crtc_state *crtc_state =
3349 intel_atomic_get_new_crtc_state(state, crtc);
3350 struct icl_port_dpll *port_dpll =
3351 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
3352 enum port port = encoder->port;
3353 unsigned long dpll_mask;
3354
3355 if (IS_ALDERLAKE_S(i915)) {
3356 dpll_mask =
3357 BIT(DPLL_ID_DG1_DPLL3) |
3358 BIT(DPLL_ID_DG1_DPLL2) |
3359 BIT(DPLL_ID_ICL_DPLL1) |
3360 BIT(DPLL_ID_ICL_DPLL0);
3361 } else if (IS_DG1(i915)) {
3362 if (port == PORT_D || port == PORT_E) {
3363 dpll_mask =
3364 BIT(DPLL_ID_DG1_DPLL2) |
3365 BIT(DPLL_ID_DG1_DPLL3);
3366 } else {
3367 dpll_mask =
3368 BIT(DPLL_ID_DG1_DPLL0) |
3369 BIT(DPLL_ID_DG1_DPLL1);
3370 }
3371 } else if (IS_ROCKETLAKE(i915)) {
3372 dpll_mask =
3373 BIT(DPLL_ID_EHL_DPLL4) |
3374 BIT(DPLL_ID_ICL_DPLL1) |
3375 BIT(DPLL_ID_ICL_DPLL0);
3376 } else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
3377 port != PORT_A) {
3378 dpll_mask =
3379 BIT(DPLL_ID_EHL_DPLL4) |
3380 BIT(DPLL_ID_ICL_DPLL1) |
3381 BIT(DPLL_ID_ICL_DPLL0);
3382 } else {
3383 dpll_mask = BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0);
3384 }
3385
3386 /* Eliminate DPLLs from consideration if reserved by HTI */
3387 dpll_mask &= ~intel_hti_dpll_mask(display);
3388
3389 port_dpll->pll = intel_find_shared_dpll(state, crtc,
3390 &port_dpll->hw_state,
3391 dpll_mask);
3392 if (!port_dpll->pll)
3393 return -EINVAL;
3394
3395 intel_reference_shared_dpll(state, crtc,
3396 port_dpll->pll, &port_dpll->hw_state);
3397
3398 icl_update_active_dpll(state, crtc, encoder);
3399
3400 return 0;
3401}
3402
3403static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
3404 struct intel_crtc *crtc)
3405{
3406 struct drm_i915_private *i915 = to_i915(state->base.dev);
3407 struct intel_crtc_state *crtc_state =
3408 intel_atomic_get_new_crtc_state(state, crtc);
3409 const struct intel_crtc_state *old_crtc_state =
3410 intel_atomic_get_old_crtc_state(state, crtc);
3411 struct icl_port_dpll *port_dpll =
3412 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
3413 struct skl_wrpll_params pll_params = {};
3414 int ret;
3415
3416 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
3417 ret = icl_calc_tbt_pll(crtc_state, &pll_params);
3418 if (ret)
3419 return ret;
3420
3421 icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state);
3422
3423 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
3424 ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
3425 if (ret)
3426 return ret;
3427
3428 /* this is mainly for the fastset check */
3429 if (old_crtc_state->shared_dpll &&
3430 old_crtc_state->shared_dpll->info->id == DPLL_ID_ICL_TBTPLL)
3431 icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
3432 else
3433 icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
3434
3435 crtc_state->port_clock = icl_ddi_mg_pll_get_freq(i915, NULL,
3436 &port_dpll->hw_state);
3437
3438 return 0;
3439}
3440
3441static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
3442 struct intel_crtc *crtc,
3443 struct intel_encoder *encoder)
3444{
3445 struct intel_crtc_state *crtc_state =
3446 intel_atomic_get_new_crtc_state(state, crtc);
3447 struct icl_port_dpll *port_dpll =
3448 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
3449 enum intel_dpll_id dpll_id;
3450 int ret;
3451
3452 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
3453 port_dpll->pll = intel_find_shared_dpll(state, crtc,
3454 &port_dpll->hw_state,
3455 BIT(DPLL_ID_ICL_TBTPLL));
3456 if (!port_dpll->pll)
3457 return -EINVAL;
3458 intel_reference_shared_dpll(state, crtc,
3459 port_dpll->pll, &port_dpll->hw_state);
3460
3461
3462 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
3463 dpll_id = icl_tc_port_to_pll_id(intel_encoder_to_tc(encoder));
3464 port_dpll->pll = intel_find_shared_dpll(state, crtc,
3465 &port_dpll->hw_state,
3466 BIT(dpll_id));
3467 if (!port_dpll->pll) {
3468 ret = -EINVAL;
3469 goto err_unreference_tbt_pll;
3470 }
3471 intel_reference_shared_dpll(state, crtc,
3472 port_dpll->pll, &port_dpll->hw_state);
3473
3474 icl_update_active_dpll(state, crtc, encoder);
3475
3476 return 0;
3477
3478err_unreference_tbt_pll:
3479 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
3480 intel_unreference_shared_dpll(state, crtc, port_dpll->pll);
3481
3482 return ret;
3483}
3484
3485static int icl_compute_dplls(struct intel_atomic_state *state,
3486 struct intel_crtc *crtc,
3487 struct intel_encoder *encoder)
3488{
3489 if (intel_encoder_is_combo(encoder))
3490 return icl_compute_combo_phy_dpll(state, crtc);
3491 else if (intel_encoder_is_tc(encoder))
3492 return icl_compute_tc_phy_dplls(state, crtc);
3493
3494 MISSING_CASE(encoder->port);
3495
3496 return 0;
3497}
3498
3499static int icl_get_dplls(struct intel_atomic_state *state,
3500 struct intel_crtc *crtc,
3501 struct intel_encoder *encoder)
3502{
3503 if (intel_encoder_is_combo(encoder))
3504 return icl_get_combo_phy_dpll(state, crtc, encoder);
3505 else if (intel_encoder_is_tc(encoder))
3506 return icl_get_tc_phy_dplls(state, crtc, encoder);
3507
3508 MISSING_CASE(encoder->port);
3509
3510 return -EINVAL;
3511}
3512
3513static void icl_put_dplls(struct intel_atomic_state *state,
3514 struct intel_crtc *crtc)
3515{
3516 const struct intel_crtc_state *old_crtc_state =
3517 intel_atomic_get_old_crtc_state(state, crtc);
3518 struct intel_crtc_state *new_crtc_state =
3519 intel_atomic_get_new_crtc_state(state, crtc);
3520 enum icl_port_dpll_id id;
3521
3522 new_crtc_state->shared_dpll = NULL;
3523
3524 for (id = ICL_PORT_DPLL_DEFAULT; id < ICL_PORT_DPLL_COUNT; id++) {
3525 const struct icl_port_dpll *old_port_dpll =
3526 &old_crtc_state->icl_port_dplls[id];
3527 struct icl_port_dpll *new_port_dpll =
3528 &new_crtc_state->icl_port_dplls[id];
3529
3530 new_port_dpll->pll = NULL;
3531
3532 if (!old_port_dpll->pll)
3533 continue;
3534
3535 intel_unreference_shared_dpll(state, crtc, old_port_dpll->pll);
3536 }
3537}
3538
3539static bool mg_pll_get_hw_state(struct drm_i915_private *i915,
3540 struct intel_shared_dpll *pll,
3541 struct intel_dpll_hw_state *dpll_hw_state)
3542{
3543 struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
3544 const enum intel_dpll_id id = pll->info->id;
3545 enum tc_port tc_port = icl_pll_id_to_tc_port(id);
3546 intel_wakeref_t wakeref;
3547 bool ret = false;
3548 u32 val;
3549
3550 i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll);
3551
3552 wakeref = intel_display_power_get_if_enabled(i915,
3553 POWER_DOMAIN_DISPLAY_CORE);
3554 if (!wakeref)
3555 return false;
3556
3557 val = intel_de_read(i915, enable_reg);
3558 if (!(val & PLL_ENABLE))
3559 goto out;
3560
3561 hw_state->mg_refclkin_ctl = intel_de_read(i915,
3562 MG_REFCLKIN_CTL(tc_port));
3563 hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
3564
3565 hw_state->mg_clktop2_coreclkctl1 =
3566 intel_de_read(i915, MG_CLKTOP2_CORECLKCTL1(tc_port));
3567 hw_state->mg_clktop2_coreclkctl1 &=
3568 MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
3569
3570 hw_state->mg_clktop2_hsclkctl =
3571 intel_de_read(i915, MG_CLKTOP2_HSCLKCTL(tc_port));
3572 hw_state->mg_clktop2_hsclkctl &=
3573 MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
3574 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
3575 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
3576 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
3577
3578 hw_state->mg_pll_div0 = intel_de_read(i915, MG_PLL_DIV0(tc_port));
3579 hw_state->mg_pll_div1 = intel_de_read(i915, MG_PLL_DIV1(tc_port));
3580 hw_state->mg_pll_lf = intel_de_read(i915, MG_PLL_LF(tc_port));
3581 hw_state->mg_pll_frac_lock = intel_de_read(i915,
3582 MG_PLL_FRAC_LOCK(tc_port));
3583 hw_state->mg_pll_ssc = intel_de_read(i915, MG_PLL_SSC(tc_port));
3584
3585 hw_state->mg_pll_bias = intel_de_read(i915, MG_PLL_BIAS(tc_port));
3586 hw_state->mg_pll_tdc_coldst_bias =
3587 intel_de_read(i915, MG_PLL_TDC_COLDST_BIAS(tc_port));
3588
3589 if (i915->display.dpll.ref_clks.nssc == 38400) {
3590 hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
3591 hw_state->mg_pll_bias_mask = 0;
3592 } else {
3593 hw_state->mg_pll_tdc_coldst_bias_mask = -1U;
3594 hw_state->mg_pll_bias_mask = -1U;
3595 }
3596
3597 hw_state->mg_pll_tdc_coldst_bias &= hw_state->mg_pll_tdc_coldst_bias_mask;
3598 hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask;
3599
3600 ret = true;
3601out:
3602 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref);
3603 return ret;
3604}
3605
3606static bool dkl_pll_get_hw_state(struct drm_i915_private *i915,
3607 struct intel_shared_dpll *pll,
3608 struct intel_dpll_hw_state *dpll_hw_state)
3609{
3610 struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
3611 const enum intel_dpll_id id = pll->info->id;
3612 enum tc_port tc_port = icl_pll_id_to_tc_port(id);
3613 intel_wakeref_t wakeref;
3614 bool ret = false;
3615 u32 val;
3616
3617 wakeref = intel_display_power_get_if_enabled(i915,
3618 POWER_DOMAIN_DISPLAY_CORE);
3619 if (!wakeref)
3620 return false;
3621
3622 val = intel_de_read(i915, intel_tc_pll_enable_reg(i915, pll));
3623 if (!(val & PLL_ENABLE))
3624 goto out;
3625
3626 /*
3627 * All registers read here have the same HIP_INDEX_REG even though
3628 * they are on different building blocks
3629 */
3630 hw_state->mg_refclkin_ctl = intel_dkl_phy_read(i915,
3631 DKL_REFCLKIN_CTL(tc_port));
3632 hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
3633
3634 hw_state->mg_clktop2_hsclkctl =
3635 intel_dkl_phy_read(i915, DKL_CLKTOP2_HSCLKCTL(tc_port));
3636 hw_state->mg_clktop2_hsclkctl &=
3637 MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
3638 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
3639 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
3640 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
3641
3642 hw_state->mg_clktop2_coreclkctl1 =
3643 intel_dkl_phy_read(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port));
3644 hw_state->mg_clktop2_coreclkctl1 &=
3645 MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
3646
3647 hw_state->mg_pll_div0 = intel_dkl_phy_read(i915, DKL_PLL_DIV0(tc_port));
3648 val = DKL_PLL_DIV0_MASK;
3649 if (i915->display.vbt.override_afc_startup)
3650 val |= DKL_PLL_DIV0_AFC_STARTUP_MASK;
3651 hw_state->mg_pll_div0 &= val;
3652
3653 hw_state->mg_pll_div1 = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port));
3654 hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK |
3655 DKL_PLL_DIV1_TDC_TARGET_CNT_MASK);
3656
3657 hw_state->mg_pll_ssc = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port));
3658 hw_state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
3659 DKL_PLL_SSC_STEP_LEN_MASK |
3660 DKL_PLL_SSC_STEP_NUM_MASK |
3661 DKL_PLL_SSC_EN);
3662
3663 hw_state->mg_pll_bias = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port));
3664 hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H |
3665 DKL_PLL_BIAS_FBDIV_FRAC_MASK);
3666
3667 hw_state->mg_pll_tdc_coldst_bias =
3668 intel_dkl_phy_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port));
3669 hw_state->mg_pll_tdc_coldst_bias &= (DKL_PLL_TDC_SSC_STEP_SIZE_MASK |
3670 DKL_PLL_TDC_FEED_FWD_GAIN_MASK);
3671
3672 ret = true;
3673out:
3674 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref);
3675 return ret;
3676}
3677
3678static bool icl_pll_get_hw_state(struct drm_i915_private *i915,
3679 struct intel_shared_dpll *pll,
3680 struct intel_dpll_hw_state *dpll_hw_state,
3681 i915_reg_t enable_reg)
3682{
3683 struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
3684 const enum intel_dpll_id id = pll->info->id;
3685 intel_wakeref_t wakeref;
3686 bool ret = false;
3687 u32 val;
3688
3689 wakeref = intel_display_power_get_if_enabled(i915,
3690 POWER_DOMAIN_DISPLAY_CORE);
3691 if (!wakeref)
3692 return false;
3693
3694 val = intel_de_read(i915, enable_reg);
3695 if (!(val & PLL_ENABLE))
3696 goto out;
3697
3698 if (IS_ALDERLAKE_S(i915)) {
3699 hw_state->cfgcr0 = intel_de_read(i915, ADLS_DPLL_CFGCR0(id));
3700 hw_state->cfgcr1 = intel_de_read(i915, ADLS_DPLL_CFGCR1(id));
3701 } else if (IS_DG1(i915)) {
3702 hw_state->cfgcr0 = intel_de_read(i915, DG1_DPLL_CFGCR0(id));
3703 hw_state->cfgcr1 = intel_de_read(i915, DG1_DPLL_CFGCR1(id));
3704 } else if (IS_ROCKETLAKE(i915)) {
3705 hw_state->cfgcr0 = intel_de_read(i915,
3706 RKL_DPLL_CFGCR0(id));
3707 hw_state->cfgcr1 = intel_de_read(i915,
3708 RKL_DPLL_CFGCR1(id));
3709 } else if (DISPLAY_VER(i915) >= 12) {
3710 hw_state->cfgcr0 = intel_de_read(i915,
3711 TGL_DPLL_CFGCR0(id));
3712 hw_state->cfgcr1 = intel_de_read(i915,
3713 TGL_DPLL_CFGCR1(id));
3714 if (i915->display.vbt.override_afc_startup) {
3715 hw_state->div0 = intel_de_read(i915, TGL_DPLL0_DIV0(id));
3716 hw_state->div0 &= TGL_DPLL0_DIV0_AFC_STARTUP_MASK;
3717 }
3718 } else {
3719 if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
3720 id == DPLL_ID_EHL_DPLL4) {
3721 hw_state->cfgcr0 = intel_de_read(i915,
3722 ICL_DPLL_CFGCR0(4));
3723 hw_state->cfgcr1 = intel_de_read(i915,
3724 ICL_DPLL_CFGCR1(4));
3725 } else {
3726 hw_state->cfgcr0 = intel_de_read(i915,
3727 ICL_DPLL_CFGCR0(id));
3728 hw_state->cfgcr1 = intel_de_read(i915,
3729 ICL_DPLL_CFGCR1(id));
3730 }
3731 }
3732
3733 ret = true;
3734out:
3735 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref);
3736 return ret;
3737}
3738
3739static bool combo_pll_get_hw_state(struct drm_i915_private *i915,
3740 struct intel_shared_dpll *pll,
3741 struct intel_dpll_hw_state *dpll_hw_state)
3742{
3743 i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll);
3744
3745 return icl_pll_get_hw_state(i915, pll, dpll_hw_state, enable_reg);
3746}
3747
3748static bool tbt_pll_get_hw_state(struct drm_i915_private *i915,
3749 struct intel_shared_dpll *pll,
3750 struct intel_dpll_hw_state *dpll_hw_state)
3751{
3752 return icl_pll_get_hw_state(i915, pll, dpll_hw_state, TBT_PLL_ENABLE);
3753}
3754
3755static void icl_dpll_write(struct drm_i915_private *i915,
3756 struct intel_shared_dpll *pll,
3757 const struct icl_dpll_hw_state *hw_state)
3758{
3759 const enum intel_dpll_id id = pll->info->id;
3760 i915_reg_t cfgcr0_reg, cfgcr1_reg, div0_reg = INVALID_MMIO_REG;
3761
3762 if (IS_ALDERLAKE_S(i915)) {
3763 cfgcr0_reg = ADLS_DPLL_CFGCR0(id);
3764 cfgcr1_reg = ADLS_DPLL_CFGCR1(id);
3765 } else if (IS_DG1(i915)) {
3766 cfgcr0_reg = DG1_DPLL_CFGCR0(id);
3767 cfgcr1_reg = DG1_DPLL_CFGCR1(id);
3768 } else if (IS_ROCKETLAKE(i915)) {
3769 cfgcr0_reg = RKL_DPLL_CFGCR0(id);
3770 cfgcr1_reg = RKL_DPLL_CFGCR1(id);
3771 } else if (DISPLAY_VER(i915) >= 12) {
3772 cfgcr0_reg = TGL_DPLL_CFGCR0(id);
3773 cfgcr1_reg = TGL_DPLL_CFGCR1(id);
3774 div0_reg = TGL_DPLL0_DIV0(id);
3775 } else {
3776 if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
3777 id == DPLL_ID_EHL_DPLL4) {
3778 cfgcr0_reg = ICL_DPLL_CFGCR0(4);
3779 cfgcr1_reg = ICL_DPLL_CFGCR1(4);
3780 } else {
3781 cfgcr0_reg = ICL_DPLL_CFGCR0(id);
3782 cfgcr1_reg = ICL_DPLL_CFGCR1(id);
3783 }
3784 }
3785
3786 intel_de_write(i915, cfgcr0_reg, hw_state->cfgcr0);
3787 intel_de_write(i915, cfgcr1_reg, hw_state->cfgcr1);
3788 drm_WARN_ON_ONCE(&i915->drm, i915->display.vbt.override_afc_startup &&
3789 !i915_mmio_reg_valid(div0_reg));
3790 if (i915->display.vbt.override_afc_startup &&
3791 i915_mmio_reg_valid(div0_reg))
3792 intel_de_rmw(i915, div0_reg,
3793 TGL_DPLL0_DIV0_AFC_STARTUP_MASK, hw_state->div0);
3794 intel_de_posting_read(i915, cfgcr1_reg);
3795}
3796
3797static void icl_mg_pll_write(struct drm_i915_private *i915,
3798 struct intel_shared_dpll *pll,
3799 const struct icl_dpll_hw_state *hw_state)
3800{
3801 enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
3802
3803 /*
3804 * Some of the following registers have reserved fields, so program
3805 * these with RMW based on a mask. The mask can be fixed or generated
3806 * during the calc/readout phase if the mask depends on some other HW
3807 * state like refclk, see icl_calc_mg_pll_state().
3808 */
3809 intel_de_rmw(i915, MG_REFCLKIN_CTL(tc_port),
3810 MG_REFCLKIN_CTL_OD_2_MUX_MASK, hw_state->mg_refclkin_ctl);
3811
3812 intel_de_rmw(i915, MG_CLKTOP2_CORECLKCTL1(tc_port),
3813 MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK,
3814 hw_state->mg_clktop2_coreclkctl1);
3815
3816 intel_de_rmw(i915, MG_CLKTOP2_HSCLKCTL(tc_port),
3817 MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
3818 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
3819 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
3820 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK,
3821 hw_state->mg_clktop2_hsclkctl);
3822
3823 intel_de_write(i915, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0);
3824 intel_de_write(i915, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1);
3825 intel_de_write(i915, MG_PLL_LF(tc_port), hw_state->mg_pll_lf);
3826 intel_de_write(i915, MG_PLL_FRAC_LOCK(tc_port),
3827 hw_state->mg_pll_frac_lock);
3828 intel_de_write(i915, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc);
3829
3830 intel_de_rmw(i915, MG_PLL_BIAS(tc_port),
3831 hw_state->mg_pll_bias_mask, hw_state->mg_pll_bias);
3832
3833 intel_de_rmw(i915, MG_PLL_TDC_COLDST_BIAS(tc_port),
3834 hw_state->mg_pll_tdc_coldst_bias_mask,
3835 hw_state->mg_pll_tdc_coldst_bias);
3836
3837 intel_de_posting_read(i915, MG_PLL_TDC_COLDST_BIAS(tc_port));
3838}
3839
3840static void dkl_pll_write(struct drm_i915_private *i915,
3841 struct intel_shared_dpll *pll,
3842 const struct icl_dpll_hw_state *hw_state)
3843{
3844 enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
3845 u32 val;
3846
3847 /*
3848 * All registers programmed here have the same HIP_INDEX_REG even
3849 * though on different building block
3850 */
3851 /* All the registers are RMW */
3852 val = intel_dkl_phy_read(i915, DKL_REFCLKIN_CTL(tc_port));
3853 val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK;
3854 val |= hw_state->mg_refclkin_ctl;
3855 intel_dkl_phy_write(i915, DKL_REFCLKIN_CTL(tc_port), val);
3856
3857 val = intel_dkl_phy_read(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port));
3858 val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
3859 val |= hw_state->mg_clktop2_coreclkctl1;
3860 intel_dkl_phy_write(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port), val);
3861
3862 val = intel_dkl_phy_read(i915, DKL_CLKTOP2_HSCLKCTL(tc_port));
3863 val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
3864 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
3865 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
3866 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
3867 val |= hw_state->mg_clktop2_hsclkctl;
3868 intel_dkl_phy_write(i915, DKL_CLKTOP2_HSCLKCTL(tc_port), val);
3869
3870 val = DKL_PLL_DIV0_MASK;
3871 if (i915->display.vbt.override_afc_startup)
3872 val |= DKL_PLL_DIV0_AFC_STARTUP_MASK;
3873 intel_dkl_phy_rmw(i915, DKL_PLL_DIV0(tc_port), val,
3874 hw_state->mg_pll_div0);
3875
3876 val = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port));
3877 val &= ~(DKL_PLL_DIV1_IREF_TRIM_MASK |
3878 DKL_PLL_DIV1_TDC_TARGET_CNT_MASK);
3879 val |= hw_state->mg_pll_div1;
3880 intel_dkl_phy_write(i915, DKL_PLL_DIV1(tc_port), val);
3881
3882 val = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port));
3883 val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
3884 DKL_PLL_SSC_STEP_LEN_MASK |
3885 DKL_PLL_SSC_STEP_NUM_MASK |
3886 DKL_PLL_SSC_EN);
3887 val |= hw_state->mg_pll_ssc;
3888 intel_dkl_phy_write(i915, DKL_PLL_SSC(tc_port), val);
3889
3890 val = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port));
3891 val &= ~(DKL_PLL_BIAS_FRAC_EN_H |
3892 DKL_PLL_BIAS_FBDIV_FRAC_MASK);
3893 val |= hw_state->mg_pll_bias;
3894 intel_dkl_phy_write(i915, DKL_PLL_BIAS(tc_port), val);
3895
3896 val = intel_dkl_phy_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port));
3897 val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK |
3898 DKL_PLL_TDC_FEED_FWD_GAIN_MASK);
3899 val |= hw_state->mg_pll_tdc_coldst_bias;
3900 intel_dkl_phy_write(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port), val);
3901
3902 intel_dkl_phy_posting_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port));
3903}
3904
3905static void icl_pll_power_enable(struct drm_i915_private *i915,
3906 struct intel_shared_dpll *pll,
3907 i915_reg_t enable_reg)
3908{
3909 intel_de_rmw(i915, enable_reg, 0, PLL_POWER_ENABLE);
3910
3911 /*
3912 * The spec says we need to "wait" but it also says it should be
3913 * immediate.
3914 */
3915 if (intel_de_wait_for_set(i915, enable_reg, PLL_POWER_STATE, 1))
3916 drm_err(&i915->drm, "PLL %d Power not enabled\n",
3917 pll->info->id);
3918}
3919
3920static void icl_pll_enable(struct drm_i915_private *i915,
3921 struct intel_shared_dpll *pll,
3922 i915_reg_t enable_reg)
3923{
3924 intel_de_rmw(i915, enable_reg, 0, PLL_ENABLE);
3925
3926 /* Timeout is actually 600us. */
3927 if (intel_de_wait_for_set(i915, enable_reg, PLL_LOCK, 1))
3928 drm_err(&i915->drm, "PLL %d not locked\n", pll->info->id);
3929}
3930
3931static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct intel_shared_dpll *pll)
3932{
3933 u32 val;
3934
3935 if (!(IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) ||
3936 pll->info->id != DPLL_ID_ICL_DPLL0)
3937 return;
3938 /*
3939 * Wa_16011069516:adl-p[a0]
3940 *
3941 * All CMTG regs are unreliable until CMTG clock gating is disabled,
3942 * so we can only assume the default TRANS_CMTG_CHICKEN reg value and
3943 * sanity check this assumption with a double read, which presumably
3944 * returns the correct value even with clock gating on.
3945 *
3946 * Instead of the usual place for workarounds we apply this one here,
3947 * since TRANS_CMTG_CHICKEN is only accessible while DPLL0 is enabled.
3948 */
3949 val = intel_de_read(i915, TRANS_CMTG_CHICKEN);
3950 val = intel_de_rmw(i915, TRANS_CMTG_CHICKEN, ~0, DISABLE_DPT_CLK_GATING);
3951 if (drm_WARN_ON(&i915->drm, val & ~DISABLE_DPT_CLK_GATING))
3952 drm_dbg_kms(&i915->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val);
3953}
3954
3955static void combo_pll_enable(struct drm_i915_private *i915,
3956 struct intel_shared_dpll *pll,
3957 const struct intel_dpll_hw_state *dpll_hw_state)
3958{
3959 const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
3960 i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll);
3961
3962 icl_pll_power_enable(i915, pll, enable_reg);
3963
3964 icl_dpll_write(i915, pll, hw_state);
3965
3966 /*
3967 * DVFS pre sequence would be here, but in our driver the cdclk code
3968 * paths should already be setting the appropriate voltage, hence we do
3969 * nothing here.
3970 */
3971
3972 icl_pll_enable(i915, pll, enable_reg);
3973
3974 adlp_cmtg_clock_gating_wa(i915, pll);
3975
3976 /* DVFS post sequence would be here. See the comment above. */
3977}
3978
3979static void tbt_pll_enable(struct drm_i915_private *i915,
3980 struct intel_shared_dpll *pll,
3981 const struct intel_dpll_hw_state *dpll_hw_state)
3982{
3983 const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
3984
3985 icl_pll_power_enable(i915, pll, TBT_PLL_ENABLE);
3986
3987 icl_dpll_write(i915, pll, hw_state);
3988
3989 /*
3990 * DVFS pre sequence would be here, but in our driver the cdclk code
3991 * paths should already be setting the appropriate voltage, hence we do
3992 * nothing here.
3993 */
3994
3995 icl_pll_enable(i915, pll, TBT_PLL_ENABLE);
3996
3997 /* DVFS post sequence would be here. See the comment above. */
3998}
3999
4000static void mg_pll_enable(struct drm_i915_private *i915,
4001 struct intel_shared_dpll *pll,
4002 const struct intel_dpll_hw_state *dpll_hw_state)
4003{
4004 const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
4005 i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll);
4006
4007 icl_pll_power_enable(i915, pll, enable_reg);
4008
4009 if (DISPLAY_VER(i915) >= 12)
4010 dkl_pll_write(i915, pll, hw_state);
4011 else
4012 icl_mg_pll_write(i915, pll, hw_state);
4013
4014 /*
4015 * DVFS pre sequence would be here, but in our driver the cdclk code
4016 * paths should already be setting the appropriate voltage, hence we do
4017 * nothing here.
4018 */
4019
4020 icl_pll_enable(i915, pll, enable_reg);
4021
4022 /* DVFS post sequence would be here. See the comment above. */
4023}
4024
4025static void icl_pll_disable(struct drm_i915_private *i915,
4026 struct intel_shared_dpll *pll,
4027 i915_reg_t enable_reg)
4028{
4029 /* The first steps are done by intel_ddi_post_disable(). */
4030
4031 /*
4032 * DVFS pre sequence would be here, but in our driver the cdclk code
4033 * paths should already be setting the appropriate voltage, hence we do
4034 * nothing here.
4035 */
4036
4037 intel_de_rmw(i915, enable_reg, PLL_ENABLE, 0);
4038
4039 /* Timeout is actually 1us. */
4040 if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 1))
4041 drm_err(&i915->drm, "PLL %d locked\n", pll->info->id);
4042
4043 /* DVFS post sequence would be here. See the comment above. */
4044
4045 intel_de_rmw(i915, enable_reg, PLL_POWER_ENABLE, 0);
4046
4047 /*
4048 * The spec says we need to "wait" but it also says it should be
4049 * immediate.
4050 */
4051 if (intel_de_wait_for_clear(i915, enable_reg, PLL_POWER_STATE, 1))
4052 drm_err(&i915->drm, "PLL %d Power not disabled\n",
4053 pll->info->id);
4054}
4055
4056static void combo_pll_disable(struct drm_i915_private *i915,
4057 struct intel_shared_dpll *pll)
4058{
4059 i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll);
4060
4061 icl_pll_disable(i915, pll, enable_reg);
4062}
4063
4064static void tbt_pll_disable(struct drm_i915_private *i915,
4065 struct intel_shared_dpll *pll)
4066{
4067 icl_pll_disable(i915, pll, TBT_PLL_ENABLE);
4068}
4069
4070static void mg_pll_disable(struct drm_i915_private *i915,
4071 struct intel_shared_dpll *pll)
4072{
4073 i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll);
4074
4075 icl_pll_disable(i915, pll, enable_reg);
4076}
4077
4078static void icl_update_dpll_ref_clks(struct drm_i915_private *i915)
4079{
4080 /* No SSC ref */
4081 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref;
4082}
4083
4084static void icl_dump_hw_state(struct drm_printer *p,
4085 const struct intel_dpll_hw_state *dpll_hw_state)
4086{
4087 const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
4088
4089 drm_printf(p, "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, div0: 0x%x, "
4090 "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, "
4091 "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
4092 "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, "
4093 "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
4094 "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n",
4095 hw_state->cfgcr0, hw_state->cfgcr1, hw_state->div0,
4096 hw_state->mg_refclkin_ctl,
4097 hw_state->mg_clktop2_coreclkctl1,
4098 hw_state->mg_clktop2_hsclkctl,
4099 hw_state->mg_pll_div0,
4100 hw_state->mg_pll_div1,
4101 hw_state->mg_pll_lf,
4102 hw_state->mg_pll_frac_lock,
4103 hw_state->mg_pll_ssc,
4104 hw_state->mg_pll_bias,
4105 hw_state->mg_pll_tdc_coldst_bias);
4106}
4107
4108static bool icl_compare_hw_state(const struct intel_dpll_hw_state *_a,
4109 const struct intel_dpll_hw_state *_b)
4110{
4111 const struct icl_dpll_hw_state *a = &_a->icl;
4112 const struct icl_dpll_hw_state *b = &_b->icl;
4113
4114 /* FIXME split combo vs. mg more thoroughly */
4115 return a->cfgcr0 == b->cfgcr0 &&
4116 a->cfgcr1 == b->cfgcr1 &&
4117 a->div0 == b->div0 &&
4118 a->mg_refclkin_ctl == b->mg_refclkin_ctl &&
4119 a->mg_clktop2_coreclkctl1 == b->mg_clktop2_coreclkctl1 &&
4120 a->mg_clktop2_hsclkctl == b->mg_clktop2_hsclkctl &&
4121 a->mg_pll_div0 == b->mg_pll_div0 &&
4122 a->mg_pll_div1 == b->mg_pll_div1 &&
4123 a->mg_pll_lf == b->mg_pll_lf &&
4124 a->mg_pll_frac_lock == b->mg_pll_frac_lock &&
4125 a->mg_pll_ssc == b->mg_pll_ssc &&
4126 a->mg_pll_bias == b->mg_pll_bias &&
4127 a->mg_pll_tdc_coldst_bias == b->mg_pll_tdc_coldst_bias;
4128}
4129
4130static const struct intel_shared_dpll_funcs combo_pll_funcs = {
4131 .enable = combo_pll_enable,
4132 .disable = combo_pll_disable,
4133 .get_hw_state = combo_pll_get_hw_state,
4134 .get_freq = icl_ddi_combo_pll_get_freq,
4135};
4136
4137static const struct intel_shared_dpll_funcs tbt_pll_funcs = {
4138 .enable = tbt_pll_enable,
4139 .disable = tbt_pll_disable,
4140 .get_hw_state = tbt_pll_get_hw_state,
4141 .get_freq = icl_ddi_tbt_pll_get_freq,
4142};
4143
4144static const struct intel_shared_dpll_funcs mg_pll_funcs = {
4145 .enable = mg_pll_enable,
4146 .disable = mg_pll_disable,
4147 .get_hw_state = mg_pll_get_hw_state,
4148 .get_freq = icl_ddi_mg_pll_get_freq,
4149};
4150
4151static const struct dpll_info icl_plls[] = {
4152 { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
4153 { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
4154 { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
4155 .is_alt_port_dpll = true, },
4156 { .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
4157 { .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
4158 { .name = "MG PLL 3", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
4159 { .name = "MG PLL 4", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
4160 {}
4161};
4162
4163static const struct intel_dpll_mgr icl_pll_mgr = {
4164 .dpll_info = icl_plls,
4165 .compute_dplls = icl_compute_dplls,
4166 .get_dplls = icl_get_dplls,
4167 .put_dplls = icl_put_dplls,
4168 .update_active_dpll = icl_update_active_dpll,
4169 .update_ref_clks = icl_update_dpll_ref_clks,
4170 .dump_hw_state = icl_dump_hw_state,
4171 .compare_hw_state = icl_compare_hw_state,
4172};
4173
4174static const struct dpll_info ehl_plls[] = {
4175 { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
4176 { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
4177 { .name = "DPLL 4", .funcs = &combo_pll_funcs, .id = DPLL_ID_EHL_DPLL4,
4178 .power_domain = POWER_DOMAIN_DC_OFF, },
4179 {}
4180};
4181
4182static const struct intel_dpll_mgr ehl_pll_mgr = {
4183 .dpll_info = ehl_plls,
4184 .compute_dplls = icl_compute_dplls,
4185 .get_dplls = icl_get_dplls,
4186 .put_dplls = icl_put_dplls,
4187 .update_ref_clks = icl_update_dpll_ref_clks,
4188 .dump_hw_state = icl_dump_hw_state,
4189 .compare_hw_state = icl_compare_hw_state,
4190};
4191
4192static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
4193 .enable = mg_pll_enable,
4194 .disable = mg_pll_disable,
4195 .get_hw_state = dkl_pll_get_hw_state,
4196 .get_freq = icl_ddi_mg_pll_get_freq,
4197};
4198
4199static const struct dpll_info tgl_plls[] = {
4200 { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
4201 { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
4202 { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
4203 .is_alt_port_dpll = true, },
4204 { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
4205 { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
4206 { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
4207 { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
4208 { .name = "TC PLL 5", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL5, },
4209 { .name = "TC PLL 6", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL6, },
4210 {}
4211};
4212
4213static const struct intel_dpll_mgr tgl_pll_mgr = {
4214 .dpll_info = tgl_plls,
4215 .compute_dplls = icl_compute_dplls,
4216 .get_dplls = icl_get_dplls,
4217 .put_dplls = icl_put_dplls,
4218 .update_active_dpll = icl_update_active_dpll,
4219 .update_ref_clks = icl_update_dpll_ref_clks,
4220 .dump_hw_state = icl_dump_hw_state,
4221 .compare_hw_state = icl_compare_hw_state,
4222};
4223
4224static const struct dpll_info rkl_plls[] = {
4225 { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
4226 { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
4227 { .name = "DPLL 4", .funcs = &combo_pll_funcs, .id = DPLL_ID_EHL_DPLL4, },
4228 {}
4229};
4230
4231static const struct intel_dpll_mgr rkl_pll_mgr = {
4232 .dpll_info = rkl_plls,
4233 .compute_dplls = icl_compute_dplls,
4234 .get_dplls = icl_get_dplls,
4235 .put_dplls = icl_put_dplls,
4236 .update_ref_clks = icl_update_dpll_ref_clks,
4237 .dump_hw_state = icl_dump_hw_state,
4238 .compare_hw_state = icl_compare_hw_state,
4239};
4240
4241static const struct dpll_info dg1_plls[] = {
4242 { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL0, },
4243 { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL1, },
4244 { .name = "DPLL 2", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL2, },
4245 { .name = "DPLL 3", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL3, },
4246 {}
4247};
4248
4249static const struct intel_dpll_mgr dg1_pll_mgr = {
4250 .dpll_info = dg1_plls,
4251 .compute_dplls = icl_compute_dplls,
4252 .get_dplls = icl_get_dplls,
4253 .put_dplls = icl_put_dplls,
4254 .update_ref_clks = icl_update_dpll_ref_clks,
4255 .dump_hw_state = icl_dump_hw_state,
4256 .compare_hw_state = icl_compare_hw_state,
4257};
4258
4259static const struct dpll_info adls_plls[] = {
4260 { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
4261 { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
4262 { .name = "DPLL 2", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL2, },
4263 { .name = "DPLL 3", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL3, },
4264 {}
4265};
4266
4267static const struct intel_dpll_mgr adls_pll_mgr = {
4268 .dpll_info = adls_plls,
4269 .compute_dplls = icl_compute_dplls,
4270 .get_dplls = icl_get_dplls,
4271 .put_dplls = icl_put_dplls,
4272 .update_ref_clks = icl_update_dpll_ref_clks,
4273 .dump_hw_state = icl_dump_hw_state,
4274 .compare_hw_state = icl_compare_hw_state,
4275};
4276
4277static const struct dpll_info adlp_plls[] = {
4278 { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
4279 { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
4280 { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
4281 .is_alt_port_dpll = true, },
4282 { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
4283 { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
4284 { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
4285 { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
4286 {}
4287};
4288
4289static const struct intel_dpll_mgr adlp_pll_mgr = {
4290 .dpll_info = adlp_plls,
4291 .compute_dplls = icl_compute_dplls,
4292 .get_dplls = icl_get_dplls,
4293 .put_dplls = icl_put_dplls,
4294 .update_active_dpll = icl_update_active_dpll,
4295 .update_ref_clks = icl_update_dpll_ref_clks,
4296 .dump_hw_state = icl_dump_hw_state,
4297 .compare_hw_state = icl_compare_hw_state,
4298};
4299
4300/**
4301 * intel_shared_dpll_init - Initialize shared DPLLs
4302 * @i915: i915 device
4303 *
4304 * Initialize shared DPLLs for @i915.
4305 */
4306void intel_shared_dpll_init(struct drm_i915_private *i915)
4307{
4308 const struct intel_dpll_mgr *dpll_mgr = NULL;
4309 const struct dpll_info *dpll_info;
4310 int i;
4311
4312 mutex_init(&i915->display.dpll.lock);
4313
4314 if (DISPLAY_VER(i915) >= 14 || IS_DG2(i915))
4315 /* No shared DPLLs on DG2; port PLLs are part of the PHY */
4316 dpll_mgr = NULL;
4317 else if (IS_ALDERLAKE_P(i915))
4318 dpll_mgr = &adlp_pll_mgr;
4319 else if (IS_ALDERLAKE_S(i915))
4320 dpll_mgr = &adls_pll_mgr;
4321 else if (IS_DG1(i915))
4322 dpll_mgr = &dg1_pll_mgr;
4323 else if (IS_ROCKETLAKE(i915))
4324 dpll_mgr = &rkl_pll_mgr;
4325 else if (DISPLAY_VER(i915) >= 12)
4326 dpll_mgr = &tgl_pll_mgr;
4327 else if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915))
4328 dpll_mgr = &ehl_pll_mgr;
4329 else if (DISPLAY_VER(i915) >= 11)
4330 dpll_mgr = &icl_pll_mgr;
4331 else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
4332 dpll_mgr = &bxt_pll_mgr;
4333 else if (DISPLAY_VER(i915) == 9)
4334 dpll_mgr = &skl_pll_mgr;
4335 else if (HAS_DDI(i915))
4336 dpll_mgr = &hsw_pll_mgr;
4337 else if (HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915))
4338 dpll_mgr = &pch_pll_mgr;
4339
4340 if (!dpll_mgr)
4341 return;
4342
4343 dpll_info = dpll_mgr->dpll_info;
4344
4345 for (i = 0; dpll_info[i].name; i++) {
4346 if (drm_WARN_ON(&i915->drm,
4347 i >= ARRAY_SIZE(i915->display.dpll.shared_dplls)))
4348 break;
4349
4350 /* must fit into unsigned long bitmask on 32bit */
4351 if (drm_WARN_ON(&i915->drm, dpll_info[i].id >= 32))
4352 break;
4353
4354 i915->display.dpll.shared_dplls[i].info = &dpll_info[i];
4355 i915->display.dpll.shared_dplls[i].index = i;
4356 }
4357
4358 i915->display.dpll.mgr = dpll_mgr;
4359 i915->display.dpll.num_shared_dpll = i;
4360}
4361
4362/**
4363 * intel_compute_shared_dplls - compute DPLL state CRTC and encoder combination
4364 * @state: atomic state
4365 * @crtc: CRTC to compute DPLLs for
4366 * @encoder: encoder
4367 *
4368 * This function computes the DPLL state for the given CRTC and encoder.
4369 *
4370 * The new configuration in the atomic commit @state is made effective by
4371 * calling intel_shared_dpll_swap_state().
4372 *
4373 * Returns:
4374 * 0 on success, negative error code on falure.
4375 */
4376int intel_compute_shared_dplls(struct intel_atomic_state *state,
4377 struct intel_crtc *crtc,
4378 struct intel_encoder *encoder)
4379{
4380 struct drm_i915_private *i915 = to_i915(state->base.dev);
4381 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr;
4382
4383 if (drm_WARN_ON(&i915->drm, !dpll_mgr))
4384 return -EINVAL;
4385
4386 return dpll_mgr->compute_dplls(state, crtc, encoder);
4387}
4388
4389/**
4390 * intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination
4391 * @state: atomic state
4392 * @crtc: CRTC to reserve DPLLs for
4393 * @encoder: encoder
4394 *
4395 * This function reserves all required DPLLs for the given CRTC and encoder
4396 * combination in the current atomic commit @state and the new @crtc atomic
4397 * state.
4398 *
4399 * The new configuration in the atomic commit @state is made effective by
4400 * calling intel_shared_dpll_swap_state().
4401 *
4402 * The reserved DPLLs should be released by calling
4403 * intel_release_shared_dplls().
4404 *
4405 * Returns:
4406 * 0 if all required DPLLs were successfully reserved,
4407 * negative error code otherwise.
4408 */
4409int intel_reserve_shared_dplls(struct intel_atomic_state *state,
4410 struct intel_crtc *crtc,
4411 struct intel_encoder *encoder)
4412{
4413 struct drm_i915_private *i915 = to_i915(state->base.dev);
4414 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr;
4415
4416 if (drm_WARN_ON(&i915->drm, !dpll_mgr))
4417 return -EINVAL;
4418
4419 return dpll_mgr->get_dplls(state, crtc, encoder);
4420}
4421
4422/**
4423 * intel_release_shared_dplls - end use of DPLLs by CRTC in atomic state
4424 * @state: atomic state
4425 * @crtc: crtc from which the DPLLs are to be released
4426 *
4427 * This function releases all DPLLs reserved by intel_reserve_shared_dplls()
4428 * from the current atomic commit @state and the old @crtc atomic state.
4429 *
4430 * The new configuration in the atomic commit @state is made effective by
4431 * calling intel_shared_dpll_swap_state().
4432 */
4433void intel_release_shared_dplls(struct intel_atomic_state *state,
4434 struct intel_crtc *crtc)
4435{
4436 struct drm_i915_private *i915 = to_i915(state->base.dev);
4437 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr;
4438
4439 /*
4440 * FIXME: this function is called for every platform having a
4441 * compute_clock hook, even though the platform doesn't yet support
4442 * the shared DPLL framework and intel_reserve_shared_dplls() is not
4443 * called on those.
4444 */
4445 if (!dpll_mgr)
4446 return;
4447
4448 dpll_mgr->put_dplls(state, crtc);
4449}
4450
4451/**
4452 * intel_update_active_dpll - update the active DPLL for a CRTC/encoder
4453 * @state: atomic state
4454 * @crtc: the CRTC for which to update the active DPLL
4455 * @encoder: encoder determining the type of port DPLL
4456 *
4457 * Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state,
4458 * from the port DPLLs reserved previously by intel_reserve_shared_dplls(). The
4459 * DPLL selected will be based on the current mode of the encoder's port.
4460 */
4461void intel_update_active_dpll(struct intel_atomic_state *state,
4462 struct intel_crtc *crtc,
4463 struct intel_encoder *encoder)
4464{
4465 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4466 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr;
4467
4468 if (drm_WARN_ON(&i915->drm, !dpll_mgr))
4469 return;
4470
4471 dpll_mgr->update_active_dpll(state, crtc, encoder);
4472}
4473
4474/**
4475 * intel_dpll_get_freq - calculate the DPLL's output frequency
4476 * @i915: i915 device
4477 * @pll: DPLL for which to calculate the output frequency
4478 * @dpll_hw_state: DPLL state from which to calculate the output frequency
4479 *
4480 * Return the output frequency corresponding to @pll's passed in @dpll_hw_state.
4481 */
4482int intel_dpll_get_freq(struct drm_i915_private *i915,
4483 const struct intel_shared_dpll *pll,
4484 const struct intel_dpll_hw_state *dpll_hw_state)
4485{
4486 if (drm_WARN_ON(&i915->drm, !pll->info->funcs->get_freq))
4487 return 0;
4488
4489 return pll->info->funcs->get_freq(i915, pll, dpll_hw_state);
4490}
4491
4492/**
4493 * intel_dpll_get_hw_state - readout the DPLL's hardware state
4494 * @i915: i915 device
4495 * @pll: DPLL for which to calculate the output frequency
4496 * @dpll_hw_state: DPLL's hardware state
4497 *
4498 * Read out @pll's hardware state into @dpll_hw_state.
4499 */
4500bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
4501 struct intel_shared_dpll *pll,
4502 struct intel_dpll_hw_state *dpll_hw_state)
4503{
4504 return pll->info->funcs->get_hw_state(i915, pll, dpll_hw_state);
4505}
4506
4507static void readout_dpll_hw_state(struct drm_i915_private *i915,
4508 struct intel_shared_dpll *pll)
4509{
4510 struct intel_crtc *crtc;
4511
4512 pll->on = intel_dpll_get_hw_state(i915, pll, &pll->state.hw_state);
4513
4514 if (pll->on && pll->info->power_domain)
4515 pll->wakeref = intel_display_power_get(i915, pll->info->power_domain);
4516
4517 pll->state.pipe_mask = 0;
4518 for_each_intel_crtc(&i915->drm, crtc) {
4519 struct intel_crtc_state *crtc_state =
4520 to_intel_crtc_state(crtc->base.state);
4521
4522 if (crtc_state->hw.active && crtc_state->shared_dpll == pll)
4523 intel_reference_shared_dpll_crtc(crtc, pll, &pll->state);
4524 }
4525 pll->active_mask = pll->state.pipe_mask;
4526
4527 drm_dbg_kms(&i915->drm,
4528 "%s hw state readout: pipe_mask 0x%x, on %i\n",
4529 pll->info->name, pll->state.pipe_mask, pll->on);
4530}
4531
4532void intel_dpll_update_ref_clks(struct drm_i915_private *i915)
4533{
4534 if (i915->display.dpll.mgr && i915->display.dpll.mgr->update_ref_clks)
4535 i915->display.dpll.mgr->update_ref_clks(i915);
4536}
4537
4538void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
4539{
4540 struct intel_shared_dpll *pll;
4541 int i;
4542
4543 for_each_shared_dpll(i915, pll, i)
4544 readout_dpll_hw_state(i915, pll);
4545}
4546
4547static void sanitize_dpll_state(struct drm_i915_private *i915,
4548 struct intel_shared_dpll *pll)
4549{
4550 if (!pll->on)
4551 return;
4552
4553 adlp_cmtg_clock_gating_wa(i915, pll);
4554
4555 if (pll->active_mask)
4556 return;
4557
4558 drm_dbg_kms(&i915->drm,
4559 "%s enabled but not in use, disabling\n",
4560 pll->info->name);
4561
4562 _intel_disable_shared_dpll(i915, pll);
4563}
4564
4565void intel_dpll_sanitize_state(struct drm_i915_private *i915)
4566{
4567 struct intel_shared_dpll *pll;
4568 int i;
4569
4570 for_each_shared_dpll(i915, pll, i)
4571 sanitize_dpll_state(i915, pll);
4572}
4573
4574/**
4575 * intel_dpll_dump_hw_state - dump hw_state
4576 * @i915: i915 drm device
4577 * @p: where to print the state to
4578 * @dpll_hw_state: hw state to be dumped
4579 *
4580 * Dumo out the relevant values in @dpll_hw_state.
4581 */
4582void intel_dpll_dump_hw_state(struct drm_i915_private *i915,
4583 struct drm_printer *p,
4584 const struct intel_dpll_hw_state *dpll_hw_state)
4585{
4586 if (i915->display.dpll.mgr) {
4587 i915->display.dpll.mgr->dump_hw_state(p, dpll_hw_state);
4588 } else {
4589 /* fallback for platforms that don't use the shared dpll
4590 * infrastructure
4591 */
4592 ibx_dump_hw_state(p, dpll_hw_state);
4593 }
4594}
4595
4596/**
4597 * intel_dpll_compare_hw_state - compare the two states
4598 * @i915: i915 drm device
4599 * @a: first DPLL hw state
4600 * @b: second DPLL hw state
4601 *
4602 * Compare DPLL hw states @a and @b.
4603 *
4604 * Returns: true if the states are equal, false if the differ
4605 */
4606bool intel_dpll_compare_hw_state(struct drm_i915_private *i915,
4607 const struct intel_dpll_hw_state *a,
4608 const struct intel_dpll_hw_state *b)
4609{
4610 if (i915->display.dpll.mgr) {
4611 return i915->display.dpll.mgr->compare_hw_state(a, b);
4612 } else {
4613 /* fallback for platforms that don't use the shared dpll
4614 * infrastructure
4615 */
4616 return ibx_compare_hw_state(a, b);
4617 }
4618}
4619
4620static void
4621verify_single_dpll_state(struct drm_i915_private *i915,
4622 struct intel_shared_dpll *pll,
4623 struct intel_crtc *crtc,
4624 const struct intel_crtc_state *new_crtc_state)
4625{
4626 struct intel_display *display = &i915->display;
4627 struct intel_dpll_hw_state dpll_hw_state = {};
4628 u8 pipe_mask;
4629 bool active;
4630
4631 active = intel_dpll_get_hw_state(i915, pll, &dpll_hw_state);
4632
4633 if (!pll->info->always_on) {
4634 INTEL_DISPLAY_STATE_WARN(display, !pll->on && pll->active_mask,
4635 "%s: pll in active use but not on in sw tracking\n",
4636 pll->info->name);
4637 INTEL_DISPLAY_STATE_WARN(display, pll->on && !pll->active_mask,
4638 "%s: pll is on but not used by any active pipe\n",
4639 pll->info->name);
4640 INTEL_DISPLAY_STATE_WARN(display, pll->on != active,
4641 "%s: pll on state mismatch (expected %i, found %i)\n",
4642 pll->info->name, pll->on, active);
4643 }
4644
4645 if (!crtc) {
4646 INTEL_DISPLAY_STATE_WARN(display,
4647 pll->active_mask & ~pll->state.pipe_mask,
4648 "%s: more active pll users than references: 0x%x vs 0x%x\n",
4649 pll->info->name, pll->active_mask, pll->state.pipe_mask);
4650
4651 return;
4652 }
4653
4654 pipe_mask = BIT(crtc->pipe);
4655
4656 if (new_crtc_state->hw.active)
4657 INTEL_DISPLAY_STATE_WARN(display, !(pll->active_mask & pipe_mask),
4658 "%s: pll active mismatch (expected pipe %c in active mask 0x%x)\n",
4659 pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
4660 else
4661 INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask,
4662 "%s: pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n",
4663 pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
4664
4665 INTEL_DISPLAY_STATE_WARN(display, !(pll->state.pipe_mask & pipe_mask),
4666 "%s: pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
4667 pll->info->name, pipe_mask, pll->state.pipe_mask);
4668
4669 INTEL_DISPLAY_STATE_WARN(display,
4670 pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state,
4671 sizeof(dpll_hw_state)),
4672 "%s: pll hw state mismatch\n",
4673 pll->info->name);
4674}
4675
4676static bool has_alt_port_dpll(const struct intel_shared_dpll *old_pll,
4677 const struct intel_shared_dpll *new_pll)
4678{
4679 return old_pll && new_pll && old_pll != new_pll &&
4680 (old_pll->info->is_alt_port_dpll || new_pll->info->is_alt_port_dpll);
4681}
4682
4683void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
4684 struct intel_crtc *crtc)
4685{
4686 struct intel_display *display = to_intel_display(state);
4687 struct drm_i915_private *i915 = to_i915(state->base.dev);
4688 const struct intel_crtc_state *old_crtc_state =
4689 intel_atomic_get_old_crtc_state(state, crtc);
4690 const struct intel_crtc_state *new_crtc_state =
4691 intel_atomic_get_new_crtc_state(state, crtc);
4692
4693 if (new_crtc_state->shared_dpll)
4694 verify_single_dpll_state(i915, new_crtc_state->shared_dpll,
4695 crtc, new_crtc_state);
4696
4697 if (old_crtc_state->shared_dpll &&
4698 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
4699 u8 pipe_mask = BIT(crtc->pipe);
4700 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
4701
4702 INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask,
4703 "%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
4704 pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
4705
4706 /* TC ports have both MG/TC and TBT PLL referenced simultaneously */
4707 INTEL_DISPLAY_STATE_WARN(display, !has_alt_port_dpll(old_crtc_state->shared_dpll,
4708 new_crtc_state->shared_dpll) &&
4709 pll->state.pipe_mask & pipe_mask,
4710 "%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n",
4711 pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask);
4712 }
4713}
4714
4715void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
4716{
4717 struct drm_i915_private *i915 = to_i915(state->base.dev);
4718 struct intel_shared_dpll *pll;
4719 int i;
4720
4721 for_each_shared_dpll(i915, pll, i)
4722 verify_single_dpll_state(i915, pll, NULL, NULL);
4723}
1/*
2 * Copyright © 2006-2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/math.h>
25#include <linux/string_helpers.h>
26
27#include "i915_reg.h"
28#include "intel_de.h"
29#include "intel_display_types.h"
30#include "intel_dkl_phy.h"
31#include "intel_dkl_phy_regs.h"
32#include "intel_dpio_phy.h"
33#include "intel_dpll.h"
34#include "intel_dpll_mgr.h"
35#include "intel_hti.h"
36#include "intel_mg_phy_regs.h"
37#include "intel_pch_refclk.h"
38#include "intel_tc.h"
39
40/**
41 * DOC: Display PLLs
42 *
43 * Display PLLs used for driving outputs vary by platform. While some have
44 * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
45 * from a pool. In the latter scenario, it is possible that multiple pipes
46 * share a PLL if their configurations match.
47 *
48 * This file provides an abstraction over display PLLs. The function
49 * intel_shared_dpll_init() initializes the PLLs for the given platform. The
50 * users of a PLL are tracked and that tracking is integrated with the atomic
51 * modset interface. During an atomic operation, required PLLs can be reserved
52 * for a given CRTC and encoder configuration by calling
53 * intel_reserve_shared_dplls() and previously reserved PLLs can be released
54 * with intel_release_shared_dplls().
55 * Changes to the users are first staged in the atomic state, and then made
56 * effective by calling intel_shared_dpll_swap_state() during the atomic
57 * commit phase.
58 */
59
60/* platform specific hooks for managing DPLLs */
61struct intel_shared_dpll_funcs {
62 /*
63 * Hook for enabling the pll, called from intel_enable_shared_dpll() if
64 * the pll is not already enabled.
65 */
66 void (*enable)(struct drm_i915_private *i915,
67 struct intel_shared_dpll *pll);
68
69 /*
70 * Hook for disabling the pll, called from intel_disable_shared_dpll()
71 * only when it is safe to disable the pll, i.e., there are no more
72 * tracked users for it.
73 */
74 void (*disable)(struct drm_i915_private *i915,
75 struct intel_shared_dpll *pll);
76
77 /*
78 * Hook for reading the values currently programmed to the DPLL
79 * registers. This is used for initial hw state readout and state
80 * verification after a mode set.
81 */
82 bool (*get_hw_state)(struct drm_i915_private *i915,
83 struct intel_shared_dpll *pll,
84 struct intel_dpll_hw_state *hw_state);
85
86 /*
87 * Hook for calculating the pll's output frequency based on its passed
88 * in state.
89 */
90 int (*get_freq)(struct drm_i915_private *i915,
91 const struct intel_shared_dpll *pll,
92 const struct intel_dpll_hw_state *pll_state);
93};
94
95struct intel_dpll_mgr {
96 const struct dpll_info *dpll_info;
97
98 int (*compute_dplls)(struct intel_atomic_state *state,
99 struct intel_crtc *crtc,
100 struct intel_encoder *encoder);
101 int (*get_dplls)(struct intel_atomic_state *state,
102 struct intel_crtc *crtc,
103 struct intel_encoder *encoder);
104 void (*put_dplls)(struct intel_atomic_state *state,
105 struct intel_crtc *crtc);
106 void (*update_active_dpll)(struct intel_atomic_state *state,
107 struct intel_crtc *crtc,
108 struct intel_encoder *encoder);
109 void (*update_ref_clks)(struct drm_i915_private *i915);
110 void (*dump_hw_state)(struct drm_i915_private *i915,
111 const struct intel_dpll_hw_state *hw_state);
112 bool (*compare_hw_state)(const struct intel_dpll_hw_state *a,
113 const struct intel_dpll_hw_state *b);
114};
115
116static void
117intel_atomic_duplicate_dpll_state(struct drm_i915_private *i915,
118 struct intel_shared_dpll_state *shared_dpll)
119{
120 struct intel_shared_dpll *pll;
121 int i;
122
123 /* Copy shared dpll state */
124 for_each_shared_dpll(i915, pll, i)
125 shared_dpll[pll->index] = pll->state;
126}
127
128static struct intel_shared_dpll_state *
129intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
130{
131 struct intel_atomic_state *state = to_intel_atomic_state(s);
132
133 drm_WARN_ON(s->dev, !drm_modeset_is_locked(&s->dev->mode_config.connection_mutex));
134
135 if (!state->dpll_set) {
136 state->dpll_set = true;
137
138 intel_atomic_duplicate_dpll_state(to_i915(s->dev),
139 state->shared_dpll);
140 }
141
142 return state->shared_dpll;
143}
144
145/**
146 * intel_get_shared_dpll_by_id - get a DPLL given its id
147 * @i915: i915 device instance
148 * @id: pll id
149 *
150 * Returns:
151 * A pointer to the DPLL with @id
152 */
153struct intel_shared_dpll *
154intel_get_shared_dpll_by_id(struct drm_i915_private *i915,
155 enum intel_dpll_id id)
156{
157 struct intel_shared_dpll *pll;
158 int i;
159
160 for_each_shared_dpll(i915, pll, i) {
161 if (pll->info->id == id)
162 return pll;
163 }
164
165 MISSING_CASE(id);
166 return NULL;
167}
168
169/* For ILK+ */
170void assert_shared_dpll(struct drm_i915_private *i915,
171 struct intel_shared_dpll *pll,
172 bool state)
173{
174 bool cur_state;
175 struct intel_dpll_hw_state hw_state;
176
177 if (drm_WARN(&i915->drm, !pll,
178 "asserting DPLL %s with no DPLL\n", str_on_off(state)))
179 return;
180
181 cur_state = intel_dpll_get_hw_state(i915, pll, &hw_state);
182 I915_STATE_WARN(i915, cur_state != state,
183 "%s assertion failure (expected %s, current %s)\n",
184 pll->info->name, str_on_off(state),
185 str_on_off(cur_state));
186}
187
188static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)
189{
190 return TC_PORT_1 + id - DPLL_ID_ICL_MGPLL1;
191}
192
193enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
194{
195 return tc_port - TC_PORT_1 + DPLL_ID_ICL_MGPLL1;
196}
197
198static i915_reg_t
199intel_combo_pll_enable_reg(struct drm_i915_private *i915,
200 struct intel_shared_dpll *pll)
201{
202 if (IS_DG1(i915))
203 return DG1_DPLL_ENABLE(pll->info->id);
204 else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
205 (pll->info->id == DPLL_ID_EHL_DPLL4))
206 return MG_PLL_ENABLE(0);
207
208 return ICL_DPLL_ENABLE(pll->info->id);
209}
210
211static i915_reg_t
212intel_tc_pll_enable_reg(struct drm_i915_private *i915,
213 struct intel_shared_dpll *pll)
214{
215 const enum intel_dpll_id id = pll->info->id;
216 enum tc_port tc_port = icl_pll_id_to_tc_port(id);
217
218 if (IS_ALDERLAKE_P(i915))
219 return ADLP_PORTTC_PLL_ENABLE(tc_port);
220
221 return MG_PLL_ENABLE(tc_port);
222}
223
224static void _intel_enable_shared_dpll(struct drm_i915_private *i915,
225 struct intel_shared_dpll *pll)
226{
227 if (pll->info->power_domain)
228 pll->wakeref = intel_display_power_get(i915, pll->info->power_domain);
229
230 pll->info->funcs->enable(i915, pll);
231 pll->on = true;
232}
233
234static void _intel_disable_shared_dpll(struct drm_i915_private *i915,
235 struct intel_shared_dpll *pll)
236{
237 pll->info->funcs->disable(i915, pll);
238 pll->on = false;
239
240 if (pll->info->power_domain)
241 intel_display_power_put(i915, pll->info->power_domain, pll->wakeref);
242}
243
244/**
245 * intel_enable_shared_dpll - enable a CRTC's shared DPLL
246 * @crtc_state: CRTC, and its state, which has a shared DPLL
247 *
248 * Enable the shared DPLL used by @crtc.
249 */
250void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
251{
252 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
253 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
254 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
255 unsigned int pipe_mask = BIT(crtc->pipe);
256 unsigned int old_mask;
257
258 if (drm_WARN_ON(&i915->drm, pll == NULL))
259 return;
260
261 mutex_lock(&i915->display.dpll.lock);
262 old_mask = pll->active_mask;
263
264 if (drm_WARN_ON(&i915->drm, !(pll->state.pipe_mask & pipe_mask)) ||
265 drm_WARN_ON(&i915->drm, pll->active_mask & pipe_mask))
266 goto out;
267
268 pll->active_mask |= pipe_mask;
269
270 drm_dbg_kms(&i915->drm,
271 "enable %s (active 0x%x, on? %d) for [CRTC:%d:%s]\n",
272 pll->info->name, pll->active_mask, pll->on,
273 crtc->base.base.id, crtc->base.name);
274
275 if (old_mask) {
276 drm_WARN_ON(&i915->drm, !pll->on);
277 assert_shared_dpll_enabled(i915, pll);
278 goto out;
279 }
280 drm_WARN_ON(&i915->drm, pll->on);
281
282 drm_dbg_kms(&i915->drm, "enabling %s\n", pll->info->name);
283
284 _intel_enable_shared_dpll(i915, pll);
285
286out:
287 mutex_unlock(&i915->display.dpll.lock);
288}
289
290/**
291 * intel_disable_shared_dpll - disable a CRTC's shared DPLL
292 * @crtc_state: CRTC, and its state, which has a shared DPLL
293 *
294 * Disable the shared DPLL used by @crtc.
295 */
296void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
297{
298 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
299 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
300 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
301 unsigned int pipe_mask = BIT(crtc->pipe);
302
303 /* PCH only available on ILK+ */
304 if (DISPLAY_VER(i915) < 5)
305 return;
306
307 if (pll == NULL)
308 return;
309
310 mutex_lock(&i915->display.dpll.lock);
311 if (drm_WARN(&i915->drm, !(pll->active_mask & pipe_mask),
312 "%s not used by [CRTC:%d:%s]\n", pll->info->name,
313 crtc->base.base.id, crtc->base.name))
314 goto out;
315
316 drm_dbg_kms(&i915->drm,
317 "disable %s (active 0x%x, on? %d) for [CRTC:%d:%s]\n",
318 pll->info->name, pll->active_mask, pll->on,
319 crtc->base.base.id, crtc->base.name);
320
321 assert_shared_dpll_enabled(i915, pll);
322 drm_WARN_ON(&i915->drm, !pll->on);
323
324 pll->active_mask &= ~pipe_mask;
325 if (pll->active_mask)
326 goto out;
327
328 drm_dbg_kms(&i915->drm, "disabling %s\n", pll->info->name);
329
330 _intel_disable_shared_dpll(i915, pll);
331
332out:
333 mutex_unlock(&i915->display.dpll.lock);
334}
335
336static unsigned long
337intel_dpll_mask_all(struct drm_i915_private *i915)
338{
339 struct intel_shared_dpll *pll;
340 unsigned long dpll_mask = 0;
341 int i;
342
343 for_each_shared_dpll(i915, pll, i) {
344 drm_WARN_ON(&i915->drm, dpll_mask & BIT(pll->info->id));
345
346 dpll_mask |= BIT(pll->info->id);
347 }
348
349 return dpll_mask;
350}
351
352static struct intel_shared_dpll *
353intel_find_shared_dpll(struct intel_atomic_state *state,
354 const struct intel_crtc *crtc,
355 const struct intel_dpll_hw_state *pll_state,
356 unsigned long dpll_mask)
357{
358 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
359 unsigned long dpll_mask_all = intel_dpll_mask_all(i915);
360 struct intel_shared_dpll_state *shared_dpll;
361 struct intel_shared_dpll *unused_pll = NULL;
362 enum intel_dpll_id id;
363
364 shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
365
366 drm_WARN_ON(&i915->drm, dpll_mask & ~dpll_mask_all);
367
368 for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
369 struct intel_shared_dpll *pll;
370
371 pll = intel_get_shared_dpll_by_id(i915, id);
372 if (!pll)
373 continue;
374
375 /* Only want to check enabled timings first */
376 if (shared_dpll[pll->index].pipe_mask == 0) {
377 if (!unused_pll)
378 unused_pll = pll;
379 continue;
380 }
381
382 if (memcmp(pll_state,
383 &shared_dpll[pll->index].hw_state,
384 sizeof(*pll_state)) == 0) {
385 drm_dbg_kms(&i915->drm,
386 "[CRTC:%d:%s] sharing existing %s (pipe mask 0x%x, active 0x%x)\n",
387 crtc->base.base.id, crtc->base.name,
388 pll->info->name,
389 shared_dpll[pll->index].pipe_mask,
390 pll->active_mask);
391 return pll;
392 }
393 }
394
395 /* Ok no matching timings, maybe there's a free one? */
396 if (unused_pll) {
397 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] allocated %s\n",
398 crtc->base.base.id, crtc->base.name,
399 unused_pll->info->name);
400 return unused_pll;
401 }
402
403 return NULL;
404}
405
406/**
407 * intel_reference_shared_dpll_crtc - Get a DPLL reference for a CRTC
408 * @crtc: CRTC on which behalf the reference is taken
409 * @pll: DPLL for which the reference is taken
410 * @shared_dpll_state: the DPLL atomic state in which the reference is tracked
411 *
412 * Take a reference for @pll tracking the use of it by @crtc.
413 */
414static void
415intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
416 const struct intel_shared_dpll *pll,
417 struct intel_shared_dpll_state *shared_dpll_state)
418{
419 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
420
421 drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);
422
423 shared_dpll_state->pipe_mask |= BIT(crtc->pipe);
424
425 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] reserving %s\n",
426 crtc->base.base.id, crtc->base.name, pll->info->name);
427}
428
429static void
430intel_reference_shared_dpll(struct intel_atomic_state *state,
431 const struct intel_crtc *crtc,
432 const struct intel_shared_dpll *pll,
433 const struct intel_dpll_hw_state *pll_state)
434{
435 struct intel_shared_dpll_state *shared_dpll;
436
437 shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
438
439 if (shared_dpll[pll->index].pipe_mask == 0)
440 shared_dpll[pll->index].hw_state = *pll_state;
441
442 intel_reference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]);
443}
444
445/**
446 * intel_unreference_shared_dpll_crtc - Drop a DPLL reference for a CRTC
447 * @crtc: CRTC on which behalf the reference is dropped
448 * @pll: DPLL for which the reference is dropped
449 * @shared_dpll_state: the DPLL atomic state in which the reference is tracked
450 *
451 * Drop a reference for @pll tracking the end of use of it by @crtc.
452 */
453void
454intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
455 const struct intel_shared_dpll *pll,
456 struct intel_shared_dpll_state *shared_dpll_state)
457{
458 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
459
460 drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);
461
462 shared_dpll_state->pipe_mask &= ~BIT(crtc->pipe);
463
464 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] releasing %s\n",
465 crtc->base.base.id, crtc->base.name, pll->info->name);
466}
467
468static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
469 const struct intel_crtc *crtc,
470 const struct intel_shared_dpll *pll)
471{
472 struct intel_shared_dpll_state *shared_dpll;
473
474 shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
475
476 intel_unreference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]);
477}
478
479static void intel_put_dpll(struct intel_atomic_state *state,
480 struct intel_crtc *crtc)
481{
482 const struct intel_crtc_state *old_crtc_state =
483 intel_atomic_get_old_crtc_state(state, crtc);
484 struct intel_crtc_state *new_crtc_state =
485 intel_atomic_get_new_crtc_state(state, crtc);
486
487 new_crtc_state->shared_dpll = NULL;
488
489 if (!old_crtc_state->shared_dpll)
490 return;
491
492 intel_unreference_shared_dpll(state, crtc, old_crtc_state->shared_dpll);
493}
494
495/**
496 * intel_shared_dpll_swap_state - make atomic DPLL configuration effective
497 * @state: atomic state
498 *
499 * This is the dpll version of drm_atomic_helper_swap_state() since the
500 * helper does not handle driver-specific global state.
501 *
502 * For consistency with atomic helpers this function does a complete swap,
503 * i.e. it also puts the current state into @state, even though there is no
504 * need for that at this moment.
505 */
506void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
507{
508 struct drm_i915_private *i915 = to_i915(state->base.dev);
509 struct intel_shared_dpll_state *shared_dpll = state->shared_dpll;
510 struct intel_shared_dpll *pll;
511 int i;
512
513 if (!state->dpll_set)
514 return;
515
516 for_each_shared_dpll(i915, pll, i)
517 swap(pll->state, shared_dpll[pll->index]);
518}
519
520static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *i915,
521 struct intel_shared_dpll *pll,
522 struct intel_dpll_hw_state *hw_state)
523{
524 const enum intel_dpll_id id = pll->info->id;
525 intel_wakeref_t wakeref;
526 u32 val;
527
528 wakeref = intel_display_power_get_if_enabled(i915,
529 POWER_DOMAIN_DISPLAY_CORE);
530 if (!wakeref)
531 return false;
532
533 val = intel_de_read(i915, PCH_DPLL(id));
534 hw_state->dpll = val;
535 hw_state->fp0 = intel_de_read(i915, PCH_FP0(id));
536 hw_state->fp1 = intel_de_read(i915, PCH_FP1(id));
537
538 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref);
539
540 return val & DPLL_VCO_ENABLE;
541}
542
543static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *i915)
544{
545 u32 val;
546 bool enabled;
547
548 val = intel_de_read(i915, PCH_DREF_CONTROL);
549 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
550 DREF_SUPERSPREAD_SOURCE_MASK));
551 I915_STATE_WARN(i915, !enabled,
552 "PCH refclk assertion failure, should be active but is disabled\n");
553}
554
555static void ibx_pch_dpll_enable(struct drm_i915_private *i915,
556 struct intel_shared_dpll *pll)
557{
558 const enum intel_dpll_id id = pll->info->id;
559
560 /* PCH refclock must be enabled first */
561 ibx_assert_pch_refclk_enabled(i915);
562
563 intel_de_write(i915, PCH_FP0(id), pll->state.hw_state.fp0);
564 intel_de_write(i915, PCH_FP1(id), pll->state.hw_state.fp1);
565
566 intel_de_write(i915, PCH_DPLL(id), pll->state.hw_state.dpll);
567
568 /* Wait for the clocks to stabilize. */
569 intel_de_posting_read(i915, PCH_DPLL(id));
570 udelay(150);
571
572 /* The pixel multiplier can only be updated once the
573 * DPLL is enabled and the clocks are stable.
574 *
575 * So write it again.
576 */
577 intel_de_write(i915, PCH_DPLL(id), pll->state.hw_state.dpll);
578 intel_de_posting_read(i915, PCH_DPLL(id));
579 udelay(200);
580}
581
582static void ibx_pch_dpll_disable(struct drm_i915_private *i915,
583 struct intel_shared_dpll *pll)
584{
585 const enum intel_dpll_id id = pll->info->id;
586
587 intel_de_write(i915, PCH_DPLL(id), 0);
588 intel_de_posting_read(i915, PCH_DPLL(id));
589 udelay(200);
590}
591
592static int ibx_compute_dpll(struct intel_atomic_state *state,
593 struct intel_crtc *crtc,
594 struct intel_encoder *encoder)
595{
596 return 0;
597}
598
599static int ibx_get_dpll(struct intel_atomic_state *state,
600 struct intel_crtc *crtc,
601 struct intel_encoder *encoder)
602{
603 struct intel_crtc_state *crtc_state =
604 intel_atomic_get_new_crtc_state(state, crtc);
605 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
606 struct intel_shared_dpll *pll;
607 enum intel_dpll_id id;
608
609 if (HAS_PCH_IBX(i915)) {
610 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
611 id = (enum intel_dpll_id) crtc->pipe;
612 pll = intel_get_shared_dpll_by_id(i915, id);
613
614 drm_dbg_kms(&i915->drm,
615 "[CRTC:%d:%s] using pre-allocated %s\n",
616 crtc->base.base.id, crtc->base.name,
617 pll->info->name);
618 } else {
619 pll = intel_find_shared_dpll(state, crtc,
620 &crtc_state->dpll_hw_state,
621 BIT(DPLL_ID_PCH_PLL_B) |
622 BIT(DPLL_ID_PCH_PLL_A));
623 }
624
625 if (!pll)
626 return -EINVAL;
627
628 /* reference the pll */
629 intel_reference_shared_dpll(state, crtc,
630 pll, &crtc_state->dpll_hw_state);
631
632 crtc_state->shared_dpll = pll;
633
634 return 0;
635}
636
637static void ibx_dump_hw_state(struct drm_i915_private *i915,
638 const struct intel_dpll_hw_state *hw_state)
639{
640 drm_dbg_kms(&i915->drm,
641 "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
642 "fp0: 0x%x, fp1: 0x%x\n",
643 hw_state->dpll,
644 hw_state->dpll_md,
645 hw_state->fp0,
646 hw_state->fp1);
647}
648
649static bool ibx_compare_hw_state(const struct intel_dpll_hw_state *a,
650 const struct intel_dpll_hw_state *b)
651{
652 return a->dpll == b->dpll &&
653 a->dpll_md == b->dpll_md &&
654 a->fp0 == b->fp0 &&
655 a->fp1 == b->fp1;
656}
657
658static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
659 .enable = ibx_pch_dpll_enable,
660 .disable = ibx_pch_dpll_disable,
661 .get_hw_state = ibx_pch_dpll_get_hw_state,
662};
663
664static const struct dpll_info pch_plls[] = {
665 { .name = "PCH DPLL A", .funcs = &ibx_pch_dpll_funcs, .id = DPLL_ID_PCH_PLL_A, },
666 { .name = "PCH DPLL B", .funcs = &ibx_pch_dpll_funcs, .id = DPLL_ID_PCH_PLL_B, },
667 {}
668};
669
670static const struct intel_dpll_mgr pch_pll_mgr = {
671 .dpll_info = pch_plls,
672 .compute_dplls = ibx_compute_dpll,
673 .get_dplls = ibx_get_dpll,
674 .put_dplls = intel_put_dpll,
675 .dump_hw_state = ibx_dump_hw_state,
676 .compare_hw_state = ibx_compare_hw_state,
677};
678
679static void hsw_ddi_wrpll_enable(struct drm_i915_private *i915,
680 struct intel_shared_dpll *pll)
681{
682 const enum intel_dpll_id id = pll->info->id;
683
684 intel_de_write(i915, WRPLL_CTL(id), pll->state.hw_state.wrpll);
685 intel_de_posting_read(i915, WRPLL_CTL(id));
686 udelay(20);
687}
688
689static void hsw_ddi_spll_enable(struct drm_i915_private *i915,
690 struct intel_shared_dpll *pll)
691{
692 intel_de_write(i915, SPLL_CTL, pll->state.hw_state.spll);
693 intel_de_posting_read(i915, SPLL_CTL);
694 udelay(20);
695}
696
697static void hsw_ddi_wrpll_disable(struct drm_i915_private *i915,
698 struct intel_shared_dpll *pll)
699{
700 const enum intel_dpll_id id = pll->info->id;
701
702 intel_de_rmw(i915, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0);
703 intel_de_posting_read(i915, WRPLL_CTL(id));
704
705 /*
706 * Try to set up the PCH reference clock once all DPLLs
707 * that depend on it have been shut down.
708 */
709 if (i915->display.dpll.pch_ssc_use & BIT(id))
710 intel_init_pch_refclk(i915);
711}
712
713static void hsw_ddi_spll_disable(struct drm_i915_private *i915,
714 struct intel_shared_dpll *pll)
715{
716 enum intel_dpll_id id = pll->info->id;
717
718 intel_de_rmw(i915, SPLL_CTL, SPLL_PLL_ENABLE, 0);
719 intel_de_posting_read(i915, SPLL_CTL);
720
721 /*
722 * Try to set up the PCH reference clock once all DPLLs
723 * that depend on it have been shut down.
724 */
725 if (i915->display.dpll.pch_ssc_use & BIT(id))
726 intel_init_pch_refclk(i915);
727}
728
729static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915,
730 struct intel_shared_dpll *pll,
731 struct intel_dpll_hw_state *hw_state)
732{
733 const enum intel_dpll_id id = pll->info->id;
734 intel_wakeref_t wakeref;
735 u32 val;
736
737 wakeref = intel_display_power_get_if_enabled(i915,
738 POWER_DOMAIN_DISPLAY_CORE);
739 if (!wakeref)
740 return false;
741
742 val = intel_de_read(i915, WRPLL_CTL(id));
743 hw_state->wrpll = val;
744
745 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref);
746
747 return val & WRPLL_PLL_ENABLE;
748}
749
750static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *i915,
751 struct intel_shared_dpll *pll,
752 struct intel_dpll_hw_state *hw_state)
753{
754 intel_wakeref_t wakeref;
755 u32 val;
756
757 wakeref = intel_display_power_get_if_enabled(i915,
758 POWER_DOMAIN_DISPLAY_CORE);
759 if (!wakeref)
760 return false;
761
762 val = intel_de_read(i915, SPLL_CTL);
763 hw_state->spll = val;
764
765 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref);
766
767 return val & SPLL_PLL_ENABLE;
768}
769
770#define LC_FREQ 2700
771#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
772
773#define P_MIN 2
774#define P_MAX 64
775#define P_INC 2
776
777/* Constraints for PLL good behavior */
778#define REF_MIN 48
779#define REF_MAX 400
780#define VCO_MIN 2400
781#define VCO_MAX 4800
782
783struct hsw_wrpll_rnp {
784 unsigned p, n2, r2;
785};
786
787static unsigned hsw_wrpll_get_budget_for_freq(int clock)
788{
789 switch (clock) {
790 case 25175000:
791 case 25200000:
792 case 27000000:
793 case 27027000:
794 case 37762500:
795 case 37800000:
796 case 40500000:
797 case 40541000:
798 case 54000000:
799 case 54054000:
800 case 59341000:
801 case 59400000:
802 case 72000000:
803 case 74176000:
804 case 74250000:
805 case 81000000:
806 case 81081000:
807 case 89012000:
808 case 89100000:
809 case 108000000:
810 case 108108000:
811 case 111264000:
812 case 111375000:
813 case 148352000:
814 case 148500000:
815 case 162000000:
816 case 162162000:
817 case 222525000:
818 case 222750000:
819 case 296703000:
820 case 297000000:
821 return 0;
822 case 233500000:
823 case 245250000:
824 case 247750000:
825 case 253250000:
826 case 298000000:
827 return 1500;
828 case 169128000:
829 case 169500000:
830 case 179500000:
831 case 202000000:
832 return 2000;
833 case 256250000:
834 case 262500000:
835 case 270000000:
836 case 272500000:
837 case 273750000:
838 case 280750000:
839 case 281250000:
840 case 286000000:
841 case 291750000:
842 return 4000;
843 case 267250000:
844 case 268500000:
845 return 5000;
846 default:
847 return 1000;
848 }
849}
850
851static void hsw_wrpll_update_rnp(u64 freq2k, unsigned int budget,
852 unsigned int r2, unsigned int n2,
853 unsigned int p,
854 struct hsw_wrpll_rnp *best)
855{
856 u64 a, b, c, d, diff, diff_best;
857
858 /* No best (r,n,p) yet */
859 if (best->p == 0) {
860 best->p = p;
861 best->n2 = n2;
862 best->r2 = r2;
863 return;
864 }
865
866 /*
867 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
868 * freq2k.
869 *
870 * delta = 1e6 *
871 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
872 * freq2k;
873 *
874 * and we would like delta <= budget.
875 *
876 * If the discrepancy is above the PPM-based budget, always prefer to
877 * improve upon the previous solution. However, if you're within the
878 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
879 */
880 a = freq2k * budget * p * r2;
881 b = freq2k * budget * best->p * best->r2;
882 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
883 diff_best = abs_diff(freq2k * best->p * best->r2,
884 LC_FREQ_2K * best->n2);
885 c = 1000000 * diff;
886 d = 1000000 * diff_best;
887
888 if (a < c && b < d) {
889 /* If both are above the budget, pick the closer */
890 if (best->p * best->r2 * diff < p * r2 * diff_best) {
891 best->p = p;
892 best->n2 = n2;
893 best->r2 = r2;
894 }
895 } else if (a >= c && b < d) {
896 /* If A is below the threshold but B is above it? Update. */
897 best->p = p;
898 best->n2 = n2;
899 best->r2 = r2;
900 } else if (a >= c && b >= d) {
901 /* Both are below the limit, so pick the higher n2/(r2*r2) */
902 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
903 best->p = p;
904 best->n2 = n2;
905 best->r2 = r2;
906 }
907 }
908 /* Otherwise a < c && b >= d, do nothing */
909}
910
911static void
912hsw_ddi_calculate_wrpll(int clock /* in Hz */,
913 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
914{
915 u64 freq2k;
916 unsigned p, n2, r2;
917 struct hsw_wrpll_rnp best = {};
918 unsigned budget;
919
920 freq2k = clock / 100;
921
922 budget = hsw_wrpll_get_budget_for_freq(clock);
923
924 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
925 * and directly pass the LC PLL to it. */
926 if (freq2k == 5400000) {
927 *n2_out = 2;
928 *p_out = 1;
929 *r2_out = 2;
930 return;
931 }
932
933 /*
934 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
935 * the WR PLL.
936 *
937 * We want R so that REF_MIN <= Ref <= REF_MAX.
938 * Injecting R2 = 2 * R gives:
939 * REF_MAX * r2 > LC_FREQ * 2 and
940 * REF_MIN * r2 < LC_FREQ * 2
941 *
942 * Which means the desired boundaries for r2 are:
943 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
944 *
945 */
946 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
947 r2 <= LC_FREQ * 2 / REF_MIN;
948 r2++) {
949
950 /*
951 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
952 *
953 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
954 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
955 * VCO_MAX * r2 > n2 * LC_FREQ and
956 * VCO_MIN * r2 < n2 * LC_FREQ)
957 *
958 * Which means the desired boundaries for n2 are:
959 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
960 */
961 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
962 n2 <= VCO_MAX * r2 / LC_FREQ;
963 n2++) {
964
965 for (p = P_MIN; p <= P_MAX; p += P_INC)
966 hsw_wrpll_update_rnp(freq2k, budget,
967 r2, n2, p, &best);
968 }
969 }
970
971 *n2_out = best.n2;
972 *p_out = best.p;
973 *r2_out = best.r2;
974}
975
976static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915,
977 const struct intel_shared_dpll *pll,
978 const struct intel_dpll_hw_state *pll_state)
979{
980 int refclk;
981 int n, p, r;
982 u32 wrpll = pll_state->wrpll;
983
984 switch (wrpll & WRPLL_REF_MASK) {
985 case WRPLL_REF_SPECIAL_HSW:
986 /* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */
987 if (IS_HASWELL(i915) && !IS_HASWELL_ULT(i915)) {
988 refclk = i915->display.dpll.ref_clks.nssc;
989 break;
990 }
991 fallthrough;
992 case WRPLL_REF_PCH_SSC:
993 /*
994 * We could calculate spread here, but our checking
995 * code only cares about 5% accuracy, and spread is a max of
996 * 0.5% downspread.
997 */
998 refclk = i915->display.dpll.ref_clks.ssc;
999 break;
1000 case WRPLL_REF_LCPLL:
1001 refclk = 2700000;
1002 break;
1003 default:
1004 MISSING_CASE(wrpll);
1005 return 0;
1006 }
1007
1008 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1009 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1010 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1011
1012 /* Convert to KHz, p & r have a fixed point portion */
1013 return (refclk * n / 10) / (p * r) * 2;
1014}
1015
1016static int
1017hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
1018 struct intel_crtc *crtc)
1019{
1020 struct drm_i915_private *i915 = to_i915(state->base.dev);
1021 struct intel_crtc_state *crtc_state =
1022 intel_atomic_get_new_crtc_state(state, crtc);
1023 unsigned int p, n2, r2;
1024
1025 hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p);
1026
1027 crtc_state->dpll_hw_state.wrpll =
1028 WRPLL_PLL_ENABLE | WRPLL_REF_LCPLL |
1029 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1030 WRPLL_DIVIDER_POST(p);
1031
1032 crtc_state->port_clock = hsw_ddi_wrpll_get_freq(i915, NULL,
1033 &crtc_state->dpll_hw_state);
1034
1035 return 0;
1036}
1037
1038static struct intel_shared_dpll *
1039hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
1040 struct intel_crtc *crtc)
1041{
1042 struct intel_crtc_state *crtc_state =
1043 intel_atomic_get_new_crtc_state(state, crtc);
1044
1045 return intel_find_shared_dpll(state, crtc,
1046 &crtc_state->dpll_hw_state,
1047 BIT(DPLL_ID_WRPLL2) |
1048 BIT(DPLL_ID_WRPLL1));
1049}
1050
1051static int
1052hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
1053{
1054 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1055 int clock = crtc_state->port_clock;
1056
1057 switch (clock / 2) {
1058 case 81000:
1059 case 135000:
1060 case 270000:
1061 return 0;
1062 default:
1063 drm_dbg_kms(&i915->drm, "Invalid clock for DP: %d\n",
1064 clock);
1065 return -EINVAL;
1066 }
1067}
1068
1069static struct intel_shared_dpll *
1070hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
1071{
1072 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1073 struct intel_shared_dpll *pll;
1074 enum intel_dpll_id pll_id;
1075 int clock = crtc_state->port_clock;
1076
1077 switch (clock / 2) {
1078 case 81000:
1079 pll_id = DPLL_ID_LCPLL_810;
1080 break;
1081 case 135000:
1082 pll_id = DPLL_ID_LCPLL_1350;
1083 break;
1084 case 270000:
1085 pll_id = DPLL_ID_LCPLL_2700;
1086 break;
1087 default:
1088 MISSING_CASE(clock / 2);
1089 return NULL;
1090 }
1091
1092 pll = intel_get_shared_dpll_by_id(i915, pll_id);
1093
1094 if (!pll)
1095 return NULL;
1096
1097 return pll;
1098}
1099
1100static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915,
1101 const struct intel_shared_dpll *pll,
1102 const struct intel_dpll_hw_state *pll_state)
1103{
1104 int link_clock = 0;
1105
1106 switch (pll->info->id) {
1107 case DPLL_ID_LCPLL_810:
1108 link_clock = 81000;
1109 break;
1110 case DPLL_ID_LCPLL_1350:
1111 link_clock = 135000;
1112 break;
1113 case DPLL_ID_LCPLL_2700:
1114 link_clock = 270000;
1115 break;
1116 default:
1117 drm_WARN(&i915->drm, 1, "bad port clock sel\n");
1118 break;
1119 }
1120
1121 return link_clock * 2;
1122}
1123
1124static int
1125hsw_ddi_spll_compute_dpll(struct intel_atomic_state *state,
1126 struct intel_crtc *crtc)
1127{
1128 struct intel_crtc_state *crtc_state =
1129 intel_atomic_get_new_crtc_state(state, crtc);
1130
1131 if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000))
1132 return -EINVAL;
1133
1134 crtc_state->dpll_hw_state.spll =
1135 SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;
1136
1137 return 0;
1138}
1139
1140static struct intel_shared_dpll *
1141hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
1142 struct intel_crtc *crtc)
1143{
1144 struct intel_crtc_state *crtc_state =
1145 intel_atomic_get_new_crtc_state(state, crtc);
1146
1147 return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state,
1148 BIT(DPLL_ID_SPLL));
1149}
1150
1151static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
1152 const struct intel_shared_dpll *pll,
1153 const struct intel_dpll_hw_state *pll_state)
1154{
1155 int link_clock = 0;
1156
1157 switch (pll_state->spll & SPLL_FREQ_MASK) {
1158 case SPLL_FREQ_810MHz:
1159 link_clock = 81000;
1160 break;
1161 case SPLL_FREQ_1350MHz:
1162 link_clock = 135000;
1163 break;
1164 case SPLL_FREQ_2700MHz:
1165 link_clock = 270000;
1166 break;
1167 default:
1168 drm_WARN(&i915->drm, 1, "bad spll freq\n");
1169 break;
1170 }
1171
1172 return link_clock * 2;
1173}
1174
1175static int hsw_compute_dpll(struct intel_atomic_state *state,
1176 struct intel_crtc *crtc,
1177 struct intel_encoder *encoder)
1178{
1179 struct intel_crtc_state *crtc_state =
1180 intel_atomic_get_new_crtc_state(state, crtc);
1181
1182 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1183 return hsw_ddi_wrpll_compute_dpll(state, crtc);
1184 else if (intel_crtc_has_dp_encoder(crtc_state))
1185 return hsw_ddi_lcpll_compute_dpll(crtc_state);
1186 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1187 return hsw_ddi_spll_compute_dpll(state, crtc);
1188 else
1189 return -EINVAL;
1190}
1191
1192static int hsw_get_dpll(struct intel_atomic_state *state,
1193 struct intel_crtc *crtc,
1194 struct intel_encoder *encoder)
1195{
1196 struct intel_crtc_state *crtc_state =
1197 intel_atomic_get_new_crtc_state(state, crtc);
1198 struct intel_shared_dpll *pll = NULL;
1199
1200 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1201 pll = hsw_ddi_wrpll_get_dpll(state, crtc);
1202 else if (intel_crtc_has_dp_encoder(crtc_state))
1203 pll = hsw_ddi_lcpll_get_dpll(crtc_state);
1204 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1205 pll = hsw_ddi_spll_get_dpll(state, crtc);
1206
1207 if (!pll)
1208 return -EINVAL;
1209
1210 intel_reference_shared_dpll(state, crtc,
1211 pll, &crtc_state->dpll_hw_state);
1212
1213 crtc_state->shared_dpll = pll;
1214
1215 return 0;
1216}
1217
1218static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915)
1219{
1220 i915->display.dpll.ref_clks.ssc = 135000;
1221 /* Non-SSC is only used on non-ULT HSW. */
1222 if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
1223 i915->display.dpll.ref_clks.nssc = 24000;
1224 else
1225 i915->display.dpll.ref_clks.nssc = 135000;
1226}
1227
1228static void hsw_dump_hw_state(struct drm_i915_private *i915,
1229 const struct intel_dpll_hw_state *hw_state)
1230{
1231 drm_dbg_kms(&i915->drm, "dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
1232 hw_state->wrpll, hw_state->spll);
1233}
1234
1235static bool hsw_compare_hw_state(const struct intel_dpll_hw_state *a,
1236 const struct intel_dpll_hw_state *b)
1237{
1238 return a->wrpll == b->wrpll &&
1239 a->spll == b->spll;
1240}
1241
1242static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
1243 .enable = hsw_ddi_wrpll_enable,
1244 .disable = hsw_ddi_wrpll_disable,
1245 .get_hw_state = hsw_ddi_wrpll_get_hw_state,
1246 .get_freq = hsw_ddi_wrpll_get_freq,
1247};
1248
1249static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
1250 .enable = hsw_ddi_spll_enable,
1251 .disable = hsw_ddi_spll_disable,
1252 .get_hw_state = hsw_ddi_spll_get_hw_state,
1253 .get_freq = hsw_ddi_spll_get_freq,
1254};
1255
1256static void hsw_ddi_lcpll_enable(struct drm_i915_private *i915,
1257 struct intel_shared_dpll *pll)
1258{
1259}
1260
1261static void hsw_ddi_lcpll_disable(struct drm_i915_private *i915,
1262 struct intel_shared_dpll *pll)
1263{
1264}
1265
1266static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *i915,
1267 struct intel_shared_dpll *pll,
1268 struct intel_dpll_hw_state *hw_state)
1269{
1270 return true;
1271}
1272
1273static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
1274 .enable = hsw_ddi_lcpll_enable,
1275 .disable = hsw_ddi_lcpll_disable,
1276 .get_hw_state = hsw_ddi_lcpll_get_hw_state,
1277 .get_freq = hsw_ddi_lcpll_get_freq,
1278};
1279
1280static const struct dpll_info hsw_plls[] = {
1281 { .name = "WRPLL 1", .funcs = &hsw_ddi_wrpll_funcs, .id = DPLL_ID_WRPLL1, },
1282 { .name = "WRPLL 2", .funcs = &hsw_ddi_wrpll_funcs, .id = DPLL_ID_WRPLL2, },
1283 { .name = "SPLL", .funcs = &hsw_ddi_spll_funcs, .id = DPLL_ID_SPLL, },
1284 { .name = "LCPLL 810", .funcs = &hsw_ddi_lcpll_funcs, .id = DPLL_ID_LCPLL_810,
1285 .always_on = true, },
1286 { .name = "LCPLL 1350", .funcs = &hsw_ddi_lcpll_funcs, .id = DPLL_ID_LCPLL_1350,
1287 .always_on = true, },
1288 { .name = "LCPLL 2700", .funcs = &hsw_ddi_lcpll_funcs, .id = DPLL_ID_LCPLL_2700,
1289 .always_on = true, },
1290 {}
1291};
1292
1293static const struct intel_dpll_mgr hsw_pll_mgr = {
1294 .dpll_info = hsw_plls,
1295 .compute_dplls = hsw_compute_dpll,
1296 .get_dplls = hsw_get_dpll,
1297 .put_dplls = intel_put_dpll,
1298 .update_ref_clks = hsw_update_dpll_ref_clks,
1299 .dump_hw_state = hsw_dump_hw_state,
1300 .compare_hw_state = hsw_compare_hw_state,
1301};
1302
1303struct skl_dpll_regs {
1304 i915_reg_t ctl, cfgcr1, cfgcr2;
1305};
1306
1307/* this array is indexed by the *shared* pll id */
1308static const struct skl_dpll_regs skl_dpll_regs[4] = {
1309 {
1310 /* DPLL 0 */
1311 .ctl = LCPLL1_CTL,
1312 /* DPLL 0 doesn't support HDMI mode */
1313 },
1314 {
1315 /* DPLL 1 */
1316 .ctl = LCPLL2_CTL,
1317 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
1318 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
1319 },
1320 {
1321 /* DPLL 2 */
1322 .ctl = WRPLL_CTL(0),
1323 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
1324 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
1325 },
1326 {
1327 /* DPLL 3 */
1328 .ctl = WRPLL_CTL(1),
1329 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
1330 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
1331 },
1332};
1333
1334static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *i915,
1335 struct intel_shared_dpll *pll)
1336{
1337 const enum intel_dpll_id id = pll->info->id;
1338
1339 intel_de_rmw(i915, DPLL_CTRL1,
1340 DPLL_CTRL1_HDMI_MODE(id) | DPLL_CTRL1_SSC(id) | DPLL_CTRL1_LINK_RATE_MASK(id),
1341 pll->state.hw_state.ctrl1 << (id * 6));
1342 intel_de_posting_read(i915, DPLL_CTRL1);
1343}
1344
1345static void skl_ddi_pll_enable(struct drm_i915_private *i915,
1346 struct intel_shared_dpll *pll)
1347{
1348 const struct skl_dpll_regs *regs = skl_dpll_regs;
1349 const enum intel_dpll_id id = pll->info->id;
1350
1351 skl_ddi_pll_write_ctrl1(i915, pll);
1352
1353 intel_de_write(i915, regs[id].cfgcr1, pll->state.hw_state.cfgcr1);
1354 intel_de_write(i915, regs[id].cfgcr2, pll->state.hw_state.cfgcr2);
1355 intel_de_posting_read(i915, regs[id].cfgcr1);
1356 intel_de_posting_read(i915, regs[id].cfgcr2);
1357
1358 /* the enable bit is always bit 31 */
1359 intel_de_rmw(i915, regs[id].ctl, 0, LCPLL_PLL_ENABLE);
1360
1361 if (intel_de_wait_for_set(i915, DPLL_STATUS, DPLL_LOCK(id), 5))
1362 drm_err(&i915->drm, "DPLL %d not locked\n", id);
1363}
1364
1365static void skl_ddi_dpll0_enable(struct drm_i915_private *i915,
1366 struct intel_shared_dpll *pll)
1367{
1368 skl_ddi_pll_write_ctrl1(i915, pll);
1369}
1370
1371static void skl_ddi_pll_disable(struct drm_i915_private *i915,
1372 struct intel_shared_dpll *pll)
1373{
1374 const struct skl_dpll_regs *regs = skl_dpll_regs;
1375 const enum intel_dpll_id id = pll->info->id;
1376
1377 /* the enable bit is always bit 31 */
1378 intel_de_rmw(i915, regs[id].ctl, LCPLL_PLL_ENABLE, 0);
1379 intel_de_posting_read(i915, regs[id].ctl);
1380}
1381
1382static void skl_ddi_dpll0_disable(struct drm_i915_private *i915,
1383 struct intel_shared_dpll *pll)
1384{
1385}
1386
1387static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915,
1388 struct intel_shared_dpll *pll,
1389 struct intel_dpll_hw_state *hw_state)
1390{
1391 u32 val;
1392 const struct skl_dpll_regs *regs = skl_dpll_regs;
1393 const enum intel_dpll_id id = pll->info->id;
1394 intel_wakeref_t wakeref;
1395 bool ret;
1396
1397 wakeref = intel_display_power_get_if_enabled(i915,
1398 POWER_DOMAIN_DISPLAY_CORE);
1399 if (!wakeref)
1400 return false;
1401
1402 ret = false;
1403
1404 val = intel_de_read(i915, regs[id].ctl);
1405 if (!(val & LCPLL_PLL_ENABLE))
1406 goto out;
1407
1408 val = intel_de_read(i915, DPLL_CTRL1);
1409 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
1410
1411 /* avoid reading back stale values if HDMI mode is not enabled */
1412 if (val & DPLL_CTRL1_HDMI_MODE(id)) {
1413 hw_state->cfgcr1 = intel_de_read(i915, regs[id].cfgcr1);
1414 hw_state->cfgcr2 = intel_de_read(i915, regs[id].cfgcr2);
1415 }
1416 ret = true;
1417
1418out:
1419 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref);
1420
1421 return ret;
1422}
1423
1424static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *i915,
1425 struct intel_shared_dpll *pll,
1426 struct intel_dpll_hw_state *hw_state)
1427{
1428 const struct skl_dpll_regs *regs = skl_dpll_regs;
1429 const enum intel_dpll_id id = pll->info->id;
1430 intel_wakeref_t wakeref;
1431 u32 val;
1432 bool ret;
1433
1434 wakeref = intel_display_power_get_if_enabled(i915,
1435 POWER_DOMAIN_DISPLAY_CORE);
1436 if (!wakeref)
1437 return false;
1438
1439 ret = false;
1440
1441 /* DPLL0 is always enabled since it drives CDCLK */
1442 val = intel_de_read(i915, regs[id].ctl);
1443 if (drm_WARN_ON(&i915->drm, !(val & LCPLL_PLL_ENABLE)))
1444 goto out;
1445
1446 val = intel_de_read(i915, DPLL_CTRL1);
1447 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
1448
1449 ret = true;
1450
1451out:
1452 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref);
1453
1454 return ret;
1455}
1456
1457struct skl_wrpll_context {
1458 u64 min_deviation; /* current minimal deviation */
1459 u64 central_freq; /* chosen central freq */
1460 u64 dco_freq; /* chosen dco freq */
1461 unsigned int p; /* chosen divider */
1462};
1463
1464/* DCO freq must be within +1%/-6% of the DCO central freq */
1465#define SKL_DCO_MAX_PDEVIATION 100
1466#define SKL_DCO_MAX_NDEVIATION 600
1467
1468static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1469 u64 central_freq,
1470 u64 dco_freq,
1471 unsigned int divider)
1472{
1473 u64 deviation;
1474
1475 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1476 central_freq);
1477
1478 /* positive deviation */
1479 if (dco_freq >= central_freq) {
1480 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1481 deviation < ctx->min_deviation) {
1482 ctx->min_deviation = deviation;
1483 ctx->central_freq = central_freq;
1484 ctx->dco_freq = dco_freq;
1485 ctx->p = divider;
1486 }
1487 /* negative deviation */
1488 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1489 deviation < ctx->min_deviation) {
1490 ctx->min_deviation = deviation;
1491 ctx->central_freq = central_freq;
1492 ctx->dco_freq = dco_freq;
1493 ctx->p = divider;
1494 }
1495}
1496
1497static void skl_wrpll_get_multipliers(unsigned int p,
1498 unsigned int *p0 /* out */,
1499 unsigned int *p1 /* out */,
1500 unsigned int *p2 /* out */)
1501{
1502 /* even dividers */
1503 if (p % 2 == 0) {
1504 unsigned int half = p / 2;
1505
1506 if (half == 1 || half == 2 || half == 3 || half == 5) {
1507 *p0 = 2;
1508 *p1 = 1;
1509 *p2 = half;
1510 } else if (half % 2 == 0) {
1511 *p0 = 2;
1512 *p1 = half / 2;
1513 *p2 = 2;
1514 } else if (half % 3 == 0) {
1515 *p0 = 3;
1516 *p1 = half / 3;
1517 *p2 = 2;
1518 } else if (half % 7 == 0) {
1519 *p0 = 7;
1520 *p1 = half / 7;
1521 *p2 = 2;
1522 }
1523 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1524 *p0 = 3;
1525 *p1 = 1;
1526 *p2 = p / 3;
1527 } else if (p == 5 || p == 7) {
1528 *p0 = p;
1529 *p1 = 1;
1530 *p2 = 1;
1531 } else if (p == 15) {
1532 *p0 = 3;
1533 *p1 = 1;
1534 *p2 = 5;
1535 } else if (p == 21) {
1536 *p0 = 7;
1537 *p1 = 1;
1538 *p2 = 3;
1539 } else if (p == 35) {
1540 *p0 = 7;
1541 *p1 = 1;
1542 *p2 = 5;
1543 }
1544}
1545
1546struct skl_wrpll_params {
1547 u32 dco_fraction;
1548 u32 dco_integer;
1549 u32 qdiv_ratio;
1550 u32 qdiv_mode;
1551 u32 kdiv;
1552 u32 pdiv;
1553 u32 central_freq;
1554};
1555
1556static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1557 u64 afe_clock,
1558 int ref_clock,
1559 u64 central_freq,
1560 u32 p0, u32 p1, u32 p2)
1561{
1562 u64 dco_freq;
1563
1564 switch (central_freq) {
1565 case 9600000000ULL:
1566 params->central_freq = 0;
1567 break;
1568 case 9000000000ULL:
1569 params->central_freq = 1;
1570 break;
1571 case 8400000000ULL:
1572 params->central_freq = 3;
1573 }
1574
1575 switch (p0) {
1576 case 1:
1577 params->pdiv = 0;
1578 break;
1579 case 2:
1580 params->pdiv = 1;
1581 break;
1582 case 3:
1583 params->pdiv = 2;
1584 break;
1585 case 7:
1586 params->pdiv = 4;
1587 break;
1588 default:
1589 WARN(1, "Incorrect PDiv\n");
1590 }
1591
1592 switch (p2) {
1593 case 5:
1594 params->kdiv = 0;
1595 break;
1596 case 2:
1597 params->kdiv = 1;
1598 break;
1599 case 3:
1600 params->kdiv = 2;
1601 break;
1602 case 1:
1603 params->kdiv = 3;
1604 break;
1605 default:
1606 WARN(1, "Incorrect KDiv\n");
1607 }
1608
1609 params->qdiv_ratio = p1;
1610 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1611
1612 dco_freq = p0 * p1 * p2 * afe_clock;
1613
1614 /*
1615 * Intermediate values are in Hz.
1616 * Divide by MHz to match bsepc
1617 */
1618 params->dco_integer = div_u64(dco_freq, ref_clock * KHz(1));
1619 params->dco_fraction =
1620 div_u64((div_u64(dco_freq, ref_clock / KHz(1)) -
1621 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
1622}
1623
1624static int
1625skl_ddi_calculate_wrpll(int clock /* in Hz */,
1626 int ref_clock,
1627 struct skl_wrpll_params *wrpll_params)
1628{
1629 static const u64 dco_central_freq[3] = { 8400000000ULL,
1630 9000000000ULL,
1631 9600000000ULL };
1632 static const u8 even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1633 24, 28, 30, 32, 36, 40, 42, 44,
1634 48, 52, 54, 56, 60, 64, 66, 68,
1635 70, 72, 76, 78, 80, 84, 88, 90,
1636 92, 96, 98 };
1637 static const u8 odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1638 static const struct {
1639 const u8 *list;
1640 int n_dividers;
1641 } dividers[] = {
1642 { even_dividers, ARRAY_SIZE(even_dividers) },
1643 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1644 };
1645 struct skl_wrpll_context ctx = {
1646 .min_deviation = U64_MAX,
1647 };
1648 unsigned int dco, d, i;
1649 unsigned int p0, p1, p2;
1650 u64 afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
1651
1652 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1653 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1654 for (i = 0; i < dividers[d].n_dividers; i++) {
1655 unsigned int p = dividers[d].list[i];
1656 u64 dco_freq = p * afe_clock;
1657
1658 skl_wrpll_try_divider(&ctx,
1659 dco_central_freq[dco],
1660 dco_freq,
1661 p);
1662 /*
1663 * Skip the remaining dividers if we're sure to
1664 * have found the definitive divider, we can't
1665 * improve a 0 deviation.
1666 */
1667 if (ctx.min_deviation == 0)
1668 goto skip_remaining_dividers;
1669 }
1670 }
1671
1672skip_remaining_dividers:
1673 /*
1674 * If a solution is found with an even divider, prefer
1675 * this one.
1676 */
1677 if (d == 0 && ctx.p)
1678 break;
1679 }
1680
1681 if (!ctx.p)
1682 return -EINVAL;
1683
1684 /*
1685 * gcc incorrectly analyses that these can be used without being
1686 * initialized. To be fair, it's hard to guess.
1687 */
1688 p0 = p1 = p2 = 0;
1689 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1690 skl_wrpll_params_populate(wrpll_params, afe_clock, ref_clock,
1691 ctx.central_freq, p0, p1, p2);
1692
1693 return 0;
1694}
1695
1696static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
1697 const struct intel_shared_dpll *pll,
1698 const struct intel_dpll_hw_state *pll_state)
1699{
1700 int ref_clock = i915->display.dpll.ref_clks.nssc;
1701 u32 p0, p1, p2, dco_freq;
1702
1703 p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1704 p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
1705
1706 if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1))
1707 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1708 else
1709 p1 = 1;
1710
1711
1712 switch (p0) {
1713 case DPLL_CFGCR2_PDIV_1:
1714 p0 = 1;
1715 break;
1716 case DPLL_CFGCR2_PDIV_2:
1717 p0 = 2;
1718 break;
1719 case DPLL_CFGCR2_PDIV_3:
1720 p0 = 3;
1721 break;
1722 case DPLL_CFGCR2_PDIV_7_INVALID:
1723 /*
1724 * Incorrect ASUS-Z170M BIOS setting, the HW seems to ignore bit#0,
1725 * handling it the same way as PDIV_7.
1726 */
1727 drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");
1728 fallthrough;
1729 case DPLL_CFGCR2_PDIV_7:
1730 p0 = 7;
1731 break;
1732 default:
1733 MISSING_CASE(p0);
1734 return 0;
1735 }
1736
1737 switch (p2) {
1738 case DPLL_CFGCR2_KDIV_5:
1739 p2 = 5;
1740 break;
1741 case DPLL_CFGCR2_KDIV_2:
1742 p2 = 2;
1743 break;
1744 case DPLL_CFGCR2_KDIV_3:
1745 p2 = 3;
1746 break;
1747 case DPLL_CFGCR2_KDIV_1:
1748 p2 = 1;
1749 break;
1750 default:
1751 MISSING_CASE(p2);
1752 return 0;
1753 }
1754
1755 dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) *
1756 ref_clock;
1757
1758 dco_freq += ((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) *
1759 ref_clock / 0x8000;
1760
1761 if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0))
1762 return 0;
1763
1764 return dco_freq / (p0 * p1 * p2 * 5);
1765}
1766
1767static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
1768{
1769 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1770 struct skl_wrpll_params wrpll_params = {};
1771 u32 ctrl1, cfgcr1, cfgcr2;
1772 int ret;
1773
1774 /*
1775 * See comment in intel_dpll_hw_state to understand why we always use 0
1776 * as the DPLL id in this function.
1777 */
1778 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1779
1780 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1781
1782 ret = skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000,
1783 i915->display.dpll.ref_clks.nssc, &wrpll_params);
1784 if (ret)
1785 return ret;
1786
1787 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1788 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1789 wrpll_params.dco_integer;
1790
1791 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1792 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1793 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1794 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1795 wrpll_params.central_freq;
1796
1797 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1798 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1799 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
1800
1801 crtc_state->port_clock = skl_ddi_wrpll_get_freq(i915, NULL,
1802 &crtc_state->dpll_hw_state);
1803
1804 return 0;
1805}
1806
1807static int
1808skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
1809{
1810 u32 ctrl1;
1811
1812 /*
1813 * See comment in intel_dpll_hw_state to understand why we always use 0
1814 * as the DPLL id in this function.
1815 */
1816 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1817 switch (crtc_state->port_clock / 2) {
1818 case 81000:
1819 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
1820 break;
1821 case 135000:
1822 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
1823 break;
1824 case 270000:
1825 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
1826 break;
1827 /* eDP 1.4 rates */
1828 case 162000:
1829 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0);
1830 break;
1831 case 108000:
1832 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
1833 break;
1834 case 216000:
1835 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
1836 break;
1837 }
1838
1839 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1840
1841 return 0;
1842}
1843
1844static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
1845 const struct intel_shared_dpll *pll,
1846 const struct intel_dpll_hw_state *pll_state)
1847{
1848 int link_clock = 0;
1849
1850 switch ((pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0)) >>
1851 DPLL_CTRL1_LINK_RATE_SHIFT(0)) {
1852 case DPLL_CTRL1_LINK_RATE_810:
1853 link_clock = 81000;
1854 break;
1855 case DPLL_CTRL1_LINK_RATE_1080:
1856 link_clock = 108000;
1857 break;
1858 case DPLL_CTRL1_LINK_RATE_1350:
1859 link_clock = 135000;
1860 break;
1861 case DPLL_CTRL1_LINK_RATE_1620:
1862 link_clock = 162000;
1863 break;
1864 case DPLL_CTRL1_LINK_RATE_2160:
1865 link_clock = 216000;
1866 break;
1867 case DPLL_CTRL1_LINK_RATE_2700:
1868 link_clock = 270000;
1869 break;
1870 default:
1871 drm_WARN(&i915->drm, 1, "Unsupported link rate\n");
1872 break;
1873 }
1874
1875 return link_clock * 2;
1876}
1877
1878static int skl_compute_dpll(struct intel_atomic_state *state,
1879 struct intel_crtc *crtc,
1880 struct intel_encoder *encoder)
1881{
1882 struct intel_crtc_state *crtc_state =
1883 intel_atomic_get_new_crtc_state(state, crtc);
1884
1885 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1886 return skl_ddi_hdmi_pll_dividers(crtc_state);
1887 else if (intel_crtc_has_dp_encoder(crtc_state))
1888 return skl_ddi_dp_set_dpll_hw_state(crtc_state);
1889 else
1890 return -EINVAL;
1891}
1892
1893static int skl_get_dpll(struct intel_atomic_state *state,
1894 struct intel_crtc *crtc,
1895 struct intel_encoder *encoder)
1896{
1897 struct intel_crtc_state *crtc_state =
1898 intel_atomic_get_new_crtc_state(state, crtc);
1899 struct intel_shared_dpll *pll;
1900
1901 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1902 pll = intel_find_shared_dpll(state, crtc,
1903 &crtc_state->dpll_hw_state,
1904 BIT(DPLL_ID_SKL_DPLL0));
1905 else
1906 pll = intel_find_shared_dpll(state, crtc,
1907 &crtc_state->dpll_hw_state,
1908 BIT(DPLL_ID_SKL_DPLL3) |
1909 BIT(DPLL_ID_SKL_DPLL2) |
1910 BIT(DPLL_ID_SKL_DPLL1));
1911 if (!pll)
1912 return -EINVAL;
1913
1914 intel_reference_shared_dpll(state, crtc,
1915 pll, &crtc_state->dpll_hw_state);
1916
1917 crtc_state->shared_dpll = pll;
1918
1919 return 0;
1920}
1921
1922static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
1923 const struct intel_shared_dpll *pll,
1924 const struct intel_dpll_hw_state *pll_state)
1925{
1926 /*
1927 * ctrl1 register is already shifted for each pll, just use 0 to get
1928 * the internal shift for each field
1929 */
1930 if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0))
1931 return skl_ddi_wrpll_get_freq(i915, pll, pll_state);
1932 else
1933 return skl_ddi_lcpll_get_freq(i915, pll, pll_state);
1934}
1935
1936static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
1937{
1938 /* No SSC ref */
1939 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref;
1940}
1941
1942static void skl_dump_hw_state(struct drm_i915_private *i915,
1943 const struct intel_dpll_hw_state *hw_state)
1944{
1945 drm_dbg_kms(&i915->drm, "dpll_hw_state: "
1946 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
1947 hw_state->ctrl1,
1948 hw_state->cfgcr1,
1949 hw_state->cfgcr2);
1950}
1951
1952static bool skl_compare_hw_state(const struct intel_dpll_hw_state *a,
1953 const struct intel_dpll_hw_state *b)
1954{
1955 return a->ctrl1 == b->ctrl1 &&
1956 a->cfgcr1 == b->cfgcr1 &&
1957 a->cfgcr2 == b->cfgcr2;
1958}
1959
1960static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
1961 .enable = skl_ddi_pll_enable,
1962 .disable = skl_ddi_pll_disable,
1963 .get_hw_state = skl_ddi_pll_get_hw_state,
1964 .get_freq = skl_ddi_pll_get_freq,
1965};
1966
1967static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
1968 .enable = skl_ddi_dpll0_enable,
1969 .disable = skl_ddi_dpll0_disable,
1970 .get_hw_state = skl_ddi_dpll0_get_hw_state,
1971 .get_freq = skl_ddi_pll_get_freq,
1972};
1973
1974static const struct dpll_info skl_plls[] = {
1975 { .name = "DPLL 0", .funcs = &skl_ddi_dpll0_funcs, .id = DPLL_ID_SKL_DPLL0,
1976 .always_on = true, },
1977 { .name = "DPLL 1", .funcs = &skl_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL1, },
1978 { .name = "DPLL 2", .funcs = &skl_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL2, },
1979 { .name = "DPLL 3", .funcs = &skl_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL3, },
1980 {}
1981};
1982
1983static const struct intel_dpll_mgr skl_pll_mgr = {
1984 .dpll_info = skl_plls,
1985 .compute_dplls = skl_compute_dpll,
1986 .get_dplls = skl_get_dpll,
1987 .put_dplls = intel_put_dpll,
1988 .update_ref_clks = skl_update_dpll_ref_clks,
1989 .dump_hw_state = skl_dump_hw_state,
1990 .compare_hw_state = skl_compare_hw_state,
1991};
1992
1993static void bxt_ddi_pll_enable(struct drm_i915_private *i915,
1994 struct intel_shared_dpll *pll)
1995{
1996 u32 temp;
1997 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
1998 enum dpio_phy phy;
1999 enum dpio_channel ch;
2000
2001 bxt_port_to_phy_channel(i915, port, &phy, &ch);
2002
2003 /* Non-SSC reference */
2004 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL);
2005
2006 if (IS_GEMINILAKE(i915)) {
2007 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port),
2008 0, PORT_PLL_POWER_ENABLE);
2009
2010 if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) &
2011 PORT_PLL_POWER_STATE), 200))
2012 drm_err(&i915->drm,
2013 "Power state not set for PLL:%d\n", port);
2014 }
2015
2016 /* Disable 10 bit clock */
2017 intel_de_rmw(i915, BXT_PORT_PLL_EBB_4(phy, ch),
2018 PORT_PLL_10BIT_CLK_ENABLE, 0);
2019
2020 /* Write P1 & P2 */
2021 intel_de_rmw(i915, BXT_PORT_PLL_EBB_0(phy, ch),
2022 PORT_PLL_P1_MASK | PORT_PLL_P2_MASK, pll->state.hw_state.ebb0);
2023
2024 /* Write M2 integer */
2025 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 0),
2026 PORT_PLL_M2_INT_MASK, pll->state.hw_state.pll0);
2027
2028 /* Write N */
2029 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 1),
2030 PORT_PLL_N_MASK, pll->state.hw_state.pll1);
2031
2032 /* Write M2 fraction */
2033 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 2),
2034 PORT_PLL_M2_FRAC_MASK, pll->state.hw_state.pll2);
2035
2036 /* Write M2 fraction enable */
2037 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 3),
2038 PORT_PLL_M2_FRAC_ENABLE, pll->state.hw_state.pll3);
2039
2040 /* Write coeff */
2041 temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6));
2042 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2043 temp &= ~PORT_PLL_INT_COEFF_MASK;
2044 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2045 temp |= pll->state.hw_state.pll6;
2046 intel_de_write(i915, BXT_PORT_PLL(phy, ch, 6), temp);
2047
2048 /* Write calibration val */
2049 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 8),
2050 PORT_PLL_TARGET_CNT_MASK, pll->state.hw_state.pll8);
2051
2052 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 9),
2053 PORT_PLL_LOCK_THRESHOLD_MASK, pll->state.hw_state.pll9);
2054
2055 temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10));
2056 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2057 temp &= ~PORT_PLL_DCO_AMP_MASK;
2058 temp |= pll->state.hw_state.pll10;
2059 intel_de_write(i915, BXT_PORT_PLL(phy, ch, 10), temp);
2060
2061 /* Recalibrate with new settings */
2062 temp = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch));
2063 temp |= PORT_PLL_RECALIBRATE;
2064 intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp);
2065 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2066 temp |= pll->state.hw_state.ebb4;
2067 intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp);
2068
2069 /* Enable PLL */
2070 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE);
2071 intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port));
2072
2073 if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),
2074 200))
2075 drm_err(&i915->drm, "PLL %d not locked\n", port);
2076
2077 if (IS_GEMINILAKE(i915)) {
2078 temp = intel_de_read(i915, BXT_PORT_TX_DW5_LN0(phy, ch));
2079 temp |= DCC_DELAY_RANGE_2;
2080 intel_de_write(i915, BXT_PORT_TX_DW5_GRP(phy, ch), temp);
2081 }
2082
2083 /*
2084 * While we write to the group register to program all lanes at once we
2085 * can read only lane registers and we pick lanes 0/1 for that.
2086 */
2087 temp = intel_de_read(i915, BXT_PORT_PCS_DW12_LN01(phy, ch));
2088 temp &= ~LANE_STAGGER_MASK;
2089 temp &= ~LANESTAGGER_STRAP_OVRD;
2090 temp |= pll->state.hw_state.pcsdw12;
2091 intel_de_write(i915, BXT_PORT_PCS_DW12_GRP(phy, ch), temp);
2092}
2093
2094static void bxt_ddi_pll_disable(struct drm_i915_private *i915,
2095 struct intel_shared_dpll *pll)
2096{
2097 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
2098
2099 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0);
2100 intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port));
2101
2102 if (IS_GEMINILAKE(i915)) {
2103 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port),
2104 PORT_PLL_POWER_ENABLE, 0);
2105
2106 if (wait_for_us(!(intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) &
2107 PORT_PLL_POWER_STATE), 200))
2108 drm_err(&i915->drm,
2109 "Power state not reset for PLL:%d\n", port);
2110 }
2111}
2112
2113static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915,
2114 struct intel_shared_dpll *pll,
2115 struct intel_dpll_hw_state *hw_state)
2116{
2117 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
2118 intel_wakeref_t wakeref;
2119 enum dpio_phy phy;
2120 enum dpio_channel ch;
2121 u32 val;
2122 bool ret;
2123
2124 bxt_port_to_phy_channel(i915, port, &phy, &ch);
2125
2126 wakeref = intel_display_power_get_if_enabled(i915,
2127 POWER_DOMAIN_DISPLAY_CORE);
2128 if (!wakeref)
2129 return false;
2130
2131 ret = false;
2132
2133 val = intel_de_read(i915, BXT_PORT_PLL_ENABLE(port));
2134 if (!(val & PORT_PLL_ENABLE))
2135 goto out;
2136
2137 hw_state->ebb0 = intel_de_read(i915, BXT_PORT_PLL_EBB_0(phy, ch));
2138 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
2139
2140 hw_state->ebb4 = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch));
2141 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
2142
2143 hw_state->pll0 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 0));
2144 hw_state->pll0 &= PORT_PLL_M2_INT_MASK;
2145
2146 hw_state->pll1 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 1));
2147 hw_state->pll1 &= PORT_PLL_N_MASK;
2148
2149 hw_state->pll2 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 2));
2150 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
2151
2152 hw_state->pll3 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 3));
2153 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
2154
2155 hw_state->pll6 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6));
2156 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
2157 PORT_PLL_INT_COEFF_MASK |
2158 PORT_PLL_GAIN_CTL_MASK;
2159
2160 hw_state->pll8 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 8));
2161 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
2162
2163 hw_state->pll9 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 9));
2164 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
2165
2166 hw_state->pll10 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10));
2167 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
2168 PORT_PLL_DCO_AMP_MASK;
2169
2170 /*
2171 * While we write to the group register to program all lanes at once we
2172 * can read only lane registers. We configure all lanes the same way, so
2173 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2174 */
2175 hw_state->pcsdw12 = intel_de_read(i915,
2176 BXT_PORT_PCS_DW12_LN01(phy, ch));
2177 if (intel_de_read(i915, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)
2178 drm_dbg(&i915->drm,
2179 "lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2180 hw_state->pcsdw12,
2181 intel_de_read(i915,
2182 BXT_PORT_PCS_DW12_LN23(phy, ch)));
2183 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
2184
2185 ret = true;
2186
2187out:
2188 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref);
2189
2190 return ret;
2191}
2192
2193/* pre-calculated values for DP linkrates */
2194static const struct dpll bxt_dp_clk_val[] = {
2195 /* m2 is .22 binary fixed point */
2196 { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
2197 { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },
2198 { .dot = 540000, .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },
2199 { .dot = 216000, .p1 = 3, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
2200 { .dot = 243000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6133333 /* 24.3 */ },
2201 { .dot = 324000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
2202 { .dot = 432000, .p1 = 3, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
2203};
2204
2205static int
2206bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
2207 struct dpll *clk_div)
2208{
2209 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2210
2211 /* Calculate HDMI div */
2212 /*
2213 * FIXME: tie the following calculation into
2214 * i9xx_crtc_compute_clock
2215 */
2216 if (!bxt_find_best_dpll(crtc_state, clk_div))
2217 return -EINVAL;
2218
2219 drm_WARN_ON(&i915->drm, clk_div->m1 != 2);
2220
2221 return 0;
2222}
2223
2224static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
2225 struct dpll *clk_div)
2226{
2227 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2228 int i;
2229
2230 *clk_div = bxt_dp_clk_val[0];
2231 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
2232 if (crtc_state->port_clock == bxt_dp_clk_val[i].dot) {
2233 *clk_div = bxt_dp_clk_val[i];
2234 break;
2235 }
2236 }
2237
2238 chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, clk_div);
2239
2240 drm_WARN_ON(&i915->drm, clk_div->vco == 0 ||
2241 clk_div->dot != crtc_state->port_clock);
2242}
2243
2244static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
2245 const struct dpll *clk_div)
2246{
2247 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2248 struct intel_dpll_hw_state *dpll_hw_state = &crtc_state->dpll_hw_state;
2249 int clock = crtc_state->port_clock;
2250 int vco = clk_div->vco;
2251 u32 prop_coef, int_coef, gain_ctl, targ_cnt;
2252 u32 lanestagger;
2253
2254 if (vco >= 6200000 && vco <= 6700000) {
2255 prop_coef = 4;
2256 int_coef = 9;
2257 gain_ctl = 3;
2258 targ_cnt = 8;
2259 } else if ((vco > 5400000 && vco < 6200000) ||
2260 (vco >= 4800000 && vco < 5400000)) {
2261 prop_coef = 5;
2262 int_coef = 11;
2263 gain_ctl = 3;
2264 targ_cnt = 9;
2265 } else if (vco == 5400000) {
2266 prop_coef = 3;
2267 int_coef = 8;
2268 gain_ctl = 1;
2269 targ_cnt = 9;
2270 } else {
2271 drm_err(&i915->drm, "Invalid VCO\n");
2272 return -EINVAL;
2273 }
2274
2275 if (clock > 270000)
2276 lanestagger = 0x18;
2277 else if (clock > 135000)
2278 lanestagger = 0x0d;
2279 else if (clock > 67000)
2280 lanestagger = 0x07;
2281 else if (clock > 33000)
2282 lanestagger = 0x04;
2283 else
2284 lanestagger = 0x02;
2285
2286 dpll_hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2);
2287 dpll_hw_state->pll0 = PORT_PLL_M2_INT(clk_div->m2 >> 22);
2288 dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n);
2289 dpll_hw_state->pll2 = PORT_PLL_M2_FRAC(clk_div->m2 & 0x3fffff);
2290
2291 if (clk_div->m2 & 0x3fffff)
2292 dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE;
2293
2294 dpll_hw_state->pll6 = PORT_PLL_PROP_COEFF(prop_coef) |
2295 PORT_PLL_INT_COEFF(int_coef) |
2296 PORT_PLL_GAIN_CTL(gain_ctl);
2297
2298 dpll_hw_state->pll8 = PORT_PLL_TARGET_CNT(targ_cnt);
2299
2300 dpll_hw_state->pll9 = PORT_PLL_LOCK_THRESHOLD(5);
2301
2302 dpll_hw_state->pll10 = PORT_PLL_DCO_AMP(15) |
2303 PORT_PLL_DCO_AMP_OVR_EN_H;
2304
2305 dpll_hw_state->ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
2306
2307 dpll_hw_state->pcsdw12 = LANESTAGGER_STRAP_OVRD | lanestagger;
2308
2309 return 0;
2310}
2311
2312static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
2313 const struct intel_shared_dpll *pll,
2314 const struct intel_dpll_hw_state *pll_state)
2315{
2316 struct dpll clock;
2317
2318 clock.m1 = 2;
2319 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, pll_state->pll0) << 22;
2320 if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
2321 clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK, pll_state->pll2);
2322 clock.n = REG_FIELD_GET(PORT_PLL_N_MASK, pll_state->pll1);
2323 clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, pll_state->ebb0);
2324 clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, pll_state->ebb0);
2325
2326 return chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, &clock);
2327}
2328
2329static int
2330bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
2331{
2332 struct dpll clk_div = {};
2333
2334 bxt_ddi_dp_pll_dividers(crtc_state, &clk_div);
2335
2336 return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
2337}
2338
2339static int
2340bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
2341{
2342 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2343 struct dpll clk_div = {};
2344 int ret;
2345
2346 bxt_ddi_hdmi_pll_dividers(crtc_state, &clk_div);
2347
2348 ret = bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
2349 if (ret)
2350 return ret;
2351
2352 crtc_state->port_clock = bxt_ddi_pll_get_freq(i915, NULL,
2353 &crtc_state->dpll_hw_state);
2354
2355 return 0;
2356}
2357
2358static int bxt_compute_dpll(struct intel_atomic_state *state,
2359 struct intel_crtc *crtc,
2360 struct intel_encoder *encoder)
2361{
2362 struct intel_crtc_state *crtc_state =
2363 intel_atomic_get_new_crtc_state(state, crtc);
2364
2365 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2366 return bxt_ddi_hdmi_set_dpll_hw_state(crtc_state);
2367 else if (intel_crtc_has_dp_encoder(crtc_state))
2368 return bxt_ddi_dp_set_dpll_hw_state(crtc_state);
2369 else
2370 return -EINVAL;
2371}
2372
2373static int bxt_get_dpll(struct intel_atomic_state *state,
2374 struct intel_crtc *crtc,
2375 struct intel_encoder *encoder)
2376{
2377 struct intel_crtc_state *crtc_state =
2378 intel_atomic_get_new_crtc_state(state, crtc);
2379 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2380 struct intel_shared_dpll *pll;
2381 enum intel_dpll_id id;
2382
2383 /* 1:1 mapping between ports and PLLs */
2384 id = (enum intel_dpll_id) encoder->port;
2385 pll = intel_get_shared_dpll_by_id(i915, id);
2386
2387 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] using pre-allocated %s\n",
2388 crtc->base.base.id, crtc->base.name, pll->info->name);
2389
2390 intel_reference_shared_dpll(state, crtc,
2391 pll, &crtc_state->dpll_hw_state);
2392
2393 crtc_state->shared_dpll = pll;
2394
2395 return 0;
2396}
2397
2398static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915)
2399{
2400 i915->display.dpll.ref_clks.ssc = 100000;
2401 i915->display.dpll.ref_clks.nssc = 100000;
2402 /* DSI non-SSC ref 19.2MHz */
2403}
2404
2405static void bxt_dump_hw_state(struct drm_i915_private *i915,
2406 const struct intel_dpll_hw_state *hw_state)
2407{
2408 drm_dbg_kms(&i915->drm, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
2409 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
2410 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
2411 hw_state->ebb0,
2412 hw_state->ebb4,
2413 hw_state->pll0,
2414 hw_state->pll1,
2415 hw_state->pll2,
2416 hw_state->pll3,
2417 hw_state->pll6,
2418 hw_state->pll8,
2419 hw_state->pll9,
2420 hw_state->pll10,
2421 hw_state->pcsdw12);
2422}
2423
2424static bool bxt_compare_hw_state(const struct intel_dpll_hw_state *a,
2425 const struct intel_dpll_hw_state *b)
2426{
2427 return a->ebb0 == b->ebb0 &&
2428 a->ebb4 == b->ebb4 &&
2429 a->pll0 == b->pll0 &&
2430 a->pll1 == b->pll1 &&
2431 a->pll2 == b->pll2 &&
2432 a->pll3 == b->pll3 &&
2433 a->pll6 == b->pll6 &&
2434 a->pll8 == b->pll8 &&
2435 a->pll10 == b->pll10 &&
2436 a->pcsdw12 == b->pcsdw12;
2437}
2438
2439static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
2440 .enable = bxt_ddi_pll_enable,
2441 .disable = bxt_ddi_pll_disable,
2442 .get_hw_state = bxt_ddi_pll_get_hw_state,
2443 .get_freq = bxt_ddi_pll_get_freq,
2444};
2445
2446static const struct dpll_info bxt_plls[] = {
2447 { .name = "PORT PLL A", .funcs = &bxt_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL0, },
2448 { .name = "PORT PLL B", .funcs = &bxt_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL1, },
2449 { .name = "PORT PLL C", .funcs = &bxt_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL2, },
2450 {}
2451};
2452
2453static const struct intel_dpll_mgr bxt_pll_mgr = {
2454 .dpll_info = bxt_plls,
2455 .compute_dplls = bxt_compute_dpll,
2456 .get_dplls = bxt_get_dpll,
2457 .put_dplls = intel_put_dpll,
2458 .update_ref_clks = bxt_update_dpll_ref_clks,
2459 .dump_hw_state = bxt_dump_hw_state,
2460 .compare_hw_state = bxt_compare_hw_state,
2461};
2462
2463static void icl_wrpll_get_multipliers(int bestdiv, int *pdiv,
2464 int *qdiv, int *kdiv)
2465{
2466 /* even dividers */
2467 if (bestdiv % 2 == 0) {
2468 if (bestdiv == 2) {
2469 *pdiv = 2;
2470 *qdiv = 1;
2471 *kdiv = 1;
2472 } else if (bestdiv % 4 == 0) {
2473 *pdiv = 2;
2474 *qdiv = bestdiv / 4;
2475 *kdiv = 2;
2476 } else if (bestdiv % 6 == 0) {
2477 *pdiv = 3;
2478 *qdiv = bestdiv / 6;
2479 *kdiv = 2;
2480 } else if (bestdiv % 5 == 0) {
2481 *pdiv = 5;
2482 *qdiv = bestdiv / 10;
2483 *kdiv = 2;
2484 } else if (bestdiv % 14 == 0) {
2485 *pdiv = 7;
2486 *qdiv = bestdiv / 14;
2487 *kdiv = 2;
2488 }
2489 } else {
2490 if (bestdiv == 3 || bestdiv == 5 || bestdiv == 7) {
2491 *pdiv = bestdiv;
2492 *qdiv = 1;
2493 *kdiv = 1;
2494 } else { /* 9, 15, 21 */
2495 *pdiv = bestdiv / 3;
2496 *qdiv = 1;
2497 *kdiv = 3;
2498 }
2499 }
2500}
2501
2502static void icl_wrpll_params_populate(struct skl_wrpll_params *params,
2503 u32 dco_freq, u32 ref_freq,
2504 int pdiv, int qdiv, int kdiv)
2505{
2506 u32 dco;
2507
2508 switch (kdiv) {
2509 case 1:
2510 params->kdiv = 1;
2511 break;
2512 case 2:
2513 params->kdiv = 2;
2514 break;
2515 case 3:
2516 params->kdiv = 4;
2517 break;
2518 default:
2519 WARN(1, "Incorrect KDiv\n");
2520 }
2521
2522 switch (pdiv) {
2523 case 2:
2524 params->pdiv = 1;
2525 break;
2526 case 3:
2527 params->pdiv = 2;
2528 break;
2529 case 5:
2530 params->pdiv = 4;
2531 break;
2532 case 7:
2533 params->pdiv = 8;
2534 break;
2535 default:
2536 WARN(1, "Incorrect PDiv\n");
2537 }
2538
2539 WARN_ON(kdiv != 2 && qdiv != 1);
2540
2541 params->qdiv_ratio = qdiv;
2542 params->qdiv_mode = (qdiv == 1) ? 0 : 1;
2543
2544 dco = div_u64((u64)dco_freq << 15, ref_freq);
2545
2546 params->dco_integer = dco >> 15;
2547 params->dco_fraction = dco & 0x7fff;
2548}
2549
2550/*
2551 * Display WA #22010492432: ehl, tgl, adl-s, adl-p
2552 * Program half of the nominal DCO divider fraction value.
2553 */
2554static bool
2555ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
2556{
2557 return ((IS_ELKHARTLAKE(i915) &&
2558 IS_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
2559 IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) &&
2560 i915->display.dpll.ref_clks.nssc == 38400;
2561}
2562
2563struct icl_combo_pll_params {
2564 int clock;
2565 struct skl_wrpll_params wrpll;
2566};
2567
2568/*
2569 * These values alrea already adjusted: they're the bits we write to the
2570 * registers, not the logical values.
2571 */
2572static const struct icl_combo_pll_params icl_dp_combo_pll_24MHz_values[] = {
2573 { 540000,
2574 { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [0]: 5.4 */
2575 .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2576 { 270000,
2577 { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [1]: 2.7 */
2578 .pdiv = 0x2 /* 3 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2579 { 162000,
2580 { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [2]: 1.62 */
2581 .pdiv = 0x4 /* 5 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2582 { 324000,
2583 { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [3]: 3.24 */
2584 .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2585 { 216000,
2586 { .dco_integer = 0x168, .dco_fraction = 0x0000, /* [4]: 2.16 */
2587 .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 1, .qdiv_ratio = 2, }, },
2588 { 432000,
2589 { .dco_integer = 0x168, .dco_fraction = 0x0000, /* [5]: 4.32 */
2590 .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2591 { 648000,
2592 { .dco_integer = 0x195, .dco_fraction = 0x0000, /* [6]: 6.48 */
2593 .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2594 { 810000,
2595 { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [7]: 8.1 */
2596 .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2597};
2598
2599
2600/* Also used for 38.4 MHz values. */
2601static const struct icl_combo_pll_params icl_dp_combo_pll_19_2MHz_values[] = {
2602 { 540000,
2603 { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [0]: 5.4 */
2604 .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2605 { 270000,
2606 { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [1]: 2.7 */
2607 .pdiv = 0x2 /* 3 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2608 { 162000,
2609 { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [2]: 1.62 */
2610 .pdiv = 0x4 /* 5 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2611 { 324000,
2612 { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [3]: 3.24 */
2613 .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2614 { 216000,
2615 { .dco_integer = 0x1C2, .dco_fraction = 0x0000, /* [4]: 2.16 */
2616 .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 1, .qdiv_ratio = 2, }, },
2617 { 432000,
2618 { .dco_integer = 0x1C2, .dco_fraction = 0x0000, /* [5]: 4.32 */
2619 .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2620 { 648000,
2621 { .dco_integer = 0x1FA, .dco_fraction = 0x2000, /* [6]: 6.48 */
2622 .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2623 { 810000,
2624 { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [7]: 8.1 */
2625 .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2626};
2627
2628static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = {
2629 .dco_integer = 0x151, .dco_fraction = 0x4000,
2630 .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0,
2631};
2632
2633static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values = {
2634 .dco_integer = 0x1A5, .dco_fraction = 0x7000,
2635 .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0,
2636};
2637
2638static const struct skl_wrpll_params tgl_tbt_pll_19_2MHz_values = {
2639 .dco_integer = 0x54, .dco_fraction = 0x3000,
2640 /* the following params are unused */
2641 .pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0,
2642};
2643
2644static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = {
2645 .dco_integer = 0x43, .dco_fraction = 0x4000,
2646 /* the following params are unused */
2647};
2648
2649static int icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
2650 struct skl_wrpll_params *pll_params)
2651{
2652 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2653 const struct icl_combo_pll_params *params =
2654 i915->display.dpll.ref_clks.nssc == 24000 ?
2655 icl_dp_combo_pll_24MHz_values :
2656 icl_dp_combo_pll_19_2MHz_values;
2657 int clock = crtc_state->port_clock;
2658 int i;
2659
2660 for (i = 0; i < ARRAY_SIZE(icl_dp_combo_pll_24MHz_values); i++) {
2661 if (clock == params[i].clock) {
2662 *pll_params = params[i].wrpll;
2663 return 0;
2664 }
2665 }
2666
2667 MISSING_CASE(clock);
2668 return -EINVAL;
2669}
2670
2671static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
2672 struct skl_wrpll_params *pll_params)
2673{
2674 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2675
2676 if (DISPLAY_VER(i915) >= 12) {
2677 switch (i915->display.dpll.ref_clks.nssc) {
2678 default:
2679 MISSING_CASE(i915->display.dpll.ref_clks.nssc);
2680 fallthrough;
2681 case 19200:
2682 case 38400:
2683 *pll_params = tgl_tbt_pll_19_2MHz_values;
2684 break;
2685 case 24000:
2686 *pll_params = tgl_tbt_pll_24MHz_values;
2687 break;
2688 }
2689 } else {
2690 switch (i915->display.dpll.ref_clks.nssc) {
2691 default:
2692 MISSING_CASE(i915->display.dpll.ref_clks.nssc);
2693 fallthrough;
2694 case 19200:
2695 case 38400:
2696 *pll_params = icl_tbt_pll_19_2MHz_values;
2697 break;
2698 case 24000:
2699 *pll_params = icl_tbt_pll_24MHz_values;
2700 break;
2701 }
2702 }
2703
2704 return 0;
2705}
2706
2707static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
2708 const struct intel_shared_dpll *pll,
2709 const struct intel_dpll_hw_state *pll_state)
2710{
2711 /*
2712 * The PLL outputs multiple frequencies at the same time, selection is
2713 * made at DDI clock mux level.
2714 */
2715 drm_WARN_ON(&i915->drm, 1);
2716
2717 return 0;
2718}
2719
2720static int icl_wrpll_ref_clock(struct drm_i915_private *i915)
2721{
2722 int ref_clock = i915->display.dpll.ref_clks.nssc;
2723
2724 /*
2725 * For ICL+, the spec states: if reference frequency is 38.4,
2726 * use 19.2 because the DPLL automatically divides that by 2.
2727 */
2728 if (ref_clock == 38400)
2729 ref_clock = 19200;
2730
2731 return ref_clock;
2732}
2733
2734static int
2735icl_calc_wrpll(struct intel_crtc_state *crtc_state,
2736 struct skl_wrpll_params *wrpll_params)
2737{
2738 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2739 int ref_clock = icl_wrpll_ref_clock(i915);
2740 u32 afe_clock = crtc_state->port_clock * 5;
2741 u32 dco_min = 7998000;
2742 u32 dco_max = 10000000;
2743 u32 dco_mid = (dco_min + dco_max) / 2;
2744 static const int dividers[] = { 2, 4, 6, 8, 10, 12, 14, 16,
2745 18, 20, 24, 28, 30, 32, 36, 40,
2746 42, 44, 48, 50, 52, 54, 56, 60,
2747 64, 66, 68, 70, 72, 76, 78, 80,
2748 84, 88, 90, 92, 96, 98, 100, 102,
2749 3, 5, 7, 9, 15, 21 };
2750 u32 dco, best_dco = 0, dco_centrality = 0;
2751 u32 best_dco_centrality = U32_MAX; /* Spec meaning of 999999 MHz */
2752 int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
2753
2754 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
2755 dco = afe_clock * dividers[d];
2756
2757 if (dco <= dco_max && dco >= dco_min) {
2758 dco_centrality = abs(dco - dco_mid);
2759
2760 if (dco_centrality < best_dco_centrality) {
2761 best_dco_centrality = dco_centrality;
2762 best_div = dividers[d];
2763 best_dco = dco;
2764 }
2765 }
2766 }
2767
2768 if (best_div == 0)
2769 return -EINVAL;
2770
2771 icl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
2772 icl_wrpll_params_populate(wrpll_params, best_dco, ref_clock,
2773 pdiv, qdiv, kdiv);
2774
2775 return 0;
2776}
2777
2778static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
2779 const struct intel_shared_dpll *pll,
2780 const struct intel_dpll_hw_state *pll_state)
2781{
2782 int ref_clock = icl_wrpll_ref_clock(i915);
2783 u32 dco_fraction;
2784 u32 p0, p1, p2, dco_freq;
2785
2786 p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
2787 p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
2788
2789 if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
2790 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
2791 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
2792 else
2793 p1 = 1;
2794
2795 switch (p0) {
2796 case DPLL_CFGCR1_PDIV_2:
2797 p0 = 2;
2798 break;
2799 case DPLL_CFGCR1_PDIV_3:
2800 p0 = 3;
2801 break;
2802 case DPLL_CFGCR1_PDIV_5:
2803 p0 = 5;
2804 break;
2805 case DPLL_CFGCR1_PDIV_7:
2806 p0 = 7;
2807 break;
2808 }
2809
2810 switch (p2) {
2811 case DPLL_CFGCR1_KDIV_1:
2812 p2 = 1;
2813 break;
2814 case DPLL_CFGCR1_KDIV_2:
2815 p2 = 2;
2816 break;
2817 case DPLL_CFGCR1_KDIV_3:
2818 p2 = 3;
2819 break;
2820 }
2821
2822 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
2823 ref_clock;
2824
2825 dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
2826 DPLL_CFGCR0_DCO_FRACTION_SHIFT;
2827
2828 if (ehl_combo_pll_div_frac_wa_needed(i915))
2829 dco_fraction *= 2;
2830
2831 dco_freq += (dco_fraction * ref_clock) / 0x8000;
2832
2833 if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0))
2834 return 0;
2835
2836 return dco_freq / (p0 * p1 * p2 * 5);
2837}
2838
2839static void icl_calc_dpll_state(struct drm_i915_private *i915,
2840 const struct skl_wrpll_params *pll_params,
2841 struct intel_dpll_hw_state *pll_state)
2842{
2843 u32 dco_fraction = pll_params->dco_fraction;
2844
2845 if (ehl_combo_pll_div_frac_wa_needed(i915))
2846 dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);
2847
2848 pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) |
2849 pll_params->dco_integer;
2850
2851 pll_state->cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params->qdiv_ratio) |
2852 DPLL_CFGCR1_QDIV_MODE(pll_params->qdiv_mode) |
2853 DPLL_CFGCR1_KDIV(pll_params->kdiv) |
2854 DPLL_CFGCR1_PDIV(pll_params->pdiv);
2855
2856 if (DISPLAY_VER(i915) >= 12)
2857 pll_state->cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;
2858 else
2859 pll_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
2860
2861 if (i915->display.vbt.override_afc_startup)
2862 pll_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->display.vbt.override_afc_startup_val);
2863}
2864
2865static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
2866 u32 *target_dco_khz,
2867 struct intel_dpll_hw_state *state,
2868 bool is_dkl)
2869{
2870 static const u8 div1_vals[] = { 7, 5, 3, 2 };
2871 u32 dco_min_freq, dco_max_freq;
2872 unsigned int i;
2873 int div2;
2874
2875 dco_min_freq = is_dp ? 8100000 : use_ssc ? 8000000 : 7992000;
2876 dco_max_freq = is_dp ? 8100000 : 10000000;
2877
2878 for (i = 0; i < ARRAY_SIZE(div1_vals); i++) {
2879 int div1 = div1_vals[i];
2880
2881 for (div2 = 10; div2 > 0; div2--) {
2882 int dco = div1 * div2 * clock_khz * 5;
2883 int a_divratio, tlinedrv, inputsel;
2884 u32 hsdiv;
2885
2886 if (dco < dco_min_freq || dco > dco_max_freq)
2887 continue;
2888
2889 if (div2 >= 2) {
2890 /*
2891 * Note: a_divratio not matching TGL BSpec
2892 * algorithm but matching hardcoded values and
2893 * working on HW for DP alt-mode at least
2894 */
2895 a_divratio = is_dp ? 10 : 5;
2896 tlinedrv = is_dkl ? 1 : 2;
2897 } else {
2898 a_divratio = 5;
2899 tlinedrv = 0;
2900 }
2901 inputsel = is_dp ? 0 : 1;
2902
2903 switch (div1) {
2904 default:
2905 MISSING_CASE(div1);
2906 fallthrough;
2907 case 2:
2908 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2;
2909 break;
2910 case 3:
2911 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3;
2912 break;
2913 case 5:
2914 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5;
2915 break;
2916 case 7:
2917 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7;
2918 break;
2919 }
2920
2921 *target_dco_khz = dco;
2922
2923 state->mg_refclkin_ctl = MG_REFCLKIN_CTL_OD_2_MUX(1);
2924
2925 state->mg_clktop2_coreclkctl1 =
2926 MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(a_divratio);
2927
2928 state->mg_clktop2_hsclkctl =
2929 MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(tlinedrv) |
2930 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(inputsel) |
2931 hsdiv |
2932 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(div2);
2933
2934 return 0;
2935 }
2936 }
2937
2938 return -EINVAL;
2939}
2940
2941/*
2942 * The specification for this function uses real numbers, so the math had to be
2943 * adapted to integer-only calculation, that's why it looks so different.
2944 */
2945static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
2946 struct intel_dpll_hw_state *pll_state)
2947{
2948 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2949 int refclk_khz = i915->display.dpll.ref_clks.nssc;
2950 int clock = crtc_state->port_clock;
2951 u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
2952 u32 iref_ndiv, iref_trim, iref_pulse_w;
2953 u32 prop_coeff, int_coeff;
2954 u32 tdc_targetcnt, feedfwgain;
2955 u64 ssc_stepsize, ssc_steplen, ssc_steplog;
2956 u64 tmp;
2957 bool use_ssc = false;
2958 bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
2959 bool is_dkl = DISPLAY_VER(i915) >= 12;
2960 int ret;
2961
2962 ret = icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
2963 pll_state, is_dkl);
2964 if (ret)
2965 return ret;
2966
2967 m1div = 2;
2968 m2div_int = dco_khz / (refclk_khz * m1div);
2969 if (m2div_int > 255) {
2970 if (!is_dkl) {
2971 m1div = 4;
2972 m2div_int = dco_khz / (refclk_khz * m1div);
2973 }
2974
2975 if (m2div_int > 255)
2976 return -EINVAL;
2977 }
2978 m2div_rem = dco_khz % (refclk_khz * m1div);
2979
2980 tmp = (u64)m2div_rem * (1 << 22);
2981 do_div(tmp, refclk_khz * m1div);
2982 m2div_frac = tmp;
2983
2984 switch (refclk_khz) {
2985 case 19200:
2986 iref_ndiv = 1;
2987 iref_trim = 28;
2988 iref_pulse_w = 1;
2989 break;
2990 case 24000:
2991 iref_ndiv = 1;
2992 iref_trim = 25;
2993 iref_pulse_w = 2;
2994 break;
2995 case 38400:
2996 iref_ndiv = 2;
2997 iref_trim = 28;
2998 iref_pulse_w = 1;
2999 break;
3000 default:
3001 MISSING_CASE(refclk_khz);
3002 return -EINVAL;
3003 }
3004
3005 /*
3006 * tdc_res = 0.000003
3007 * tdc_targetcnt = int(2 / (tdc_res * 8 * 50 * 1.1) / refclk_mhz + 0.5)
3008 *
3009 * The multiplication by 1000 is due to refclk MHz to KHz conversion. It
3010 * was supposed to be a division, but we rearranged the operations of
3011 * the formula to avoid early divisions so we don't multiply the
3012 * rounding errors.
3013 *
3014 * 0.000003 * 8 * 50 * 1.1 = 0.00132, also known as 132 / 100000, which
3015 * we also rearrange to work with integers.
3016 *
3017 * The 0.5 transformed to 5 results in a multiplication by 10 and the
3018 * last division by 10.
3019 */
3020 tdc_targetcnt = (2 * 1000 * 100000 * 10 / (132 * refclk_khz) + 5) / 10;
3021
3022 /*
3023 * Here we divide dco_khz by 10 in order to allow the dividend to fit in
3024 * 32 bits. That's not a problem since we round the division down
3025 * anyway.
3026 */
3027 feedfwgain = (use_ssc || m2div_rem > 0) ?
3028 m1div * 1000000 * 100 / (dco_khz * 3 / 10) : 0;
3029
3030 if (dco_khz >= 9000000) {
3031 prop_coeff = 5;
3032 int_coeff = 10;
3033 } else {
3034 prop_coeff = 4;
3035 int_coeff = 8;
3036 }
3037
3038 if (use_ssc) {
3039 tmp = mul_u32_u32(dco_khz, 47 * 32);
3040 do_div(tmp, refclk_khz * m1div * 10000);
3041 ssc_stepsize = tmp;
3042
3043 tmp = mul_u32_u32(dco_khz, 1000);
3044 ssc_steplen = DIV_ROUND_UP_ULL(tmp, 32 * 2 * 32);
3045 } else {
3046 ssc_stepsize = 0;
3047 ssc_steplen = 0;
3048 }
3049 ssc_steplog = 4;
3050
3051 /* write pll_state calculations */
3052 if (is_dkl) {
3053 pll_state->mg_pll_div0 = DKL_PLL_DIV0_INTEG_COEFF(int_coeff) |
3054 DKL_PLL_DIV0_PROP_COEFF(prop_coeff) |
3055 DKL_PLL_DIV0_FBPREDIV(m1div) |
3056 DKL_PLL_DIV0_FBDIV_INT(m2div_int);
3057 if (i915->display.vbt.override_afc_startup) {
3058 u8 val = i915->display.vbt.override_afc_startup_val;
3059
3060 pll_state->mg_pll_div0 |= DKL_PLL_DIV0_AFC_STARTUP(val);
3061 }
3062
3063 pll_state->mg_pll_div1 = DKL_PLL_DIV1_IREF_TRIM(iref_trim) |
3064 DKL_PLL_DIV1_TDC_TARGET_CNT(tdc_targetcnt);
3065
3066 pll_state->mg_pll_ssc = DKL_PLL_SSC_IREF_NDIV_RATIO(iref_ndiv) |
3067 DKL_PLL_SSC_STEP_LEN(ssc_steplen) |
3068 DKL_PLL_SSC_STEP_NUM(ssc_steplog) |
3069 (use_ssc ? DKL_PLL_SSC_EN : 0);
3070
3071 pll_state->mg_pll_bias = (m2div_frac ? DKL_PLL_BIAS_FRAC_EN_H : 0) |
3072 DKL_PLL_BIAS_FBDIV_FRAC(m2div_frac);
3073
3074 pll_state->mg_pll_tdc_coldst_bias =
3075 DKL_PLL_TDC_SSC_STEP_SIZE(ssc_stepsize) |
3076 DKL_PLL_TDC_FEED_FWD_GAIN(feedfwgain);
3077
3078 } else {
3079 pll_state->mg_pll_div0 =
3080 (m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H : 0) |
3081 MG_PLL_DIV0_FBDIV_FRAC(m2div_frac) |
3082 MG_PLL_DIV0_FBDIV_INT(m2div_int);
3083
3084 pll_state->mg_pll_div1 =
3085 MG_PLL_DIV1_IREF_NDIVRATIO(iref_ndiv) |
3086 MG_PLL_DIV1_DITHER_DIV_2 |
3087 MG_PLL_DIV1_NDIVRATIO(1) |
3088 MG_PLL_DIV1_FBPREDIV(m1div);
3089
3090 pll_state->mg_pll_lf =
3091 MG_PLL_LF_TDCTARGETCNT(tdc_targetcnt) |
3092 MG_PLL_LF_AFCCNTSEL_512 |
3093 MG_PLL_LF_GAINCTRL(1) |
3094 MG_PLL_LF_INT_COEFF(int_coeff) |
3095 MG_PLL_LF_PROP_COEFF(prop_coeff);
3096
3097 pll_state->mg_pll_frac_lock =
3098 MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 |
3099 MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 |
3100 MG_PLL_FRAC_LOCK_LOCKTHRESH(10) |
3101 MG_PLL_FRAC_LOCK_DCODITHEREN |
3102 MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(feedfwgain);
3103 if (use_ssc || m2div_rem > 0)
3104 pll_state->mg_pll_frac_lock |=
3105 MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN;
3106
3107 pll_state->mg_pll_ssc =
3108 (use_ssc ? MG_PLL_SSC_EN : 0) |
3109 MG_PLL_SSC_TYPE(2) |
3110 MG_PLL_SSC_STEPLENGTH(ssc_steplen) |
3111 MG_PLL_SSC_STEPNUM(ssc_steplog) |
3112 MG_PLL_SSC_FLLEN |
3113 MG_PLL_SSC_STEPSIZE(ssc_stepsize);
3114
3115 pll_state->mg_pll_tdc_coldst_bias =
3116 MG_PLL_TDC_COLDST_COLDSTART |
3117 MG_PLL_TDC_COLDST_IREFINT_EN |
3118 MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(iref_pulse_w) |
3119 MG_PLL_TDC_TDCOVCCORR_EN |
3120 MG_PLL_TDC_TDCSEL(3);
3121
3122 pll_state->mg_pll_bias =
3123 MG_PLL_BIAS_BIAS_GB_SEL(3) |
3124 MG_PLL_BIAS_INIT_DCOAMP(0x3F) |
3125 MG_PLL_BIAS_BIAS_BONUS(10) |
3126 MG_PLL_BIAS_BIASCAL_EN |
3127 MG_PLL_BIAS_CTRIM(12) |
3128 MG_PLL_BIAS_VREF_RDAC(4) |
3129 MG_PLL_BIAS_IREFTRIM(iref_trim);
3130
3131 if (refclk_khz == 38400) {
3132 pll_state->mg_pll_tdc_coldst_bias_mask =
3133 MG_PLL_TDC_COLDST_COLDSTART;
3134 pll_state->mg_pll_bias_mask = 0;
3135 } else {
3136 pll_state->mg_pll_tdc_coldst_bias_mask = -1U;
3137 pll_state->mg_pll_bias_mask = -1U;
3138 }
3139
3140 pll_state->mg_pll_tdc_coldst_bias &=
3141 pll_state->mg_pll_tdc_coldst_bias_mask;
3142 pll_state->mg_pll_bias &= pll_state->mg_pll_bias_mask;
3143 }
3144
3145 return 0;
3146}
3147
3148static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *i915,
3149 const struct intel_shared_dpll *pll,
3150 const struct intel_dpll_hw_state *pll_state)
3151{
3152 u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
3153 u64 tmp;
3154
3155 ref_clock = i915->display.dpll.ref_clks.nssc;
3156
3157 if (DISPLAY_VER(i915) >= 12) {
3158 m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
3159 m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT;
3160 m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK;
3161
3162 if (pll_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) {
3163 m2_frac = pll_state->mg_pll_bias &
3164 DKL_PLL_BIAS_FBDIV_FRAC_MASK;
3165 m2_frac = m2_frac >> DKL_PLL_BIAS_FBDIV_SHIFT;
3166 } else {
3167 m2_frac = 0;
3168 }
3169 } else {
3170 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
3171 m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
3172
3173 if (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) {
3174 m2_frac = pll_state->mg_pll_div0 &
3175 MG_PLL_DIV0_FBDIV_FRAC_MASK;
3176 m2_frac = m2_frac >> MG_PLL_DIV0_FBDIV_FRAC_SHIFT;
3177 } else {
3178 m2_frac = 0;
3179 }
3180 }
3181
3182 switch (pll_state->mg_clktop2_hsclkctl &
3183 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
3184 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
3185 div1 = 2;
3186 break;
3187 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
3188 div1 = 3;
3189 break;
3190 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
3191 div1 = 5;
3192 break;
3193 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
3194 div1 = 7;
3195 break;
3196 default:
3197 MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
3198 return 0;
3199 }
3200
3201 div2 = (pll_state->mg_clktop2_hsclkctl &
3202 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
3203 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
3204
3205 /* div2 value of 0 is same as 1 means no div */
3206 if (div2 == 0)
3207 div2 = 1;
3208
3209 /*
3210 * Adjust the original formula to delay the division by 2^22 in order to
3211 * minimize possible rounding errors.
3212 */
3213 tmp = (u64)m1 * m2_int * ref_clock +
3214 (((u64)m1 * m2_frac * ref_clock) >> 22);
3215 tmp = div_u64(tmp, 5 * div1 * div2);
3216
3217 return tmp;
3218}
3219
3220/**
3221 * icl_set_active_port_dpll - select the active port DPLL for a given CRTC
3222 * @crtc_state: state for the CRTC to select the DPLL for
3223 * @port_dpll_id: the active @port_dpll_id to select
3224 *
3225 * Select the given @port_dpll_id instance from the DPLLs reserved for the
3226 * CRTC.
3227 */
3228void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
3229 enum icl_port_dpll_id port_dpll_id)
3230{
3231 struct icl_port_dpll *port_dpll =
3232 &crtc_state->icl_port_dplls[port_dpll_id];
3233
3234 crtc_state->shared_dpll = port_dpll->pll;
3235 crtc_state->dpll_hw_state = port_dpll->hw_state;
3236}
3237
3238static void icl_update_active_dpll(struct intel_atomic_state *state,
3239 struct intel_crtc *crtc,
3240 struct intel_encoder *encoder)
3241{
3242 struct intel_crtc_state *crtc_state =
3243 intel_atomic_get_new_crtc_state(state, crtc);
3244 struct intel_digital_port *primary_port;
3245 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
3246
3247 primary_port = encoder->type == INTEL_OUTPUT_DP_MST ?
3248 enc_to_mst(encoder)->primary :
3249 enc_to_dig_port(encoder);
3250
3251 if (primary_port &&
3252 (intel_tc_port_in_dp_alt_mode(primary_port) ||
3253 intel_tc_port_in_legacy_mode(primary_port)))
3254 port_dpll_id = ICL_PORT_DPLL_MG_PHY;
3255
3256 icl_set_active_port_dpll(crtc_state, port_dpll_id);
3257}
3258
3259static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
3260 struct intel_crtc *crtc)
3261{
3262 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3263 struct intel_crtc_state *crtc_state =
3264 intel_atomic_get_new_crtc_state(state, crtc);
3265 struct icl_port_dpll *port_dpll =
3266 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
3267 struct skl_wrpll_params pll_params = {};
3268 int ret;
3269
3270 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
3271 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
3272 ret = icl_calc_wrpll(crtc_state, &pll_params);
3273 else
3274 ret = icl_calc_dp_combo_pll(crtc_state, &pll_params);
3275
3276 if (ret)
3277 return ret;
3278
3279 icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state);
3280
3281 /* this is mainly for the fastset check */
3282 icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
3283
3284 crtc_state->port_clock = icl_ddi_combo_pll_get_freq(i915, NULL,
3285 &port_dpll->hw_state);
3286
3287 return 0;
3288}
3289
3290static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
3291 struct intel_crtc *crtc,
3292 struct intel_encoder *encoder)
3293{
3294 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3295 struct intel_crtc_state *crtc_state =
3296 intel_atomic_get_new_crtc_state(state, crtc);
3297 struct icl_port_dpll *port_dpll =
3298 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
3299 enum port port = encoder->port;
3300 unsigned long dpll_mask;
3301
3302 if (IS_ALDERLAKE_S(i915)) {
3303 dpll_mask =
3304 BIT(DPLL_ID_DG1_DPLL3) |
3305 BIT(DPLL_ID_DG1_DPLL2) |
3306 BIT(DPLL_ID_ICL_DPLL1) |
3307 BIT(DPLL_ID_ICL_DPLL0);
3308 } else if (IS_DG1(i915)) {
3309 if (port == PORT_D || port == PORT_E) {
3310 dpll_mask =
3311 BIT(DPLL_ID_DG1_DPLL2) |
3312 BIT(DPLL_ID_DG1_DPLL3);
3313 } else {
3314 dpll_mask =
3315 BIT(DPLL_ID_DG1_DPLL0) |
3316 BIT(DPLL_ID_DG1_DPLL1);
3317 }
3318 } else if (IS_ROCKETLAKE(i915)) {
3319 dpll_mask =
3320 BIT(DPLL_ID_EHL_DPLL4) |
3321 BIT(DPLL_ID_ICL_DPLL1) |
3322 BIT(DPLL_ID_ICL_DPLL0);
3323 } else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
3324 port != PORT_A) {
3325 dpll_mask =
3326 BIT(DPLL_ID_EHL_DPLL4) |
3327 BIT(DPLL_ID_ICL_DPLL1) |
3328 BIT(DPLL_ID_ICL_DPLL0);
3329 } else {
3330 dpll_mask = BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0);
3331 }
3332
3333 /* Eliminate DPLLs from consideration if reserved by HTI */
3334 dpll_mask &= ~intel_hti_dpll_mask(i915);
3335
3336 port_dpll->pll = intel_find_shared_dpll(state, crtc,
3337 &port_dpll->hw_state,
3338 dpll_mask);
3339 if (!port_dpll->pll)
3340 return -EINVAL;
3341
3342 intel_reference_shared_dpll(state, crtc,
3343 port_dpll->pll, &port_dpll->hw_state);
3344
3345 icl_update_active_dpll(state, crtc, encoder);
3346
3347 return 0;
3348}
3349
3350static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
3351 struct intel_crtc *crtc)
3352{
3353 struct drm_i915_private *i915 = to_i915(state->base.dev);
3354 struct intel_crtc_state *crtc_state =
3355 intel_atomic_get_new_crtc_state(state, crtc);
3356 const struct intel_crtc_state *old_crtc_state =
3357 intel_atomic_get_old_crtc_state(state, crtc);
3358 struct icl_port_dpll *port_dpll =
3359 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
3360 struct skl_wrpll_params pll_params = {};
3361 int ret;
3362
3363 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
3364 ret = icl_calc_tbt_pll(crtc_state, &pll_params);
3365 if (ret)
3366 return ret;
3367
3368 icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state);
3369
3370 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
3371 ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
3372 if (ret)
3373 return ret;
3374
3375 /* this is mainly for the fastset check */
3376 if (old_crtc_state->shared_dpll &&
3377 old_crtc_state->shared_dpll->info->id == DPLL_ID_ICL_TBTPLL)
3378 icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
3379 else
3380 icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
3381
3382 crtc_state->port_clock = icl_ddi_mg_pll_get_freq(i915, NULL,
3383 &port_dpll->hw_state);
3384
3385 return 0;
3386}
3387
3388static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
3389 struct intel_crtc *crtc,
3390 struct intel_encoder *encoder)
3391{
3392 struct drm_i915_private *i915 = to_i915(state->base.dev);
3393 struct intel_crtc_state *crtc_state =
3394 intel_atomic_get_new_crtc_state(state, crtc);
3395 struct icl_port_dpll *port_dpll =
3396 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
3397 enum intel_dpll_id dpll_id;
3398 int ret;
3399
3400 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
3401 port_dpll->pll = intel_find_shared_dpll(state, crtc,
3402 &port_dpll->hw_state,
3403 BIT(DPLL_ID_ICL_TBTPLL));
3404 if (!port_dpll->pll)
3405 return -EINVAL;
3406 intel_reference_shared_dpll(state, crtc,
3407 port_dpll->pll, &port_dpll->hw_state);
3408
3409
3410 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
3411 dpll_id = icl_tc_port_to_pll_id(intel_port_to_tc(i915,
3412 encoder->port));
3413 port_dpll->pll = intel_find_shared_dpll(state, crtc,
3414 &port_dpll->hw_state,
3415 BIT(dpll_id));
3416 if (!port_dpll->pll) {
3417 ret = -EINVAL;
3418 goto err_unreference_tbt_pll;
3419 }
3420 intel_reference_shared_dpll(state, crtc,
3421 port_dpll->pll, &port_dpll->hw_state);
3422
3423 icl_update_active_dpll(state, crtc, encoder);
3424
3425 return 0;
3426
3427err_unreference_tbt_pll:
3428 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
3429 intel_unreference_shared_dpll(state, crtc, port_dpll->pll);
3430
3431 return ret;
3432}
3433
3434static int icl_compute_dplls(struct intel_atomic_state *state,
3435 struct intel_crtc *crtc,
3436 struct intel_encoder *encoder)
3437{
3438 struct drm_i915_private *i915 = to_i915(state->base.dev);
3439 enum phy phy = intel_port_to_phy(i915, encoder->port);
3440
3441 if (intel_phy_is_combo(i915, phy))
3442 return icl_compute_combo_phy_dpll(state, crtc);
3443 else if (intel_phy_is_tc(i915, phy))
3444 return icl_compute_tc_phy_dplls(state, crtc);
3445
3446 MISSING_CASE(phy);
3447
3448 return 0;
3449}
3450
3451static int icl_get_dplls(struct intel_atomic_state *state,
3452 struct intel_crtc *crtc,
3453 struct intel_encoder *encoder)
3454{
3455 struct drm_i915_private *i915 = to_i915(state->base.dev);
3456 enum phy phy = intel_port_to_phy(i915, encoder->port);
3457
3458 if (intel_phy_is_combo(i915, phy))
3459 return icl_get_combo_phy_dpll(state, crtc, encoder);
3460 else if (intel_phy_is_tc(i915, phy))
3461 return icl_get_tc_phy_dplls(state, crtc, encoder);
3462
3463 MISSING_CASE(phy);
3464
3465 return -EINVAL;
3466}
3467
3468static void icl_put_dplls(struct intel_atomic_state *state,
3469 struct intel_crtc *crtc)
3470{
3471 const struct intel_crtc_state *old_crtc_state =
3472 intel_atomic_get_old_crtc_state(state, crtc);
3473 struct intel_crtc_state *new_crtc_state =
3474 intel_atomic_get_new_crtc_state(state, crtc);
3475 enum icl_port_dpll_id id;
3476
3477 new_crtc_state->shared_dpll = NULL;
3478
3479 for (id = ICL_PORT_DPLL_DEFAULT; id < ICL_PORT_DPLL_COUNT; id++) {
3480 const struct icl_port_dpll *old_port_dpll =
3481 &old_crtc_state->icl_port_dplls[id];
3482 struct icl_port_dpll *new_port_dpll =
3483 &new_crtc_state->icl_port_dplls[id];
3484
3485 new_port_dpll->pll = NULL;
3486
3487 if (!old_port_dpll->pll)
3488 continue;
3489
3490 intel_unreference_shared_dpll(state, crtc, old_port_dpll->pll);
3491 }
3492}
3493
3494static bool mg_pll_get_hw_state(struct drm_i915_private *i915,
3495 struct intel_shared_dpll *pll,
3496 struct intel_dpll_hw_state *hw_state)
3497{
3498 const enum intel_dpll_id id = pll->info->id;
3499 enum tc_port tc_port = icl_pll_id_to_tc_port(id);
3500 intel_wakeref_t wakeref;
3501 bool ret = false;
3502 u32 val;
3503
3504 i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll);
3505
3506 wakeref = intel_display_power_get_if_enabled(i915,
3507 POWER_DOMAIN_DISPLAY_CORE);
3508 if (!wakeref)
3509 return false;
3510
3511 val = intel_de_read(i915, enable_reg);
3512 if (!(val & PLL_ENABLE))
3513 goto out;
3514
3515 hw_state->mg_refclkin_ctl = intel_de_read(i915,
3516 MG_REFCLKIN_CTL(tc_port));
3517 hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
3518
3519 hw_state->mg_clktop2_coreclkctl1 =
3520 intel_de_read(i915, MG_CLKTOP2_CORECLKCTL1(tc_port));
3521 hw_state->mg_clktop2_coreclkctl1 &=
3522 MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
3523
3524 hw_state->mg_clktop2_hsclkctl =
3525 intel_de_read(i915, MG_CLKTOP2_HSCLKCTL(tc_port));
3526 hw_state->mg_clktop2_hsclkctl &=
3527 MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
3528 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
3529 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
3530 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
3531
3532 hw_state->mg_pll_div0 = intel_de_read(i915, MG_PLL_DIV0(tc_port));
3533 hw_state->mg_pll_div1 = intel_de_read(i915, MG_PLL_DIV1(tc_port));
3534 hw_state->mg_pll_lf = intel_de_read(i915, MG_PLL_LF(tc_port));
3535 hw_state->mg_pll_frac_lock = intel_de_read(i915,
3536 MG_PLL_FRAC_LOCK(tc_port));
3537 hw_state->mg_pll_ssc = intel_de_read(i915, MG_PLL_SSC(tc_port));
3538
3539 hw_state->mg_pll_bias = intel_de_read(i915, MG_PLL_BIAS(tc_port));
3540 hw_state->mg_pll_tdc_coldst_bias =
3541 intel_de_read(i915, MG_PLL_TDC_COLDST_BIAS(tc_port));
3542
3543 if (i915->display.dpll.ref_clks.nssc == 38400) {
3544 hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
3545 hw_state->mg_pll_bias_mask = 0;
3546 } else {
3547 hw_state->mg_pll_tdc_coldst_bias_mask = -1U;
3548 hw_state->mg_pll_bias_mask = -1U;
3549 }
3550
3551 hw_state->mg_pll_tdc_coldst_bias &= hw_state->mg_pll_tdc_coldst_bias_mask;
3552 hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask;
3553
3554 ret = true;
3555out:
3556 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref);
3557 return ret;
3558}
3559
3560static bool dkl_pll_get_hw_state(struct drm_i915_private *i915,
3561 struct intel_shared_dpll *pll,
3562 struct intel_dpll_hw_state *hw_state)
3563{
3564 const enum intel_dpll_id id = pll->info->id;
3565 enum tc_port tc_port = icl_pll_id_to_tc_port(id);
3566 intel_wakeref_t wakeref;
3567 bool ret = false;
3568 u32 val;
3569
3570 wakeref = intel_display_power_get_if_enabled(i915,
3571 POWER_DOMAIN_DISPLAY_CORE);
3572 if (!wakeref)
3573 return false;
3574
3575 val = intel_de_read(i915, intel_tc_pll_enable_reg(i915, pll));
3576 if (!(val & PLL_ENABLE))
3577 goto out;
3578
3579 /*
3580 * All registers read here have the same HIP_INDEX_REG even though
3581 * they are on different building blocks
3582 */
3583 hw_state->mg_refclkin_ctl = intel_dkl_phy_read(i915,
3584 DKL_REFCLKIN_CTL(tc_port));
3585 hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
3586
3587 hw_state->mg_clktop2_hsclkctl =
3588 intel_dkl_phy_read(i915, DKL_CLKTOP2_HSCLKCTL(tc_port));
3589 hw_state->mg_clktop2_hsclkctl &=
3590 MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
3591 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
3592 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
3593 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
3594
3595 hw_state->mg_clktop2_coreclkctl1 =
3596 intel_dkl_phy_read(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port));
3597 hw_state->mg_clktop2_coreclkctl1 &=
3598 MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
3599
3600 hw_state->mg_pll_div0 = intel_dkl_phy_read(i915, DKL_PLL_DIV0(tc_port));
3601 val = DKL_PLL_DIV0_MASK;
3602 if (i915->display.vbt.override_afc_startup)
3603 val |= DKL_PLL_DIV0_AFC_STARTUP_MASK;
3604 hw_state->mg_pll_div0 &= val;
3605
3606 hw_state->mg_pll_div1 = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port));
3607 hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK |
3608 DKL_PLL_DIV1_TDC_TARGET_CNT_MASK);
3609
3610 hw_state->mg_pll_ssc = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port));
3611 hw_state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
3612 DKL_PLL_SSC_STEP_LEN_MASK |
3613 DKL_PLL_SSC_STEP_NUM_MASK |
3614 DKL_PLL_SSC_EN);
3615
3616 hw_state->mg_pll_bias = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port));
3617 hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H |
3618 DKL_PLL_BIAS_FBDIV_FRAC_MASK);
3619
3620 hw_state->mg_pll_tdc_coldst_bias =
3621 intel_dkl_phy_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port));
3622 hw_state->mg_pll_tdc_coldst_bias &= (DKL_PLL_TDC_SSC_STEP_SIZE_MASK |
3623 DKL_PLL_TDC_FEED_FWD_GAIN_MASK);
3624
3625 ret = true;
3626out:
3627 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref);
3628 return ret;
3629}
3630
3631static bool icl_pll_get_hw_state(struct drm_i915_private *i915,
3632 struct intel_shared_dpll *pll,
3633 struct intel_dpll_hw_state *hw_state,
3634 i915_reg_t enable_reg)
3635{
3636 const enum intel_dpll_id id = pll->info->id;
3637 intel_wakeref_t wakeref;
3638 bool ret = false;
3639 u32 val;
3640
3641 wakeref = intel_display_power_get_if_enabled(i915,
3642 POWER_DOMAIN_DISPLAY_CORE);
3643 if (!wakeref)
3644 return false;
3645
3646 val = intel_de_read(i915, enable_reg);
3647 if (!(val & PLL_ENABLE))
3648 goto out;
3649
3650 if (IS_ALDERLAKE_S(i915)) {
3651 hw_state->cfgcr0 = intel_de_read(i915, ADLS_DPLL_CFGCR0(id));
3652 hw_state->cfgcr1 = intel_de_read(i915, ADLS_DPLL_CFGCR1(id));
3653 } else if (IS_DG1(i915)) {
3654 hw_state->cfgcr0 = intel_de_read(i915, DG1_DPLL_CFGCR0(id));
3655 hw_state->cfgcr1 = intel_de_read(i915, DG1_DPLL_CFGCR1(id));
3656 } else if (IS_ROCKETLAKE(i915)) {
3657 hw_state->cfgcr0 = intel_de_read(i915,
3658 RKL_DPLL_CFGCR0(id));
3659 hw_state->cfgcr1 = intel_de_read(i915,
3660 RKL_DPLL_CFGCR1(id));
3661 } else if (DISPLAY_VER(i915) >= 12) {
3662 hw_state->cfgcr0 = intel_de_read(i915,
3663 TGL_DPLL_CFGCR0(id));
3664 hw_state->cfgcr1 = intel_de_read(i915,
3665 TGL_DPLL_CFGCR1(id));
3666 if (i915->display.vbt.override_afc_startup) {
3667 hw_state->div0 = intel_de_read(i915, TGL_DPLL0_DIV0(id));
3668 hw_state->div0 &= TGL_DPLL0_DIV0_AFC_STARTUP_MASK;
3669 }
3670 } else {
3671 if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
3672 id == DPLL_ID_EHL_DPLL4) {
3673 hw_state->cfgcr0 = intel_de_read(i915,
3674 ICL_DPLL_CFGCR0(4));
3675 hw_state->cfgcr1 = intel_de_read(i915,
3676 ICL_DPLL_CFGCR1(4));
3677 } else {
3678 hw_state->cfgcr0 = intel_de_read(i915,
3679 ICL_DPLL_CFGCR0(id));
3680 hw_state->cfgcr1 = intel_de_read(i915,
3681 ICL_DPLL_CFGCR1(id));
3682 }
3683 }
3684
3685 ret = true;
3686out:
3687 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref);
3688 return ret;
3689}
3690
3691static bool combo_pll_get_hw_state(struct drm_i915_private *i915,
3692 struct intel_shared_dpll *pll,
3693 struct intel_dpll_hw_state *hw_state)
3694{
3695 i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll);
3696
3697 return icl_pll_get_hw_state(i915, pll, hw_state, enable_reg);
3698}
3699
3700static bool tbt_pll_get_hw_state(struct drm_i915_private *i915,
3701 struct intel_shared_dpll *pll,
3702 struct intel_dpll_hw_state *hw_state)
3703{
3704 return icl_pll_get_hw_state(i915, pll, hw_state, TBT_PLL_ENABLE);
3705}
3706
3707static void icl_dpll_write(struct drm_i915_private *i915,
3708 struct intel_shared_dpll *pll)
3709{
3710 struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
3711 const enum intel_dpll_id id = pll->info->id;
3712 i915_reg_t cfgcr0_reg, cfgcr1_reg, div0_reg = INVALID_MMIO_REG;
3713
3714 if (IS_ALDERLAKE_S(i915)) {
3715 cfgcr0_reg = ADLS_DPLL_CFGCR0(id);
3716 cfgcr1_reg = ADLS_DPLL_CFGCR1(id);
3717 } else if (IS_DG1(i915)) {
3718 cfgcr0_reg = DG1_DPLL_CFGCR0(id);
3719 cfgcr1_reg = DG1_DPLL_CFGCR1(id);
3720 } else if (IS_ROCKETLAKE(i915)) {
3721 cfgcr0_reg = RKL_DPLL_CFGCR0(id);
3722 cfgcr1_reg = RKL_DPLL_CFGCR1(id);
3723 } else if (DISPLAY_VER(i915) >= 12) {
3724 cfgcr0_reg = TGL_DPLL_CFGCR0(id);
3725 cfgcr1_reg = TGL_DPLL_CFGCR1(id);
3726 div0_reg = TGL_DPLL0_DIV0(id);
3727 } else {
3728 if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
3729 id == DPLL_ID_EHL_DPLL4) {
3730 cfgcr0_reg = ICL_DPLL_CFGCR0(4);
3731 cfgcr1_reg = ICL_DPLL_CFGCR1(4);
3732 } else {
3733 cfgcr0_reg = ICL_DPLL_CFGCR0(id);
3734 cfgcr1_reg = ICL_DPLL_CFGCR1(id);
3735 }
3736 }
3737
3738 intel_de_write(i915, cfgcr0_reg, hw_state->cfgcr0);
3739 intel_de_write(i915, cfgcr1_reg, hw_state->cfgcr1);
3740 drm_WARN_ON_ONCE(&i915->drm, i915->display.vbt.override_afc_startup &&
3741 !i915_mmio_reg_valid(div0_reg));
3742 if (i915->display.vbt.override_afc_startup &&
3743 i915_mmio_reg_valid(div0_reg))
3744 intel_de_rmw(i915, div0_reg,
3745 TGL_DPLL0_DIV0_AFC_STARTUP_MASK, hw_state->div0);
3746 intel_de_posting_read(i915, cfgcr1_reg);
3747}
3748
3749static void icl_mg_pll_write(struct drm_i915_private *i915,
3750 struct intel_shared_dpll *pll)
3751{
3752 struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
3753 enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
3754
3755 /*
3756 * Some of the following registers have reserved fields, so program
3757 * these with RMW based on a mask. The mask can be fixed or generated
3758 * during the calc/readout phase if the mask depends on some other HW
3759 * state like refclk, see icl_calc_mg_pll_state().
3760 */
3761 intel_de_rmw(i915, MG_REFCLKIN_CTL(tc_port),
3762 MG_REFCLKIN_CTL_OD_2_MUX_MASK, hw_state->mg_refclkin_ctl);
3763
3764 intel_de_rmw(i915, MG_CLKTOP2_CORECLKCTL1(tc_port),
3765 MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK,
3766 hw_state->mg_clktop2_coreclkctl1);
3767
3768 intel_de_rmw(i915, MG_CLKTOP2_HSCLKCTL(tc_port),
3769 MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
3770 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
3771 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
3772 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK,
3773 hw_state->mg_clktop2_hsclkctl);
3774
3775 intel_de_write(i915, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0);
3776 intel_de_write(i915, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1);
3777 intel_de_write(i915, MG_PLL_LF(tc_port), hw_state->mg_pll_lf);
3778 intel_de_write(i915, MG_PLL_FRAC_LOCK(tc_port),
3779 hw_state->mg_pll_frac_lock);
3780 intel_de_write(i915, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc);
3781
3782 intel_de_rmw(i915, MG_PLL_BIAS(tc_port),
3783 hw_state->mg_pll_bias_mask, hw_state->mg_pll_bias);
3784
3785 intel_de_rmw(i915, MG_PLL_TDC_COLDST_BIAS(tc_port),
3786 hw_state->mg_pll_tdc_coldst_bias_mask,
3787 hw_state->mg_pll_tdc_coldst_bias);
3788
3789 intel_de_posting_read(i915, MG_PLL_TDC_COLDST_BIAS(tc_port));
3790}
3791
3792static void dkl_pll_write(struct drm_i915_private *i915,
3793 struct intel_shared_dpll *pll)
3794{
3795 struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
3796 enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
3797 u32 val;
3798
3799 /*
3800 * All registers programmed here have the same HIP_INDEX_REG even
3801 * though on different building block
3802 */
3803 /* All the registers are RMW */
3804 val = intel_dkl_phy_read(i915, DKL_REFCLKIN_CTL(tc_port));
3805 val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK;
3806 val |= hw_state->mg_refclkin_ctl;
3807 intel_dkl_phy_write(i915, DKL_REFCLKIN_CTL(tc_port), val);
3808
3809 val = intel_dkl_phy_read(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port));
3810 val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
3811 val |= hw_state->mg_clktop2_coreclkctl1;
3812 intel_dkl_phy_write(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port), val);
3813
3814 val = intel_dkl_phy_read(i915, DKL_CLKTOP2_HSCLKCTL(tc_port));
3815 val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
3816 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
3817 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
3818 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
3819 val |= hw_state->mg_clktop2_hsclkctl;
3820 intel_dkl_phy_write(i915, DKL_CLKTOP2_HSCLKCTL(tc_port), val);
3821
3822 val = DKL_PLL_DIV0_MASK;
3823 if (i915->display.vbt.override_afc_startup)
3824 val |= DKL_PLL_DIV0_AFC_STARTUP_MASK;
3825 intel_dkl_phy_rmw(i915, DKL_PLL_DIV0(tc_port), val,
3826 hw_state->mg_pll_div0);
3827
3828 val = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port));
3829 val &= ~(DKL_PLL_DIV1_IREF_TRIM_MASK |
3830 DKL_PLL_DIV1_TDC_TARGET_CNT_MASK);
3831 val |= hw_state->mg_pll_div1;
3832 intel_dkl_phy_write(i915, DKL_PLL_DIV1(tc_port), val);
3833
3834 val = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port));
3835 val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
3836 DKL_PLL_SSC_STEP_LEN_MASK |
3837 DKL_PLL_SSC_STEP_NUM_MASK |
3838 DKL_PLL_SSC_EN);
3839 val |= hw_state->mg_pll_ssc;
3840 intel_dkl_phy_write(i915, DKL_PLL_SSC(tc_port), val);
3841
3842 val = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port));
3843 val &= ~(DKL_PLL_BIAS_FRAC_EN_H |
3844 DKL_PLL_BIAS_FBDIV_FRAC_MASK);
3845 val |= hw_state->mg_pll_bias;
3846 intel_dkl_phy_write(i915, DKL_PLL_BIAS(tc_port), val);
3847
3848 val = intel_dkl_phy_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port));
3849 val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK |
3850 DKL_PLL_TDC_FEED_FWD_GAIN_MASK);
3851 val |= hw_state->mg_pll_tdc_coldst_bias;
3852 intel_dkl_phy_write(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port), val);
3853
3854 intel_dkl_phy_posting_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port));
3855}
3856
3857static void icl_pll_power_enable(struct drm_i915_private *i915,
3858 struct intel_shared_dpll *pll,
3859 i915_reg_t enable_reg)
3860{
3861 intel_de_rmw(i915, enable_reg, 0, PLL_POWER_ENABLE);
3862
3863 /*
3864 * The spec says we need to "wait" but it also says it should be
3865 * immediate.
3866 */
3867 if (intel_de_wait_for_set(i915, enable_reg, PLL_POWER_STATE, 1))
3868 drm_err(&i915->drm, "PLL %d Power not enabled\n",
3869 pll->info->id);
3870}
3871
3872static void icl_pll_enable(struct drm_i915_private *i915,
3873 struct intel_shared_dpll *pll,
3874 i915_reg_t enable_reg)
3875{
3876 intel_de_rmw(i915, enable_reg, 0, PLL_ENABLE);
3877
3878 /* Timeout is actually 600us. */
3879 if (intel_de_wait_for_set(i915, enable_reg, PLL_LOCK, 1))
3880 drm_err(&i915->drm, "PLL %d not locked\n", pll->info->id);
3881}
3882
3883static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct intel_shared_dpll *pll)
3884{
3885 u32 val;
3886
3887 if (!(IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) ||
3888 pll->info->id != DPLL_ID_ICL_DPLL0)
3889 return;
3890 /*
3891 * Wa_16011069516:adl-p[a0]
3892 *
3893 * All CMTG regs are unreliable until CMTG clock gating is disabled,
3894 * so we can only assume the default TRANS_CMTG_CHICKEN reg value and
3895 * sanity check this assumption with a double read, which presumably
3896 * returns the correct value even with clock gating on.
3897 *
3898 * Instead of the usual place for workarounds we apply this one here,
3899 * since TRANS_CMTG_CHICKEN is only accessible while DPLL0 is enabled.
3900 */
3901 val = intel_de_read(i915, TRANS_CMTG_CHICKEN);
3902 val = intel_de_rmw(i915, TRANS_CMTG_CHICKEN, ~0, DISABLE_DPT_CLK_GATING);
3903 if (drm_WARN_ON(&i915->drm, val & ~DISABLE_DPT_CLK_GATING))
3904 drm_dbg_kms(&i915->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val);
3905}
3906
3907static void combo_pll_enable(struct drm_i915_private *i915,
3908 struct intel_shared_dpll *pll)
3909{
3910 i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll);
3911
3912 icl_pll_power_enable(i915, pll, enable_reg);
3913
3914 icl_dpll_write(i915, pll);
3915
3916 /*
3917 * DVFS pre sequence would be here, but in our driver the cdclk code
3918 * paths should already be setting the appropriate voltage, hence we do
3919 * nothing here.
3920 */
3921
3922 icl_pll_enable(i915, pll, enable_reg);
3923
3924 adlp_cmtg_clock_gating_wa(i915, pll);
3925
3926 /* DVFS post sequence would be here. See the comment above. */
3927}
3928
3929static void tbt_pll_enable(struct drm_i915_private *i915,
3930 struct intel_shared_dpll *pll)
3931{
3932 icl_pll_power_enable(i915, pll, TBT_PLL_ENABLE);
3933
3934 icl_dpll_write(i915, pll);
3935
3936 /*
3937 * DVFS pre sequence would be here, but in our driver the cdclk code
3938 * paths should already be setting the appropriate voltage, hence we do
3939 * nothing here.
3940 */
3941
3942 icl_pll_enable(i915, pll, TBT_PLL_ENABLE);
3943
3944 /* DVFS post sequence would be here. See the comment above. */
3945}
3946
3947static void mg_pll_enable(struct drm_i915_private *i915,
3948 struct intel_shared_dpll *pll)
3949{
3950 i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll);
3951
3952 icl_pll_power_enable(i915, pll, enable_reg);
3953
3954 if (DISPLAY_VER(i915) >= 12)
3955 dkl_pll_write(i915, pll);
3956 else
3957 icl_mg_pll_write(i915, pll);
3958
3959 /*
3960 * DVFS pre sequence would be here, but in our driver the cdclk code
3961 * paths should already be setting the appropriate voltage, hence we do
3962 * nothing here.
3963 */
3964
3965 icl_pll_enable(i915, pll, enable_reg);
3966
3967 /* DVFS post sequence would be here. See the comment above. */
3968}
3969
3970static void icl_pll_disable(struct drm_i915_private *i915,
3971 struct intel_shared_dpll *pll,
3972 i915_reg_t enable_reg)
3973{
3974 /* The first steps are done by intel_ddi_post_disable(). */
3975
3976 /*
3977 * DVFS pre sequence would be here, but in our driver the cdclk code
3978 * paths should already be setting the appropriate voltage, hence we do
3979 * nothing here.
3980 */
3981
3982 intel_de_rmw(i915, enable_reg, PLL_ENABLE, 0);
3983
3984 /* Timeout is actually 1us. */
3985 if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 1))
3986 drm_err(&i915->drm, "PLL %d locked\n", pll->info->id);
3987
3988 /* DVFS post sequence would be here. See the comment above. */
3989
3990 intel_de_rmw(i915, enable_reg, PLL_POWER_ENABLE, 0);
3991
3992 /*
3993 * The spec says we need to "wait" but it also says it should be
3994 * immediate.
3995 */
3996 if (intel_de_wait_for_clear(i915, enable_reg, PLL_POWER_STATE, 1))
3997 drm_err(&i915->drm, "PLL %d Power not disabled\n",
3998 pll->info->id);
3999}
4000
4001static void combo_pll_disable(struct drm_i915_private *i915,
4002 struct intel_shared_dpll *pll)
4003{
4004 i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll);
4005
4006 icl_pll_disable(i915, pll, enable_reg);
4007}
4008
4009static void tbt_pll_disable(struct drm_i915_private *i915,
4010 struct intel_shared_dpll *pll)
4011{
4012 icl_pll_disable(i915, pll, TBT_PLL_ENABLE);
4013}
4014
4015static void mg_pll_disable(struct drm_i915_private *i915,
4016 struct intel_shared_dpll *pll)
4017{
4018 i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll);
4019
4020 icl_pll_disable(i915, pll, enable_reg);
4021}
4022
4023static void icl_update_dpll_ref_clks(struct drm_i915_private *i915)
4024{
4025 /* No SSC ref */
4026 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref;
4027}
4028
4029static void icl_dump_hw_state(struct drm_i915_private *i915,
4030 const struct intel_dpll_hw_state *hw_state)
4031{
4032 drm_dbg_kms(&i915->drm,
4033 "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, div0: 0x%x, "
4034 "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, "
4035 "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
4036 "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, "
4037 "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
4038 "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n",
4039 hw_state->cfgcr0, hw_state->cfgcr1,
4040 hw_state->div0,
4041 hw_state->mg_refclkin_ctl,
4042 hw_state->mg_clktop2_coreclkctl1,
4043 hw_state->mg_clktop2_hsclkctl,
4044 hw_state->mg_pll_div0,
4045 hw_state->mg_pll_div1,
4046 hw_state->mg_pll_lf,
4047 hw_state->mg_pll_frac_lock,
4048 hw_state->mg_pll_ssc,
4049 hw_state->mg_pll_bias,
4050 hw_state->mg_pll_tdc_coldst_bias);
4051}
4052
4053static bool icl_compare_hw_state(const struct intel_dpll_hw_state *a,
4054 const struct intel_dpll_hw_state *b)
4055{
4056 /* FIXME split combo vs. mg more thoroughly */
4057 return a->cfgcr0 == b->cfgcr0 &&
4058 a->cfgcr1 == b->cfgcr1 &&
4059 a->div0 == b->div0 &&
4060 a->mg_refclkin_ctl == b->mg_refclkin_ctl &&
4061 a->mg_clktop2_coreclkctl1 == b->mg_clktop2_coreclkctl1 &&
4062 a->mg_clktop2_hsclkctl == b->mg_clktop2_hsclkctl &&
4063 a->mg_pll_div0 == b->mg_pll_div0 &&
4064 a->mg_pll_div1 == b->mg_pll_div1 &&
4065 a->mg_pll_lf == b->mg_pll_lf &&
4066 a->mg_pll_frac_lock == b->mg_pll_frac_lock &&
4067 a->mg_pll_ssc == b->mg_pll_ssc &&
4068 a->mg_pll_bias == b->mg_pll_bias &&
4069 a->mg_pll_tdc_coldst_bias == b->mg_pll_tdc_coldst_bias;
4070}
4071
4072static const struct intel_shared_dpll_funcs combo_pll_funcs = {
4073 .enable = combo_pll_enable,
4074 .disable = combo_pll_disable,
4075 .get_hw_state = combo_pll_get_hw_state,
4076 .get_freq = icl_ddi_combo_pll_get_freq,
4077};
4078
4079static const struct intel_shared_dpll_funcs tbt_pll_funcs = {
4080 .enable = tbt_pll_enable,
4081 .disable = tbt_pll_disable,
4082 .get_hw_state = tbt_pll_get_hw_state,
4083 .get_freq = icl_ddi_tbt_pll_get_freq,
4084};
4085
4086static const struct intel_shared_dpll_funcs mg_pll_funcs = {
4087 .enable = mg_pll_enable,
4088 .disable = mg_pll_disable,
4089 .get_hw_state = mg_pll_get_hw_state,
4090 .get_freq = icl_ddi_mg_pll_get_freq,
4091};
4092
4093static const struct dpll_info icl_plls[] = {
4094 { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
4095 { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
4096 { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
4097 .is_alt_port_dpll = true, },
4098 { .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
4099 { .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
4100 { .name = "MG PLL 3", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
4101 { .name = "MG PLL 4", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
4102 {}
4103};
4104
4105static const struct intel_dpll_mgr icl_pll_mgr = {
4106 .dpll_info = icl_plls,
4107 .compute_dplls = icl_compute_dplls,
4108 .get_dplls = icl_get_dplls,
4109 .put_dplls = icl_put_dplls,
4110 .update_active_dpll = icl_update_active_dpll,
4111 .update_ref_clks = icl_update_dpll_ref_clks,
4112 .dump_hw_state = icl_dump_hw_state,
4113 .compare_hw_state = icl_compare_hw_state,
4114};
4115
4116static const struct dpll_info ehl_plls[] = {
4117 { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
4118 { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
4119 { .name = "DPLL 4", .funcs = &combo_pll_funcs, .id = DPLL_ID_EHL_DPLL4,
4120 .power_domain = POWER_DOMAIN_DC_OFF, },
4121 {}
4122};
4123
4124static const struct intel_dpll_mgr ehl_pll_mgr = {
4125 .dpll_info = ehl_plls,
4126 .compute_dplls = icl_compute_dplls,
4127 .get_dplls = icl_get_dplls,
4128 .put_dplls = icl_put_dplls,
4129 .update_ref_clks = icl_update_dpll_ref_clks,
4130 .dump_hw_state = icl_dump_hw_state,
4131 .compare_hw_state = icl_compare_hw_state,
4132};
4133
4134static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
4135 .enable = mg_pll_enable,
4136 .disable = mg_pll_disable,
4137 .get_hw_state = dkl_pll_get_hw_state,
4138 .get_freq = icl_ddi_mg_pll_get_freq,
4139};
4140
4141static const struct dpll_info tgl_plls[] = {
4142 { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
4143 { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
4144 { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
4145 .is_alt_port_dpll = true, },
4146 { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
4147 { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
4148 { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
4149 { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
4150 { .name = "TC PLL 5", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL5, },
4151 { .name = "TC PLL 6", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL6, },
4152 {}
4153};
4154
4155static const struct intel_dpll_mgr tgl_pll_mgr = {
4156 .dpll_info = tgl_plls,
4157 .compute_dplls = icl_compute_dplls,
4158 .get_dplls = icl_get_dplls,
4159 .put_dplls = icl_put_dplls,
4160 .update_active_dpll = icl_update_active_dpll,
4161 .update_ref_clks = icl_update_dpll_ref_clks,
4162 .dump_hw_state = icl_dump_hw_state,
4163 .compare_hw_state = icl_compare_hw_state,
4164};
4165
4166static const struct dpll_info rkl_plls[] = {
4167 { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
4168 { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
4169 { .name = "DPLL 4", .funcs = &combo_pll_funcs, .id = DPLL_ID_EHL_DPLL4, },
4170 {}
4171};
4172
4173static const struct intel_dpll_mgr rkl_pll_mgr = {
4174 .dpll_info = rkl_plls,
4175 .compute_dplls = icl_compute_dplls,
4176 .get_dplls = icl_get_dplls,
4177 .put_dplls = icl_put_dplls,
4178 .update_ref_clks = icl_update_dpll_ref_clks,
4179 .dump_hw_state = icl_dump_hw_state,
4180 .compare_hw_state = icl_compare_hw_state,
4181};
4182
4183static const struct dpll_info dg1_plls[] = {
4184 { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL0, },
4185 { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL1, },
4186 { .name = "DPLL 2", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL2, },
4187 { .name = "DPLL 3", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL3, },
4188 {}
4189};
4190
4191static const struct intel_dpll_mgr dg1_pll_mgr = {
4192 .dpll_info = dg1_plls,
4193 .compute_dplls = icl_compute_dplls,
4194 .get_dplls = icl_get_dplls,
4195 .put_dplls = icl_put_dplls,
4196 .update_ref_clks = icl_update_dpll_ref_clks,
4197 .dump_hw_state = icl_dump_hw_state,
4198 .compare_hw_state = icl_compare_hw_state,
4199};
4200
4201static const struct dpll_info adls_plls[] = {
4202 { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
4203 { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
4204 { .name = "DPLL 2", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL2, },
4205 { .name = "DPLL 3", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL3, },
4206 {}
4207};
4208
4209static const struct intel_dpll_mgr adls_pll_mgr = {
4210 .dpll_info = adls_plls,
4211 .compute_dplls = icl_compute_dplls,
4212 .get_dplls = icl_get_dplls,
4213 .put_dplls = icl_put_dplls,
4214 .update_ref_clks = icl_update_dpll_ref_clks,
4215 .dump_hw_state = icl_dump_hw_state,
4216 .compare_hw_state = icl_compare_hw_state,
4217};
4218
4219static const struct dpll_info adlp_plls[] = {
4220 { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
4221 { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
4222 { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
4223 .is_alt_port_dpll = true, },
4224 { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
4225 { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
4226 { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
4227 { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
4228 {}
4229};
4230
4231static const struct intel_dpll_mgr adlp_pll_mgr = {
4232 .dpll_info = adlp_plls,
4233 .compute_dplls = icl_compute_dplls,
4234 .get_dplls = icl_get_dplls,
4235 .put_dplls = icl_put_dplls,
4236 .update_active_dpll = icl_update_active_dpll,
4237 .update_ref_clks = icl_update_dpll_ref_clks,
4238 .dump_hw_state = icl_dump_hw_state,
4239 .compare_hw_state = icl_compare_hw_state,
4240};
4241
4242/**
4243 * intel_shared_dpll_init - Initialize shared DPLLs
4244 * @i915: i915 device
4245 *
4246 * Initialize shared DPLLs for @i915.
4247 */
4248void intel_shared_dpll_init(struct drm_i915_private *i915)
4249{
4250 const struct intel_dpll_mgr *dpll_mgr = NULL;
4251 const struct dpll_info *dpll_info;
4252 int i;
4253
4254 mutex_init(&i915->display.dpll.lock);
4255
4256 if (DISPLAY_VER(i915) >= 14 || IS_DG2(i915))
4257 /* No shared DPLLs on DG2; port PLLs are part of the PHY */
4258 dpll_mgr = NULL;
4259 else if (IS_ALDERLAKE_P(i915))
4260 dpll_mgr = &adlp_pll_mgr;
4261 else if (IS_ALDERLAKE_S(i915))
4262 dpll_mgr = &adls_pll_mgr;
4263 else if (IS_DG1(i915))
4264 dpll_mgr = &dg1_pll_mgr;
4265 else if (IS_ROCKETLAKE(i915))
4266 dpll_mgr = &rkl_pll_mgr;
4267 else if (DISPLAY_VER(i915) >= 12)
4268 dpll_mgr = &tgl_pll_mgr;
4269 else if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915))
4270 dpll_mgr = &ehl_pll_mgr;
4271 else if (DISPLAY_VER(i915) >= 11)
4272 dpll_mgr = &icl_pll_mgr;
4273 else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
4274 dpll_mgr = &bxt_pll_mgr;
4275 else if (DISPLAY_VER(i915) == 9)
4276 dpll_mgr = &skl_pll_mgr;
4277 else if (HAS_DDI(i915))
4278 dpll_mgr = &hsw_pll_mgr;
4279 else if (HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915))
4280 dpll_mgr = &pch_pll_mgr;
4281
4282 if (!dpll_mgr)
4283 return;
4284
4285 dpll_info = dpll_mgr->dpll_info;
4286
4287 for (i = 0; dpll_info[i].name; i++) {
4288 if (drm_WARN_ON(&i915->drm,
4289 i >= ARRAY_SIZE(i915->display.dpll.shared_dplls)))
4290 break;
4291
4292 /* must fit into unsigned long bitmask on 32bit */
4293 if (drm_WARN_ON(&i915->drm, dpll_info[i].id >= 32))
4294 break;
4295
4296 i915->display.dpll.shared_dplls[i].info = &dpll_info[i];
4297 i915->display.dpll.shared_dplls[i].index = i;
4298 }
4299
4300 i915->display.dpll.mgr = dpll_mgr;
4301 i915->display.dpll.num_shared_dpll = i;
4302}
4303
4304/**
4305 * intel_compute_shared_dplls - compute DPLL state CRTC and encoder combination
4306 * @state: atomic state
4307 * @crtc: CRTC to compute DPLLs for
4308 * @encoder: encoder
4309 *
4310 * This function computes the DPLL state for the given CRTC and encoder.
4311 *
4312 * The new configuration in the atomic commit @state is made effective by
4313 * calling intel_shared_dpll_swap_state().
4314 *
4315 * Returns:
4316 * 0 on success, negative error code on falure.
4317 */
4318int intel_compute_shared_dplls(struct intel_atomic_state *state,
4319 struct intel_crtc *crtc,
4320 struct intel_encoder *encoder)
4321{
4322 struct drm_i915_private *i915 = to_i915(state->base.dev);
4323 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr;
4324
4325 if (drm_WARN_ON(&i915->drm, !dpll_mgr))
4326 return -EINVAL;
4327
4328 return dpll_mgr->compute_dplls(state, crtc, encoder);
4329}
4330
4331/**
4332 * intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination
4333 * @state: atomic state
4334 * @crtc: CRTC to reserve DPLLs for
4335 * @encoder: encoder
4336 *
4337 * This function reserves all required DPLLs for the given CRTC and encoder
4338 * combination in the current atomic commit @state and the new @crtc atomic
4339 * state.
4340 *
4341 * The new configuration in the atomic commit @state is made effective by
4342 * calling intel_shared_dpll_swap_state().
4343 *
4344 * The reserved DPLLs should be released by calling
4345 * intel_release_shared_dplls().
4346 *
4347 * Returns:
4348 * 0 if all required DPLLs were successfully reserved,
4349 * negative error code otherwise.
4350 */
4351int intel_reserve_shared_dplls(struct intel_atomic_state *state,
4352 struct intel_crtc *crtc,
4353 struct intel_encoder *encoder)
4354{
4355 struct drm_i915_private *i915 = to_i915(state->base.dev);
4356 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr;
4357
4358 if (drm_WARN_ON(&i915->drm, !dpll_mgr))
4359 return -EINVAL;
4360
4361 return dpll_mgr->get_dplls(state, crtc, encoder);
4362}
4363
4364/**
4365 * intel_release_shared_dplls - end use of DPLLs by CRTC in atomic state
4366 * @state: atomic state
4367 * @crtc: crtc from which the DPLLs are to be released
4368 *
4369 * This function releases all DPLLs reserved by intel_reserve_shared_dplls()
4370 * from the current atomic commit @state and the old @crtc atomic state.
4371 *
4372 * The new configuration in the atomic commit @state is made effective by
4373 * calling intel_shared_dpll_swap_state().
4374 */
4375void intel_release_shared_dplls(struct intel_atomic_state *state,
4376 struct intel_crtc *crtc)
4377{
4378 struct drm_i915_private *i915 = to_i915(state->base.dev);
4379 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr;
4380
4381 /*
4382 * FIXME: this function is called for every platform having a
4383 * compute_clock hook, even though the platform doesn't yet support
4384 * the shared DPLL framework and intel_reserve_shared_dplls() is not
4385 * called on those.
4386 */
4387 if (!dpll_mgr)
4388 return;
4389
4390 dpll_mgr->put_dplls(state, crtc);
4391}
4392
4393/**
4394 * intel_update_active_dpll - update the active DPLL for a CRTC/encoder
4395 * @state: atomic state
4396 * @crtc: the CRTC for which to update the active DPLL
4397 * @encoder: encoder determining the type of port DPLL
4398 *
4399 * Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state,
4400 * from the port DPLLs reserved previously by intel_reserve_shared_dplls(). The
4401 * DPLL selected will be based on the current mode of the encoder's port.
4402 */
4403void intel_update_active_dpll(struct intel_atomic_state *state,
4404 struct intel_crtc *crtc,
4405 struct intel_encoder *encoder)
4406{
4407 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4408 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr;
4409
4410 if (drm_WARN_ON(&i915->drm, !dpll_mgr))
4411 return;
4412
4413 dpll_mgr->update_active_dpll(state, crtc, encoder);
4414}
4415
4416/**
4417 * intel_dpll_get_freq - calculate the DPLL's output frequency
4418 * @i915: i915 device
4419 * @pll: DPLL for which to calculate the output frequency
4420 * @pll_state: DPLL state from which to calculate the output frequency
4421 *
4422 * Return the output frequency corresponding to @pll's passed in @pll_state.
4423 */
4424int intel_dpll_get_freq(struct drm_i915_private *i915,
4425 const struct intel_shared_dpll *pll,
4426 const struct intel_dpll_hw_state *pll_state)
4427{
4428 if (drm_WARN_ON(&i915->drm, !pll->info->funcs->get_freq))
4429 return 0;
4430
4431 return pll->info->funcs->get_freq(i915, pll, pll_state);
4432}
4433
4434/**
4435 * intel_dpll_get_hw_state - readout the DPLL's hardware state
4436 * @i915: i915 device
4437 * @pll: DPLL for which to calculate the output frequency
4438 * @hw_state: DPLL's hardware state
4439 *
4440 * Read out @pll's hardware state into @hw_state.
4441 */
4442bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
4443 struct intel_shared_dpll *pll,
4444 struct intel_dpll_hw_state *hw_state)
4445{
4446 return pll->info->funcs->get_hw_state(i915, pll, hw_state);
4447}
4448
4449static void readout_dpll_hw_state(struct drm_i915_private *i915,
4450 struct intel_shared_dpll *pll)
4451{
4452 struct intel_crtc *crtc;
4453
4454 pll->on = intel_dpll_get_hw_state(i915, pll, &pll->state.hw_state);
4455
4456 if (pll->on && pll->info->power_domain)
4457 pll->wakeref = intel_display_power_get(i915, pll->info->power_domain);
4458
4459 pll->state.pipe_mask = 0;
4460 for_each_intel_crtc(&i915->drm, crtc) {
4461 struct intel_crtc_state *crtc_state =
4462 to_intel_crtc_state(crtc->base.state);
4463
4464 if (crtc_state->hw.active && crtc_state->shared_dpll == pll)
4465 intel_reference_shared_dpll_crtc(crtc, pll, &pll->state);
4466 }
4467 pll->active_mask = pll->state.pipe_mask;
4468
4469 drm_dbg_kms(&i915->drm,
4470 "%s hw state readout: pipe_mask 0x%x, on %i\n",
4471 pll->info->name, pll->state.pipe_mask, pll->on);
4472}
4473
4474void intel_dpll_update_ref_clks(struct drm_i915_private *i915)
4475{
4476 if (i915->display.dpll.mgr && i915->display.dpll.mgr->update_ref_clks)
4477 i915->display.dpll.mgr->update_ref_clks(i915);
4478}
4479
4480void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
4481{
4482 struct intel_shared_dpll *pll;
4483 int i;
4484
4485 for_each_shared_dpll(i915, pll, i)
4486 readout_dpll_hw_state(i915, pll);
4487}
4488
4489static void sanitize_dpll_state(struct drm_i915_private *i915,
4490 struct intel_shared_dpll *pll)
4491{
4492 if (!pll->on)
4493 return;
4494
4495 adlp_cmtg_clock_gating_wa(i915, pll);
4496
4497 if (pll->active_mask)
4498 return;
4499
4500 drm_dbg_kms(&i915->drm,
4501 "%s enabled but not in use, disabling\n",
4502 pll->info->name);
4503
4504 _intel_disable_shared_dpll(i915, pll);
4505}
4506
4507void intel_dpll_sanitize_state(struct drm_i915_private *i915)
4508{
4509 struct intel_shared_dpll *pll;
4510 int i;
4511
4512 for_each_shared_dpll(i915, pll, i)
4513 sanitize_dpll_state(i915, pll);
4514}
4515
4516/**
4517 * intel_dpll_dump_hw_state - write hw_state to dmesg
4518 * @i915: i915 drm device
4519 * @hw_state: hw state to be written to the log
4520 *
4521 * Write the relevant values in @hw_state to dmesg using drm_dbg_kms.
4522 */
4523void intel_dpll_dump_hw_state(struct drm_i915_private *i915,
4524 const struct intel_dpll_hw_state *hw_state)
4525{
4526 if (i915->display.dpll.mgr) {
4527 i915->display.dpll.mgr->dump_hw_state(i915, hw_state);
4528 } else {
4529 /* fallback for platforms that don't use the shared dpll
4530 * infrastructure
4531 */
4532 ibx_dump_hw_state(i915, hw_state);
4533 }
4534}
4535
4536/**
4537 * intel_dpll_compare_hw_state - compare the two states
4538 * @i915: i915 drm device
4539 * @a: first DPLL hw state
4540 * @b: second DPLL hw state
4541 *
4542 * Compare DPLL hw states @a and @b.
4543 *
4544 * Returns: true if the states are equal, false if the differ
4545 */
4546bool intel_dpll_compare_hw_state(struct drm_i915_private *i915,
4547 const struct intel_dpll_hw_state *a,
4548 const struct intel_dpll_hw_state *b)
4549{
4550 if (i915->display.dpll.mgr) {
4551 return i915->display.dpll.mgr->compare_hw_state(a, b);
4552 } else {
4553 /* fallback for platforms that don't use the shared dpll
4554 * infrastructure
4555 */
4556 return ibx_compare_hw_state(a, b);
4557 }
4558}
4559
4560static void
4561verify_single_dpll_state(struct drm_i915_private *i915,
4562 struct intel_shared_dpll *pll,
4563 struct intel_crtc *crtc,
4564 const struct intel_crtc_state *new_crtc_state)
4565{
4566 struct intel_dpll_hw_state dpll_hw_state = {};
4567 u8 pipe_mask;
4568 bool active;
4569
4570 active = intel_dpll_get_hw_state(i915, pll, &dpll_hw_state);
4571
4572 if (!pll->info->always_on) {
4573 I915_STATE_WARN(i915, !pll->on && pll->active_mask,
4574 "%s: pll in active use but not on in sw tracking\n",
4575 pll->info->name);
4576 I915_STATE_WARN(i915, pll->on && !pll->active_mask,
4577 "%s: pll is on but not used by any active pipe\n",
4578 pll->info->name);
4579 I915_STATE_WARN(i915, pll->on != active,
4580 "%s: pll on state mismatch (expected %i, found %i)\n",
4581 pll->info->name, pll->on, active);
4582 }
4583
4584 if (!crtc) {
4585 I915_STATE_WARN(i915,
4586 pll->active_mask & ~pll->state.pipe_mask,
4587 "%s: more active pll users than references: 0x%x vs 0x%x\n",
4588 pll->info->name, pll->active_mask, pll->state.pipe_mask);
4589
4590 return;
4591 }
4592
4593 pipe_mask = BIT(crtc->pipe);
4594
4595 if (new_crtc_state->hw.active)
4596 I915_STATE_WARN(i915, !(pll->active_mask & pipe_mask),
4597 "%s: pll active mismatch (expected pipe %c in active mask 0x%x)\n",
4598 pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
4599 else
4600 I915_STATE_WARN(i915, pll->active_mask & pipe_mask,
4601 "%s: pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n",
4602 pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
4603
4604 I915_STATE_WARN(i915, !(pll->state.pipe_mask & pipe_mask),
4605 "%s: pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
4606 pll->info->name, pipe_mask, pll->state.pipe_mask);
4607
4608 I915_STATE_WARN(i915,
4609 pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state,
4610 sizeof(dpll_hw_state)),
4611 "%s: pll hw state mismatch\n",
4612 pll->info->name);
4613}
4614
4615static bool has_alt_port_dpll(const struct intel_shared_dpll *old_pll,
4616 const struct intel_shared_dpll *new_pll)
4617{
4618 return old_pll && new_pll && old_pll != new_pll &&
4619 (old_pll->info->is_alt_port_dpll || new_pll->info->is_alt_port_dpll);
4620}
4621
4622void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
4623 struct intel_crtc *crtc)
4624{
4625 struct drm_i915_private *i915 = to_i915(state->base.dev);
4626 const struct intel_crtc_state *old_crtc_state =
4627 intel_atomic_get_old_crtc_state(state, crtc);
4628 const struct intel_crtc_state *new_crtc_state =
4629 intel_atomic_get_new_crtc_state(state, crtc);
4630
4631 if (new_crtc_state->shared_dpll)
4632 verify_single_dpll_state(i915, new_crtc_state->shared_dpll,
4633 crtc, new_crtc_state);
4634
4635 if (old_crtc_state->shared_dpll &&
4636 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
4637 u8 pipe_mask = BIT(crtc->pipe);
4638 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
4639
4640 I915_STATE_WARN(i915, pll->active_mask & pipe_mask,
4641 "%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
4642 pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
4643
4644 /* TC ports have both MG/TC and TBT PLL referenced simultaneously */
4645 I915_STATE_WARN(i915, !has_alt_port_dpll(old_crtc_state->shared_dpll,
4646 new_crtc_state->shared_dpll) &&
4647 pll->state.pipe_mask & pipe_mask,
4648 "%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n",
4649 pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask);
4650 }
4651}
4652
4653void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
4654{
4655 struct drm_i915_private *i915 = to_i915(state->base.dev);
4656 struct intel_shared_dpll *pll;
4657 int i;
4658
4659 for_each_shared_dpll(i915, pll, i)
4660 verify_single_dpll_state(i915, pll, NULL, NULL);
4661}