1===============================
   2PINCTRL (PIN CONTROL) subsystem
   3===============================
   4
   5This document outlines the pin control subsystem in Linux
   6
   7This subsystem deals with:
   8
   9- Enumerating and naming controllable pins
  10
  11- Multiplexing of pins, pads, fingers (etc) see below for details
  12
  13- Configuration of pins, pads, fingers (etc), such as software-controlled
  14  biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
  15  load capacitance etc.
  16
  17Top-level interface
  18===================
  19
  20Definitions:
  21
  22- A PIN CONTROLLER is a piece of hardware, usually a set of registers, that
  23  can control PINs. It may be able to multiplex, bias, set load capacitance,
  24  set drive strength, etc. for individual pins or groups of pins.
  25
  26- PINS are equal to pads, fingers, balls or whatever packaging input or
  27  output line you want to control and these are denoted by unsigned integers
  28  in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
  29  there may be several such number spaces in a system. This pin space may
  30  be sparse - i.e. there may be gaps in the space with numbers where no
  31  pin exists.
  32
  33When a PIN CONTROLLER is instantiated, it will register a descriptor to the
  34pin control framework, and this descriptor contains an array of pin descriptors
  35describing the pins handled by this specific pin controller.
  36
  37Here is an example of a PGA (Pin Grid Array) chip seen from underneath::
  38
  39        A   B   C   D   E   F   G   H
  40
  41   8    o   o   o   o   o   o   o   o
  42
  43   7    o   o   o   o   o   o   o   o
  44
  45   6    o   o   o   o   o   o   o   o
  46
  47   5    o   o   o   o   o   o   o   o
  48
  49   4    o   o   o   o   o   o   o   o
  50
  51   3    o   o   o   o   o   o   o   o
  52
  53   2    o   o   o   o   o   o   o   o
  54
  55   1    o   o   o   o   o   o   o   o
  56
  57To register a pin controller and name all the pins on this package we can do
  58this in our driver:
  59
  60.. code-block:: c
  61
  62	#include <linux/pinctrl/pinctrl.h>
  63
  64	const struct pinctrl_pin_desc foo_pins[] = {
  65		PINCTRL_PIN(0, "A8"),
  66		PINCTRL_PIN(1, "B8"),
  67		PINCTRL_PIN(2, "C8"),
  68		...
  69		PINCTRL_PIN(61, "F1"),
  70		PINCTRL_PIN(62, "G1"),
  71		PINCTRL_PIN(63, "H1"),
  72	};
  73
  74	static struct pinctrl_desc foo_desc = {
  75		.name = "foo",
  76		.pins = foo_pins,
  77		.npins = ARRAY_SIZE(foo_pins),
  78		.owner = THIS_MODULE,
  79	};
  80
  81	int __init foo_init(void)
  82	{
  83		int error;
  84
  85		struct pinctrl_dev *pctl;
  86
  87		error = pinctrl_register_and_init(&foo_desc, <PARENT>, NULL, &pctl);
  88		if (error)
  89			return error;
  90
  91		return pinctrl_enable(pctl);
  92	}
  93
  94To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and
  95selected drivers, you need to select them from your machine's Kconfig entry,
  96since these are so tightly integrated with the machines they are used on.
  97See ``arch/arm/mach-ux500/Kconfig`` for an example.
  98
  99Pins usually have fancier names than this. You can find these in the datasheet
 100for your chip. Notice that the core pinctrl.h file provides a fancy macro
 101called ``PINCTRL_PIN()`` to create the struct entries. As you can see the pins are
 102enumerated from 0 in the upper left corner to 63 in the lower right corner.
 103This enumeration was arbitrarily chosen, in practice you need to think
 104through your numbering system so that it matches the layout of registers
 105and such things in your driver, or the code may become complicated. You must
 106also consider matching of offsets to the GPIO ranges that may be handled by
 107the pin controller.
 108
 109For a padding with 467 pads, as opposed to actual pins, the enumeration will
 110be like this, walking around the edge of the chip, which seems to be industry
 111standard too (all these pads had names, too)::
 112
 113
 114     0 ..... 104
 115   466        105
 116     .        .
 117     .        .
 118   358        224
 119    357 .... 225
 120
 121
 122Pin groups
 123==========
 124
 125Many controllers need to deal with groups of pins, so the pin controller
 126subsystem has a mechanism for enumerating groups of pins and retrieving the
 127actual enumerated pins that are part of a certain group.
 128
 129For example, say that we have a group of pins dealing with an SPI interface
 130on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins
 131on { 24, 25 }.
 132
 133These two groups are presented to the pin control subsystem by implementing
 134some generic ``pinctrl_ops`` like this:
 135
 136.. code-block:: c
 137
 138	#include <linux/pinctrl/pinctrl.h>
 139
 140	static const unsigned int spi0_pins[] = { 0, 8, 16, 24 };
 141	static const unsigned int i2c0_pins[] = { 24, 25 };
 142
 143	static const struct pingroup foo_groups[] = {
 144		PINCTRL_PINGROUP("spi0_grp", spi0_pins, ARRAY_SIZE(spi0_pins)),
 145		PINCTRL_PINGROUP("i2c0_grp", i2c0_pins, ARRAY_SIZE(i2c0_pins)),
 146	};
 147
 148	static int foo_get_groups_count(struct pinctrl_dev *pctldev)
 149	{
 150		return ARRAY_SIZE(foo_groups);
 151	}
 152
 153	static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
 154					      unsigned int selector)
 155	{
 156		return foo_groups[selector].name;
 157	}
 158
 159	static int foo_get_group_pins(struct pinctrl_dev *pctldev,
 160				      unsigned int selector,
 161				      const unsigned int **pins,
 162				      unsigned int *npins)
 163	{
 164		*pins = foo_groups[selector].pins;
 165		*npins = foo_groups[selector].npins;
 166		return 0;
 167	}
 168
 169	static struct pinctrl_ops foo_pctrl_ops = {
 170		.get_groups_count = foo_get_groups_count,
 171		.get_group_name = foo_get_group_name,
 172		.get_group_pins = foo_get_group_pins,
 173	};
 174
 175	static struct pinctrl_desc foo_desc = {
 176		...
 177		.pctlops = &foo_pctrl_ops,
 178	};
 179
 180The pin control subsystem will call the ``.get_groups_count()`` function to
 181determine the total number of legal selectors, then it will call the other functions
 182to retrieve the name and pins of the group. Maintaining the data structure of
 183the groups is up to the driver, this is just a simple example - in practice you
 184may need more entries in your group structure, for example specific register
 185ranges associated with each group and so on.
 186
 187
 188Pin configuration
 189=================
 190
 191Pins can sometimes be software-configured in various ways, mostly related
 192to their electronic properties when used as inputs or outputs. For example you
 193may be able to make an output pin high impedance (Hi-Z), or "tristate" meaning it is
 194effectively disconnected. You may be able to connect an input pin to VDD or GND
 195using a certain resistor value - pull up and pull down - so that the pin has a
 196stable value when nothing is driving the rail it is connected to, or when it's
 197unconnected.
 198
 199Pin configuration can be programmed by adding configuration entries into the
 200mapping table; see section `Board/machine configuration`_ below.
 201
 202The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP
 203above, is entirely defined by the pin controller driver.
 204
 205The pin configuration driver implements callbacks for changing pin
 206configuration in the pin controller ops like this:
 207
 208.. code-block:: c
 209
 210	#include <linux/pinctrl/pinconf.h>
 211	#include <linux/pinctrl/pinctrl.h>
 212
 213	#include "platform_x_pindefs.h"
 214
 215	static int foo_pin_config_get(struct pinctrl_dev *pctldev,
 216				      unsigned int offset,
 217				      unsigned long *config)
 218	{
 219		struct my_conftype conf;
 220
 221		/* ... Find setting for pin @ offset ... */
 222
 223		*config = (unsigned long) conf;
 224	}
 225
 226	static int foo_pin_config_set(struct pinctrl_dev *pctldev,
 227				      unsigned int offset,
 228				      unsigned long config)
 229	{
 230		struct my_conftype *conf = (struct my_conftype *) config;
 231
 232		switch (conf) {
 233			case PLATFORM_X_PULL_UP:
 234			...
 235			break;
 236		}
 237	}
 238
 239	static int foo_pin_config_group_get(struct pinctrl_dev *pctldev,
 240					    unsigned selector,
 241					    unsigned long *config)
 242	{
 243		...
 244	}
 245
 246	static int foo_pin_config_group_set(struct pinctrl_dev *pctldev,
 247					    unsigned selector,
 248					    unsigned long config)
 249	{
 250		...
 251	}
 252
 253	static struct pinconf_ops foo_pconf_ops = {
 254		.pin_config_get = foo_pin_config_get,
 255		.pin_config_set = foo_pin_config_set,
 256		.pin_config_group_get = foo_pin_config_group_get,
 257		.pin_config_group_set = foo_pin_config_group_set,
 258	};
 259
 260	/* Pin config operations are handled by some pin controller */
 261	static struct pinctrl_desc foo_desc = {
 262		...
 263		.confops = &foo_pconf_ops,
 264	};
 265
 266Interaction with the GPIO subsystem
 267===================================
 268
 269The GPIO drivers may want to perform operations of various types on the same
 270physical pins that are also registered as pin controller pins.
 271
 272First and foremost, the two subsystems can be used as completely orthogonal,
 273see the section named `Pin control requests from drivers`_ and
 274`Drivers needing both pin control and GPIOs`_ below for details. But in some
 275situations a cross-subsystem mapping between pins and GPIOs is needed.
 276
 277Since the pin controller subsystem has its pinspace local to the pin controller
 278we need a mapping so that the pin control subsystem can figure out which pin
 279controller handles control of a certain GPIO pin. Since a single pin controller
 280may be muxing several GPIO ranges (typically SoCs that have one set of pins,
 281but internally several GPIO silicon blocks, each modelled as a struct
 282gpio_chip) any number of GPIO ranges can be added to a pin controller instance
 283like this:
 284
 285.. code-block:: c
 286
 287	#include <linux/gpio/driver.h>
 288
 289	#include <linux/pinctrl/pinctrl.h>
 290
 291	struct gpio_chip chip_a;
 292	struct gpio_chip chip_b;
 293
 294	static struct pinctrl_gpio_range gpio_range_a = {
 295		.name = "chip a",
 296		.id = 0,
 297		.base = 32,
 298		.pin_base = 32,
 299		.npins = 16,
 300		.gc = &chip_a,
 301	};
 302
 303	static struct pinctrl_gpio_range gpio_range_b = {
 304		.name = "chip b",
 305		.id = 0,
 306		.base = 48,
 307		.pin_base = 64,
 308		.npins = 8,
 309		.gc = &chip_b;
 310	};
 311
 312	int __init foo_init(void)
 313	{
 314		struct pinctrl_dev *pctl;
 315		...
 316		pinctrl_add_gpio_range(pctl, &gpio_range_a);
 317		pinctrl_add_gpio_range(pctl, &gpio_range_b);
 318		...
 319	}
 320
 321So this complex system has one pin controller handling two different
 322GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and
 323"chip b" have different ``pin_base``, which means a start pin number of the
 324GPIO range.
 325
 326The GPIO range of "chip a" starts from the GPIO base of 32 and actual
 327pin range also starts from 32. However "chip b" has different starting
 328offset for the GPIO range and pin range. The GPIO range of "chip b" starts
 329from GPIO number 48, while the pin range of "chip b" starts from 64.
 330
 331We can convert a gpio number to actual pin number using this ``pin_base``.
 332They are mapped in the global GPIO pin space at:
 333
 334chip a:
 335 - GPIO range : [32 .. 47]
 336 - pin range  : [32 .. 47]
 337chip b:
 338 - GPIO range : [48 .. 55]
 339 - pin range  : [64 .. 71]
 340
 341The above examples assume the mapping between the GPIOs and pins is
 342linear. If the mapping is sparse or haphazard, an array of arbitrary pin
 343numbers can be encoded in the range like this:
 344
 345.. code-block:: c
 346
 347	static const unsigned int range_pins[] = { 14, 1, 22, 17, 10, 8, 6, 2 };
 348
 349	static struct pinctrl_gpio_range gpio_range = {
 350		.name = "chip",
 351		.id = 0,
 352		.base = 32,
 353		.pins = &range_pins,
 354		.npins = ARRAY_SIZE(range_pins),
 355		.gc = &chip,
 356	};
 357
 358In this case the ``pin_base`` property will be ignored. If the name of a pin
 359group is known, the pins and npins elements of the above structure can be
 360initialised using the function ``pinctrl_get_group_pins()``, e.g. for pin
 361group "foo":
 362
 363.. code-block:: c
 364
 365	pinctrl_get_group_pins(pctl, "foo", &gpio_range.pins, &gpio_range.npins);
 366
 367When GPIO-specific functions in the pin control subsystem are called, these
 368ranges will be used to look up the appropriate pin controller by inspecting
 369and matching the pin to the pin ranges across all controllers. When a
 370pin controller handling the matching range is found, GPIO-specific functions
 371will be called on that specific pin controller.
 372
 373For all functionalities dealing with pin biasing, pin muxing etc, the pin
 374controller subsystem will look up the corresponding pin number from the passed
 375in gpio number, and use the range's internals to retrieve a pin number. After
 376that, the subsystem passes it on to the pin control driver, so the driver
 377will get a pin number into its handled number range. Further it is also passed
 378the range ID value, so that the pin controller knows which range it should
 379deal with.
 380
 381Calling ``pinctrl_add_gpio_range()`` from pinctrl driver is DEPRECATED. Please see
 382section 2.1 of ``Documentation/devicetree/bindings/gpio/gpio.txt`` on how to bind
 383pinctrl and gpio drivers.
 384
 385
 386PINMUX interfaces
 387=================
 388
 389These calls use the pinmux_* naming prefix.  No other calls should use that
 390prefix.
 391
 392
 393What is pinmuxing?
 394==================
 395
 396PINMUX, also known as padmux, ballmux, alternate functions or mission modes
 397is a way for chip vendors producing some kind of electrical packages to use
 398a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive
 399functions, depending on the application. By "application" in this context
 400we usually mean a way of soldering or wiring the package into an electronic
 401system, even though the framework makes it possible to also change the function
 402at runtime.
 403
 404Here is an example of a PGA (Pin Grid Array) chip seen from underneath::
 405
 406        A   B   C   D   E   F   G   H
 407      +---+
 408   8  | o | o   o   o   o   o   o   o
 409      |   |
 410   7  | o | o   o   o   o   o   o   o
 411      |   |
 412   6  | o | o   o   o   o   o   o   o
 413      +---+---+
 414   5  | o | o | o   o   o   o   o   o
 415      +---+---+               +---+
 416   4    o   o   o   o   o   o | o | o
 417                              |   |
 418   3    o   o   o   o   o   o | o | o
 419                              |   |
 420   2    o   o   o   o   o   o | o | o
 421      +-------+-------+-------+---+---+
 422   1  | o   o | o   o | o   o | o | o |
 423      +-------+-------+-------+---+---+
 424
 425This is not tetris. The game to think of is chess. Not all PGA/BGA packages
 426are chessboard-like, big ones have "holes" in some arrangement according to
 427different design patterns, but we're using this as a simple example. Of the
 428pins you see some will be taken by things like a few VCC and GND to feed power
 429to the chip, and quite a few will be taken by large ports like an external
 430memory interface. The remaining pins will often be subject to pin multiplexing.
 431
 432The example 8x8 PGA package above will have pin numbers 0 through 63 assigned
 433to its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using
 434pinctrl_register_pins() and a suitable data set as shown earlier.
 435
 436In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port
 437(these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as
 438some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can
 439be used as an I2C port (these are just two pins: SCL, SDA). Needless to say,
 440we cannot use the SPI port and I2C port at the same time. However in the inside
 441of the package the silicon performing the SPI logic can alternatively be routed
 442out on pins { G4, G3, G2, G1 }.
 443
 444On the bottom row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something
 445special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will
 446consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or
 447{ A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI
 448port on pins { G4, G3, G2, G1 } of course.
 449
 450This way the silicon blocks present inside the chip can be multiplexed "muxed"
 451out on different pin ranges. Often contemporary SoC (systems on chip) will
 452contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to
 453different pins by pinmux settings.
 454
 455Since general-purpose I/O pins (GPIO) are typically always in shortage, it is
 456common to be able to use almost any pin as a GPIO pin if it is not currently
 457in use by some other I/O port.
 458
 459
 460Pinmux conventions
 461==================
 462
 463The purpose of the pinmux functionality in the pin controller subsystem is to
 464abstract and provide pinmux settings to the devices you choose to instantiate
 465in your machine configuration. It is inspired by the clk, GPIO and regulator
 466subsystems, so devices will request their mux setting, but it's also possible
 467to request a single pin for e.g. GPIO.
 468
 469The conventions are:
 470
 471- FUNCTIONS can be switched in and out by a driver residing with the pin
 472  control subsystem in the ``drivers/pinctrl`` directory of the kernel. The
 473  pin control driver knows the possible functions. In the example above you can
 474  identify three pinmux functions, one for spi, one for i2c and one for mmc.
 475
 476- FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array.
 477  In this case the array could be something like: { spi0, i2c0, mmc0 }
 478  for the three available functions.
 479
 480- FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain
 481  function is *always* associated with a certain set of pin groups, could
 482  be just a single one, but could also be many. In the example above the
 483  function i2c is associated with the pins { A5, B5 }, enumerated as
 484  { 24, 25 } in the controller pin space.
 485
 486  The Function spi is associated with pin groups { A8, A7, A6, A5 }
 487  and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and
 488  { 38, 46, 54, 62 } respectively.
 489
 490  Group names must be unique per pin controller, no two groups on the same
 491  controller may have the same name.
 492
 493- The combination of a FUNCTION and a PIN GROUP determine a certain function
 494  for a certain set of pins. The knowledge of the functions and pin groups
 495  and their machine-specific particulars are kept inside the pinmux driver,
 496  from the outside only the enumerators are known, and the driver core can
 497  request:
 498
 499  - The name of a function with a certain selector (>= 0)
 500  - A list of groups associated with a certain function
 501  - That a certain group in that list to be activated for a certain function
 502
 503  As already described above, pin groups are in turn self-descriptive, so
 504  the core will retrieve the actual pin range in a certain group from the
 505  driver.
 506
 507- FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain
 508  device by the board file, device tree or similar machine setup configuration
 509  mechanism, similar to how regulators are connected to devices, usually by
 510  name. Defining a pin controller, function and group thus uniquely identify
 511  the set of pins to be used by a certain device. (If only one possible group
 512  of pins is available for the function, no group name need to be supplied -
 513  the core will simply select the first and only group available.)
 514
 515  In the example case we can define that this particular machine shall
 516  use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function
 517  fi2c0 group gi2c0, on the primary pin controller, we get mappings
 518  like these:
 519
 520  .. code-block:: c
 521
 522	{
 523		{"map-spi0", spi0, pinctrl0, fspi0, gspi0},
 524		{"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0},
 525	}
 526
 527  Every map must be assigned a state name, pin controller, device and
 528  function. The group is not compulsory - if it is omitted the first group
 529  presented by the driver as applicable for the function will be selected,
 530  which is useful for simple cases.
 531
 532  It is possible to map several groups to the same combination of device,
 533  pin controller and function. This is for cases where a certain function on
 534  a certain pin controller may use different sets of pins in different
 535  configurations.
 536
 537- PINS for a certain FUNCTION using a certain PIN GROUP on a certain
 538  PIN CONTROLLER are provided on a first-come first-serve basis, so if some
 539  other device mux setting or GPIO pin request has already taken your physical
 540  pin, you will be denied the use of it. To get (activate) a new setting, the
 541  old one has to be put (deactivated) first.
 542
 543Sometimes the documentation and hardware registers will be oriented around
 544pads (or "fingers") rather than pins - these are the soldering surfaces on the
 545silicon inside the package, and may or may not match the actual number of
 546pins/balls underneath the capsule. Pick some enumeration that makes sense to
 547you. Define enumerators only for the pins you can control if that makes sense.
 548
 549Assumptions:
 550
 551We assume that the number of possible function maps to pin groups is limited by
 552the hardware. I.e. we assume that there is no system where any function can be
 553mapped to any pin, like in a phone exchange. So the available pin groups for
 554a certain function will be limited to a few choices (say up to eight or so),
 555not hundreds or any amount of choices. This is the characteristic we have found
 556by inspecting available pinmux hardware, and a necessary assumption since we
 557expect pinmux drivers to present *all* possible function vs pin group mappings
 558to the subsystem.
 559
 560
 561Pinmux drivers
 562==============
 563
 564The pinmux core takes care of preventing conflicts on pins and calling
 565the pin controller driver to execute different settings.
 566
 567It is the responsibility of the pinmux driver to impose further restrictions
 568(say for example infer electronic limitations due to load, etc.) to determine
 569whether or not the requested function can actually be allowed, and in case it
 570is possible to perform the requested mux setting, poke the hardware so that
 571this happens.
 572
 573Pinmux drivers are required to supply a few callback functions, some are
 574optional. Usually the ``.set_mux()`` function is implemented, writing values into
 575some certain registers to activate a certain mux setting for a certain pin.
 576
 577A simple driver for the above example will work by setting bits 0, 1, 2, 3, 4, or 5
 578into some register named MUX to select a certain function with a certain
 579group of pins would work something like this:
 580
 581.. code-block:: c
 582
 583	#include <linux/pinctrl/pinctrl.h>
 584	#include <linux/pinctrl/pinmux.h>
 585
 586	static const unsigned int spi0_0_pins[] = { 0, 8, 16, 24 };
 587	static const unsigned int spi0_1_pins[] = { 38, 46, 54, 62 };
 588	static const unsigned int i2c0_pins[] = { 24, 25 };
 589	static const unsigned int mmc0_1_pins[] = { 56, 57 };
 590	static const unsigned int mmc0_2_pins[] = { 58, 59 };
 591	static const unsigned int mmc0_3_pins[] = { 60, 61, 62, 63 };
 592
 593	static const struct pingroup foo_groups[] = {
 594		PINCTRL_PINGROUP("spi0_0_grp", spi0_0_pins, ARRAY_SIZE(spi0_0_pins)),
 595		PINCTRL_PINGROUP("spi0_1_grp", spi0_1_pins, ARRAY_SIZE(spi0_1_pins)),
 596		PINCTRL_PINGROUP("i2c0_grp", i2c0_pins, ARRAY_SIZE(i2c0_pins)),
 597		PINCTRL_PINGROUP("mmc0_1_grp", mmc0_1_pins, ARRAY_SIZE(mmc0_1_pins)),
 598		PINCTRL_PINGROUP("mmc0_2_grp", mmc0_2_pins, ARRAY_SIZE(mmc0_2_pins)),
 599		PINCTRL_PINGROUP("mmc0_3_grp", mmc0_3_pins, ARRAY_SIZE(mmc0_3_pins)),
 600	};
 601
 602	static int foo_get_groups_count(struct pinctrl_dev *pctldev)
 603	{
 604		return ARRAY_SIZE(foo_groups);
 605	}
 606
 607	static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
 608					      unsigned int selector)
 609	{
 610		return foo_groups[selector].name;
 611	}
 612
 613	static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
 614				      const unsigned int **pins,
 615				      unsigned int *npins)
 616	{
 617		*pins = foo_groups[selector].pins;
 618		*npins = foo_groups[selector].npins;
 619		return 0;
 620	}
 621
 622	static struct pinctrl_ops foo_pctrl_ops = {
 623		.get_groups_count = foo_get_groups_count,
 624		.get_group_name = foo_get_group_name,
 625		.get_group_pins = foo_get_group_pins,
 626	};
 627
 628	static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
 629	static const char * const i2c0_groups[] = { "i2c0_grp" };
 630	static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp", "mmc0_3_grp" };
 631
 632	static const struct pinfunction foo_functions[] = {
 633		PINCTRL_PINFUNCTION("spi0", spi0_groups, ARRAY_SIZE(spi0_groups)),
 634		PINCTRL_PINFUNCTION("i2c0", i2c0_groups, ARRAY_SIZE(i2c0_groups)),
 635		PINCTRL_PINFUNCTION("mmc0", mmc0_groups, ARRAY_SIZE(mmc0_groups)),
 636	};
 637
 638	static int foo_get_functions_count(struct pinctrl_dev *pctldev)
 639	{
 640		return ARRAY_SIZE(foo_functions);
 641	}
 642
 643	static const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned int selector)
 644	{
 645		return foo_functions[selector].name;
 646	}
 647
 648	static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned int selector,
 649				  const char * const **groups,
 650				  unsigned int * const ngroups)
 651	{
 652		*groups = foo_functions[selector].groups;
 653		*ngroups = foo_functions[selector].ngroups;
 654		return 0;
 655	}
 656
 657	static int foo_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
 658			       unsigned int group)
 659	{
 660		u8 regbit = BIT(group);
 661
 662		writeb((readb(MUX) | regbit), MUX);
 663		return 0;
 664	}
 665
 666	static struct pinmux_ops foo_pmxops = {
 667		.get_functions_count = foo_get_functions_count,
 668		.get_function_name = foo_get_fname,
 669		.get_function_groups = foo_get_groups,
 670		.set_mux = foo_set_mux,
 671		.strict = true,
 672	};
 673
 674	/* Pinmux operations are handled by some pin controller */
 675	static struct pinctrl_desc foo_desc = {
 676		...
 677		.pctlops = &foo_pctrl_ops,
 678		.pmxops = &foo_pmxops,
 679	};
 680
 681In the example activating muxing 0 and 2 at the same time setting bits
 6820 and 2, uses pin 24 in common so they would collide. All the same for
 683the muxes 1 and 5, which have pin 62 in common.
 684
 685The beauty of the pinmux subsystem is that since it keeps track of all
 686pins and who is using them, it will already have denied an impossible
 687request like that, so the driver does not need to worry about such
 688things - when it gets a selector passed in, the pinmux subsystem makes
 689sure no other device or GPIO assignment is already using the selected
 690pins. Thus bits 0 and 2, or 1 and 5 in the control register will never
 691be set at the same time.
 692
 693All the above functions are mandatory to implement for a pinmux driver.
 694
 695
 696Pin control interaction with the GPIO subsystem
 697===============================================
 698
 699Note that the following implies that the use case is to use a certain pin
 700from the Linux kernel using the API in ``<linux/gpio/consumer.h>`` with gpiod_get()
 701and similar functions. There are cases where you may be using something
 702that your datasheet calls "GPIO mode", but actually is just an electrical
 703configuration for a certain device. See the section below named
 704`GPIO mode pitfalls`_ for more details on this scenario.
 705
 706The public pinmux API contains two functions named ``pinctrl_gpio_request()``
 707and ``pinctrl_gpio_free()``. These two functions shall *ONLY* be called from
 708gpiolib-based drivers as part of their ``.request()`` and ``.free()`` semantics.
 709Likewise the ``pinctrl_gpio_direction_input()`` / ``pinctrl_gpio_direction_output()``
 710shall only be called from within respective ``.direction_input()`` /
 711``.direction_output()`` gpiolib implementation.
 712
 713NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be
 714controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have
 715that driver request proper muxing and other control for its pins.
 716
 717The function list could become long, especially if you can convert every
 718individual pin into a GPIO pin independent of any other pins, and then try
 719the approach to define every pin as a function.
 720
 721In this case, the function array would become 64 entries for each GPIO
 722setting and then the device functions.
 723
 724For this reason there are two functions a pin control driver can implement
 725to enable only GPIO on an individual pin: ``.gpio_request_enable()`` and
 726``.gpio_disable_free()``.
 727
 728This function will pass in the affected GPIO range identified by the pin
 729controller core, so you know which GPIO pins are being affected by the request
 730operation.
 731
 732If your driver needs to have an indication from the framework of whether the
 733GPIO pin shall be used for input or output you can implement the
 734``.gpio_set_direction()`` function. As described this shall be called from the
 735gpiolib driver and the affected GPIO range, pin offset and desired direction
 736will be passed along to this function.
 737
 738Alternatively to using these special functions, it is fully allowed to use
 739named functions for each GPIO pin, the ``pinctrl_gpio_request()`` will attempt to
 740obtain the function "gpioN" where "N" is the global GPIO pin number if no
 741special GPIO-handler is registered.
 742
 743
 744GPIO mode pitfalls
 745==================
 746
 747Due to the naming conventions used by hardware engineers, where "GPIO"
 748is taken to mean different things than what the kernel does, the developer
 749may be confused by a datasheet talking about a pin being possible to set
 750into "GPIO mode". It appears that what hardware engineers mean with
 751"GPIO mode" is not necessarily the use case that is implied in the kernel
 752interface ``<linux/gpio/consumer.h>``: a pin that you grab from kernel code and then
 753either listen for input or drive high/low to assert/deassert some
 754external line.
 755
 756Rather hardware engineers think that "GPIO mode" means that you can
 757software-control a few electrical properties of the pin that you would
 758not be able to control if the pin was in some other mode, such as muxed in
 759for a device.
 760
 761The GPIO portions of a pin and its relation to a certain pin controller
 762configuration and muxing logic can be constructed in several ways. Here
 763are two examples.
 764
 765Example **(A)**::
 766
 767                       pin config
 768                       logic regs
 769                       |               +- SPI
 770     Physical pins --- pad --- pinmux -+- I2C
 771                               |       +- mmc
 772                               |       +- GPIO
 773                               pin
 774                               multiplex
 775                               logic regs
 776
 777Here some electrical properties of the pin can be configured no matter
 778whether the pin is used for GPIO or not. If you multiplex a GPIO onto a
 779pin, you can also drive it high/low from "GPIO" registers.
 780Alternatively, the pin can be controlled by a certain peripheral, while
 781still applying desired pin config properties. GPIO functionality is thus
 782orthogonal to any other device using the pin.
 783
 784In this arrangement the registers for the GPIO portions of the pin controller,
 785or the registers for the GPIO hardware module are likely to reside in a
 786separate memory range only intended for GPIO driving, and the register
 787range dealing with pin config and pin multiplexing get placed into a
 788different memory range and a separate section of the data sheet.
 789
 790A flag "strict" in struct pinmux_ops is available to check and deny
 791simultaneous access to the same pin from GPIO and pin multiplexing
 792consumers on hardware of this type. The pinctrl driver should set this flag
 793accordingly.
 794
 795Example **(B)**::
 796
 797                       pin config
 798                       logic regs
 799                       |               +- SPI
 800     Physical pins --- pad --- pinmux -+- I2C
 801                       |       |       +- mmc
 802                       |       |
 803                       GPIO    pin
 804                               multiplex
 805                               logic regs
 806
 807In this arrangement, the GPIO functionality can always be enabled, such that
 808e.g. a GPIO input can be used to "spy" on the SPI/I2C/MMC signal while it is
 809pulsed out. It is likely possible to disrupt the traffic on the pin by doing
 810wrong things on the GPIO block, as it is never really disconnected. It is
 811possible that the GPIO, pin config and pin multiplex registers are placed into
 812the same memory range and the same section of the data sheet, although that
 813need not be the case.
 814
 815In some pin controllers, although the physical pins are designed in the same
 816way as (B), the GPIO function still can't be enabled at the same time as the
 817peripheral functions. So again the "strict" flag should be set, denying
 818simultaneous activation by GPIO and other muxed in devices.
 819
 820From a kernel point of view, however, these are different aspects of the
 821hardware and shall be put into different subsystems:
 822
 823- Registers (or fields within registers) that control electrical
 824  properties of the pin such as biasing and drive strength should be
 825  exposed through the pinctrl subsystem, as "pin configuration" settings.
 826
 827- Registers (or fields within registers) that control muxing of signals
 828  from various other HW blocks (e.g. I2C, MMC, or GPIO) onto pins should
 829  be exposed through the pinctrl subsystem, as mux functions.
 830
 831- Registers (or fields within registers) that control GPIO functionality
 832  such as setting a GPIO's output value, reading a GPIO's input value, or
 833  setting GPIO pin direction should be exposed through the GPIO subsystem,
 834  and if they also support interrupt capabilities, through the irqchip
 835  abstraction.
 836
 837Depending on the exact HW register design, some functions exposed by the
 838GPIO subsystem may call into the pinctrl subsystem in order to
 839coordinate register settings across HW modules. In particular, this may
 840be needed for HW with separate GPIO and pin controller HW modules, where
 841e.g. GPIO direction is determined by a register in the pin controller HW
 842module rather than the GPIO HW module.
 843
 844Electrical properties of the pin such as biasing and drive strength
 845may be placed at some pin-specific register in all cases or as part
 846of the GPIO register in case (B) especially. This doesn't mean that such
 847properties necessarily pertain to what the Linux kernel calls "GPIO".
 848
 849Example: a pin is usually muxed in to be used as a UART TX line. But during
 850system sleep, we need to put this pin into "GPIO mode" and ground it.
 851
 852If you make a 1-to-1 map to the GPIO subsystem for this pin, you may start
 853to think that you need to come up with something really complex, that the
 854pin shall be used for UART TX and GPIO at the same time, that you will grab
 855a pin control handle and set it to a certain state to enable UART TX to be
 856muxed in, then twist it over to GPIO mode and use gpiod_direction_output()
 857to drive it low during sleep, then mux it over to UART TX again when you
 858wake up and maybe even gpiod_get() / gpiod_put() as part of this cycle. This
 859all gets very complicated.
 860
 861The solution is to not think that what the datasheet calls "GPIO mode"
 862has to be handled by the ``<linux/gpio/consumer.h>`` interface. Instead view this as
 863a certain pin config setting. Look in e.g. ``<linux/pinctrl/pinconf-generic.h>``
 864and you find this in the documentation:
 865
 866  PIN_CONFIG_OUTPUT:
 867     this will configure the pin in output, use argument
 868     1 to indicate high level, argument 0 to indicate low level.
 869
 870So it is perfectly possible to push a pin into "GPIO mode" and drive the
 871line low as part of the usual pin control map. So for example your UART
 872driver may look like this:
 873
 874.. code-block:: c
 875
 876	#include <linux/pinctrl/consumer.h>
 877
 878	struct pinctrl          *pinctrl;
 879	struct pinctrl_state    *pins_default;
 880	struct pinctrl_state    *pins_sleep;
 881
 882	pins_default = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_DEFAULT);
 883	pins_sleep = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_SLEEP);
 884
 885	/* Normal mode */
 886	retval = pinctrl_select_state(pinctrl, pins_default);
 887
 888	/* Sleep mode */
 889	retval = pinctrl_select_state(pinctrl, pins_sleep);
 890
 891And your machine configuration may look like this:
 892
 893.. code-block:: c
 894
 895	static unsigned long uart_default_mode[] = {
 896		PIN_CONF_PACKED(PIN_CONFIG_DRIVE_PUSH_PULL, 0),
 897	};
 898
 899	static unsigned long uart_sleep_mode[] = {
 900		PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0),
 901	};
 902
 903	static struct pinctrl_map pinmap[] __initdata = {
 904		PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
 905				  "u0_group", "u0"),
 906		PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
 907				    "UART_TX_PIN", uart_default_mode),
 908		PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
 909				  "u0_group", "gpio-mode"),
 910		PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
 911				    "UART_TX_PIN", uart_sleep_mode),
 912	};
 913
 914	foo_init(void)
 915	{
 916		pinctrl_register_mappings(pinmap, ARRAY_SIZE(pinmap));
 917	}
 918
 919Here the pins we want to control are in the "u0_group" and there is some
 920function called "u0" that can be enabled on this group of pins, and then
 921everything is UART business as usual. But there is also some function
 922named "gpio-mode" that can be mapped onto the same pins to move them into
 923GPIO mode.
 924
 925This will give the desired effect without any bogus interaction with the
 926GPIO subsystem. It is just an electrical configuration used by that device
 927when going to sleep, it might imply that the pin is set into something the
 928datasheet calls "GPIO mode", but that is not the point: it is still used
 929by that UART device to control the pins that pertain to that very UART
 930driver, putting them into modes needed by the UART. GPIO in the Linux
 931kernel sense are just some 1-bit line, and is a different use case.
 932
 933How the registers are poked to attain the push or pull, and output low
 934configuration and the muxing of the "u0" or "gpio-mode" group onto these
 935pins is a question for the driver.
 936
 937Some datasheets will be more helpful and refer to the "GPIO mode" as
 938"low power mode" rather than anything to do with GPIO. This often means
 939the same thing electrically speaking, but in this latter case the
 940software engineers will usually quickly identify that this is some
 941specific muxing or configuration rather than anything related to the GPIO
 942API.
 943
 944
 945Board/machine configuration
 946===========================
 947
 948Boards and machines define how a certain complete running system is put
 949together, including how GPIOs and devices are muxed, how regulators are
 950constrained and how the clock tree looks. Of course pinmux settings are also
 951part of this.
 952
 953A pin controller configuration for a machine looks pretty much like a simple
 954regulator configuration, so for the example array above we want to enable i2c
 955and spi on the second function mapping:
 956
 957.. code-block:: c
 958
 959	#include <linux/pinctrl/machine.h>
 960
 961	static const struct pinctrl_map mapping[] __initconst = {
 962		{
 963			.dev_name = "foo-spi.0",
 964			.name = PINCTRL_STATE_DEFAULT,
 965			.type = PIN_MAP_TYPE_MUX_GROUP,
 966			.ctrl_dev_name = "pinctrl-foo",
 967			.data.mux.function = "spi0",
 968		},
 969		{
 970			.dev_name = "foo-i2c.0",
 971			.name = PINCTRL_STATE_DEFAULT,
 972			.type = PIN_MAP_TYPE_MUX_GROUP,
 973			.ctrl_dev_name = "pinctrl-foo",
 974			.data.mux.function = "i2c0",
 975		},
 976		{
 977			.dev_name = "foo-mmc.0",
 978			.name = PINCTRL_STATE_DEFAULT,
 979			.type = PIN_MAP_TYPE_MUX_GROUP,
 980			.ctrl_dev_name = "pinctrl-foo",
 981			.data.mux.function = "mmc0",
 982		},
 983	};
 984
 985The dev_name here matches to the unique device name that can be used to look
 986up the device struct (just like with clockdev or regulators). The function name
 987must match a function provided by the pinmux driver handling this pin range.
 988
 989As you can see we may have several pin controllers on the system and thus
 990we need to specify which one of them contains the functions we wish to map.
 991
 992You register this pinmux mapping to the pinmux subsystem by simply:
 993
 994.. code-block:: c
 995
 996       ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping));
 997
 998Since the above construct is pretty common there is a helper macro to make
 999it even more compact which assumes you want to use pinctrl-foo and position
10000 for mapping, for example:
1001
1002.. code-block:: c
1003
1004	static struct pinctrl_map mapping[] __initdata = {
1005		PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT,
1006				  "pinctrl-foo", NULL, "i2c0"),
1007	};
1008
1009The mapping table may also contain pin configuration entries. It's common for
1010each pin/group to have a number of configuration entries that affect it, so
1011the table entries for configuration reference an array of config parameters
1012and values. An example using the convenience macros is shown below:
1013
1014.. code-block:: c
1015
1016	static unsigned long i2c_grp_configs[] = {
1017		FOO_PIN_DRIVEN,
1018		FOO_PIN_PULLUP,
1019	};
1020
1021	static unsigned long i2c_pin_configs[] = {
1022		FOO_OPEN_COLLECTOR,
1023		FOO_SLEW_RATE_SLOW,
1024	};
1025
1026	static struct pinctrl_map mapping[] __initdata = {
1027		PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT,
1028				  "pinctrl-foo", "i2c0", "i2c0"),
1029		PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT,
1030				      "pinctrl-foo", "i2c0", i2c_grp_configs),
1031		PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT,
1032				    "pinctrl-foo", "i2c0scl", i2c_pin_configs),
1033		PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT,
1034				    "pinctrl-foo", "i2c0sda", i2c_pin_configs),
1035	};
1036
1037Finally, some devices expect the mapping table to contain certain specific
1038named states. When running on hardware that doesn't need any pin controller
1039configuration, the mapping table must still contain those named states, in
1040order to explicitly indicate that the states were provided and intended to
1041be empty. Table entry macro ``PIN_MAP_DUMMY_STATE()`` serves the purpose of defining
1042a named state without causing any pin controller to be programmed:
1043
1044.. code-block:: c
1045
1046	static struct pinctrl_map mapping[] __initdata = {
1047		PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT),
1048	};
1049
1050
1051Complex mappings
1052================
1053
1054As it is possible to map a function to different groups of pins an optional
1055.group can be specified like this:
1056
1057.. code-block:: c
1058
1059	...
1060	{
1061		.dev_name = "foo-spi.0",
1062		.name = "spi0-pos-A",
1063		.type = PIN_MAP_TYPE_MUX_GROUP,
1064		.ctrl_dev_name = "pinctrl-foo",
1065		.function = "spi0",
1066		.group = "spi0_0_grp",
1067	},
1068	{
1069		.dev_name = "foo-spi.0",
1070		.name = "spi0-pos-B",
1071		.type = PIN_MAP_TYPE_MUX_GROUP,
1072		.ctrl_dev_name = "pinctrl-foo",
1073		.function = "spi0",
1074		.group = "spi0_1_grp",
1075	},
1076	...
1077
1078This example mapping is used to switch between two positions for spi0 at
1079runtime, as described further below under the heading `Runtime pinmuxing`_.
1080
1081Further it is possible for one named state to affect the muxing of several
1082groups of pins, say for example in the mmc0 example above, where you can
1083additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all
1084three groups for a total of 2 + 2 + 4 = 8 pins (for an 8-bit MMC bus as is the
1085case), we define a mapping like this:
1086
1087.. code-block:: c
1088
1089	...
1090	{
1091		.dev_name = "foo-mmc.0",
1092		.name = "2bit"
1093		.type = PIN_MAP_TYPE_MUX_GROUP,
1094		.ctrl_dev_name = "pinctrl-foo",
1095		.function = "mmc0",
1096		.group = "mmc0_1_grp",
1097	},
1098	{
1099		.dev_name = "foo-mmc.0",
1100		.name = "4bit"
1101		.type = PIN_MAP_TYPE_MUX_GROUP,
1102		.ctrl_dev_name = "pinctrl-foo",
1103		.function = "mmc0",
1104		.group = "mmc0_1_grp",
1105	},
1106	{
1107		.dev_name = "foo-mmc.0",
1108		.name = "4bit"
1109		.type = PIN_MAP_TYPE_MUX_GROUP,
1110		.ctrl_dev_name = "pinctrl-foo",
1111		.function = "mmc0",
1112		.group = "mmc0_2_grp",
1113	},
1114	{
1115		.dev_name = "foo-mmc.0",
1116		.name = "8bit"
1117		.type = PIN_MAP_TYPE_MUX_GROUP,
1118		.ctrl_dev_name = "pinctrl-foo",
1119		.function = "mmc0",
1120		.group = "mmc0_1_grp",
1121	},
1122	{
1123		.dev_name = "foo-mmc.0",
1124		.name = "8bit"
1125		.type = PIN_MAP_TYPE_MUX_GROUP,
1126		.ctrl_dev_name = "pinctrl-foo",
1127		.function = "mmc0",
1128		.group = "mmc0_2_grp",
1129	},
1130	{
1131		.dev_name = "foo-mmc.0",
1132		.name = "8bit"
1133		.type = PIN_MAP_TYPE_MUX_GROUP,
1134		.ctrl_dev_name = "pinctrl-foo",
1135		.function = "mmc0",
1136		.group = "mmc0_3_grp",
1137	},
1138	...
1139
1140The result of grabbing this mapping from the device with something like
1141this (see next paragraph):
1142
1143.. code-block:: c
1144
1145	p = devm_pinctrl_get(dev);
1146	s = pinctrl_lookup_state(p, "8bit");
1147	ret = pinctrl_select_state(p, s);
1148
1149or more simply:
1150
1151.. code-block:: c
1152
1153	p = devm_pinctrl_get_select(dev, "8bit");
1154
1155Will be that you activate all the three bottom records in the mapping at
1156once. Since they share the same name, pin controller device, function and
1157device, and since we allow multiple groups to match to a single device, they
1158all get selected, and they all get enabled and disable simultaneously by the
1159pinmux core.
1160
1161
1162Pin control requests from drivers
1163=================================
1164
1165When a device driver is about to probe the device core will automatically
1166attempt to issue ``pinctrl_get_select_default()`` on these devices.
1167This way driver writers do not need to add any of the boilerplate code
1168of the type found below. However when doing fine-grained state selection
1169and not using the "default" state, you may have to do some device driver
1170handling of the pinctrl handles and states.
1171
1172So if you just want to put the pins for a certain device into the default
1173state and be done with it, there is nothing you need to do besides
1174providing the proper mapping table. The device core will take care of
1175the rest.
1176
1177Generally it is discouraged to let individual drivers get and enable pin
1178control. So if possible, handle the pin control in platform code or some other
1179place where you have access to all the affected struct device * pointers. In
1180some cases where a driver needs to e.g. switch between different mux mappings
1181at runtime this is not possible.
1182
1183A typical case is if a driver needs to switch bias of pins from normal
1184operation and going to sleep, moving from the ``PINCTRL_STATE_DEFAULT`` to
1185``PINCTRL_STATE_SLEEP`` at runtime, re-biasing or even re-muxing pins to save
1186current in sleep mode.
1187
1188A driver may request a certain control state to be activated, usually just the
1189default state like this:
1190
1191.. code-block:: c
1192
1193	#include <linux/pinctrl/consumer.h>
1194
1195	struct foo_state {
1196	struct pinctrl *p;
1197	struct pinctrl_state *s;
1198	...
1199	};
1200
1201	foo_probe()
1202	{
1203		/* Allocate a state holder named "foo" etc */
1204		struct foo_state *foo = ...;
1205
1206		foo->p = devm_pinctrl_get(&device);
1207		if (IS_ERR(foo->p)) {
1208			/* FIXME: clean up "foo" here */
1209			return PTR_ERR(foo->p);
1210		}
1211
1212		foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
1213		if (IS_ERR(foo->s)) {
1214			/* FIXME: clean up "foo" here */
1215			return PTR_ERR(foo->s);
1216		}
1217
1218		ret = pinctrl_select_state(foo->p, foo->s);
1219		if (ret < 0) {
1220			/* FIXME: clean up "foo" here */
1221			return ret;
1222		}
1223	}
1224
1225This get/lookup/select/put sequence can just as well be handled by bus drivers
1226if you don't want each and every driver to handle it and you know the
1227arrangement on your bus.
1228
1229The semantics of the pinctrl APIs are:
1230
1231- ``pinctrl_get()`` is called in process context to obtain a handle to all pinctrl
1232  information for a given client device. It will allocate a struct from the
1233  kernel memory to hold the pinmux state. All mapping table parsing or similar
1234  slow operations take place within this API.
1235
1236- ``devm_pinctrl_get()`` is a variant of pinctrl_get() that causes ``pinctrl_put()``
1237  to be called automatically on the retrieved pointer when the associated
1238  device is removed. It is recommended to use this function over plain
1239  ``pinctrl_get()``.
1240
1241- ``pinctrl_lookup_state()`` is called in process context to obtain a handle to a
1242  specific state for a client device. This operation may be slow, too.
1243
1244- ``pinctrl_select_state()`` programs pin controller hardware according to the
1245  definition of the state as given by the mapping table. In theory, this is a
1246  fast-path operation, since it only involved blasting some register settings
1247  into hardware. However, note that some pin controllers may have their
1248  registers on a slow/IRQ-based bus, so client devices should not assume they
1249  can call ``pinctrl_select_state()`` from non-blocking contexts.
1250
1251- ``pinctrl_put()`` frees all information associated with a pinctrl handle.
1252
1253- ``devm_pinctrl_put()`` is a variant of ``pinctrl_put()`` that may be used to
1254  explicitly destroy a pinctrl object returned by ``devm_pinctrl_get()``.
1255  However, use of this function will be rare, due to the automatic cleanup
1256  that will occur even without calling it.
1257
1258  ``pinctrl_get()`` must be paired with a plain ``pinctrl_put()``.
1259  ``pinctrl_get()`` may not be paired with ``devm_pinctrl_put()``.
1260  ``devm_pinctrl_get()`` can optionally be paired with ``devm_pinctrl_put()``.
1261  ``devm_pinctrl_get()`` may not be paired with plain ``pinctrl_put()``.
1262
1263Usually the pin control core handled the get/put pair and call out to the
1264device drivers bookkeeping operations, like checking available functions and
1265the associated pins, whereas ``pinctrl_select_state()`` pass on to the pin controller
1266driver which takes care of activating and/or deactivating the mux setting by
1267quickly poking some registers.
1268
1269The pins are allocated for your device when you issue the ``devm_pinctrl_get()``
1270call, after this you should be able to see this in the debugfs listing of all
1271pins.
1272
1273NOTE: the pinctrl system will return ``-EPROBE_DEFER`` if it cannot find the
1274requested pinctrl handles, for example if the pinctrl driver has not yet
1275registered. Thus make sure that the error path in your driver gracefully
1276cleans up and is ready to retry the probing later in the startup process.
1277
1278
1279Drivers needing both pin control and GPIOs
1280==========================================
1281
1282Again, it is discouraged to let drivers lookup and select pin control states
1283themselves, but again sometimes this is unavoidable.
1284
1285So say that your driver is fetching its resources like this:
1286
1287.. code-block:: c
1288
1289	#include <linux/pinctrl/consumer.h>
1290	#include <linux/gpio/consumer.h>
1291
1292	struct pinctrl *pinctrl;
1293	struct gpio_desc *gpio;
1294
1295	pinctrl = devm_pinctrl_get_select_default(&dev);
1296	gpio = devm_gpiod_get(&dev, "foo");
1297
1298Here we first request a certain pin state and then request GPIO "foo" to be
1299used. If you're using the subsystems orthogonally like this, you should
1300nominally always get your pinctrl handle and select the desired pinctrl
1301state BEFORE requesting the GPIO. This is a semantic convention to avoid
1302situations that can be electrically unpleasant, you will certainly want to
1303mux in and bias pins in a certain way before the GPIO subsystems starts to
1304deal with them.
1305
1306The above can be hidden: using the device core, the pinctrl core may be
1307setting up the config and muxing for the pins right before the device is
1308probing, nevertheless orthogonal to the GPIO subsystem.
1309
1310But there are also situations where it makes sense for the GPIO subsystem
1311to communicate directly with the pinctrl subsystem, using the latter as a
1312back-end. This is when the GPIO driver may call out to the functions
1313described in the section `Pin control interaction with the GPIO subsystem`_
1314above. This only involves per-pin multiplexing, and will be completely
1315hidden behind the gpiod_*() function namespace. In this case, the driver
1316need not interact with the pin control subsystem at all.
1317
1318If a pin control driver and a GPIO driver is dealing with the same pins
1319and the use cases involve multiplexing, you MUST implement the pin controller
1320as a back-end for the GPIO driver like this, unless your hardware design
1321is such that the GPIO controller can override the pin controller's
1322multiplexing state through hardware without the need to interact with the
1323pin control system.
1324
1325
1326System pin control hogging
1327==========================
1328
1329Pin control map entries can be hogged by the core when the pin controller
1330is registered. This means that the core will attempt to call ``pinctrl_get()``,
1331``pinctrl_lookup_state()`` and ``pinctrl_select_state()`` on it immediately after
1332the pin control device has been registered.
1333
1334This occurs for mapping table entries where the client device name is equal
1335to the pin controller device name, and the state name is ``PINCTRL_STATE_DEFAULT``:
1336
1337.. code-block:: c
1338
1339	{
1340		.dev_name = "pinctrl-foo",
1341		.name = PINCTRL_STATE_DEFAULT,
1342		.type = PIN_MAP_TYPE_MUX_GROUP,
1343		.ctrl_dev_name = "pinctrl-foo",
1344		.function = "power_func",
1345	},
1346
1347Since it may be common to request the core to hog a few always-applicable
1348mux settings on the primary pin controller, there is a convenience macro for
1349this:
1350
1351.. code-block:: c
1352
1353	PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */,
1354				      "power_func")
1355
1356This gives the exact same result as the above construction.
1357
1358
1359Runtime pinmuxing
1360=================
1361
1362It is possible to mux a certain function in and out at runtime, say to move
1363an SPI port from one set of pins to another set of pins. Say for example for
1364spi0 in the example above, we expose two different groups of pins for the same
1365function, but with different named in the mapping as described under
1366"Advanced mapping" above. So that for an SPI device, we have two states named
1367"pos-A" and "pos-B".
1368
1369This snippet first initializes a state object for both groups (in foo_probe()),
1370then muxes the function in the pins defined by group A, and finally muxes it in
1371on the pins defined by group B:
1372
1373.. code-block:: c
1374
1375	#include <linux/pinctrl/consumer.h>
1376
1377	struct pinctrl *p;
1378	struct pinctrl_state *s1, *s2;
1379
1380	foo_probe()
1381	{
1382		/* Setup */
1383		p = devm_pinctrl_get(&device);
1384		if (IS_ERR(p))
1385			...
1386
1387		s1 = pinctrl_lookup_state(p, "pos-A");
1388		if (IS_ERR(s1))
1389			...
1390
1391		s2 = pinctrl_lookup_state(p, "pos-B");
1392		if (IS_ERR(s2))
1393			...
1394	}
1395
1396	foo_switch()
1397	{
1398		/* Enable on position A */
1399		ret = pinctrl_select_state(p, s1);
1400		if (ret < 0)
1401			...
1402
1403		...
1404
1405		/* Enable on position B */
1406		ret = pinctrl_select_state(p, s2);
1407		if (ret < 0)
1408			...
1409
1410		...
1411	}
1412
1413The above has to be done from process context. The reservation of the pins
1414will be done when the state is activated, so in effect one specific pin
1415can be used by different functions at different times on a running system.
1416
1417
1418Debugfs files
1419=============
1420
1421These files are created in ``/sys/kernel/debug/pinctrl``:
1422
1423- ``pinctrl-devices``: prints each pin controller device along with columns to
1424  indicate support for pinmux and pinconf
1425
1426- ``pinctrl-handles``: prints each configured pin controller handle and the
1427  corresponding pinmux maps
1428
1429- ``pinctrl-maps``: prints all pinctrl maps
1430
1431A sub-directory is created inside of ``/sys/kernel/debug/pinctrl`` for each pin
1432controller device containing these files:
1433
1434- ``pins``: prints a line for each pin registered on the pin controller. The
1435  pinctrl driver may add additional information such as register contents.
1436
1437- ``gpio-ranges``: prints ranges that map gpio lines to pins on the controller
1438
1439- ``pingroups``: prints all pin groups registered on the pin controller
1440
1441- ``pinconf-pins``: prints pin config settings for each pin
1442
1443- ``pinconf-groups``: prints pin config settings per pin group
1444
1445- ``pinmux-functions``: prints each pin function along with the pin groups that
1446  map to the pin function
1447
1448- ``pinmux-pins``: iterates through all pins and prints mux owner, gpio owner
1449  and if the pin is a hog
1450
1451- ``pinmux-select``: write to this file to activate a pin function for a group:
1452
1453  .. code-block:: sh
1454
1455        echo "<group-name function-name>" > pinmux-select

   1===============================
   2PINCTRL (PIN CONTROL) subsystem
   3===============================
   4
   5This document outlines the pin control subsystem in Linux
   6
   7This subsystem deals with:
   8
   9- Enumerating and naming controllable pins
  10
  11- Multiplexing of pins, pads, fingers (etc) see below for details
  12
  13- Configuration of pins, pads, fingers (etc), such as software-controlled
  14  biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
  15  load capacitance etc.
  16
  17Top-level interface
  18===================
  19
  20Definitions:
  21
  22- A PIN CONTROLLER is a piece of hardware, usually a set of registers, that
  23  can control PINs. It may be able to multiplex, bias, set load capacitance,
  24  set drive strength, etc. for individual pins or groups of pins.
  25
  26- PINS are equal to pads, fingers, balls or whatever packaging input or
  27  output line you want to control and these are denoted by unsigned integers
  28  in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
  29  there may be several such number spaces in a system. This pin space may
  30  be sparse - i.e. there may be gaps in the space with numbers where no
  31  pin exists.
  32
  33When a PIN CONTROLLER is instantiated, it will register a descriptor to the
  34pin control framework, and this descriptor contains an array of pin descriptors
  35describing the pins handled by this specific pin controller.
  36
  37Here is an example of a PGA (Pin Grid Array) chip seen from underneath::
  38
  39        A   B   C   D   E   F   G   H
  40
  41   8    o   o   o   o   o   o   o   o
  42
  43   7    o   o   o   o   o   o   o   o
  44
  45   6    o   o   o   o   o   o   o   o
  46
  47   5    o   o   o   o   o   o   o   o
  48
  49   4    o   o   o   o   o   o   o   o
  50
  51   3    o   o   o   o   o   o   o   o
  52
  53   2    o   o   o   o   o   o   o   o
  54
  55   1    o   o   o   o   o   o   o   o
  56
  57To register a pin controller and name all the pins on this package we can do
  58this in our driver:
  59
  60.. code-block:: c
  61
  62	#include <linux/pinctrl/pinctrl.h>
  63
  64	const struct pinctrl_pin_desc foo_pins[] = {
  65		PINCTRL_PIN(0, "A8"),
  66		PINCTRL_PIN(1, "B8"),
  67		PINCTRL_PIN(2, "C8"),
  68		...
  69		PINCTRL_PIN(61, "F1"),
  70		PINCTRL_PIN(62, "G1"),
  71		PINCTRL_PIN(63, "H1"),
  72	};
  73
  74	static struct pinctrl_desc foo_desc = {
  75		.name = "foo",
  76		.pins = foo_pins,
  77		.npins = ARRAY_SIZE(foo_pins),
  78		.owner = THIS_MODULE,
  79	};
  80
  81	int __init foo_init(void)
  82	{
  83		int error;
  84
  85		struct pinctrl_dev *pctl;
  86
  87		error = pinctrl_register_and_init(&foo_desc, <PARENT>, NULL, &pctl);
  88		if (error)
  89			return error;
  90
  91		return pinctrl_enable(pctl);
  92	}
  93
  94To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and
  95selected drivers, you need to select them from your machine's Kconfig entry,
  96since these are so tightly integrated with the machines they are used on.
  97See ``arch/arm/mach-ux500/Kconfig`` for an example.
  98
  99Pins usually have fancier names than this. You can find these in the datasheet
 100for your chip. Notice that the core pinctrl.h file provides a fancy macro
 101called ``PINCTRL_PIN()`` to create the struct entries. As you can see the pins are
 102enumerated from 0 in the upper left corner to 63 in the lower right corner.
 103This enumeration was arbitrarily chosen, in practice you need to think
 104through your numbering system so that it matches the layout of registers
 105and such things in your driver, or the code may become complicated. You must
 106also consider matching of offsets to the GPIO ranges that may be handled by
 107the pin controller.
 108
 109For a padding with 467 pads, as opposed to actual pins, the enumeration will
 110be like this, walking around the edge of the chip, which seems to be industry
 111standard too (all these pads had names, too)::
 112
 113
 114     0 ..... 104
 115   466        105
 116     .        .
 117     .        .
 118   358        224
 119    357 .... 225
 120
 121
 122Pin groups
 123==========
 124
 125Many controllers need to deal with groups of pins, so the pin controller
 126subsystem has a mechanism for enumerating groups of pins and retrieving the
 127actual enumerated pins that are part of a certain group.
 128
 129For example, say that we have a group of pins dealing with an SPI interface
 130on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins
 131on { 24, 25 }.
 132
 133These two groups are presented to the pin control subsystem by implementing
 134some generic ``pinctrl_ops`` like this:
 135
 136.. code-block:: c
 137
 138	#include <linux/pinctrl/pinctrl.h>
 139
 140	static const unsigned int spi0_pins[] = { 0, 8, 16, 24 };
 141	static const unsigned int i2c0_pins[] = { 24, 25 };
 142
 143	static const struct pingroup foo_groups[] = {
 144		PINCTRL_PINGROUP("spi0_grp", spi0_pins, ARRAY_SIZE(spi0_pins)),
 145		PINCTRL_PINGROUP("i2c0_grp", i2c0_pins, ARRAY_SIZE(i2c0_pins)),
 146	};
 147
 148	static int foo_get_groups_count(struct pinctrl_dev *pctldev)
 149	{
 150		return ARRAY_SIZE(foo_groups);
 151	}
 152
 153	static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
 154					      unsigned int selector)
 155	{
 156		return foo_groups[selector].name;
 157	}
 158
 159	static int foo_get_group_pins(struct pinctrl_dev *pctldev,
 160				      unsigned int selector,
 161				      const unsigned int **pins,
 162				      unsigned int *npins)
 163	{
 164		*pins = foo_groups[selector].pins;
 165		*npins = foo_groups[selector].npins;
 166		return 0;
 167	}
 168
 169	static struct pinctrl_ops foo_pctrl_ops = {
 170		.get_groups_count = foo_get_groups_count,
 171		.get_group_name = foo_get_group_name,
 172		.get_group_pins = foo_get_group_pins,
 173	};
 174
 175	static struct pinctrl_desc foo_desc = {
 176		...
 177		.pctlops = &foo_pctrl_ops,
 178	};
 179
 180The pin control subsystem will call the ``.get_groups_count()`` function to
 181determine the total number of legal selectors, then it will call the other functions
 182to retrieve the name and pins of the group. Maintaining the data structure of
 183the groups is up to the driver, this is just a simple example - in practice you
 184may need more entries in your group structure, for example specific register
 185ranges associated with each group and so on.
 186
 187
 188Pin configuration
 189=================
 190
 191Pins can sometimes be software-configured in various ways, mostly related
 192to their electronic properties when used as inputs or outputs. For example you
 193may be able to make an output pin high impedance (Hi-Z), or "tristate" meaning it is
 194effectively disconnected. You may be able to connect an input pin to VDD or GND
 195using a certain resistor value - pull up and pull down - so that the pin has a
 196stable value when nothing is driving the rail it is connected to, or when it's
 197unconnected.
 198
 199Pin configuration can be programmed by adding configuration entries into the
 200mapping table; see section `Board/machine configuration`_ below.
 201
 202The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP
 203above, is entirely defined by the pin controller driver.
 204
 205The pin configuration driver implements callbacks for changing pin
 206configuration in the pin controller ops like this:
 207
 208.. code-block:: c
 209
 210	#include <linux/pinctrl/pinconf.h>
 211	#include <linux/pinctrl/pinctrl.h>
 212
 213	#include "platform_x_pindefs.h"
 214
 215	static int foo_pin_config_get(struct pinctrl_dev *pctldev,
 216				      unsigned int offset,
 217				      unsigned long *config)
 218	{
 219		struct my_conftype conf;
 220
 221		/* ... Find setting for pin @ offset ... */
 222
 223		*config = (unsigned long) conf;
 224	}
 225
 226	static int foo_pin_config_set(struct pinctrl_dev *pctldev,
 227				      unsigned int offset,
 228				      unsigned long config)
 229	{
 230		struct my_conftype *conf = (struct my_conftype *) config;
 231
 232		switch (conf) {
 233			case PLATFORM_X_PULL_UP:
 234			...
 235			break;
 236		}
 237	}
 238
 239	static int foo_pin_config_group_get(struct pinctrl_dev *pctldev,
 240					    unsigned selector,
 241					    unsigned long *config)
 242	{
 243		...
 244	}
 245
 246	static int foo_pin_config_group_set(struct pinctrl_dev *pctldev,
 247					    unsigned selector,
 248					    unsigned long config)
 249	{
 250		...
 251	}
 252
 253	static struct pinconf_ops foo_pconf_ops = {
 254		.pin_config_get = foo_pin_config_get,
 255		.pin_config_set = foo_pin_config_set,
 256		.pin_config_group_get = foo_pin_config_group_get,
 257		.pin_config_group_set = foo_pin_config_group_set,
 258	};
 259
 260	/* Pin config operations are handled by some pin controller */
 261	static struct pinctrl_desc foo_desc = {
 262		...
 263		.confops = &foo_pconf_ops,
 264	};
 265
 266Interaction with the GPIO subsystem
 267===================================
 268
 269The GPIO drivers may want to perform operations of various types on the same
 270physical pins that are also registered as pin controller pins.
 271
 272First and foremost, the two subsystems can be used as completely orthogonal,
 273see the section named `Pin control requests from drivers`_ and
 274`Drivers needing both pin control and GPIOs`_ below for details. But in some
 275situations a cross-subsystem mapping between pins and GPIOs is needed.
 276
 277Since the pin controller subsystem has its pinspace local to the pin controller
 278we need a mapping so that the pin control subsystem can figure out which pin
 279controller handles control of a certain GPIO pin. Since a single pin controller
 280may be muxing several GPIO ranges (typically SoCs that have one set of pins,
 281but internally several GPIO silicon blocks, each modelled as a struct
 282gpio_chip) any number of GPIO ranges can be added to a pin controller instance
 283like this:
 284
 285.. code-block:: c
 286
 287	#include <linux/gpio/driver.h>
 288
 289	#include <linux/pinctrl/pinctrl.h>
 290
 291	struct gpio_chip chip_a;
 292	struct gpio_chip chip_b;
 293
 294	static struct pinctrl_gpio_range gpio_range_a = {
 295		.name = "chip a",
 296		.id = 0,
 297		.base = 32,
 298		.pin_base = 32,
 299		.npins = 16,
 300		.gc = &chip_a,
 301	};
 302
 303	static struct pinctrl_gpio_range gpio_range_b = {
 304		.name = "chip b",
 305		.id = 0,
 306		.base = 48,
 307		.pin_base = 64,
 308		.npins = 8,
 309		.gc = &chip_b;
 310	};
 311
 312	int __init foo_init(void)
 313	{
 314		struct pinctrl_dev *pctl;
 315		...
 316		pinctrl_add_gpio_range(pctl, &gpio_range_a);
 317		pinctrl_add_gpio_range(pctl, &gpio_range_b);
 318		...
 319	}
 320
 321So this complex system has one pin controller handling two different
 322GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and
 323"chip b" have different ``pin_base``, which means a start pin number of the
 324GPIO range.
 325
 326The GPIO range of "chip a" starts from the GPIO base of 32 and actual
 327pin range also starts from 32. However "chip b" has different starting
 328offset for the GPIO range and pin range. The GPIO range of "chip b" starts
 329from GPIO number 48, while the pin range of "chip b" starts from 64.
 330
 331We can convert a gpio number to actual pin number using this ``pin_base``.
 332They are mapped in the global GPIO pin space at:
 333
 334chip a:
 335 - GPIO range : [32 .. 47]
 336 - pin range  : [32 .. 47]
 337chip b:
 338 - GPIO range : [48 .. 55]
 339 - pin range  : [64 .. 71]
 340
 341The above examples assume the mapping between the GPIOs and pins is
 342linear. If the mapping is sparse or haphazard, an array of arbitrary pin
 343numbers can be encoded in the range like this:
 344
 345.. code-block:: c
 346
 347	static const unsigned int range_pins[] = { 14, 1, 22, 17, 10, 8, 6, 2 };
 348
 349	static struct pinctrl_gpio_range gpio_range = {
 350		.name = "chip",
 351		.id = 0,
 352		.base = 32,
 353		.pins = &range_pins,
 354		.npins = ARRAY_SIZE(range_pins),
 355		.gc = &chip,
 356	};
 357
 358In this case the ``pin_base`` property will be ignored. If the name of a pin
 359group is known, the pins and npins elements of the above structure can be
 360initialised using the function ``pinctrl_get_group_pins()``, e.g. for pin
 361group "foo":
 362
 363.. code-block:: c
 364
 365	pinctrl_get_group_pins(pctl, "foo", &gpio_range.pins, &gpio_range.npins);
 366
 367When GPIO-specific functions in the pin control subsystem are called, these
 368ranges will be used to look up the appropriate pin controller by inspecting
 369and matching the pin to the pin ranges across all controllers. When a
 370pin controller handling the matching range is found, GPIO-specific functions
 371will be called on that specific pin controller.
 372
 373For all functionalities dealing with pin biasing, pin muxing etc, the pin
 374controller subsystem will look up the corresponding pin number from the passed
 375in gpio number, and use the range's internals to retrieve a pin number. After
 376that, the subsystem passes it on to the pin control driver, so the driver
 377will get a pin number into its handled number range. Further it is also passed
 378the range ID value, so that the pin controller knows which range it should
 379deal with.
 380
 381Calling ``pinctrl_add_gpio_range()`` from pinctrl driver is DEPRECATED. Please see
 382section 2.1 of ``Documentation/devicetree/bindings/gpio/gpio.txt`` on how to bind
 383pinctrl and gpio drivers.
 384
 385
 386PINMUX interfaces
 387=================
 388
 389These calls use the pinmux_* naming prefix.  No other calls should use that
 390prefix.
 391
 392
 393What is pinmuxing?
 394==================
 395
 396PINMUX, also known as padmux, ballmux, alternate functions or mission modes
 397is a way for chip vendors producing some kind of electrical packages to use
 398a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive
 399functions, depending on the application. By "application" in this context
 400we usually mean a way of soldering or wiring the package into an electronic
 401system, even though the framework makes it possible to also change the function
 402at runtime.
 403
 404Here is an example of a PGA (Pin Grid Array) chip seen from underneath::
 405
 406        A   B   C   D   E   F   G   H
 407      +---+
 408   8  | o | o   o   o   o   o   o   o
 409      |   |
 410   7  | o | o   o   o   o   o   o   o
 411      |   |
 412   6  | o | o   o   o   o   o   o   o
 413      +---+---+
 414   5  | o | o | o   o   o   o   o   o
 415      +---+---+               +---+
 416   4    o   o   o   o   o   o | o | o
 417                              |   |
 418   3    o   o   o   o   o   o | o | o
 419                              |   |
 420   2    o   o   o   o   o   o | o | o
 421      +-------+-------+-------+---+---+
 422   1  | o   o | o   o | o   o | o | o |
 423      +-------+-------+-------+---+---+
 424
 425This is not tetris. The game to think of is chess. Not all PGA/BGA packages
 426are chessboard-like, big ones have "holes" in some arrangement according to
 427different design patterns, but we're using this as a simple example. Of the
 428pins you see some will be taken by things like a few VCC and GND to feed power
 429to the chip, and quite a few will be taken by large ports like an external
 430memory interface. The remaining pins will often be subject to pin multiplexing.
 431
 432The example 8x8 PGA package above will have pin numbers 0 through 63 assigned
 433to its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using
 434pinctrl_register_pins() and a suitable data set as shown earlier.
 435
 436In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port
 437(these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as
 438some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can
 439be used as an I2C port (these are just two pins: SCL, SDA). Needless to say,
 440we cannot use the SPI port and I2C port at the same time. However in the inside
 441of the package the silicon performing the SPI logic can alternatively be routed
 442out on pins { G4, G3, G2, G1 }.
 443
 444On the bottom row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something
 445special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will
 446consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or
 447{ A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI
 448port on pins { G4, G3, G2, G1 } of course.
 449
 450This way the silicon blocks present inside the chip can be multiplexed "muxed"
 451out on different pin ranges. Often contemporary SoC (systems on chip) will
 452contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to
 453different pins by pinmux settings.
 454
 455Since general-purpose I/O pins (GPIO) are typically always in shortage, it is
 456common to be able to use almost any pin as a GPIO pin if it is not currently
 457in use by some other I/O port.
 458
 459
 460Pinmux conventions
 461==================
 462
 463The purpose of the pinmux functionality in the pin controller subsystem is to
 464abstract and provide pinmux settings to the devices you choose to instantiate
 465in your machine configuration. It is inspired by the clk, GPIO and regulator
 466subsystems, so devices will request their mux setting, but it's also possible
 467to request a single pin for e.g. GPIO.
 468
 469The conventions are:
 470
 471- FUNCTIONS can be switched in and out by a driver residing with the pin
 472  control subsystem in the ``drivers/pinctrl`` directory of the kernel. The
 473  pin control driver knows the possible functions. In the example above you can
 474  identify three pinmux functions, one for spi, one for i2c and one for mmc.
 475
 476- FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array.
 477  In this case the array could be something like: { spi0, i2c0, mmc0 }
 478  for the three available functions.
 479
 480- FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain
 481  function is *always* associated with a certain set of pin groups, could
 482  be just a single one, but could also be many. In the example above the
 483  function i2c is associated with the pins { A5, B5 }, enumerated as
 484  { 24, 25 } in the controller pin space.
 485
 486  The Function spi is associated with pin groups { A8, A7, A6, A5 }
 487  and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and
 488  { 38, 46, 54, 62 } respectively.
 489
 490  Group names must be unique per pin controller, no two groups on the same
 491  controller may have the same name.
 492
 493- The combination of a FUNCTION and a PIN GROUP determine a certain function
 494  for a certain set of pins. The knowledge of the functions and pin groups
 495  and their machine-specific particulars are kept inside the pinmux driver,
 496  from the outside only the enumerators are known, and the driver core can
 497  request:
 498
 499  - The name of a function with a certain selector (>= 0)
 500  - A list of groups associated with a certain function
 501  - That a certain group in that list to be activated for a certain function
 502
 503  As already described above, pin groups are in turn self-descriptive, so
 504  the core will retrieve the actual pin range in a certain group from the
 505  driver.
 506
 507- FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain
 508  device by the board file, device tree or similar machine setup configuration
 509  mechanism, similar to how regulators are connected to devices, usually by
 510  name. Defining a pin controller, function and group thus uniquely identify
 511  the set of pins to be used by a certain device. (If only one possible group
 512  of pins is available for the function, no group name need to be supplied -
 513  the core will simply select the first and only group available.)
 514
 515  In the example case we can define that this particular machine shall
 516  use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function
 517  fi2c0 group gi2c0, on the primary pin controller, we get mappings
 518  like these:
 519
 520  .. code-block:: c
 521
 522	{
 523		{"map-spi0", spi0, pinctrl0, fspi0, gspi0},
 524		{"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0},
 525	}
 526
 527  Every map must be assigned a state name, pin controller, device and
 528  function. The group is not compulsory - if it is omitted the first group
 529  presented by the driver as applicable for the function will be selected,
 530  which is useful for simple cases.
 531
 532  It is possible to map several groups to the same combination of device,
 533  pin controller and function. This is for cases where a certain function on
 534  a certain pin controller may use different sets of pins in different
 535  configurations.
 536
 537- PINS for a certain FUNCTION using a certain PIN GROUP on a certain
 538  PIN CONTROLLER are provided on a first-come first-serve basis, so if some
 539  other device mux setting or GPIO pin request has already taken your physical
 540  pin, you will be denied the use of it. To get (activate) a new setting, the
 541  old one has to be put (deactivated) first.
 542
 543Sometimes the documentation and hardware registers will be oriented around
 544pads (or "fingers") rather than pins - these are the soldering surfaces on the
 545silicon inside the package, and may or may not match the actual number of
 546pins/balls underneath the capsule. Pick some enumeration that makes sense to
 547you. Define enumerators only for the pins you can control if that makes sense.
 548
 549Assumptions:
 550
 551We assume that the number of possible function maps to pin groups is limited by
 552the hardware. I.e. we assume that there is no system where any function can be
 553mapped to any pin, like in a phone exchange. So the available pin groups for
 554a certain function will be limited to a few choices (say up to eight or so),
 555not hundreds or any amount of choices. This is the characteristic we have found
 556by inspecting available pinmux hardware, and a necessary assumption since we
 557expect pinmux drivers to present *all* possible function vs pin group mappings
 558to the subsystem.
 559
 560
 561Pinmux drivers
 562==============
 563
 564The pinmux core takes care of preventing conflicts on pins and calling
 565the pin controller driver to execute different settings.
 566
 567It is the responsibility of the pinmux driver to impose further restrictions
 568(say for example infer electronic limitations due to load, etc.) to determine
 569whether or not the requested function can actually be allowed, and in case it
 570is possible to perform the requested mux setting, poke the hardware so that
 571this happens.
 572
 573Pinmux drivers are required to supply a few callback functions, some are
 574optional. Usually the ``.set_mux()`` function is implemented, writing values into
 575some certain registers to activate a certain mux setting for a certain pin.
 576
 577A simple driver for the above example will work by setting bits 0, 1, 2, 3, 4, or 5
 578into some register named MUX to select a certain function with a certain
 579group of pins would work something like this:
 580
 581.. code-block:: c
 582
 583	#include <linux/pinctrl/pinctrl.h>
 584	#include <linux/pinctrl/pinmux.h>
 585
 586	static const unsigned int spi0_0_pins[] = { 0, 8, 16, 24 };
 587	static const unsigned int spi0_1_pins[] = { 38, 46, 54, 62 };
 588	static const unsigned int i2c0_pins[] = { 24, 25 };
 589	static const unsigned int mmc0_1_pins[] = { 56, 57 };
 590	static const unsigned int mmc0_2_pins[] = { 58, 59 };
 591	static const unsigned int mmc0_3_pins[] = { 60, 61, 62, 63 };
 592
 593	static const struct pingroup foo_groups[] = {
 594		PINCTRL_PINGROUP("spi0_0_grp", spi0_0_pins, ARRAY_SIZE(spi0_0_pins)),
 595		PINCTRL_PINGROUP("spi0_1_grp", spi0_1_pins, ARRAY_SIZE(spi0_1_pins)),
 596		PINCTRL_PINGROUP("i2c0_grp", i2c0_pins, ARRAY_SIZE(i2c0_pins)),
 597		PINCTRL_PINGROUP("mmc0_1_grp", mmc0_1_pins, ARRAY_SIZE(mmc0_1_pins)),
 598		PINCTRL_PINGROUP("mmc0_2_grp", mmc0_2_pins, ARRAY_SIZE(mmc0_2_pins)),
 599		PINCTRL_PINGROUP("mmc0_3_grp", mmc0_3_pins, ARRAY_SIZE(mmc0_3_pins)),
 600	};
 601
 602	static int foo_get_groups_count(struct pinctrl_dev *pctldev)
 603	{
 604		return ARRAY_SIZE(foo_groups);
 605	}
 606
 607	static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
 608					      unsigned int selector)
 609	{
 610		return foo_groups[selector].name;
 611	}
 612
 613	static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
 614				      const unsigned int **pins,
 615				      unsigned int *npins)
 616	{
 617		*pins = foo_groups[selector].pins;
 618		*npins = foo_groups[selector].npins;
 619		return 0;
 620	}
 621
 622	static struct pinctrl_ops foo_pctrl_ops = {
 623		.get_groups_count = foo_get_groups_count,
 624		.get_group_name = foo_get_group_name,
 625		.get_group_pins = foo_get_group_pins,
 626	};
 627
 628	static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
 629	static const char * const i2c0_groups[] = { "i2c0_grp" };
 630	static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp", "mmc0_3_grp" };
 631
 632	static const struct pinfunction foo_functions[] = {
 633		PINCTRL_PINFUNCTION("spi0", spi0_groups, ARRAY_SIZE(spi0_groups)),
 634		PINCTRL_PINFUNCTION("i2c0", i2c0_groups, ARRAY_SIZE(i2c0_groups)),
 635		PINCTRL_PINFUNCTION("mmc0", mmc0_groups, ARRAY_SIZE(mmc0_groups)),
 636	};
 637
 638	static int foo_get_functions_count(struct pinctrl_dev *pctldev)
 639	{
 640		return ARRAY_SIZE(foo_functions);
 641	}
 642
 643	static const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned int selector)
 644	{
 645		return foo_functions[selector].name;
 646	}
 647
 648	static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned int selector,
 649				  const char * const **groups,
 650				  unsigned int * const ngroups)
 651	{
 652		*groups = foo_functions[selector].groups;
 653		*ngroups = foo_functions[selector].ngroups;
 654		return 0;
 655	}
 656
 657	static int foo_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
 658			       unsigned int group)
 659	{
 660		u8 regbit = BIT(group);
 661
 662		writeb((readb(MUX) | regbit), MUX);
 663		return 0;
 664	}
 665
 666	static struct pinmux_ops foo_pmxops = {
 667		.get_functions_count = foo_get_functions_count,
 668		.get_function_name = foo_get_fname,
 669		.get_function_groups = foo_get_groups,
 670		.set_mux = foo_set_mux,
 671		.strict = true,
 672	};
 673
 674	/* Pinmux operations are handled by some pin controller */
 675	static struct pinctrl_desc foo_desc = {
 676		...
 677		.pctlops = &foo_pctrl_ops,
 678		.pmxops = &foo_pmxops,
 679	};
 680
 681In the example activating muxing 0 and 2 at the same time setting bits
 6820 and 2, uses pin 24 in common so they would collide. All the same for
 683the muxes 1 and 5, which have pin 62 in common.
 684
 685The beauty of the pinmux subsystem is that since it keeps track of all
 686pins and who is using them, it will already have denied an impossible
 687request like that, so the driver does not need to worry about such
 688things - when it gets a selector passed in, the pinmux subsystem makes
 689sure no other device or GPIO assignment is already using the selected
 690pins. Thus bits 0 and 2, or 1 and 5 in the control register will never
 691be set at the same time.
 692
 693All the above functions are mandatory to implement for a pinmux driver.
 694
 695
 696Pin control interaction with the GPIO subsystem
 697===============================================
 698
 699Note that the following implies that the use case is to use a certain pin
 700from the Linux kernel using the API in ``<linux/gpio/consumer.h>`` with gpiod_get()
 701and similar functions. There are cases where you may be using something
 702that your datasheet calls "GPIO mode", but actually is just an electrical
 703configuration for a certain device. See the section below named
 704`GPIO mode pitfalls`_ for more details on this scenario.
 705
 706The public pinmux API contains two functions named ``pinctrl_gpio_request()``
 707and ``pinctrl_gpio_free()``. These two functions shall *ONLY* be called from
 708gpiolib-based drivers as part of their ``.request()`` and ``.free()`` semantics.
 709Likewise the ``pinctrl_gpio_direction_input()`` / ``pinctrl_gpio_direction_output()``
 710shall only be called from within respective ``.direction_input()`` /
 711``.direction_output()`` gpiolib implementation.
 712
 713NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be
 714controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have
 715that driver request proper muxing and other control for its pins.
 716
 717The function list could become long, especially if you can convert every
 718individual pin into a GPIO pin independent of any other pins, and then try
 719the approach to define every pin as a function.
 720
 721In this case, the function array would become 64 entries for each GPIO
 722setting and then the device functions.
 723
 724For this reason there are two functions a pin control driver can implement
 725to enable only GPIO on an individual pin: ``.gpio_request_enable()`` and
 726``.gpio_disable_free()``.
 727
 728This function will pass in the affected GPIO range identified by the pin
 729controller core, so you know which GPIO pins are being affected by the request
 730operation.
 731
 732If your driver needs to have an indication from the framework of whether the
 733GPIO pin shall be used for input or output you can implement the
 734``.gpio_set_direction()`` function. As described this shall be called from the
 735gpiolib driver and the affected GPIO range, pin offset and desired direction
 736will be passed along to this function.
 737
 738Alternatively to using these special functions, it is fully allowed to use
 739named functions for each GPIO pin, the ``pinctrl_gpio_request()`` will attempt to
 740obtain the function "gpioN" where "N" is the global GPIO pin number if no
 741special GPIO-handler is registered.
 742
 743
 744GPIO mode pitfalls
 745==================
 746
 747Due to the naming conventions used by hardware engineers, where "GPIO"
 748is taken to mean different things than what the kernel does, the developer
 749may be confused by a datasheet talking about a pin being possible to set
 750into "GPIO mode". It appears that what hardware engineers mean with
 751"GPIO mode" is not necessarily the use case that is implied in the kernel
 752interface ``<linux/gpio/consumer.h>``: a pin that you grab from kernel code and then
 753either listen for input or drive high/low to assert/deassert some
 754external line.
 755
 756Rather hardware engineers think that "GPIO mode" means that you can
 757software-control a few electrical properties of the pin that you would
 758not be able to control if the pin was in some other mode, such as muxed in
 759for a device.
 760
 761The GPIO portions of a pin and its relation to a certain pin controller
 762configuration and muxing logic can be constructed in several ways. Here
 763are two examples.
 764
 765Example **(A)**::
 766
 767                       pin config
 768                       logic regs
 769                       |               +- SPI
 770     Physical pins --- pad --- pinmux -+- I2C
 771                               |       +- mmc
 772                               |       +- GPIO
 773                               pin
 774                               multiplex
 775                               logic regs
 776
 777Here some electrical properties of the pin can be configured no matter
 778whether the pin is used for GPIO or not. If you multiplex a GPIO onto a
 779pin, you can also drive it high/low from "GPIO" registers.
 780Alternatively, the pin can be controlled by a certain peripheral, while
 781still applying desired pin config properties. GPIO functionality is thus
 782orthogonal to any other device using the pin.
 783
 784In this arrangement the registers for the GPIO portions of the pin controller,
 785or the registers for the GPIO hardware module are likely to reside in a
 786separate memory range only intended for GPIO driving, and the register
 787range dealing with pin config and pin multiplexing get placed into a
 788different memory range and a separate section of the data sheet.
 789
 790A flag "strict" in struct pinmux_ops is available to check and deny
 791simultaneous access to the same pin from GPIO and pin multiplexing
 792consumers on hardware of this type. The pinctrl driver should set this flag
 793accordingly.
 794
 795Example **(B)**::
 796
 797                       pin config
 798                       logic regs
 799                       |               +- SPI
 800     Physical pins --- pad --- pinmux -+- I2C
 801                       |       |       +- mmc
 802                       |       |
 803                       GPIO    pin
 804                               multiplex
 805                               logic regs
 806
 807In this arrangement, the GPIO functionality can always be enabled, such that
 808e.g. a GPIO input can be used to "spy" on the SPI/I2C/MMC signal while it is
 809pulsed out. It is likely possible to disrupt the traffic on the pin by doing
 810wrong things on the GPIO block, as it is never really disconnected. It is
 811possible that the GPIO, pin config and pin multiplex registers are placed into
 812the same memory range and the same section of the data sheet, although that
 813need not be the case.
 814
 815In some pin controllers, although the physical pins are designed in the same
 816way as (B), the GPIO function still can't be enabled at the same time as the
 817peripheral functions. So again the "strict" flag should be set, denying
 818simultaneous activation by GPIO and other muxed in devices.
 819
 820From a kernel point of view, however, these are different aspects of the
 821hardware and shall be put into different subsystems:
 822
 823- Registers (or fields within registers) that control electrical
 824  properties of the pin such as biasing and drive strength should be
 825  exposed through the pinctrl subsystem, as "pin configuration" settings.
 826
 827- Registers (or fields within registers) that control muxing of signals
 828  from various other HW blocks (e.g. I2C, MMC, or GPIO) onto pins should
 829  be exposed through the pinctrl subsystem, as mux functions.
 830
 831- Registers (or fields within registers) that control GPIO functionality
 832  such as setting a GPIO's output value, reading a GPIO's input value, or
 833  setting GPIO pin direction should be exposed through the GPIO subsystem,
 834  and if they also support interrupt capabilities, through the irqchip
 835  abstraction.
 836
 837Depending on the exact HW register design, some functions exposed by the
 838GPIO subsystem may call into the pinctrl subsystem in order to
 839coordinate register settings across HW modules. In particular, this may
 840be needed for HW with separate GPIO and pin controller HW modules, where
 841e.g. GPIO direction is determined by a register in the pin controller HW
 842module rather than the GPIO HW module.
 843
 844Electrical properties of the pin such as biasing and drive strength
 845may be placed at some pin-specific register in all cases or as part
 846of the GPIO register in case (B) especially. This doesn't mean that such
 847properties necessarily pertain to what the Linux kernel calls "GPIO".
 848
 849Example: a pin is usually muxed in to be used as a UART TX line. But during
 850system sleep, we need to put this pin into "GPIO mode" and ground it.
 851
 852If you make a 1-to-1 map to the GPIO subsystem for this pin, you may start
 853to think that you need to come up with something really complex, that the
 854pin shall be used for UART TX and GPIO at the same time, that you will grab
 855a pin control handle and set it to a certain state to enable UART TX to be
 856muxed in, then twist it over to GPIO mode and use gpiod_direction_output()
 857to drive it low during sleep, then mux it over to UART TX again when you
 858wake up and maybe even gpiod_get() / gpiod_put() as part of this cycle. This
 859all gets very complicated.
 860
 861The solution is to not think that what the datasheet calls "GPIO mode"
 862has to be handled by the ``<linux/gpio/consumer.h>`` interface. Instead view this as
 863a certain pin config setting. Look in e.g. ``<linux/pinctrl/pinconf-generic.h>``
 864and you find this in the documentation:
 865
 866  PIN_CONFIG_OUTPUT:
 867     this will configure the pin in output, use argument
 868     1 to indicate high level, argument 0 to indicate low level.
 869
 870So it is perfectly possible to push a pin into "GPIO mode" and drive the
 871line low as part of the usual pin control map. So for example your UART
 872driver may look like this:
 873
 874.. code-block:: c
 875
 876	#include <linux/pinctrl/consumer.h>
 877
 878	struct pinctrl          *pinctrl;
 879	struct pinctrl_state    *pins_default;
 880	struct pinctrl_state    *pins_sleep;
 881
 882	pins_default = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_DEFAULT);
 883	pins_sleep = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_SLEEP);
 884
 885	/* Normal mode */
 886	retval = pinctrl_select_state(pinctrl, pins_default);
 887
 888	/* Sleep mode */
 889	retval = pinctrl_select_state(pinctrl, pins_sleep);
 890
 891And your machine configuration may look like this:
 892
 893.. code-block:: c
 894
 895	static unsigned long uart_default_mode[] = {
 896		PIN_CONF_PACKED(PIN_CONFIG_DRIVE_PUSH_PULL, 0),
 897	};
 898
 899	static unsigned long uart_sleep_mode[] = {
 900		PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0),
 901	};
 902
 903	static struct pinctrl_map pinmap[] __initdata = {
 904		PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
 905				  "u0_group", "u0"),
 906		PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
 907				    "UART_TX_PIN", uart_default_mode),
 908		PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
 909				  "u0_group", "gpio-mode"),
 910		PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
 911				    "UART_TX_PIN", uart_sleep_mode),
 912	};
 913
 914	foo_init(void)
 915	{
 916		pinctrl_register_mappings(pinmap, ARRAY_SIZE(pinmap));
 917	}
 918
 919Here the pins we want to control are in the "u0_group" and there is some
 920function called "u0" that can be enabled on this group of pins, and then
 921everything is UART business as usual. But there is also some function
 922named "gpio-mode" that can be mapped onto the same pins to move them into
 923GPIO mode.
 924
 925This will give the desired effect without any bogus interaction with the
 926GPIO subsystem. It is just an electrical configuration used by that device
 927when going to sleep, it might imply that the pin is set into something the
 928datasheet calls "GPIO mode", but that is not the point: it is still used
 929by that UART device to control the pins that pertain to that very UART
 930driver, putting them into modes needed by the UART. GPIO in the Linux
 931kernel sense are just some 1-bit line, and is a different use case.
 932
 933How the registers are poked to attain the push or pull, and output low
 934configuration and the muxing of the "u0" or "gpio-mode" group onto these
 935pins is a question for the driver.
 936
 937Some datasheets will be more helpful and refer to the "GPIO mode" as
 938"low power mode" rather than anything to do with GPIO. This often means
 939the same thing electrically speaking, but in this latter case the
 940software engineers will usually quickly identify that this is some
 941specific muxing or configuration rather than anything related to the GPIO
 942API.
 943
 944
 945Board/machine configuration
 946===========================
 947
 948Boards and machines define how a certain complete running system is put
 949together, including how GPIOs and devices are muxed, how regulators are
 950constrained and how the clock tree looks. Of course pinmux settings are also
 951part of this.
 952
 953A pin controller configuration for a machine looks pretty much like a simple
 954regulator configuration, so for the example array above we want to enable i2c
 955and spi on the second function mapping:
 956
 957.. code-block:: c
 958
 959	#include <linux/pinctrl/machine.h>
 960
 961	static const struct pinctrl_map mapping[] __initconst = {
 962		{
 963			.dev_name = "foo-spi.0",
 964			.name = PINCTRL_STATE_DEFAULT,
 965			.type = PIN_MAP_TYPE_MUX_GROUP,
 966			.ctrl_dev_name = "pinctrl-foo",
 967			.data.mux.function = "spi0",
 968		},
 969		{
 970			.dev_name = "foo-i2c.0",
 971			.name = PINCTRL_STATE_DEFAULT,
 972			.type = PIN_MAP_TYPE_MUX_GROUP,
 973			.ctrl_dev_name = "pinctrl-foo",
 974			.data.mux.function = "i2c0",
 975		},
 976		{
 977			.dev_name = "foo-mmc.0",
 978			.name = PINCTRL_STATE_DEFAULT,
 979			.type = PIN_MAP_TYPE_MUX_GROUP,
 980			.ctrl_dev_name = "pinctrl-foo",
 981			.data.mux.function = "mmc0",
 982		},
 983	};
 984
 985The dev_name here matches to the unique device name that can be used to look
 986up the device struct (just like with clockdev or regulators). The function name
 987must match a function provided by the pinmux driver handling this pin range.
 988
 989As you can see we may have several pin controllers on the system and thus
 990we need to specify which one of them contains the functions we wish to map.
 991
 992You register this pinmux mapping to the pinmux subsystem by simply:
 993
 994.. code-block:: c
 995
 996       ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping));
 997
 998Since the above construct is pretty common there is a helper macro to make
 999it even more compact which assumes you want to use pinctrl-foo and position
10000 for mapping, for example:
1001
1002.. code-block:: c
1003
1004	static struct pinctrl_map mapping[] __initdata = {
1005		PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT,
1006				  "pinctrl-foo", NULL, "i2c0"),
1007	};
1008
1009The mapping table may also contain pin configuration entries. It's common for
1010each pin/group to have a number of configuration entries that affect it, so
1011the table entries for configuration reference an array of config parameters
1012and values. An example using the convenience macros is shown below:
1013
1014.. code-block:: c
1015
1016	static unsigned long i2c_grp_configs[] = {
1017		FOO_PIN_DRIVEN,
1018		FOO_PIN_PULLUP,
1019	};
1020
1021	static unsigned long i2c_pin_configs[] = {
1022		FOO_OPEN_COLLECTOR,
1023		FOO_SLEW_RATE_SLOW,
1024	};
1025
1026	static struct pinctrl_map mapping[] __initdata = {
1027		PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT,
1028				  "pinctrl-foo", "i2c0", "i2c0"),
1029		PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT,
1030				      "pinctrl-foo", "i2c0", i2c_grp_configs),
1031		PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT,
1032				    "pinctrl-foo", "i2c0scl", i2c_pin_configs),
1033		PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT,
1034				    "pinctrl-foo", "i2c0sda", i2c_pin_configs),
1035	};
1036
1037Finally, some devices expect the mapping table to contain certain specific
1038named states. When running on hardware that doesn't need any pin controller
1039configuration, the mapping table must still contain those named states, in
1040order to explicitly indicate that the states were provided and intended to
1041be empty. Table entry macro ``PIN_MAP_DUMMY_STATE()`` serves the purpose of defining
1042a named state without causing any pin controller to be programmed:
1043
1044.. code-block:: c
1045
1046	static struct pinctrl_map mapping[] __initdata = {
1047		PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT),
1048	};
1049
1050
1051Complex mappings
1052================
1053
1054As it is possible to map a function to different groups of pins an optional
1055.group can be specified like this:
1056
1057.. code-block:: c
1058
1059	...
1060	{
1061		.dev_name = "foo-spi.0",
1062		.name = "spi0-pos-A",
1063		.type = PIN_MAP_TYPE_MUX_GROUP,
1064		.ctrl_dev_name = "pinctrl-foo",
1065		.function = "spi0",
1066		.group = "spi0_0_grp",
1067	},
1068	{
1069		.dev_name = "foo-spi.0",
1070		.name = "spi0-pos-B",
1071		.type = PIN_MAP_TYPE_MUX_GROUP,
1072		.ctrl_dev_name = "pinctrl-foo",
1073		.function = "spi0",
1074		.group = "spi0_1_grp",
1075	},
1076	...
1077
1078This example mapping is used to switch between two positions for spi0 at
1079runtime, as described further below under the heading `Runtime pinmuxing`_.
1080
1081Further it is possible for one named state to affect the muxing of several
1082groups of pins, say for example in the mmc0 example above, where you can
1083additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all
1084three groups for a total of 2 + 2 + 4 = 8 pins (for an 8-bit MMC bus as is the
1085case), we define a mapping like this:
1086
1087.. code-block:: c
1088
1089	...
1090	{
1091		.dev_name = "foo-mmc.0",
1092		.name = "2bit"
1093		.type = PIN_MAP_TYPE_MUX_GROUP,
1094		.ctrl_dev_name = "pinctrl-foo",
1095		.function = "mmc0",
1096		.group = "mmc0_1_grp",
1097	},
1098	{
1099		.dev_name = "foo-mmc.0",
1100		.name = "4bit"
1101		.type = PIN_MAP_TYPE_MUX_GROUP,
1102		.ctrl_dev_name = "pinctrl-foo",
1103		.function = "mmc0",
1104		.group = "mmc0_1_grp",
1105	},
1106	{
1107		.dev_name = "foo-mmc.0",
1108		.name = "4bit"
1109		.type = PIN_MAP_TYPE_MUX_GROUP,
1110		.ctrl_dev_name = "pinctrl-foo",
1111		.function = "mmc0",
1112		.group = "mmc0_2_grp",
1113	},
1114	{
1115		.dev_name = "foo-mmc.0",
1116		.name = "8bit"
1117		.type = PIN_MAP_TYPE_MUX_GROUP,
1118		.ctrl_dev_name = "pinctrl-foo",
1119		.function = "mmc0",
1120		.group = "mmc0_1_grp",
1121	},
1122	{
1123		.dev_name = "foo-mmc.0",
1124		.name = "8bit"
1125		.type = PIN_MAP_TYPE_MUX_GROUP,
1126		.ctrl_dev_name = "pinctrl-foo",
1127		.function = "mmc0",
1128		.group = "mmc0_2_grp",
1129	},
1130	{
1131		.dev_name = "foo-mmc.0",
1132		.name = "8bit"
1133		.type = PIN_MAP_TYPE_MUX_GROUP,
1134		.ctrl_dev_name = "pinctrl-foo",
1135		.function = "mmc0",
1136		.group = "mmc0_3_grp",
1137	},
1138	...
1139
1140The result of grabbing this mapping from the device with something like
1141this (see next paragraph):
1142
1143.. code-block:: c
1144
1145	p = devm_pinctrl_get(dev);
1146	s = pinctrl_lookup_state(p, "8bit");
1147	ret = pinctrl_select_state(p, s);
1148
1149or more simply:
1150
1151.. code-block:: c
1152
1153	p = devm_pinctrl_get_select(dev, "8bit");
1154
1155Will be that you activate all the three bottom records in the mapping at
1156once. Since they share the same name, pin controller device, function and
1157device, and since we allow multiple groups to match to a single device, they
1158all get selected, and they all get enabled and disable simultaneously by the
1159pinmux core.
1160
1161
1162Pin control requests from drivers
1163=================================
1164
1165When a device driver is about to probe the device core will automatically
1166attempt to issue ``pinctrl_get_select_default()`` on these devices.
1167This way driver writers do not need to add any of the boilerplate code
1168of the type found below. However when doing fine-grained state selection
1169and not using the "default" state, you may have to do some device driver
1170handling of the pinctrl handles and states.
1171
1172So if you just want to put the pins for a certain device into the default
1173state and be done with it, there is nothing you need to do besides
1174providing the proper mapping table. The device core will take care of
1175the rest.
1176
1177Generally it is discouraged to let individual drivers get and enable pin
1178control. So if possible, handle the pin control in platform code or some other
1179place where you have access to all the affected struct device * pointers. In
1180some cases where a driver needs to e.g. switch between different mux mappings
1181at runtime this is not possible.
1182
1183A typical case is if a driver needs to switch bias of pins from normal
1184operation and going to sleep, moving from the ``PINCTRL_STATE_DEFAULT`` to
1185``PINCTRL_STATE_SLEEP`` at runtime, re-biasing or even re-muxing pins to save
1186current in sleep mode.
1187
1188A driver may request a certain control state to be activated, usually just the
1189default state like this:
1190
1191.. code-block:: c
1192
1193	#include <linux/pinctrl/consumer.h>
1194
1195	struct foo_state {
1196	struct pinctrl *p;
1197	struct pinctrl_state *s;
1198	...
1199	};
1200
1201	foo_probe()
1202	{
1203		/* Allocate a state holder named "foo" etc */
1204		struct foo_state *foo = ...;
1205
1206		foo->p = devm_pinctrl_get(&device);
1207		if (IS_ERR(foo->p)) {
1208			/* FIXME: clean up "foo" here */
1209			return PTR_ERR(foo->p);
1210		}
1211
1212		foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
1213		if (IS_ERR(foo->s)) {
1214			/* FIXME: clean up "foo" here */
1215			return PTR_ERR(foo->s);
1216		}
1217
1218		ret = pinctrl_select_state(foo->p, foo->s);
1219		if (ret < 0) {
1220			/* FIXME: clean up "foo" here */
1221			return ret;
1222		}
1223	}
1224
1225This get/lookup/select/put sequence can just as well be handled by bus drivers
1226if you don't want each and every driver to handle it and you know the
1227arrangement on your bus.
1228
1229The semantics of the pinctrl APIs are:
1230
1231- ``pinctrl_get()`` is called in process context to obtain a handle to all pinctrl
1232  information for a given client device. It will allocate a struct from the
1233  kernel memory to hold the pinmux state. All mapping table parsing or similar
1234  slow operations take place within this API.
1235
1236- ``devm_pinctrl_get()`` is a variant of pinctrl_get() that causes ``pinctrl_put()``
1237  to be called automatically on the retrieved pointer when the associated
1238  device is removed. It is recommended to use this function over plain
1239  ``pinctrl_get()``.
1240
1241- ``pinctrl_lookup_state()`` is called in process context to obtain a handle to a
1242  specific state for a client device. This operation may be slow, too.
1243
1244- ``pinctrl_select_state()`` programs pin controller hardware according to the
1245  definition of the state as given by the mapping table. In theory, this is a
1246  fast-path operation, since it only involved blasting some register settings
1247  into hardware. However, note that some pin controllers may have their
1248  registers on a slow/IRQ-based bus, so client devices should not assume they
1249  can call ``pinctrl_select_state()`` from non-blocking contexts.
1250
1251- ``pinctrl_put()`` frees all information associated with a pinctrl handle.
1252
1253- ``devm_pinctrl_put()`` is a variant of ``pinctrl_put()`` that may be used to
1254  explicitly destroy a pinctrl object returned by ``devm_pinctrl_get()``.
1255  However, use of this function will be rare, due to the automatic cleanup
1256  that will occur even without calling it.
1257
1258  ``pinctrl_get()`` must be paired with a plain ``pinctrl_put()``.
1259  ``pinctrl_get()`` may not be paired with ``devm_pinctrl_put()``.
1260  ``devm_pinctrl_get()`` can optionally be paired with ``devm_pinctrl_put()``.
1261  ``devm_pinctrl_get()`` may not be paired with plain ``pinctrl_put()``.
1262
1263Usually the pin control core handled the get/put pair and call out to the
1264device drivers bookkeeping operations, like checking available functions and
1265the associated pins, whereas ``pinctrl_select_state()`` pass on to the pin controller
1266driver which takes care of activating and/or deactivating the mux setting by
1267quickly poking some registers.
1268
1269The pins are allocated for your device when you issue the ``devm_pinctrl_get()``
1270call, after this you should be able to see this in the debugfs listing of all
1271pins.
1272
1273NOTE: the pinctrl system will return ``-EPROBE_DEFER`` if it cannot find the
1274requested pinctrl handles, for example if the pinctrl driver has not yet
1275registered. Thus make sure that the error path in your driver gracefully
1276cleans up and is ready to retry the probing later in the startup process.
1277
1278
1279Drivers needing both pin control and GPIOs
1280==========================================
1281
1282Again, it is discouraged to let drivers lookup and select pin control states
1283themselves, but again sometimes this is unavoidable.
1284
1285So say that your driver is fetching its resources like this:
1286
1287.. code-block:: c
1288
1289	#include <linux/pinctrl/consumer.h>
1290	#include <linux/gpio/consumer.h>
1291
1292	struct pinctrl *pinctrl;
1293	struct gpio_desc *gpio;
1294
1295	pinctrl = devm_pinctrl_get_select_default(&dev);
1296	gpio = devm_gpiod_get(&dev, "foo");
1297
1298Here we first request a certain pin state and then request GPIO "foo" to be
1299used. If you're using the subsystems orthogonally like this, you should
1300nominally always get your pinctrl handle and select the desired pinctrl
1301state BEFORE requesting the GPIO. This is a semantic convention to avoid
1302situations that can be electrically unpleasant, you will certainly want to
1303mux in and bias pins in a certain way before the GPIO subsystems starts to
1304deal with them.
1305
1306The above can be hidden: using the device core, the pinctrl core may be
1307setting up the config and muxing for the pins right before the device is
1308probing, nevertheless orthogonal to the GPIO subsystem.
1309
1310But there are also situations where it makes sense for the GPIO subsystem
1311to communicate directly with the pinctrl subsystem, using the latter as a
1312back-end. This is when the GPIO driver may call out to the functions
1313described in the section `Pin control interaction with the GPIO subsystem`_
1314above. This only involves per-pin multiplexing, and will be completely
1315hidden behind the gpiod_*() function namespace. In this case, the driver
1316need not interact with the pin control subsystem at all.
1317
1318If a pin control driver and a GPIO driver is dealing with the same pins
1319and the use cases involve multiplexing, you MUST implement the pin controller
1320as a back-end for the GPIO driver like this, unless your hardware design
1321is such that the GPIO controller can override the pin controller's
1322multiplexing state through hardware without the need to interact with the
1323pin control system.
1324
1325
1326System pin control hogging
1327==========================
1328
1329Pin control map entries can be hogged by the core when the pin controller
1330is registered. This means that the core will attempt to call ``pinctrl_get()``,
1331``pinctrl_lookup_state()`` and ``pinctrl_select_state()`` on it immediately after
1332the pin control device has been registered.
1333
1334This occurs for mapping table entries where the client device name is equal
1335to the pin controller device name, and the state name is ``PINCTRL_STATE_DEFAULT``:
1336
1337.. code-block:: c
1338
1339	{
1340		.dev_name = "pinctrl-foo",
1341		.name = PINCTRL_STATE_DEFAULT,
1342		.type = PIN_MAP_TYPE_MUX_GROUP,
1343		.ctrl_dev_name = "pinctrl-foo",
1344		.function = "power_func",
1345	},
1346
1347Since it may be common to request the core to hog a few always-applicable
1348mux settings on the primary pin controller, there is a convenience macro for
1349this:
1350
1351.. code-block:: c
1352
1353	PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */,
1354				      "power_func")
1355
1356This gives the exact same result as the above construction.
1357
1358
1359Runtime pinmuxing
1360=================
1361
1362It is possible to mux a certain function in and out at runtime, say to move
1363an SPI port from one set of pins to another set of pins. Say for example for
1364spi0 in the example above, we expose two different groups of pins for the same
1365function, but with different named in the mapping as described under
1366"Advanced mapping" above. So that for an SPI device, we have two states named
1367"pos-A" and "pos-B".
1368
1369This snippet first initializes a state object for both groups (in foo_probe()),
1370then muxes the function in the pins defined by group A, and finally muxes it in
1371on the pins defined by group B:
1372
1373.. code-block:: c
1374
1375	#include <linux/pinctrl/consumer.h>
1376
1377	struct pinctrl *p;
1378	struct pinctrl_state *s1, *s2;
1379
1380	foo_probe()
1381	{
1382		/* Setup */
1383		p = devm_pinctrl_get(&device);
1384		if (IS_ERR(p))
1385			...
1386
1387		s1 = pinctrl_lookup_state(p, "pos-A");
1388		if (IS_ERR(s1))
1389			...
1390
1391		s2 = pinctrl_lookup_state(p, "pos-B");
1392		if (IS_ERR(s2))
1393			...
1394	}
1395
1396	foo_switch()
1397	{
1398		/* Enable on position A */
1399		ret = pinctrl_select_state(p, s1);
1400		if (ret < 0)
1401			...
1402
1403		...
1404
1405		/* Enable on position B */
1406		ret = pinctrl_select_state(p, s2);
1407		if (ret < 0)
1408			...
1409
1410		...
1411	}
1412
1413The above has to be done from process context. The reservation of the pins
1414will be done when the state is activated, so in effect one specific pin
1415can be used by different functions at different times on a running system.
1416
1417
1418Debugfs files
1419=============
1420
1421These files are created in ``/sys/kernel/debug/pinctrl``:
1422
1423- ``pinctrl-devices``: prints each pin controller device along with columns to
1424  indicate support for pinmux and pinconf
1425
1426- ``pinctrl-handles``: prints each configured pin controller handle and the
1427  corresponding pinmux maps
1428
1429- ``pinctrl-maps``: prints all pinctrl maps
1430
1431A sub-directory is created inside of ``/sys/kernel/debug/pinctrl`` for each pin
1432controller device containing these files:
1433
1434- ``pins``: prints a line for each pin registered on the pin controller. The
1435  pinctrl driver may add additional information such as register contents.
1436
1437- ``gpio-ranges``: prints ranges that map gpio lines to pins on the controller
1438
1439- ``pingroups``: prints all pin groups registered on the pin controller
1440
1441- ``pinconf-pins``: prints pin config settings for each pin
1442
1443- ``pinconf-groups``: prints pin config settings per pin group
1444
1445- ``pinmux-functions``: prints each pin function along with the pin groups that
1446  map to the pin function
1447
1448- ``pinmux-pins``: iterates through all pins and prints mux owner, gpio owner
1449  and if the pin is a hog
1450
1451- ``pinmux-select``: write to this file to activate a pin function for a group:
1452
1453  .. code-block:: sh
1454
1455        echo "<group-name function-name>" > pinmux-select