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1// SPDX-License-Identifier: GPL-2.0
2//
3// CS42L43 CODEC driver
4//
5// Copyright (C) 2022-2023 Cirrus Logic, Inc. and
6// Cirrus Logic International Semiconductor Ltd.
7
8#include <linux/bitops.h>
9#include <linux/bits.h>
10#include <linux/build_bug.h>
11#include <linux/clk.h>
12#include <linux/device.h>
13#include <linux/err.h>
14#include <linux/errno.h>
15#include <linux/find.h>
16#include <linux/gcd.h>
17#include <linux/irq.h>
18#include <linux/irqdomain.h>
19#include <linux/jiffies.h>
20#include <linux/mfd/cs42l43.h>
21#include <linux/mfd/cs42l43-regs.h>
22#include <linux/mod_devicetable.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/pm_runtime.h>
26#include <linux/regmap.h>
27#include <linux/string.h>
28#include <linux/workqueue.h>
29#include <sound/control.h>
30#include <sound/cs42l43.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc-component.h>
34#include <sound/soc-dapm.h>
35#include <sound/soc-dai.h>
36#include <sound/soc.h>
37#include <sound/tlv.h>
38
39#include "cs42l43.h"
40
41#define CS42L43_DECL_MUX(name, reg) \
42static SOC_VALUE_ENUM_SINGLE_DECL(cs42l43_##name##_enum, reg, \
43 0, CS42L43_MIXER_SRC_MASK, \
44 cs42l43_mixer_texts, cs42l43_mixer_values); \
45static const struct snd_kcontrol_new cs42l43_##name##_mux = \
46 SOC_DAPM_ENUM("Route", cs42l43_##name##_enum)
47
48#define CS42L43_DECL_MIXER(name, reg) \
49 CS42L43_DECL_MUX(name##_in1, reg); \
50 CS42L43_DECL_MUX(name##_in2, reg + 0x4); \
51 CS42L43_DECL_MUX(name##_in3, reg + 0x8); \
52 CS42L43_DECL_MUX(name##_in4, reg + 0xC)
53
54#define CS42L43_DAPM_MUX(name_str, name) \
55 SND_SOC_DAPM_MUX(name_str " Input", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_mux)
56
57#define CS42L43_DAPM_MIXER(name_str, name) \
58 SND_SOC_DAPM_MUX(name_str " Input 1", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in1_mux), \
59 SND_SOC_DAPM_MUX(name_str " Input 2", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in2_mux), \
60 SND_SOC_DAPM_MUX(name_str " Input 3", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in3_mux), \
61 SND_SOC_DAPM_MUX(name_str " Input 4", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in4_mux), \
62 SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
63
64#define CS42L43_BASE_ROUTES(name_str) \
65 { name_str, "Tone Generator 1", "Tone 1" }, \
66 { name_str, "Tone Generator 2", "Tone 2" }, \
67 { name_str, "Decimator 1", "Decimator 1" }, \
68 { name_str, "Decimator 2", "Decimator 2" }, \
69 { name_str, "Decimator 3", "Decimator 3" }, \
70 { name_str, "Decimator 4", "Decimator 4" }, \
71 { name_str, "ASPRX1", "ASPRX1" }, \
72 { name_str, "ASPRX2", "ASPRX2" }, \
73 { name_str, "ASPRX3", "ASPRX3" }, \
74 { name_str, "ASPRX4", "ASPRX4" }, \
75 { name_str, "ASPRX5", "ASPRX5" }, \
76 { name_str, "ASPRX6", "ASPRX6" }, \
77 { name_str, "DP5RX1", "DP5RX1" }, \
78 { name_str, "DP5RX2", "DP5RX2" }, \
79 { name_str, "DP6RX1", "DP6RX1" }, \
80 { name_str, "DP6RX2", "DP6RX2" }, \
81 { name_str, "DP7RX1", "DP7RX1" }, \
82 { name_str, "DP7RX2", "DP7RX2" }, \
83 { name_str, "ASRC INT1", "ASRC_INT1" }, \
84 { name_str, "ASRC INT2", "ASRC_INT2" }, \
85 { name_str, "ASRC INT3", "ASRC_INT3" }, \
86 { name_str, "ASRC INT4", "ASRC_INT4" }, \
87 { name_str, "ASRC DEC1", "ASRC_DEC1" }, \
88 { name_str, "ASRC DEC2", "ASRC_DEC2" }, \
89 { name_str, "ASRC DEC3", "ASRC_DEC3" }, \
90 { name_str, "ASRC DEC4", "ASRC_DEC4" }, \
91 { name_str, "ISRC1 INT1", "ISRC1INT1" }, \
92 { name_str, "ISRC1 INT2", "ISRC1INT2" }, \
93 { name_str, "ISRC1 DEC1", "ISRC1DEC1" }, \
94 { name_str, "ISRC1 DEC2", "ISRC1DEC2" }, \
95 { name_str, "ISRC2 INT1", "ISRC2INT1" }, \
96 { name_str, "ISRC2 INT2", "ISRC2INT2" }, \
97 { name_str, "ISRC2 DEC1", "ISRC2DEC1" }, \
98 { name_str, "ISRC2 DEC2", "ISRC2DEC2" }, \
99 { name_str, "EQ1", "EQ" }, \
100 { name_str, "EQ2", "EQ" }
101
102#define CS42L43_MUX_ROUTES(name_str, widget) \
103 { widget, NULL, name_str " Input" }, \
104 { name_str " Input", NULL, "Mixer Core" }, \
105 CS42L43_BASE_ROUTES(name_str " Input")
106
107#define CS42L43_MIXER_ROUTES(name_str, widget) \
108 { name_str " Mixer", NULL, name_str " Input 1" }, \
109 { name_str " Mixer", NULL, name_str " Input 2" }, \
110 { name_str " Mixer", NULL, name_str " Input 3" }, \
111 { name_str " Mixer", NULL, name_str " Input 4" }, \
112 { widget, NULL, name_str " Mixer" }, \
113 { name_str " Mixer", NULL, "Mixer Core" }, \
114 CS42L43_BASE_ROUTES(name_str " Input 1"), \
115 CS42L43_BASE_ROUTES(name_str " Input 2"), \
116 CS42L43_BASE_ROUTES(name_str " Input 3"), \
117 CS42L43_BASE_ROUTES(name_str " Input 4")
118
119#define CS42L43_MIXER_VOLUMES(name_str, base) \
120 SOC_SINGLE_RANGE_TLV(name_str " Input 1 Volume", base, \
121 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
122 cs42l43_mixer_tlv), \
123 SOC_SINGLE_RANGE_TLV(name_str " Input 2 Volume", base + 4, \
124 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
125 cs42l43_mixer_tlv), \
126 SOC_SINGLE_RANGE_TLV(name_str " Input 3 Volume", base + 8, \
127 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
128 cs42l43_mixer_tlv), \
129 SOC_SINGLE_RANGE_TLV(name_str " Input 4 Volume", base + 12, \
130 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
131 cs42l43_mixer_tlv)
132
133#define CS42L43_IRQ_ERROR(name) \
134static irqreturn_t cs42l43_##name(int irq, void *data) \
135{ \
136 struct cs42l43_codec *priv = data; \
137 dev_err(priv->dev, "Error " #name " IRQ\n"); \
138 return IRQ_HANDLED; \
139}
140
141CS42L43_IRQ_ERROR(pll_lost_lock)
142CS42L43_IRQ_ERROR(spkr_clock_stop)
143CS42L43_IRQ_ERROR(spkl_clock_stop)
144CS42L43_IRQ_ERROR(spkr_brown_out)
145CS42L43_IRQ_ERROR(spkl_brown_out)
146CS42L43_IRQ_ERROR(spkr_therm_shutdown)
147CS42L43_IRQ_ERROR(spkl_therm_shutdown)
148CS42L43_IRQ_ERROR(spkr_therm_warm)
149CS42L43_IRQ_ERROR(spkl_therm_warm)
150CS42L43_IRQ_ERROR(spkr_sc_detect)
151CS42L43_IRQ_ERROR(spkl_sc_detect)
152
153static void cs42l43_hp_ilimit_clear_work(struct work_struct *work)
154{
155 struct cs42l43_codec *priv = container_of(work, struct cs42l43_codec,
156 hp_ilimit_clear_work.work);
157 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(priv->component);
158
159 snd_soc_dapm_mutex_lock(dapm);
160
161 priv->hp_ilimit_count--;
162
163 if (priv->hp_ilimit_count)
164 queue_delayed_work(system_wq, &priv->hp_ilimit_clear_work,
165 msecs_to_jiffies(CS42L43_HP_ILIMIT_DECAY_MS));
166
167 snd_soc_dapm_mutex_unlock(dapm);
168}
169
170static void cs42l43_hp_ilimit_work(struct work_struct *work)
171{
172 struct cs42l43_codec *priv = container_of(work, struct cs42l43_codec,
173 hp_ilimit_work);
174 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(priv->component);
175 struct cs42l43 *cs42l43 = priv->core;
176
177 snd_soc_dapm_mutex_lock(dapm);
178
179 if (priv->hp_ilimit_count < CS42L43_HP_ILIMIT_MAX_COUNT) {
180 if (!priv->hp_ilimit_count)
181 queue_delayed_work(system_wq, &priv->hp_ilimit_clear_work,
182 msecs_to_jiffies(CS42L43_HP_ILIMIT_DECAY_MS));
183
184 priv->hp_ilimit_count++;
185 snd_soc_dapm_mutex_unlock(dapm);
186 return;
187 }
188
189 dev_err(priv->dev, "Disabling headphone for %dmS, due to frequent current limit\n",
190 CS42L43_HP_ILIMIT_BACKOFF_MS);
191
192 priv->hp_ilimited = true;
193
194 // No need to wait for disable, as just disabling for a period of time
195 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8,
196 CS42L43_HP_EN_MASK, 0);
197
198 snd_soc_dapm_mutex_unlock(dapm);
199
200 msleep(CS42L43_HP_ILIMIT_BACKOFF_MS);
201
202 snd_soc_dapm_mutex_lock(dapm);
203
204 if (priv->hp_ena && !priv->load_detect_running) {
205 unsigned long time_left;
206
207 reinit_completion(&priv->hp_startup);
208
209 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8,
210 CS42L43_HP_EN_MASK, priv->hp_ena);
211
212 time_left = wait_for_completion_timeout(&priv->hp_startup,
213 msecs_to_jiffies(CS42L43_HP_TIMEOUT_MS));
214 if (!time_left)
215 dev_err(priv->dev, "ilimit HP restore timed out\n");
216 }
217
218 priv->hp_ilimited = false;
219
220 snd_soc_dapm_mutex_unlock(dapm);
221}
222
223static irqreturn_t cs42l43_hp_ilimit(int irq, void *data)
224{
225 struct cs42l43_codec *priv = data;
226
227 dev_dbg(priv->dev, "headphone ilimit IRQ\n");
228
229 queue_work(system_long_wq, &priv->hp_ilimit_work);
230
231 return IRQ_HANDLED;
232}
233
234#define CS42L43_IRQ_COMPLETE(name) \
235static irqreturn_t cs42l43_##name(int irq, void *data) \
236{ \
237 struct cs42l43_codec *priv = data; \
238 dev_dbg(priv->dev, #name " completed\n"); \
239 complete(&priv->name); \
240 return IRQ_HANDLED; \
241}
242
243CS42L43_IRQ_COMPLETE(pll_ready)
244CS42L43_IRQ_COMPLETE(hp_startup)
245CS42L43_IRQ_COMPLETE(hp_shutdown)
246CS42L43_IRQ_COMPLETE(type_detect)
247CS42L43_IRQ_COMPLETE(spkr_shutdown)
248CS42L43_IRQ_COMPLETE(spkl_shutdown)
249CS42L43_IRQ_COMPLETE(spkr_startup)
250CS42L43_IRQ_COMPLETE(spkl_startup)
251CS42L43_IRQ_COMPLETE(load_detect)
252
253static irqreturn_t cs42l43_mic_shutter(int irq, void *data)
254{
255 struct cs42l43_codec *priv = data;
256 struct snd_soc_component *component = priv->component;
257 int i;
258
259 dev_dbg(priv->dev, "Microphone shutter changed\n");
260
261 if (!component)
262 return IRQ_NONE;
263
264 for (i = 1; i < ARRAY_SIZE(priv->kctl); i++) {
265 if (!priv->kctl[i])
266 return IRQ_NONE;
267
268 snd_ctl_notify(component->card->snd_card,
269 SNDRV_CTL_EVENT_MASK_VALUE, &priv->kctl[i]->id);
270 }
271
272 return IRQ_HANDLED;
273}
274
275static irqreturn_t cs42l43_spk_shutter(int irq, void *data)
276{
277 struct cs42l43_codec *priv = data;
278 struct snd_soc_component *component = priv->component;
279
280 dev_dbg(priv->dev, "Speaker shutter changed\n");
281
282 if (!component)
283 return IRQ_NONE;
284
285 if (!priv->kctl[0])
286 return IRQ_NONE;
287
288 snd_ctl_notify(component->card->snd_card,
289 SNDRV_CTL_EVENT_MASK_VALUE, &priv->kctl[0]->id);
290
291 return IRQ_HANDLED;
292}
293
294static const unsigned int cs42l43_sample_rates[] = {
295 8000, 16000, 24000, 32000, 44100, 48000, 96000, 192000,
296};
297
298#define CS42L43_CONSUMER_RATE_MASK 0xFF
299#define CS42L43_PROVIDER_RATE_MASK 0xEF // 44.1k only supported as consumer
300
301static const struct snd_pcm_hw_constraint_list cs42l43_constraint = {
302 .count = ARRAY_SIZE(cs42l43_sample_rates),
303 .list = cs42l43_sample_rates,
304};
305
306static int cs42l43_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
307{
308 struct snd_soc_component *component = dai->component;
309 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
310 struct cs42l43 *cs42l43 = priv->core;
311 int provider = !dai->id || !!regmap_test_bits(cs42l43->regmap,
312 CS42L43_ASP_CLK_CONFIG2,
313 CS42L43_ASP_MASTER_MODE_MASK);
314
315 if (provider)
316 priv->constraint.mask = CS42L43_PROVIDER_RATE_MASK;
317 else
318 priv->constraint.mask = CS42L43_CONSUMER_RATE_MASK;
319
320 return snd_pcm_hw_constraint_list(substream->runtime, 0,
321 SNDRV_PCM_HW_PARAM_RATE,
322 &priv->constraint);
323}
324
325static int cs42l43_convert_sample_rate(unsigned int rate)
326{
327 switch (rate) {
328 case 8000:
329 return 0x11;
330 case 16000:
331 return 0x12;
332 case 24000:
333 return 0x02;
334 case 32000:
335 return 0x13;
336 case 44100:
337 return 0x0B;
338 case 48000:
339 return 0x03;
340 case 96000:
341 return 0x04;
342 case 192000:
343 return 0x05;
344 default:
345 return -EINVAL;
346 }
347}
348
349static int cs42l43_set_sample_rate(struct snd_pcm_substream *substream,
350 struct snd_pcm_hw_params *params,
351 struct snd_soc_dai *dai)
352{
353 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(dai->component);
354 struct cs42l43 *cs42l43 = priv->core;
355 int ret;
356
357 ret = cs42l43_convert_sample_rate(params_rate(params));
358 if (ret < 0) {
359 dev_err(priv->dev, "Failed to convert sample rate: %d\n", ret);
360 return ret;
361 }
362
363 //FIXME: For now lets just set sample rate 1, this needs expanded in the future
364 regmap_update_bits(cs42l43->regmap, CS42L43_SAMPLE_RATE1,
365 CS42L43_SAMPLE_RATE_MASK, ret);
366
367 return 0;
368}
369
370static int cs42l43_asp_hw_params(struct snd_pcm_substream *substream,
371 struct snd_pcm_hw_params *params,
372 struct snd_soc_dai *dai)
373{
374 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(dai->component);
375 struct cs42l43 *cs42l43 = priv->core;
376 int dsp_mode = !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CTRL,
377 CS42L43_ASP_FSYNC_MODE_MASK);
378 int provider = !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2,
379 CS42L43_ASP_MASTER_MODE_MASK);
380 int n_chans = params_channels(params);
381 int data_width = params_width(params);
382 int n_slots = n_chans;
383 int slot_width = data_width;
384 int frame, bclk_target, i;
385 unsigned int reg;
386 int *slots;
387
388 if (priv->n_slots) {
389 n_slots = priv->n_slots;
390 slot_width = priv->slot_width;
391 }
392
393 if (!dsp_mode && (n_slots & 0x1)) {
394 dev_dbg(priv->dev, "Forcing balanced channels on ASP\n");
395 n_slots++;
396 }
397
398 frame = n_slots * slot_width;
399 bclk_target = params_rate(params) * frame;
400
401 if (provider) {
402 unsigned int gcd_nm = gcd(bclk_target, CS42L43_INTERNAL_SYSCLK);
403 int n = bclk_target / gcd_nm;
404 int m = CS42L43_INTERNAL_SYSCLK / gcd_nm;
405
406 if (n > (CS42L43_ASP_BCLK_N_MASK >> CS42L43_ASP_BCLK_N_SHIFT) ||
407 m > CS42L43_ASP_BCLK_M_MASK) {
408 dev_err(priv->dev, "Can't produce %dHz bclk\n", bclk_target);
409 return -EINVAL;
410 }
411
412 dev_dbg(priv->dev, "bclk %d/%d = %dHz, with %dx%d frame\n",
413 n, m, bclk_target, n_slots, slot_width);
414
415 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG1,
416 CS42L43_ASP_BCLK_N_MASK | CS42L43_ASP_BCLK_M_MASK,
417 n << CS42L43_ASP_BCLK_N_SHIFT |
418 m << CS42L43_ASP_BCLK_M_SHIFT);
419 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL1,
420 CS42L43_ASP_FSYNC_M_MASK, frame);
421 }
422
423 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL4,
424 CS42L43_ASP_NUM_BCLKS_PER_FSYNC_MASK,
425 frame << CS42L43_ASP_NUM_BCLKS_PER_FSYNC_SHIFT);
426
427 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
428 reg = CS42L43_ASP_TX_CH1_CTRL;
429 slots = priv->tx_slots;
430 } else {
431 reg = CS42L43_ASP_RX_CH1_CTRL;
432 slots = priv->rx_slots;
433 }
434
435 for (i = 0; i < n_chans; i++, reg += 4) {
436 int slot_phase = dsp_mode | (i & CS42L43_ASP_CH_SLOT_PHASE_MASK);
437 int slot_pos;
438
439 if (dsp_mode)
440 slot_pos = slots[i] * slot_width;
441 else
442 slot_pos = (slots[i] / 2) * slot_width;
443
444 dev_dbg(priv->dev, "Configure channel %d at slot %d (%d,%d)\n",
445 i, slots[i], slot_pos, slot_phase);
446
447 regmap_update_bits(cs42l43->regmap, reg,
448 CS42L43_ASP_CH_WIDTH_MASK |
449 CS42L43_ASP_CH_SLOT_MASK |
450 CS42L43_ASP_CH_SLOT_PHASE_MASK,
451 ((data_width - 1) << CS42L43_ASP_CH_WIDTH_SHIFT) |
452 (slot_pos << CS42L43_ASP_CH_SLOT_SHIFT) |
453 slot_phase);
454 }
455
456 return cs42l43_set_sample_rate(substream, params, dai);
457}
458
459static int cs42l43_asp_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
460{
461 struct snd_soc_component *component = dai->component;
462 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
463 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
464 struct cs42l43 *cs42l43 = priv->core;
465 int provider = regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2,
466 CS42L43_ASP_MASTER_MODE_MASK);
467 struct snd_soc_dapm_route routes[] = {
468 { "BCLK", NULL, "FSYNC" },
469 };
470 unsigned int asp_ctrl = 0;
471 unsigned int data_ctrl = 0;
472 unsigned int fsync_ctrl = 0;
473 unsigned int clk_config = 0;
474
475 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
476 case SND_SOC_DAIFMT_DSP_A:
477 data_ctrl |= 2 << CS42L43_ASP_FSYNC_FRAME_START_DLY_SHIFT;
478 fallthrough;
479 case SND_SOC_DAIFMT_DSP_B:
480 asp_ctrl |= CS42L43_ASP_FSYNC_MODE_MASK;
481 data_ctrl |= CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK;
482 break;
483 case SND_SOC_DAIFMT_I2S:
484 data_ctrl |= 2 << CS42L43_ASP_FSYNC_FRAME_START_DLY_SHIFT;
485 break;
486 case SND_SOC_DAIFMT_LEFT_J:
487 data_ctrl |= CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK;
488 break;
489 default:
490 dev_err(priv->dev, "Unsupported DAI format 0x%x\n",
491 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
492 return -EINVAL;
493 }
494
495 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
496 case SND_SOC_DAIFMT_CBC_CFC:
497 if (provider)
498 snd_soc_dapm_del_routes(dapm, routes, ARRAY_SIZE(routes));
499 break;
500 case SND_SOC_DAIFMT_CBP_CFP:
501 if (!provider)
502 snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes));
503 clk_config |= CS42L43_ASP_MASTER_MODE_MASK;
504 break;
505 default:
506 dev_err(priv->dev, "Unsupported ASP mode 0x%x\n",
507 fmt & SND_SOC_DAIFMT_MASTER_MASK);
508 return -EINVAL;
509 }
510
511 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
512 case SND_SOC_DAIFMT_NB_NF:
513 clk_config |= CS42L43_ASP_BCLK_INV_MASK; /* Yes BCLK_INV = NB */
514 break;
515 case SND_SOC_DAIFMT_IB_NF:
516 break;
517 case SND_SOC_DAIFMT_NB_IF:
518 clk_config |= CS42L43_ASP_BCLK_INV_MASK;
519 fsync_ctrl |= CS42L43_ASP_FSYNC_IN_INV_MASK |
520 CS42L43_ASP_FSYNC_OUT_INV_MASK;
521 break;
522 case SND_SOC_DAIFMT_IB_IF:
523 fsync_ctrl |= CS42L43_ASP_FSYNC_IN_INV_MASK |
524 CS42L43_ASP_FSYNC_OUT_INV_MASK;
525 break;
526 default:
527 dev_err(priv->dev, "Unsupported invert mode 0x%x\n",
528 fmt & SND_SOC_DAIFMT_INV_MASK);
529 return -EINVAL;
530 }
531
532 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CTRL,
533 CS42L43_ASP_FSYNC_MODE_MASK,
534 asp_ctrl);
535 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_DATA_CTRL,
536 CS42L43_ASP_FSYNC_FRAME_START_DLY_MASK |
537 CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK,
538 data_ctrl);
539 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2,
540 CS42L43_ASP_MASTER_MODE_MASK |
541 CS42L43_ASP_BCLK_INV_MASK,
542 clk_config);
543 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL3,
544 CS42L43_ASP_FSYNC_IN_INV_MASK |
545 CS42L43_ASP_FSYNC_OUT_INV_MASK,
546 fsync_ctrl);
547
548 return 0;
549}
550
551static void cs42l43_mask_to_slots(struct cs42l43_codec *priv, unsigned long mask,
552 int *slots, unsigned int nslots)
553{
554 int i = 0;
555 int slot;
556
557 for_each_set_bit(slot, &mask, BITS_PER_TYPE(mask)) {
558 if (i == nslots) {
559 dev_warn(priv->dev, "Too many channels in TDM mask: %lx\n",
560 mask);
561 return;
562 }
563
564 slots[i++] = slot;
565 }
566
567}
568
569static int cs42l43_asp_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
570 unsigned int rx_mask, int slots, int slot_width)
571{
572 struct snd_soc_component *component = dai->component;
573 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
574
575 priv->n_slots = slots;
576 priv->slot_width = slot_width;
577
578 if (!slots) {
579 tx_mask = CS42L43_DEFAULT_SLOTS;
580 rx_mask = CS42L43_DEFAULT_SLOTS;
581 }
582
583 cs42l43_mask_to_slots(priv, tx_mask, priv->tx_slots,
584 ARRAY_SIZE(priv->tx_slots));
585 cs42l43_mask_to_slots(priv, rx_mask, priv->rx_slots,
586 ARRAY_SIZE(priv->rx_slots));
587
588 return 0;
589}
590
591static int cs42l43_dai_probe(struct snd_soc_dai *dai)
592{
593 struct snd_soc_component *component = dai->component;
594 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
595 static const char * const controls[] = {
596 "Speaker Digital Switch",
597 "Decimator 1 Switch",
598 "Decimator 2 Switch",
599 "Decimator 3 Switch",
600 "Decimator 4 Switch",
601 };
602 int i;
603
604 static_assert(ARRAY_SIZE(controls) == ARRAY_SIZE(priv->kctl));
605
606 for (i = 0; i < ARRAY_SIZE(controls); i++) {
607 if (priv->kctl[i])
608 continue;
609
610 priv->kctl[i] = snd_soc_component_get_kcontrol(component, controls[i]);
611 }
612
613 return 0;
614}
615
616static int cs42l43_dai_remove(struct snd_soc_dai *dai)
617{
618 struct snd_soc_component *component = dai->component;
619 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
620 int i;
621
622 for (i = 0; i < ARRAY_SIZE(priv->kctl); i++)
623 priv->kctl[i] = NULL;
624
625 return 0;
626}
627
628static const struct snd_soc_dai_ops cs42l43_asp_ops = {
629 .probe = cs42l43_dai_probe,
630 .remove = cs42l43_dai_remove,
631 .startup = cs42l43_startup,
632 .hw_params = cs42l43_asp_hw_params,
633 .set_fmt = cs42l43_asp_set_fmt,
634 .set_tdm_slot = cs42l43_asp_set_tdm_slot,
635};
636
637static int cs42l43_sdw_hw_params(struct snd_pcm_substream *substream,
638 struct snd_pcm_hw_params *params,
639 struct snd_soc_dai *dai)
640{
641 int ret;
642
643 ret = cs42l43_sdw_add_peripheral(substream, params, dai);
644 if (ret)
645 return ret;
646
647 return cs42l43_set_sample_rate(substream, params, dai);
648}
649
650static const struct snd_soc_dai_ops cs42l43_sdw_ops = {
651 .probe = cs42l43_dai_probe,
652 .remove = cs42l43_dai_remove,
653 .startup = cs42l43_startup,
654 .set_stream = cs42l43_sdw_set_stream,
655 .hw_params = cs42l43_sdw_hw_params,
656 .hw_free = cs42l43_sdw_remove_peripheral,
657};
658
659#define CS42L43_ASP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
660 SNDRV_PCM_FMTBIT_S32_LE)
661#define CS42L43_SDW_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
662
663static struct snd_soc_dai_driver cs42l43_dais[] = {
664 {
665 .name = "cs42l43-asp",
666 .ops = &cs42l43_asp_ops,
667 .symmetric_rate = 1,
668 .capture = {
669 .stream_name = "ASP Capture",
670 .channels_min = 1,
671 .channels_max = CS42L43_ASP_MAX_CHANNELS,
672 .rates = SNDRV_PCM_RATE_KNOT,
673 .formats = CS42L43_ASP_FORMATS,
674 },
675 .playback = {
676 .stream_name = "ASP Playback",
677 .channels_min = 1,
678 .channels_max = CS42L43_ASP_MAX_CHANNELS,
679 .rates = SNDRV_PCM_RATE_KNOT,
680 .formats = CS42L43_ASP_FORMATS,
681 },
682 },
683 {
684 .name = "cs42l43-dp1",
685 .id = 1,
686 .ops = &cs42l43_sdw_ops,
687 .capture = {
688 .stream_name = "DP1 Capture",
689 .channels_min = 1,
690 .channels_max = 4,
691 .rates = SNDRV_PCM_RATE_KNOT,
692 .formats = CS42L43_SDW_FORMATS,
693 },
694 },
695 {
696 .name = "cs42l43-dp2",
697 .id = 2,
698 .ops = &cs42l43_sdw_ops,
699 .capture = {
700 .stream_name = "DP2 Capture",
701 .channels_min = 1,
702 .channels_max = 2,
703 .rates = SNDRV_PCM_RATE_KNOT,
704 .formats = CS42L43_SDW_FORMATS,
705 },
706 },
707 {
708 .name = "cs42l43-dp3",
709 .id = 3,
710 .ops = &cs42l43_sdw_ops,
711 .capture = {
712 .stream_name = "DP3 Capture",
713 .channels_min = 1,
714 .channels_max = 2,
715 .rates = SNDRV_PCM_RATE_KNOT,
716 .formats = CS42L43_SDW_FORMATS,
717 },
718 },
719 {
720 .name = "cs42l43-dp4",
721 .id = 4,
722 .ops = &cs42l43_sdw_ops,
723 .capture = {
724 .stream_name = "DP4 Capture",
725 .channels_min = 1,
726 .channels_max = 2,
727 .rates = SNDRV_PCM_RATE_KNOT,
728 .formats = CS42L43_SDW_FORMATS,
729 },
730 },
731 {
732 .name = "cs42l43-dp5",
733 .id = 5,
734 .ops = &cs42l43_sdw_ops,
735 .playback = {
736 .stream_name = "DP5 Playback",
737 .channels_min = 1,
738 .channels_max = 2,
739 .rates = SNDRV_PCM_RATE_KNOT,
740 .formats = CS42L43_SDW_FORMATS,
741 },
742 },
743 {
744 .name = "cs42l43-dp6",
745 .id = 6,
746 .ops = &cs42l43_sdw_ops,
747 .playback = {
748 .stream_name = "DP6 Playback",
749 .channels_min = 1,
750 .channels_max = 2,
751 .rates = SNDRV_PCM_RATE_KNOT,
752 .formats = CS42L43_SDW_FORMATS,
753 },
754 },
755 {
756 .name = "cs42l43-dp7",
757 .id = 7,
758 .ops = &cs42l43_sdw_ops,
759 .playback = {
760 .stream_name = "DP7 Playback",
761 .channels_min = 1,
762 .channels_max = 2,
763 .rates = SNDRV_PCM_RATE_KNOT,
764 .formats = CS42L43_SDW_FORMATS,
765 },
766 },
767};
768
769static const DECLARE_TLV_DB_SCALE(cs42l43_mixer_tlv, -3200, 100, 0);
770
771static const char * const cs42l43_ramp_text[] = {
772 "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB",
773 "15ms/6dB", "30ms/6dB",
774};
775
776static const char * const cs42l43_adc1_input_text[] = { "IN1", "IN2" };
777
778static SOC_ENUM_SINGLE_DECL(cs42l43_adc1_input, CS42L43_ADC_B_CTRL1,
779 CS42L43_ADC_AIN_SEL_SHIFT,
780 cs42l43_adc1_input_text);
781
782static const struct snd_kcontrol_new cs42l43_adc1_input_ctl =
783 SOC_DAPM_ENUM("ADC1 Input", cs42l43_adc1_input);
784
785static const char * const cs42l43_dec_mode_text[] = { "ADC", "PDM" };
786
787static SOC_ENUM_SINGLE_VIRT_DECL(cs42l43_dec1_mode, cs42l43_dec_mode_text);
788static SOC_ENUM_SINGLE_VIRT_DECL(cs42l43_dec2_mode, cs42l43_dec_mode_text);
789
790static const struct snd_kcontrol_new cs42l43_dec_mode_ctl[] = {
791 SOC_DAPM_ENUM("Decimator 1 Mode", cs42l43_dec1_mode),
792 SOC_DAPM_ENUM("Decimator 2 Mode", cs42l43_dec2_mode),
793};
794
795static const char * const cs42l43_pdm_clk_text[] = {
796 "3.072MHz", "1.536MHz", "768kHz",
797};
798
799static SOC_ENUM_SINGLE_DECL(cs42l43_pdm1_clk, CS42L43_PDM_CONTROL,
800 CS42L43_PDM1_CLK_DIV_SHIFT, cs42l43_pdm_clk_text);
801static SOC_ENUM_SINGLE_DECL(cs42l43_pdm2_clk, CS42L43_PDM_CONTROL,
802 CS42L43_PDM2_CLK_DIV_SHIFT, cs42l43_pdm_clk_text);
803
804static DECLARE_TLV_DB_SCALE(cs42l43_adc_tlv, -600, 600, 0);
805static DECLARE_TLV_DB_SCALE(cs42l43_dec_tlv, -6400, 50, 0);
806
807static const char * const cs42l43_wnf_corner_text[] = {
808 "160Hz", "180Hz", "200Hz", "220Hz", "240Hz", "260Hz", "280Hz", "300Hz",
809};
810
811static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL1,
812 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
813static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL2,
814 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
815static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL3,
816 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
817static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL4,
818 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
819
820static const char * const cs42l43_hpf_corner_text[] = {
821 "3Hz", "12Hz", "48Hz", "96Hz",
822};
823
824static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL1,
825 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
826static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL2,
827 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
828static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL3,
829 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
830static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL4,
831 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
832
833static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_ramp_up, CS42L43_DECIM_VOL_CTRL_CH1_CH2,
834 CS42L43_DECIM1_VI_RAMP_SHIFT, cs42l43_ramp_text);
835static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_ramp_down, CS42L43_DECIM_VOL_CTRL_CH1_CH2,
836 CS42L43_DECIM1_VD_RAMP_SHIFT, cs42l43_ramp_text);
837static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_ramp_up, CS42L43_DECIM_VOL_CTRL_CH1_CH2,
838 CS42L43_DECIM2_VI_RAMP_SHIFT, cs42l43_ramp_text);
839static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_ramp_down, CS42L43_DECIM_VOL_CTRL_CH1_CH2,
840 CS42L43_DECIM2_VD_RAMP_SHIFT, cs42l43_ramp_text);
841static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_ramp_up, CS42L43_DECIM_VOL_CTRL_CH3_CH4,
842 CS42L43_DECIM3_VI_RAMP_SHIFT, cs42l43_ramp_text);
843static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_ramp_down, CS42L43_DECIM_VOL_CTRL_CH3_CH4,
844 CS42L43_DECIM3_VD_RAMP_SHIFT, cs42l43_ramp_text);
845static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_ramp_up, CS42L43_DECIM_VOL_CTRL_CH3_CH4,
846 CS42L43_DECIM4_VI_RAMP_SHIFT, cs42l43_ramp_text);
847static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_ramp_down, CS42L43_DECIM_VOL_CTRL_CH3_CH4,
848 CS42L43_DECIM4_VD_RAMP_SHIFT, cs42l43_ramp_text);
849
850static DECLARE_TLV_DB_SCALE(cs42l43_speaker_tlv, -6400, 50, 0);
851
852static SOC_ENUM_SINGLE_DECL(cs42l43_speaker_ramp_up, CS42L43_AMP1_2_VOL_RAMP,
853 CS42L43_AMP1_2_VI_RAMP_SHIFT, cs42l43_ramp_text);
854
855static SOC_ENUM_SINGLE_DECL(cs42l43_speaker_ramp_down, CS42L43_AMP1_2_VOL_RAMP,
856 CS42L43_AMP1_2_VD_RAMP_SHIFT, cs42l43_ramp_text);
857
858static DECLARE_TLV_DB_SCALE(cs42l43_headphone_tlv, -11450, 50, 1);
859
860static const char * const cs42l43_headphone_ramp_text[] = {
861 "1", "2", "4", "6", "8", "11", "12", "16", "22", "24", "33", "36", "44",
862 "48", "66", "72",
863};
864
865static SOC_ENUM_SINGLE_DECL(cs42l43_headphone_ramp, CS42L43_PGAVOL,
866 CS42L43_HP_PATH_VOL_RAMP_SHIFT,
867 cs42l43_headphone_ramp_text);
868
869static const char * const cs42l43_tone_freq_text[] = {
870 "1kHz", "2kHz", "4kHz", "6kHz", "8kHz",
871};
872
873static SOC_ENUM_SINGLE_DECL(cs42l43_tone1_freq, CS42L43_TONE_CH1_CTRL,
874 CS42L43_TONE_FREQ_SHIFT, cs42l43_tone_freq_text);
875
876static SOC_ENUM_SINGLE_DECL(cs42l43_tone2_freq, CS42L43_TONE_CH2_CTRL,
877 CS42L43_TONE_FREQ_SHIFT, cs42l43_tone_freq_text);
878
879static const char * const cs42l43_mixer_texts[] = {
880 "None",
881 "Tone Generator 1", "Tone Generator 2",
882 "Decimator 1", "Decimator 2", "Decimator 3", "Decimator 4",
883 "ASPRX1", "ASPRX2", "ASPRX3", "ASPRX4", "ASPRX5", "ASPRX6",
884 "DP5RX1", "DP5RX2", "DP6RX1", "DP6RX2", "DP7RX1", "DP7RX2",
885 "ASRC INT1", "ASRC INT2", "ASRC INT3", "ASRC INT4",
886 "ASRC DEC1", "ASRC DEC2", "ASRC DEC3", "ASRC DEC4",
887 "ISRC1 INT1", "ISRC1 INT2",
888 "ISRC1 DEC1", "ISRC1 DEC2",
889 "ISRC2 INT1", "ISRC2 INT2",
890 "ISRC2 DEC1", "ISRC2 DEC2",
891 "EQ1", "EQ2",
892};
893
894static const unsigned int cs42l43_mixer_values[] = {
895 0x00, // None
896 0x04, 0x05, // Tone Generator 1, 2
897 0x10, 0x11, 0x12, 0x13, // Decimator 1, 2, 3, 4
898 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, // ASPRX1,2,3,4,5,6
899 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, // DP5, 6, 7RX1, 2
900 0x40, 0x41, 0x42, 0x43, // ASRC INT1, 2, 3, 4
901 0x44, 0x45, 0x46, 0x47, // ASRC DEC1, 2, 3, 4
902 0x50, 0x51, // ISRC1 INT1, 2
903 0x52, 0x53, // ISRC1 DEC1, 2
904 0x54, 0x55, // ISRC2 INT1, 2
905 0x56, 0x57, // ISRC2 DEC1, 2
906 0x58, 0x59, // EQ1, 2
907};
908
909CS42L43_DECL_MUX(asptx1, CS42L43_ASPTX1_INPUT);
910CS42L43_DECL_MUX(asptx2, CS42L43_ASPTX2_INPUT);
911CS42L43_DECL_MUX(asptx3, CS42L43_ASPTX3_INPUT);
912CS42L43_DECL_MUX(asptx4, CS42L43_ASPTX4_INPUT);
913CS42L43_DECL_MUX(asptx5, CS42L43_ASPTX5_INPUT);
914CS42L43_DECL_MUX(asptx6, CS42L43_ASPTX6_INPUT);
915
916CS42L43_DECL_MUX(dp1tx1, CS42L43_SWIRE_DP1_CH1_INPUT);
917CS42L43_DECL_MUX(dp1tx2, CS42L43_SWIRE_DP1_CH2_INPUT);
918CS42L43_DECL_MUX(dp1tx3, CS42L43_SWIRE_DP1_CH3_INPUT);
919CS42L43_DECL_MUX(dp1tx4, CS42L43_SWIRE_DP1_CH4_INPUT);
920CS42L43_DECL_MUX(dp2tx1, CS42L43_SWIRE_DP2_CH1_INPUT);
921CS42L43_DECL_MUX(dp2tx2, CS42L43_SWIRE_DP2_CH2_INPUT);
922CS42L43_DECL_MUX(dp3tx1, CS42L43_SWIRE_DP3_CH1_INPUT);
923CS42L43_DECL_MUX(dp3tx2, CS42L43_SWIRE_DP3_CH2_INPUT);
924CS42L43_DECL_MUX(dp4tx1, CS42L43_SWIRE_DP4_CH1_INPUT);
925CS42L43_DECL_MUX(dp4tx2, CS42L43_SWIRE_DP4_CH2_INPUT);
926
927CS42L43_DECL_MUX(asrcint1, CS42L43_ASRC_INT1_INPUT1);
928CS42L43_DECL_MUX(asrcint2, CS42L43_ASRC_INT2_INPUT1);
929CS42L43_DECL_MUX(asrcint3, CS42L43_ASRC_INT3_INPUT1);
930CS42L43_DECL_MUX(asrcint4, CS42L43_ASRC_INT4_INPUT1);
931CS42L43_DECL_MUX(asrcdec1, CS42L43_ASRC_DEC1_INPUT1);
932CS42L43_DECL_MUX(asrcdec2, CS42L43_ASRC_DEC2_INPUT1);
933CS42L43_DECL_MUX(asrcdec3, CS42L43_ASRC_DEC3_INPUT1);
934CS42L43_DECL_MUX(asrcdec4, CS42L43_ASRC_DEC4_INPUT1);
935
936CS42L43_DECL_MUX(isrc1int1, CS42L43_ISRC1INT1_INPUT1);
937CS42L43_DECL_MUX(isrc1int2, CS42L43_ISRC1INT2_INPUT1);
938CS42L43_DECL_MUX(isrc1dec1, CS42L43_ISRC1DEC1_INPUT1);
939CS42L43_DECL_MUX(isrc1dec2, CS42L43_ISRC1DEC2_INPUT1);
940CS42L43_DECL_MUX(isrc2int1, CS42L43_ISRC2INT1_INPUT1);
941CS42L43_DECL_MUX(isrc2int2, CS42L43_ISRC2INT2_INPUT1);
942CS42L43_DECL_MUX(isrc2dec1, CS42L43_ISRC2DEC1_INPUT1);
943CS42L43_DECL_MUX(isrc2dec2, CS42L43_ISRC2DEC2_INPUT1);
944
945CS42L43_DECL_MUX(spdif1, CS42L43_SPDIF1_INPUT1);
946CS42L43_DECL_MUX(spdif2, CS42L43_SPDIF2_INPUT1);
947
948CS42L43_DECL_MIXER(eq1, CS42L43_EQ1MIX_INPUT1);
949CS42L43_DECL_MIXER(eq2, CS42L43_EQ2MIX_INPUT1);
950
951CS42L43_DECL_MIXER(amp1, CS42L43_AMP1MIX_INPUT1);
952CS42L43_DECL_MIXER(amp2, CS42L43_AMP2MIX_INPUT1);
953
954CS42L43_DECL_MIXER(amp3, CS42L43_AMP3MIX_INPUT1);
955CS42L43_DECL_MIXER(amp4, CS42L43_AMP4MIX_INPUT1);
956
957static int cs42l43_dapm_get_volsw(struct snd_kcontrol *kcontrol,
958 struct snd_ctl_elem_value *ucontrol)
959{
960 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
961 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
962 int ret;
963
964 snd_soc_dapm_mutex_lock(dapm);
965 ret = snd_soc_get_volsw(kcontrol, ucontrol);
966 snd_soc_dapm_mutex_unlock(dapm);
967
968 return ret;
969}
970
971static int cs42l43_dapm_put_volsw(struct snd_kcontrol *kcontrol,
972 struct snd_ctl_elem_value *ucontrol)
973{
974 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
975 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
976 int ret;
977
978 snd_soc_dapm_mutex_lock(dapm);
979 ret = snd_soc_put_volsw(kcontrol, ucontrol);
980 snd_soc_dapm_mutex_unlock(dapm);
981
982 return ret;
983}
984
985static int cs42l43_dapm_get_enum(struct snd_kcontrol *kcontrol,
986 struct snd_ctl_elem_value *ucontrol)
987{
988 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
989 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
990 int ret;
991
992 snd_soc_dapm_mutex_lock(dapm);
993 ret = snd_soc_get_enum_double(kcontrol, ucontrol);
994 snd_soc_dapm_mutex_unlock(dapm);
995
996 return ret;
997}
998
999static int cs42l43_dapm_put_enum(struct snd_kcontrol *kcontrol,
1000 struct snd_ctl_elem_value *ucontrol)
1001{
1002 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1003 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1004 int ret;
1005
1006 snd_soc_dapm_mutex_lock(dapm);
1007 ret = snd_soc_put_enum_double(kcontrol, ucontrol);
1008 snd_soc_dapm_mutex_unlock(dapm);
1009
1010 return ret;
1011}
1012
1013static int cs42l43_eq_get(struct snd_kcontrol *kcontrol,
1014 struct snd_ctl_elem_value *ucontrol)
1015{
1016 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1017 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1018
1019 memcpy(ucontrol->value.integer.value, priv->eq_coeffs, sizeof(priv->eq_coeffs));
1020
1021 return 0;
1022}
1023
1024static int cs42l43_eq_put(struct snd_kcontrol *kcontrol,
1025 struct snd_ctl_elem_value *ucontrol)
1026{
1027 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1028 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1029 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1030
1031 snd_soc_dapm_mutex_lock(dapm);
1032
1033 memcpy(priv->eq_coeffs, ucontrol->value.integer.value, sizeof(priv->eq_coeffs));
1034
1035 snd_soc_dapm_mutex_unlock(dapm);
1036
1037 return 0;
1038}
1039
1040static void cs42l43_spk_vu_sync(struct cs42l43_codec *priv)
1041{
1042 struct cs42l43 *cs42l43 = priv->core;
1043
1044 mutex_lock(&priv->spk_vu_lock);
1045
1046 regmap_update_bits(cs42l43->regmap, CS42L43_INTP_VOLUME_CTRL1,
1047 CS42L43_AMP1_2_VU_MASK, CS42L43_AMP1_2_VU_MASK);
1048 regmap_update_bits(cs42l43->regmap, CS42L43_INTP_VOLUME_CTRL1,
1049 CS42L43_AMP1_2_VU_MASK, 0);
1050
1051 mutex_unlock(&priv->spk_vu_lock);
1052}
1053
1054static int cs42l43_shutter_get(struct cs42l43_codec *priv, unsigned int shift)
1055{
1056 struct cs42l43 *cs42l43 = priv->core;
1057 unsigned int val;
1058 int ret;
1059
1060 ret = pm_runtime_resume_and_get(priv->dev);
1061 if (ret) {
1062 dev_err(priv->dev, "Failed to resume for shutters: %d\n", ret);
1063 return ret;
1064 }
1065
1066 /*
1067 * SHUTTER_CONTROL is a mix of volatile and non-volatile bits, so must
1068 * be cached for the non-volatiles, so drop it from the cache here so
1069 * we force a read.
1070 */
1071 ret = regcache_drop_region(cs42l43->regmap, CS42L43_SHUTTER_CONTROL,
1072 CS42L43_SHUTTER_CONTROL);
1073 if (ret) {
1074 dev_err(priv->dev, "Failed to drop shutter from cache: %d\n", ret);
1075 goto error;
1076 }
1077
1078 ret = regmap_read(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, &val);
1079 if (ret) {
1080 dev_err(priv->dev, "Failed to check shutter status: %d\n", ret);
1081 goto error;
1082 }
1083
1084 ret = !(val & BIT(shift));
1085
1086 dev_dbg(priv->dev, "%s shutter is %s\n",
1087 BIT(shift) == CS42L43_STATUS_MIC_SHUTTER_MUTE_MASK ? "Mic" : "Speaker",
1088 ret ? "open" : "closed");
1089
1090error:
1091 pm_runtime_mark_last_busy(priv->dev);
1092 pm_runtime_put_autosuspend(priv->dev);
1093
1094 return ret;
1095}
1096
1097static int cs42l43_decim_get(struct snd_kcontrol *kcontrol,
1098 struct snd_ctl_elem_value *ucontrol)
1099{
1100 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1101 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1102 int ret;
1103
1104 ret = cs42l43_shutter_get(priv, CS42L43_STATUS_MIC_SHUTTER_MUTE_SHIFT);
1105 if (ret > 0)
1106 ret = cs42l43_dapm_get_volsw(kcontrol, ucontrol);
1107 else if (!ret)
1108 ucontrol->value.integer.value[0] = ret;
1109
1110 return ret;
1111}
1112
1113static int cs42l43_spk_get(struct snd_kcontrol *kcontrol,
1114 struct snd_ctl_elem_value *ucontrol)
1115{
1116 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1117 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1118 int ret;
1119
1120 ret = cs42l43_shutter_get(priv, CS42L43_STATUS_SPK_SHUTTER_MUTE_SHIFT);
1121 if (ret > 0)
1122 ret = snd_soc_get_volsw(kcontrol, ucontrol);
1123 else if (!ret)
1124 ucontrol->value.integer.value[0] = ret;
1125
1126 return ret;
1127}
1128
1129static int cs42l43_spk_put(struct snd_kcontrol *kcontrol,
1130 struct snd_ctl_elem_value *ucontrol)
1131{
1132 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1133 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1134 int ret;
1135
1136 ret = snd_soc_put_volsw(kcontrol, ucontrol);
1137 if (ret > 0)
1138 cs42l43_spk_vu_sync(priv);
1139
1140 return ret;
1141}
1142
1143static const struct snd_kcontrol_new cs42l43_controls[] = {
1144 SOC_ENUM_EXT("Jack Override", cs42l43_jack_enum,
1145 cs42l43_jack_get, cs42l43_jack_put),
1146
1147 SOC_DOUBLE_R_SX_TLV("ADC Volume", CS42L43_ADC_B_CTRL1, CS42L43_ADC_B_CTRL2,
1148 CS42L43_ADC_PGA_GAIN_SHIFT,
1149 0xF, 5, cs42l43_adc_tlv),
1150
1151 SOC_DOUBLE("PDM1 Invert Switch", CS42L43_DMIC_PDM_CTRL,
1152 CS42L43_PDM1L_INV_SHIFT, CS42L43_PDM1R_INV_SHIFT, 1, 0),
1153 SOC_DOUBLE("PDM2 Invert Switch", CS42L43_DMIC_PDM_CTRL,
1154 CS42L43_PDM2L_INV_SHIFT, CS42L43_PDM2R_INV_SHIFT, 1, 0),
1155 SOC_ENUM("PDM1 Clock", cs42l43_pdm1_clk),
1156 SOC_ENUM("PDM2 Clock", cs42l43_pdm2_clk),
1157
1158 SOC_SINGLE("Decimator 1 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL1,
1159 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
1160 SOC_SINGLE("Decimator 2 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL2,
1161 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
1162 SOC_SINGLE("Decimator 3 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL3,
1163 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
1164 SOC_SINGLE("Decimator 4 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL4,
1165 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
1166
1167 SOC_ENUM("Decimator 1 WNF Corner Frequency", cs42l43_dec1_wnf_corner),
1168 SOC_ENUM("Decimator 2 WNF Corner Frequency", cs42l43_dec2_wnf_corner),
1169 SOC_ENUM("Decimator 3 WNF Corner Frequency", cs42l43_dec3_wnf_corner),
1170 SOC_ENUM("Decimator 4 WNF Corner Frequency", cs42l43_dec4_wnf_corner),
1171
1172 SOC_SINGLE("Decimator 1 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL1,
1173 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
1174 SOC_SINGLE("Decimator 2 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL2,
1175 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
1176 SOC_SINGLE("Decimator 3 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL3,
1177 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
1178 SOC_SINGLE("Decimator 4 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL4,
1179 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
1180
1181 SOC_ENUM("Decimator 1 HPF Corner Frequency", cs42l43_dec1_hpf_corner),
1182 SOC_ENUM("Decimator 2 HPF Corner Frequency", cs42l43_dec2_hpf_corner),
1183 SOC_ENUM("Decimator 3 HPF Corner Frequency", cs42l43_dec3_hpf_corner),
1184 SOC_ENUM("Decimator 4 HPF Corner Frequency", cs42l43_dec4_hpf_corner),
1185
1186 SOC_SINGLE_TLV("Decimator 1 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2,
1187 CS42L43_DECIM1_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
1188 SOC_SINGLE_EXT("Decimator 1 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2,
1189 CS42L43_DECIM1_MUTE_SHIFT, 1, 1,
1190 cs42l43_decim_get, cs42l43_dapm_put_volsw),
1191 SOC_SINGLE_TLV("Decimator 2 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2,
1192 CS42L43_DECIM2_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
1193 SOC_SINGLE_EXT("Decimator 2 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2,
1194 CS42L43_DECIM2_MUTE_SHIFT, 1, 1,
1195 cs42l43_decim_get, cs42l43_dapm_put_volsw),
1196 SOC_SINGLE_TLV("Decimator 3 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4,
1197 CS42L43_DECIM3_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
1198 SOC_SINGLE_EXT("Decimator 3 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4,
1199 CS42L43_DECIM3_MUTE_SHIFT, 1, 1,
1200 cs42l43_decim_get, cs42l43_dapm_put_volsw),
1201 SOC_SINGLE_TLV("Decimator 4 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4,
1202 CS42L43_DECIM4_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
1203 SOC_SINGLE_EXT("Decimator 4 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4,
1204 CS42L43_DECIM4_MUTE_SHIFT, 1, 1,
1205 cs42l43_decim_get, cs42l43_dapm_put_volsw),
1206
1207 SOC_ENUM_EXT("Decimator 1 Ramp Up", cs42l43_dec1_ramp_up,
1208 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1209 SOC_ENUM_EXT("Decimator 1 Ramp Down", cs42l43_dec1_ramp_down,
1210 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1211 SOC_ENUM_EXT("Decimator 2 Ramp Up", cs42l43_dec2_ramp_up,
1212 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1213 SOC_ENUM_EXT("Decimator 2 Ramp Down", cs42l43_dec2_ramp_down,
1214 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1215 SOC_ENUM_EXT("Decimator 3 Ramp Up", cs42l43_dec3_ramp_up,
1216 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1217 SOC_ENUM_EXT("Decimator 3 Ramp Down", cs42l43_dec3_ramp_down,
1218 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1219 SOC_ENUM_EXT("Decimator 4 Ramp Up", cs42l43_dec4_ramp_up,
1220 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1221 SOC_ENUM_EXT("Decimator 4 Ramp Down", cs42l43_dec4_ramp_down,
1222 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1223
1224 SOC_DOUBLE_R_EXT("Speaker Digital Switch",
1225 CS42L43_INTP_VOLUME_CTRL1, CS42L43_INTP_VOLUME_CTRL2,
1226 CS42L43_AMP_MUTE_SHIFT, 1, 1,
1227 cs42l43_spk_get, cs42l43_spk_put),
1228
1229 SOC_DOUBLE_R_EXT_TLV("Speaker Digital Volume",
1230 CS42L43_INTP_VOLUME_CTRL1, CS42L43_INTP_VOLUME_CTRL2,
1231 CS42L43_AMP_VOL_SHIFT,
1232 0xBF, 0, snd_soc_get_volsw, cs42l43_spk_put,
1233 cs42l43_speaker_tlv),
1234
1235 SOC_ENUM("Speaker Ramp Up", cs42l43_speaker_ramp_up),
1236 SOC_ENUM("Speaker Ramp Down", cs42l43_speaker_ramp_down),
1237
1238 CS42L43_MIXER_VOLUMES("Speaker L", CS42L43_AMP1MIX_INPUT1),
1239 CS42L43_MIXER_VOLUMES("Speaker R", CS42L43_AMP2MIX_INPUT1),
1240
1241 SOC_DOUBLE_SX_TLV("Headphone Digital Volume", CS42L43_HPPATHVOL,
1242 CS42L43_AMP3_PATH_VOL_SHIFT, CS42L43_AMP4_PATH_VOL_SHIFT,
1243 0x11B, 229, cs42l43_headphone_tlv),
1244
1245 SOC_DOUBLE("Headphone Invert Switch", CS42L43_DACCNFG1,
1246 CS42L43_AMP3_INV_SHIFT, CS42L43_AMP4_INV_SHIFT, 1, 0),
1247
1248 SOC_SINGLE("Headphone Zero Cross Switch", CS42L43_PGAVOL,
1249 CS42L43_HP_PATH_VOL_ZC_SHIFT, 1, 0),
1250 SOC_SINGLE("Headphone Ramp Switch", CS42L43_PGAVOL,
1251 CS42L43_HP_PATH_VOL_SFT_SHIFT, 1, 0),
1252 SOC_ENUM("Headphone Ramp Rate", cs42l43_headphone_ramp),
1253
1254 CS42L43_MIXER_VOLUMES("Headphone L", CS42L43_AMP3MIX_INPUT1),
1255 CS42L43_MIXER_VOLUMES("Headphone R", CS42L43_AMP4MIX_INPUT1),
1256
1257 SOC_ENUM("Tone 1 Frequency", cs42l43_tone1_freq),
1258 SOC_ENUM("Tone 2 Frequency", cs42l43_tone2_freq),
1259
1260 SOC_DOUBLE_EXT("EQ Switch",
1261 CS42L43_MUTE_EQ_IN0, CS42L43_MUTE_EQ_CH1_SHIFT,
1262 CS42L43_MUTE_EQ_CH2_SHIFT, 1, 1,
1263 cs42l43_dapm_get_volsw, cs42l43_dapm_put_volsw),
1264
1265 SND_SOC_BYTES_E("EQ Coefficients", 0, CS42L43_N_EQ_COEFFS,
1266 cs42l43_eq_get, cs42l43_eq_put),
1267
1268 CS42L43_MIXER_VOLUMES("EQ1", CS42L43_EQ1MIX_INPUT1),
1269 CS42L43_MIXER_VOLUMES("EQ2", CS42L43_EQ2MIX_INPUT1),
1270};
1271
1272static int cs42l43_eq_ev(struct snd_soc_dapm_widget *w,
1273 struct snd_kcontrol *kcontrol, int event)
1274{
1275 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1276 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1277 struct cs42l43 *cs42l43 = priv->core;
1278 unsigned int val;
1279 int i, ret;
1280
1281 switch (event) {
1282 case SND_SOC_DAPM_PRE_PMU:
1283 regmap_update_bits(cs42l43->regmap, CS42L43_MUTE_EQ_IN0,
1284 CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK,
1285 CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK);
1286
1287 regmap_update_bits(cs42l43->regmap, CS42L43_COEFF_RD_WR0,
1288 CS42L43_WRITE_MODE_MASK, CS42L43_WRITE_MODE_MASK);
1289
1290 for (i = 0; i < CS42L43_N_EQ_COEFFS; i++)
1291 regmap_write(cs42l43->regmap, CS42L43_COEFF_DATA_IN0,
1292 priv->eq_coeffs[i]);
1293
1294 regmap_update_bits(cs42l43->regmap, CS42L43_COEFF_RD_WR0,
1295 CS42L43_WRITE_MODE_MASK, 0);
1296
1297 return 0;
1298 case SND_SOC_DAPM_POST_PMU:
1299 ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_INIT_DONE0,
1300 val, (val & CS42L43_INITIALIZE_DONE_MASK),
1301 2000, 10000);
1302 if (ret)
1303 dev_err(priv->dev, "Failed to start EQs: %d\n", ret);
1304
1305 regmap_update_bits(cs42l43->regmap, CS42L43_MUTE_EQ_IN0,
1306 CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK, 0);
1307 return ret;
1308 default:
1309 return 0;
1310 }
1311}
1312
1313struct cs42l43_pll_config {
1314 unsigned int freq;
1315
1316 unsigned int div;
1317 unsigned int mode;
1318 unsigned int cal;
1319};
1320
1321static const struct cs42l43_pll_config cs42l43_pll_configs[] = {
1322 { 2400000, 0x50000000, 0x1, 0xA4 },
1323 { 3000000, 0x40000000, 0x1, 0x83 },
1324 { 3072000, 0x40000000, 0x3, 0x80 },
1325};
1326
1327static int cs42l43_set_pll(struct cs42l43_codec *priv, unsigned int src,
1328 unsigned int freq)
1329{
1330 struct cs42l43 *cs42l43 = priv->core;
1331
1332 lockdep_assert_held(&cs42l43->pll_lock);
1333
1334 if (priv->refclk_src == src && priv->refclk_freq == freq)
1335 return 0;
1336
1337 if (regmap_test_bits(cs42l43->regmap, CS42L43_CTRL_REG, CS42L43_PLL_EN_MASK)) {
1338 dev_err(priv->dev, "PLL active, can't change configuration\n");
1339 return -EBUSY;
1340 }
1341
1342 switch (src) {
1343 case CS42L43_SYSCLK_MCLK:
1344 case CS42L43_SYSCLK_SDW:
1345 dev_dbg(priv->dev, "Source PLL from %s at %uHz\n",
1346 src ? "SoundWire" : "MCLK", freq);
1347
1348 priv->refclk_src = src;
1349 priv->refclk_freq = freq;
1350
1351 return 0;
1352 default:
1353 dev_err(priv->dev, "Invalid PLL source: 0x%x\n", src);
1354 return -EINVAL;
1355 }
1356}
1357
1358static int cs42l43_enable_pll(struct cs42l43_codec *priv)
1359{
1360 static const struct reg_sequence enable_seq[] = {
1361 { CS42L43_OSC_DIV_SEL, 0x0, },
1362 { CS42L43_MCLK_SRC_SEL, CS42L43_OSC_PLL_MCLK_SEL_MASK, 5, },
1363 };
1364 struct cs42l43 *cs42l43 = priv->core;
1365 const struct cs42l43_pll_config *config = NULL;
1366 unsigned int div = 0;
1367 unsigned int freq = priv->refclk_freq;
1368 unsigned long time_left;
1369
1370 lockdep_assert_held(&cs42l43->pll_lock);
1371
1372 if (priv->refclk_src == CS42L43_SYSCLK_SDW) {
1373 if (!freq)
1374 freq = cs42l43->sdw_freq;
1375 else if (!cs42l43->sdw_freq)
1376 cs42l43->sdw_freq = freq;
1377 }
1378
1379 dev_dbg(priv->dev, "Enabling PLL at %uHz\n", freq);
1380
1381 div = fls(freq) -
1382 fls(cs42l43_pll_configs[ARRAY_SIZE(cs42l43_pll_configs) - 1].freq);
1383 freq >>= div;
1384
1385 if (div <= CS42L43_PLL_REFCLK_DIV_MASK) {
1386 int i;
1387
1388 for (i = 0; i < ARRAY_SIZE(cs42l43_pll_configs); i++) {
1389 if (freq == cs42l43_pll_configs[i].freq) {
1390 config = &cs42l43_pll_configs[i];
1391 break;
1392 }
1393 }
1394 }
1395
1396 if (!config) {
1397 dev_err(priv->dev, "No suitable PLL config: 0x%x, %uHz\n", div, freq);
1398 return -EINVAL;
1399 }
1400
1401 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
1402 CS42L43_PLL_REFCLK_DIV_MASK | CS42L43_PLL_REFCLK_SRC_MASK,
1403 div << CS42L43_PLL_REFCLK_DIV_SHIFT |
1404 priv->refclk_src << CS42L43_PLL_REFCLK_SRC_SHIFT);
1405 regmap_write(cs42l43->regmap, CS42L43_FDIV_FRAC, config->div);
1406 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG,
1407 CS42L43_PLL_MODE_BYPASS_500_MASK |
1408 CS42L43_PLL_MODE_BYPASS_1029_MASK,
1409 config->mode << CS42L43_PLL_MODE_BYPASS_1029_SHIFT);
1410 regmap_update_bits(cs42l43->regmap, CS42L43_CAL_RATIO,
1411 CS42L43_PLL_CAL_RATIO_MASK, config->cal);
1412 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
1413 CS42L43_PLL_REFCLK_EN_MASK, CS42L43_PLL_REFCLK_EN_MASK);
1414
1415 reinit_completion(&priv->pll_ready);
1416
1417 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG,
1418 CS42L43_PLL_EN_MASK, CS42L43_PLL_EN_MASK);
1419
1420 time_left = wait_for_completion_timeout(&priv->pll_ready,
1421 msecs_to_jiffies(CS42L43_PLL_TIMEOUT_MS));
1422 if (!time_left) {
1423 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG,
1424 CS42L43_PLL_EN_MASK, 0);
1425 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
1426 CS42L43_PLL_REFCLK_EN_MASK, 0);
1427
1428 dev_err(priv->dev, "Timeout out waiting for PLL\n");
1429 return -ETIMEDOUT;
1430 }
1431
1432 if (priv->refclk_src == CS42L43_SYSCLK_SDW)
1433 cs42l43->sdw_pll_active = true;
1434
1435 dev_dbg(priv->dev, "PLL locked in %ums\n", 200 - jiffies_to_msecs(time_left));
1436
1437 /*
1438 * Reads are not allowed over Soundwire without OSC_DIV2_EN or the PLL,
1439 * but you can not change to PLL with OSC_DIV2_EN set. So ensure the whole
1440 * change over happens under the regmap lock to prevent any reads.
1441 */
1442 regmap_multi_reg_write(cs42l43->regmap, enable_seq, ARRAY_SIZE(enable_seq));
1443
1444 return 0;
1445}
1446
1447static int cs42l43_disable_pll(struct cs42l43_codec *priv)
1448{
1449 static const struct reg_sequence disable_seq[] = {
1450 { CS42L43_MCLK_SRC_SEL, 0x0, 5, },
1451 { CS42L43_OSC_DIV_SEL, CS42L43_OSC_DIV2_EN_MASK, },
1452 };
1453 struct cs42l43 *cs42l43 = priv->core;
1454
1455 dev_dbg(priv->dev, "Disabling PLL\n");
1456
1457 lockdep_assert_held(&cs42l43->pll_lock);
1458
1459 regmap_multi_reg_write(cs42l43->regmap, disable_seq, ARRAY_SIZE(disable_seq));
1460 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG, CS42L43_PLL_EN_MASK, 0);
1461 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
1462 CS42L43_PLL_REFCLK_EN_MASK, 0);
1463
1464 cs42l43->sdw_pll_active = false;
1465
1466 return 0;
1467}
1468
1469static int cs42l43_pll_ev(struct snd_soc_dapm_widget *w,
1470 struct snd_kcontrol *kcontrol, int event)
1471{
1472 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1473 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1474 struct cs42l43 *cs42l43 = priv->core;
1475 int ret;
1476
1477 mutex_lock(&cs42l43->pll_lock);
1478
1479 switch (event) {
1480 case SND_SOC_DAPM_PRE_PMU:
1481 if (priv->refclk_src == CS42L43_SYSCLK_MCLK) {
1482 ret = clk_prepare_enable(priv->mclk);
1483 if (ret) {
1484 dev_err(priv->dev, "Failed to enable MCLK: %d\n", ret);
1485 break;
1486 }
1487 }
1488
1489 ret = cs42l43_enable_pll(priv);
1490 break;
1491 case SND_SOC_DAPM_POST_PMD:
1492 ret = cs42l43_disable_pll(priv);
1493
1494 if (priv->refclk_src == CS42L43_SYSCLK_MCLK)
1495 clk_disable_unprepare(priv->mclk);
1496 break;
1497 default:
1498 ret = 0;
1499 break;
1500 }
1501
1502 mutex_unlock(&cs42l43->pll_lock);
1503
1504 return ret;
1505}
1506
1507static int cs42l43_dapm_wait_completion(struct completion *pmu, struct completion *pmd,
1508 int event, int timeout_ms)
1509{
1510 unsigned long time_left;
1511
1512 switch (event) {
1513 case SND_SOC_DAPM_PRE_PMU:
1514 reinit_completion(pmu);
1515 return 0;
1516 case SND_SOC_DAPM_PRE_PMD:
1517 reinit_completion(pmd);
1518 return 0;
1519 case SND_SOC_DAPM_POST_PMU:
1520 time_left = wait_for_completion_timeout(pmu, msecs_to_jiffies(timeout_ms));
1521 break;
1522 case SND_SOC_DAPM_POST_PMD:
1523 time_left = wait_for_completion_timeout(pmd, msecs_to_jiffies(timeout_ms));
1524 break;
1525 default:
1526 return 0;
1527 }
1528
1529 if (!time_left)
1530 return -ETIMEDOUT;
1531 else
1532 return 0;
1533}
1534
1535static int cs42l43_spkr_ev(struct snd_soc_dapm_widget *w,
1536 struct snd_kcontrol *kcontrol, int event)
1537{
1538 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1539 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1540
1541 return cs42l43_dapm_wait_completion(&priv->spkr_startup,
1542 &priv->spkr_shutdown, event,
1543 CS42L43_SPK_TIMEOUT_MS);
1544}
1545
1546static int cs42l43_spkl_ev(struct snd_soc_dapm_widget *w,
1547 struct snd_kcontrol *kcontrol, int event)
1548{
1549 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1550 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1551
1552 return cs42l43_dapm_wait_completion(&priv->spkl_startup,
1553 &priv->spkl_shutdown, event,
1554 CS42L43_SPK_TIMEOUT_MS);
1555}
1556
1557static int cs42l43_hp_ev(struct snd_soc_dapm_widget *w,
1558 struct snd_kcontrol *kcontrol, int event)
1559{
1560 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1561 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1562 struct cs42l43 *cs42l43 = priv->core;
1563 unsigned int mask = 1 << w->shift;
1564 unsigned int val = 0;
1565 int ret;
1566
1567 switch (event) {
1568 case SND_SOC_DAPM_PRE_PMU:
1569 val = mask;
1570 fallthrough;
1571 case SND_SOC_DAPM_PRE_PMD:
1572 priv->hp_ena &= ~mask;
1573 priv->hp_ena |= val;
1574
1575 ret = cs42l43_dapm_wait_completion(&priv->hp_startup,
1576 &priv->hp_shutdown, event,
1577 CS42L43_HP_TIMEOUT_MS);
1578 if (ret)
1579 return ret;
1580
1581 if (!priv->load_detect_running && !priv->hp_ilimited)
1582 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8,
1583 mask, val);
1584 break;
1585 case SND_SOC_DAPM_POST_PMU:
1586 case SND_SOC_DAPM_POST_PMD:
1587 if (priv->load_detect_running || priv->hp_ilimited)
1588 break;
1589
1590 ret = cs42l43_dapm_wait_completion(&priv->hp_startup,
1591 &priv->hp_shutdown, event,
1592 CS42L43_HP_TIMEOUT_MS);
1593 if (ret)
1594 return ret;
1595 break;
1596 default:
1597 break;
1598 }
1599
1600 return 0;
1601}
1602
1603static int cs42l43_mic_ev(struct snd_soc_dapm_widget *w,
1604 struct snd_kcontrol *kcontrol, int event)
1605{
1606 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1607 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1608 struct cs42l43 *cs42l43 = priv->core;
1609 unsigned int reg, ramp, mute;
1610 unsigned int *val;
1611 int ret;
1612
1613 switch (w->shift) {
1614 case CS42L43_ADC1_EN_SHIFT:
1615 case CS42L43_PDM1_DIN_L_EN_SHIFT:
1616 reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2;
1617 ramp = CS42L43_DECIM1_VD_RAMP_MASK;
1618 mute = CS42L43_DECIM1_MUTE_MASK;
1619 val = &priv->decim_cache[0];
1620 break;
1621 case CS42L43_ADC2_EN_SHIFT:
1622 case CS42L43_PDM1_DIN_R_EN_SHIFT:
1623 reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2;
1624 ramp = CS42L43_DECIM2_VD_RAMP_MASK;
1625 mute = CS42L43_DECIM2_MUTE_MASK;
1626 val = &priv->decim_cache[1];
1627 break;
1628 case CS42L43_PDM2_DIN_L_EN_SHIFT:
1629 reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4;
1630 ramp = CS42L43_DECIM3_VD_RAMP_MASK;
1631 mute = CS42L43_DECIM3_MUTE_MASK;
1632 val = &priv->decim_cache[2];
1633 break;
1634 case CS42L43_PDM2_DIN_R_EN_SHIFT:
1635 reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4;
1636 ramp = CS42L43_DECIM4_VD_RAMP_MASK;
1637 mute = CS42L43_DECIM4_MUTE_MASK;
1638 val = &priv->decim_cache[3];
1639 break;
1640 default:
1641 dev_err(priv->dev, "Invalid microphone shift: %d\n", w->shift);
1642 return -EINVAL;
1643 }
1644
1645 switch (event) {
1646 case SND_SOC_DAPM_PRE_PMU:
1647 ret = regmap_read(cs42l43->regmap, reg, val);
1648 if (ret) {
1649 dev_err(priv->dev,
1650 "Failed to cache decimator settings: %d\n",
1651 ret);
1652 return ret;
1653 }
1654
1655 regmap_update_bits(cs42l43->regmap, reg, mute | ramp, mute);
1656 break;
1657 case SND_SOC_DAPM_POST_PMU:
1658 regmap_update_bits(cs42l43->regmap, reg, mute | ramp, *val);
1659 break;
1660 default:
1661 break;
1662 }
1663
1664 return 0;
1665}
1666
1667static int cs42l43_adc_ev(struct snd_soc_dapm_widget *w,
1668 struct snd_kcontrol *kcontrol, int event)
1669{
1670 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1671 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1672 struct cs42l43 *cs42l43 = priv->core;
1673 unsigned int mask = 1 << w->shift;
1674 unsigned int val = 0;
1675 int ret;
1676
1677 ret = cs42l43_mic_ev(w, kcontrol, event);
1678 if (ret)
1679 return ret;
1680
1681 switch (event) {
1682 case SND_SOC_DAPM_PRE_PMU:
1683 val = mask;
1684 fallthrough;
1685 case SND_SOC_DAPM_PRE_PMD:
1686 priv->adc_ena &= ~mask;
1687 priv->adc_ena |= val;
1688
1689 if (!priv->load_detect_running)
1690 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN3,
1691 mask, val);
1692 fallthrough;
1693 default:
1694 return 0;
1695 }
1696}
1697
1698static const struct snd_soc_dapm_widget cs42l43_widgets[] = {
1699 SND_SOC_DAPM_SUPPLY("PLL", SND_SOC_NOPM, 0, 0, cs42l43_pll_ev,
1700 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1701
1702 SND_SOC_DAPM_INPUT("ADC1_IN1_P"),
1703 SND_SOC_DAPM_INPUT("ADC1_IN1_N"),
1704 SND_SOC_DAPM_INPUT("ADC1_IN2_P"),
1705 SND_SOC_DAPM_INPUT("ADC1_IN2_N"),
1706 SND_SOC_DAPM_INPUT("ADC2_IN_P"),
1707 SND_SOC_DAPM_INPUT("ADC2_IN_N"),
1708
1709 SND_SOC_DAPM_INPUT("PDM1_DIN"),
1710 SND_SOC_DAPM_INPUT("PDM2_DIN"),
1711
1712 SND_SOC_DAPM_MUX("ADC1 Input", SND_SOC_NOPM, 0, 0, &cs42l43_adc1_input_ctl),
1713
1714 SND_SOC_DAPM_PGA_E("ADC1", SND_SOC_NOPM, CS42L43_ADC1_EN_SHIFT, 0, NULL, 0,
1715 cs42l43_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1716 SND_SOC_DAPM_PRE_PMD),
1717 SND_SOC_DAPM_PGA_E("ADC2", SND_SOC_NOPM, CS42L43_ADC2_EN_SHIFT, 0, NULL, 0,
1718 cs42l43_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1719 SND_SOC_DAPM_PRE_PMD),
1720
1721 SND_SOC_DAPM_PGA_E("PDM1L", CS42L43_BLOCK_EN3, CS42L43_PDM1_DIN_L_EN_SHIFT,
1722 0, NULL, 0, cs42l43_mic_ev,
1723 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1724 SND_SOC_DAPM_PGA_E("PDM1R", CS42L43_BLOCK_EN3, CS42L43_PDM1_DIN_R_EN_SHIFT,
1725 0, NULL, 0, cs42l43_mic_ev,
1726 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1727 SND_SOC_DAPM_PGA_E("PDM2L", CS42L43_BLOCK_EN3, CS42L43_PDM2_DIN_L_EN_SHIFT,
1728 0, NULL, 0, cs42l43_mic_ev,
1729 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1730 SND_SOC_DAPM_PGA_E("PDM2R", CS42L43_BLOCK_EN3, CS42L43_PDM2_DIN_R_EN_SHIFT,
1731 0, NULL, 0, cs42l43_mic_ev,
1732 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1733
1734 SND_SOC_DAPM_MUX("Decimator 1 Mode", SND_SOC_NOPM, 0, 0,
1735 &cs42l43_dec_mode_ctl[0]),
1736 SND_SOC_DAPM_MUX("Decimator 2 Mode", SND_SOC_NOPM, 0, 0,
1737 &cs42l43_dec_mode_ctl[1]),
1738
1739 SND_SOC_DAPM_PGA("Decimator 1", SND_SOC_NOPM, 0, 0, NULL, 0),
1740 SND_SOC_DAPM_PGA("Decimator 2", SND_SOC_NOPM, 0, 0, NULL, 0),
1741 SND_SOC_DAPM_PGA("Decimator 3", SND_SOC_NOPM, 0, 0, NULL, 0),
1742 SND_SOC_DAPM_PGA("Decimator 4", SND_SOC_NOPM, 0, 0, NULL, 0),
1743
1744 SND_SOC_DAPM_SUPPLY_S("FSYNC", 0, CS42L43_ASP_CTRL, CS42L43_ASP_FSYNC_EN_SHIFT,
1745 0, NULL, 0),
1746 SND_SOC_DAPM_SUPPLY_S("BCLK", 1, CS42L43_ASP_CTRL, CS42L43_ASP_BCLK_EN_SHIFT,
1747 0, NULL, 0),
1748
1749 SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0,
1750 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH1_EN_SHIFT, 0),
1751 SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 1,
1752 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH2_EN_SHIFT, 0),
1753 SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 2,
1754 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH3_EN_SHIFT, 0),
1755 SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 3,
1756 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH4_EN_SHIFT, 0),
1757 SND_SOC_DAPM_AIF_OUT("ASPTX5", NULL, 4,
1758 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH5_EN_SHIFT, 0),
1759 SND_SOC_DAPM_AIF_OUT("ASPTX6", NULL, 5,
1760 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH6_EN_SHIFT, 0),
1761
1762 SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0,
1763 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH1_EN_SHIFT, 0),
1764 SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 1,
1765 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH2_EN_SHIFT, 0),
1766 SND_SOC_DAPM_AIF_IN("ASPRX3", NULL, 2,
1767 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH3_EN_SHIFT, 0),
1768 SND_SOC_DAPM_AIF_IN("ASPRX4", NULL, 3,
1769 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH4_EN_SHIFT, 0),
1770 SND_SOC_DAPM_AIF_IN("ASPRX5", NULL, 4,
1771 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH5_EN_SHIFT, 0),
1772 SND_SOC_DAPM_AIF_IN("ASPRX6", NULL, 5,
1773 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH6_EN_SHIFT, 0),
1774
1775 SND_SOC_DAPM_AIF_OUT("DP1TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1776 SND_SOC_DAPM_AIF_OUT("DP1TX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1777 SND_SOC_DAPM_AIF_OUT("DP1TX3", NULL, 2, SND_SOC_NOPM, 0, 0),
1778 SND_SOC_DAPM_AIF_OUT("DP1TX4", NULL, 3, SND_SOC_NOPM, 0, 0),
1779
1780 SND_SOC_DAPM_AIF_OUT("DP2TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1781 SND_SOC_DAPM_AIF_OUT("DP2TX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1782
1783 SND_SOC_DAPM_AIF_OUT("DP3TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1784 SND_SOC_DAPM_AIF_OUT("DP3TX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1785
1786 SND_SOC_DAPM_AIF_OUT("DP4TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1787 SND_SOC_DAPM_AIF_OUT("DP4TX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1788
1789 SND_SOC_DAPM_AIF_IN("DP5RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1790 SND_SOC_DAPM_AIF_IN("DP5RX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1791
1792 SND_SOC_DAPM_AIF_IN("DP6RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1793 SND_SOC_DAPM_AIF_IN("DP6RX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1794
1795 SND_SOC_DAPM_AIF_IN("DP7RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1796 SND_SOC_DAPM_AIF_IN("DP7RX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1797
1798 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-amp", 0, 0),
1799
1800 SND_SOC_DAPM_PGA_E("AMP1", CS42L43_BLOCK_EN10, CS42L43_AMP1_EN_SHIFT, 0, NULL, 0,
1801 cs42l43_spkl_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1802 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1803 SND_SOC_DAPM_PGA_E("AMP2", CS42L43_BLOCK_EN10, CS42L43_AMP2_EN_SHIFT, 0, NULL, 0,
1804 cs42l43_spkr_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1805 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1806
1807 SND_SOC_DAPM_OUTPUT("AMP1_OUT_P"),
1808 SND_SOC_DAPM_OUTPUT("AMP1_OUT_N"),
1809 SND_SOC_DAPM_OUTPUT("AMP2_OUT_P"),
1810 SND_SOC_DAPM_OUTPUT("AMP2_OUT_N"),
1811
1812 SND_SOC_DAPM_PGA("SPDIF", CS42L43_BLOCK_EN11, CS42L43_SPDIF_EN_SHIFT,
1813 0, NULL, 0),
1814 SND_SOC_DAPM_OUTPUT("SPDIF_TX"),
1815
1816 SND_SOC_DAPM_PGA_E("HP", SND_SOC_NOPM, CS42L43_HP_EN_SHIFT, 0, NULL, 0,
1817 cs42l43_hp_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1818 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1819 SND_SOC_DAPM_OUTPUT("AMP3_OUT"),
1820 SND_SOC_DAPM_OUTPUT("AMP4_OUT"),
1821
1822 SND_SOC_DAPM_SIGGEN("Tone"),
1823 SND_SOC_DAPM_SUPPLY("Tone Generator", CS42L43_BLOCK_EN9, CS42L43_TONE_EN_SHIFT,
1824 0, NULL, 0),
1825 SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Tone 1", CS42L43_TONE_CH1_CTRL,
1826 CS42L43_TONE_SEL_SHIFT, CS42L43_TONE_SEL_MASK, 0xA, 0),
1827 SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Tone 2", CS42L43_TONE_CH2_CTRL,
1828 CS42L43_TONE_SEL_SHIFT, CS42L43_TONE_SEL_MASK, 0xA, 0),
1829
1830 SND_SOC_DAPM_SUPPLY("ISRC1", CS42L43_BLOCK_EN5, CS42L43_ISRC1_BANK_EN_SHIFT,
1831 0, NULL, 0),
1832 SND_SOC_DAPM_SUPPLY("ISRC2", CS42L43_BLOCK_EN5, CS42L43_ISRC2_BANK_EN_SHIFT,
1833 0, NULL, 0),
1834
1835 SND_SOC_DAPM_PGA("ISRC1INT2", CS42L43_ISRC1_CTRL,
1836 CS42L43_ISRC_INT2_EN_SHIFT, 0, NULL, 0),
1837 SND_SOC_DAPM_PGA("ISRC1INT1", CS42L43_ISRC1_CTRL,
1838 CS42L43_ISRC_INT1_EN_SHIFT, 0, NULL, 0),
1839 SND_SOC_DAPM_PGA("ISRC1DEC2", CS42L43_ISRC1_CTRL,
1840 CS42L43_ISRC_DEC2_EN_SHIFT, 0, NULL, 0),
1841 SND_SOC_DAPM_PGA("ISRC1DEC1", CS42L43_ISRC1_CTRL,
1842 CS42L43_ISRC_DEC1_EN_SHIFT, 0, NULL, 0),
1843
1844 SND_SOC_DAPM_PGA("ISRC2INT2", CS42L43_ISRC2_CTRL,
1845 CS42L43_ISRC_INT2_EN_SHIFT, 0, NULL, 0),
1846 SND_SOC_DAPM_PGA("ISRC2INT1", CS42L43_ISRC2_CTRL,
1847 CS42L43_ISRC_INT1_EN_SHIFT, 0, NULL, 0),
1848 SND_SOC_DAPM_PGA("ISRC2DEC2", CS42L43_ISRC2_CTRL,
1849 CS42L43_ISRC_DEC2_EN_SHIFT, 0, NULL, 0),
1850 SND_SOC_DAPM_PGA("ISRC2DEC1", CS42L43_ISRC2_CTRL,
1851 CS42L43_ISRC_DEC1_EN_SHIFT, 0, NULL, 0),
1852
1853 SND_SOC_DAPM_SUPPLY("ASRC_INT", CS42L43_BLOCK_EN4,
1854 CS42L43_ASRC_INT_BANK_EN_SHIFT, 0, NULL, 0),
1855 SND_SOC_DAPM_SUPPLY("ASRC_DEC", CS42L43_BLOCK_EN4,
1856 CS42L43_ASRC_DEC_BANK_EN_SHIFT, 0, NULL, 0),
1857
1858 SND_SOC_DAPM_PGA("ASRC_INT1", CS42L43_ASRC_INT_ENABLES,
1859 CS42L43_ASRC_INT1_EN_SHIFT, 0, NULL, 0),
1860 SND_SOC_DAPM_PGA("ASRC_INT2", CS42L43_ASRC_INT_ENABLES,
1861 CS42L43_ASRC_INT2_EN_SHIFT, 0, NULL, 0),
1862 SND_SOC_DAPM_PGA("ASRC_INT3", CS42L43_ASRC_INT_ENABLES,
1863 CS42L43_ASRC_INT3_EN_SHIFT, 0, NULL, 0),
1864 SND_SOC_DAPM_PGA("ASRC_INT4", CS42L43_ASRC_INT_ENABLES,
1865 CS42L43_ASRC_INT4_EN_SHIFT, 0, NULL, 0),
1866 SND_SOC_DAPM_PGA("ASRC_DEC1", CS42L43_ASRC_DEC_ENABLES,
1867 CS42L43_ASRC_DEC1_EN_SHIFT, 0, NULL, 0),
1868 SND_SOC_DAPM_PGA("ASRC_DEC2", CS42L43_ASRC_DEC_ENABLES,
1869 CS42L43_ASRC_DEC2_EN_SHIFT, 0, NULL, 0),
1870 SND_SOC_DAPM_PGA("ASRC_DEC3", CS42L43_ASRC_DEC_ENABLES,
1871 CS42L43_ASRC_DEC3_EN_SHIFT, 0, NULL, 0),
1872 SND_SOC_DAPM_PGA("ASRC_DEC4", CS42L43_ASRC_DEC_ENABLES,
1873 CS42L43_ASRC_DEC4_EN_SHIFT, 0, NULL, 0),
1874
1875 SND_SOC_DAPM_SUPPLY("EQ Clock", CS42L43_BLOCK_EN7, CS42L43_EQ_EN_SHIFT,
1876 0, NULL, 0),
1877 SND_SOC_DAPM_PGA_E("EQ", CS42L43_START_EQZ0, CS42L43_START_FILTER_SHIFT,
1878 0, NULL, 0, cs42l43_eq_ev,
1879 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1880
1881 SND_SOC_DAPM_SUPPLY("Mixer Core", CS42L43_BLOCK_EN6, CS42L43_MIXER_EN_SHIFT,
1882 0, NULL, 0),
1883 CS42L43_DAPM_MUX("ASPTX1", asptx1),
1884 CS42L43_DAPM_MUX("ASPTX2", asptx2),
1885 CS42L43_DAPM_MUX("ASPTX3", asptx3),
1886 CS42L43_DAPM_MUX("ASPTX4", asptx4),
1887 CS42L43_DAPM_MUX("ASPTX5", asptx5),
1888 CS42L43_DAPM_MUX("ASPTX6", asptx6),
1889
1890 CS42L43_DAPM_MUX("DP1TX1", dp1tx1),
1891 CS42L43_DAPM_MUX("DP1TX2", dp1tx2),
1892 CS42L43_DAPM_MUX("DP1TX3", dp1tx3),
1893 CS42L43_DAPM_MUX("DP1TX4", dp1tx4),
1894 CS42L43_DAPM_MUX("DP2TX1", dp2tx1),
1895 CS42L43_DAPM_MUX("DP2TX2", dp2tx2),
1896 CS42L43_DAPM_MUX("DP3TX1", dp3tx1),
1897 CS42L43_DAPM_MUX("DP3TX2", dp3tx2),
1898 CS42L43_DAPM_MUX("DP4TX1", dp4tx1),
1899 CS42L43_DAPM_MUX("DP4TX2", dp4tx2),
1900
1901 CS42L43_DAPM_MUX("ASRC INT1", asrcint1),
1902 CS42L43_DAPM_MUX("ASRC INT2", asrcint2),
1903 CS42L43_DAPM_MUX("ASRC INT3", asrcint3),
1904 CS42L43_DAPM_MUX("ASRC INT4", asrcint4),
1905 CS42L43_DAPM_MUX("ASRC DEC1", asrcdec1),
1906 CS42L43_DAPM_MUX("ASRC DEC2", asrcdec2),
1907 CS42L43_DAPM_MUX("ASRC DEC3", asrcdec3),
1908 CS42L43_DAPM_MUX("ASRC DEC4", asrcdec4),
1909
1910 CS42L43_DAPM_MUX("ISRC1INT1", isrc1int1),
1911 CS42L43_DAPM_MUX("ISRC1INT2", isrc1int2),
1912 CS42L43_DAPM_MUX("ISRC1DEC1", isrc1dec1),
1913 CS42L43_DAPM_MUX("ISRC1DEC2", isrc1dec2),
1914 CS42L43_DAPM_MUX("ISRC2INT1", isrc2int1),
1915 CS42L43_DAPM_MUX("ISRC2INT2", isrc2int2),
1916 CS42L43_DAPM_MUX("ISRC2DEC1", isrc2dec1),
1917 CS42L43_DAPM_MUX("ISRC2DEC2", isrc2dec2),
1918
1919 CS42L43_DAPM_MUX("SPDIF1", spdif1),
1920 CS42L43_DAPM_MUX("SPDIF2", spdif2),
1921
1922 CS42L43_DAPM_MIXER("EQ1", eq1),
1923 CS42L43_DAPM_MIXER("EQ2", eq2),
1924
1925 CS42L43_DAPM_MIXER("Speaker L", amp1),
1926 CS42L43_DAPM_MIXER("Speaker R", amp2),
1927
1928 CS42L43_DAPM_MIXER("Headphone L", amp3),
1929 CS42L43_DAPM_MIXER("Headphone R", amp4),
1930};
1931
1932static const struct snd_soc_dapm_route cs42l43_routes[] = {
1933 { "ADC1_IN1_P", NULL, "PLL" },
1934 { "ADC1_IN1_N", NULL, "PLL" },
1935 { "ADC1_IN2_P", NULL, "PLL" },
1936 { "ADC1_IN2_N", NULL, "PLL" },
1937 { "ADC2_IN_P", NULL, "PLL" },
1938 { "ADC2_IN_N", NULL, "PLL" },
1939 { "PDM1_DIN", NULL, "PLL" },
1940 { "PDM2_DIN", NULL, "PLL" },
1941 { "AMP1_OUT_P", NULL, "PLL" },
1942 { "AMP1_OUT_N", NULL, "PLL" },
1943 { "AMP2_OUT_P", NULL, "PLL" },
1944 { "AMP2_OUT_N", NULL, "PLL" },
1945 { "SPDIF_TX", NULL, "PLL" },
1946 { "HP", NULL, "PLL" },
1947 { "AMP3_OUT", NULL, "PLL" },
1948 { "AMP4_OUT", NULL, "PLL" },
1949 { "Tone 1", NULL, "PLL" },
1950 { "Tone 2", NULL, "PLL" },
1951 { "ASP Playback", NULL, "PLL" },
1952 { "ASP Capture", NULL, "PLL" },
1953 { "DP1 Capture", NULL, "PLL" },
1954 { "DP2 Capture", NULL, "PLL" },
1955 { "DP3 Capture", NULL, "PLL" },
1956 { "DP4 Capture", NULL, "PLL" },
1957 { "DP5 Playback", NULL, "PLL" },
1958 { "DP6 Playback", NULL, "PLL" },
1959 { "DP7 Playback", NULL, "PLL" },
1960
1961 { "ADC1 Input", "IN1", "ADC1_IN1_P" },
1962 { "ADC1 Input", "IN1", "ADC1_IN1_N" },
1963 { "ADC1 Input", "IN2", "ADC1_IN2_P" },
1964 { "ADC1 Input", "IN2", "ADC1_IN2_N" },
1965
1966 { "ADC1", NULL, "ADC1 Input" },
1967 { "ADC2", NULL, "ADC2_IN_P" },
1968 { "ADC2", NULL, "ADC2_IN_N" },
1969
1970 { "PDM1L", NULL, "PDM1_DIN" },
1971 { "PDM1R", NULL, "PDM1_DIN" },
1972 { "PDM2L", NULL, "PDM2_DIN" },
1973 { "PDM2R", NULL, "PDM2_DIN" },
1974
1975 { "Decimator 1 Mode", "PDM", "PDM1L" },
1976 { "Decimator 1 Mode", "ADC", "ADC1" },
1977 { "Decimator 2 Mode", "PDM", "PDM1R" },
1978 { "Decimator 2 Mode", "ADC", "ADC2" },
1979
1980 { "Decimator 1", NULL, "Decimator 1 Mode" },
1981 { "Decimator 2", NULL, "Decimator 2 Mode" },
1982 { "Decimator 3", NULL, "PDM2L" },
1983 { "Decimator 4", NULL, "PDM2R" },
1984
1985 { "ASP Capture", NULL, "ASPTX1" },
1986 { "ASP Capture", NULL, "ASPTX2" },
1987 { "ASP Capture", NULL, "ASPTX3" },
1988 { "ASP Capture", NULL, "ASPTX4" },
1989 { "ASP Capture", NULL, "ASPTX5" },
1990 { "ASP Capture", NULL, "ASPTX6" },
1991 { "ASPTX1", NULL, "BCLK" },
1992 { "ASPTX2", NULL, "BCLK" },
1993 { "ASPTX3", NULL, "BCLK" },
1994 { "ASPTX4", NULL, "BCLK" },
1995 { "ASPTX5", NULL, "BCLK" },
1996 { "ASPTX6", NULL, "BCLK" },
1997
1998 { "ASPRX1", NULL, "ASP Playback" },
1999 { "ASPRX2", NULL, "ASP Playback" },
2000 { "ASPRX3", NULL, "ASP Playback" },
2001 { "ASPRX4", NULL, "ASP Playback" },
2002 { "ASPRX5", NULL, "ASP Playback" },
2003 { "ASPRX6", NULL, "ASP Playback" },
2004 { "ASPRX1", NULL, "BCLK" },
2005 { "ASPRX2", NULL, "BCLK" },
2006 { "ASPRX3", NULL, "BCLK" },
2007 { "ASPRX4", NULL, "BCLK" },
2008 { "ASPRX5", NULL, "BCLK" },
2009 { "ASPRX6", NULL, "BCLK" },
2010
2011 { "DP1 Capture", NULL, "DP1TX1" },
2012 { "DP1 Capture", NULL, "DP1TX2" },
2013 { "DP1 Capture", NULL, "DP1TX3" },
2014 { "DP1 Capture", NULL, "DP1TX4" },
2015
2016 { "DP2 Capture", NULL, "DP2TX1" },
2017 { "DP2 Capture", NULL, "DP2TX2" },
2018
2019 { "DP3 Capture", NULL, "DP3TX1" },
2020 { "DP3 Capture", NULL, "DP3TX2" },
2021
2022 { "DP4 Capture", NULL, "DP4TX1" },
2023 { "DP4 Capture", NULL, "DP4TX2" },
2024
2025 { "DP5RX1", NULL, "DP5 Playback" },
2026 { "DP5RX2", NULL, "DP5 Playback" },
2027
2028 { "DP6RX1", NULL, "DP6 Playback" },
2029 { "DP6RX2", NULL, "DP6 Playback" },
2030
2031 { "DP7RX1", NULL, "DP7 Playback" },
2032 { "DP7RX2", NULL, "DP7 Playback" },
2033
2034 { "AMP1", NULL, "vdd-amp" },
2035 { "AMP2", NULL, "vdd-amp" },
2036
2037 { "AMP1_OUT_P", NULL, "AMP1" },
2038 { "AMP1_OUT_N", NULL, "AMP1" },
2039 { "AMP2_OUT_P", NULL, "AMP2" },
2040 { "AMP2_OUT_N", NULL, "AMP2" },
2041
2042 { "SPDIF_TX", NULL, "SPDIF" },
2043
2044 { "AMP3_OUT", NULL, "HP" },
2045 { "AMP4_OUT", NULL, "HP" },
2046
2047 { "Tone 1", NULL, "Tone" },
2048 { "Tone 1", NULL, "Tone Generator" },
2049 { "Tone 2", NULL, "Tone" },
2050 { "Tone 2", NULL, "Tone Generator" },
2051
2052 { "ISRC1INT2", NULL, "ISRC1" },
2053 { "ISRC1INT1", NULL, "ISRC1" },
2054 { "ISRC1DEC2", NULL, "ISRC1" },
2055 { "ISRC1DEC1", NULL, "ISRC1" },
2056
2057 { "ISRC2INT2", NULL, "ISRC2" },
2058 { "ISRC2INT1", NULL, "ISRC2" },
2059 { "ISRC2DEC2", NULL, "ISRC2" },
2060 { "ISRC2DEC1", NULL, "ISRC2" },
2061
2062 { "ASRC_INT1", NULL, "ASRC_INT" },
2063 { "ASRC_INT2", NULL, "ASRC_INT" },
2064 { "ASRC_INT3", NULL, "ASRC_INT" },
2065 { "ASRC_INT4", NULL, "ASRC_INT" },
2066 { "ASRC_DEC1", NULL, "ASRC_DEC" },
2067 { "ASRC_DEC2", NULL, "ASRC_DEC" },
2068 { "ASRC_DEC3", NULL, "ASRC_DEC" },
2069 { "ASRC_DEC4", NULL, "ASRC_DEC" },
2070
2071 { "EQ", NULL, "EQ Clock" },
2072
2073 CS42L43_MUX_ROUTES("ASPTX1", "ASPTX1"),
2074 CS42L43_MUX_ROUTES("ASPTX2", "ASPTX2"),
2075 CS42L43_MUX_ROUTES("ASPTX3", "ASPTX3"),
2076 CS42L43_MUX_ROUTES("ASPTX4", "ASPTX4"),
2077 CS42L43_MUX_ROUTES("ASPTX5", "ASPTX5"),
2078 CS42L43_MUX_ROUTES("ASPTX6", "ASPTX6"),
2079
2080 CS42L43_MUX_ROUTES("DP1TX1", "DP1TX1"),
2081 CS42L43_MUX_ROUTES("DP1TX2", "DP1TX2"),
2082 CS42L43_MUX_ROUTES("DP1TX3", "DP1TX3"),
2083 CS42L43_MUX_ROUTES("DP1TX4", "DP1TX4"),
2084 CS42L43_MUX_ROUTES("DP2TX1", "DP2TX1"),
2085 CS42L43_MUX_ROUTES("DP2TX2", "DP2TX2"),
2086 CS42L43_MUX_ROUTES("DP3TX1", "DP3TX1"),
2087 CS42L43_MUX_ROUTES("DP3TX2", "DP3TX2"),
2088 CS42L43_MUX_ROUTES("DP4TX1", "DP4TX1"),
2089 CS42L43_MUX_ROUTES("DP4TX2", "DP4TX2"),
2090
2091 CS42L43_MUX_ROUTES("ASRC INT1", "ASRC_INT1"),
2092 CS42L43_MUX_ROUTES("ASRC INT2", "ASRC_INT2"),
2093 CS42L43_MUX_ROUTES("ASRC INT3", "ASRC_INT3"),
2094 CS42L43_MUX_ROUTES("ASRC INT4", "ASRC_INT4"),
2095 CS42L43_MUX_ROUTES("ASRC DEC1", "ASRC_DEC1"),
2096 CS42L43_MUX_ROUTES("ASRC DEC2", "ASRC_DEC2"),
2097 CS42L43_MUX_ROUTES("ASRC DEC3", "ASRC_DEC3"),
2098 CS42L43_MUX_ROUTES("ASRC DEC4", "ASRC_DEC4"),
2099
2100 CS42L43_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"),
2101 CS42L43_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"),
2102 CS42L43_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"),
2103 CS42L43_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"),
2104 CS42L43_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"),
2105 CS42L43_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"),
2106 CS42L43_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"),
2107 CS42L43_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"),
2108
2109 CS42L43_MUX_ROUTES("SPDIF1", "SPDIF"),
2110 CS42L43_MUX_ROUTES("SPDIF2", "SPDIF"),
2111
2112 CS42L43_MIXER_ROUTES("EQ1", "EQ"),
2113 CS42L43_MIXER_ROUTES("EQ2", "EQ"),
2114
2115 CS42L43_MIXER_ROUTES("Speaker L", "AMP1"),
2116 CS42L43_MIXER_ROUTES("Speaker R", "AMP2"),
2117
2118 CS42L43_MIXER_ROUTES("Headphone L", "HP"),
2119 CS42L43_MIXER_ROUTES("Headphone R", "HP"),
2120};
2121
2122static int cs42l43_set_sysclk(struct snd_soc_component *component, int clk_id,
2123 int src, unsigned int freq, int dir)
2124{
2125 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
2126 struct cs42l43 *cs42l43 = priv->core;
2127 int ret;
2128
2129 mutex_lock(&cs42l43->pll_lock);
2130 ret = cs42l43_set_pll(priv, src, freq);
2131 mutex_unlock(&cs42l43->pll_lock);
2132
2133 return ret;
2134}
2135
2136static int cs42l43_component_probe(struct snd_soc_component *component)
2137{
2138 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
2139 struct cs42l43 *cs42l43 = priv->core;
2140
2141 snd_soc_component_init_regmap(component, cs42l43->regmap);
2142
2143 cs42l43_mask_to_slots(priv, CS42L43_DEFAULT_SLOTS, priv->tx_slots,
2144 ARRAY_SIZE(priv->tx_slots));
2145 cs42l43_mask_to_slots(priv, CS42L43_DEFAULT_SLOTS, priv->rx_slots,
2146 ARRAY_SIZE(priv->rx_slots));
2147
2148 priv->component = component;
2149 priv->constraint = cs42l43_constraint;
2150
2151 return 0;
2152}
2153
2154static void cs42l43_component_remove(struct snd_soc_component *component)
2155{
2156 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
2157
2158 cs42l43_set_jack(priv->component, NULL, NULL);
2159
2160 cancel_delayed_work_sync(&priv->bias_sense_timeout);
2161 cancel_delayed_work_sync(&priv->tip_sense_work);
2162 cancel_delayed_work_sync(&priv->button_press_work);
2163 cancel_work_sync(&priv->button_release_work);
2164
2165 cancel_work_sync(&priv->hp_ilimit_work);
2166 cancel_delayed_work_sync(&priv->hp_ilimit_clear_work);
2167
2168 priv->component = NULL;
2169}
2170
2171static const struct snd_soc_component_driver cs42l43_component_drv = {
2172 .name = "cs42l43-codec",
2173
2174 .probe = cs42l43_component_probe,
2175 .remove = cs42l43_component_remove,
2176 .set_sysclk = cs42l43_set_sysclk,
2177 .set_jack = cs42l43_set_jack,
2178
2179 .endianness = 1,
2180
2181 .controls = cs42l43_controls,
2182 .num_controls = ARRAY_SIZE(cs42l43_controls),
2183 .dapm_widgets = cs42l43_widgets,
2184 .num_dapm_widgets = ARRAY_SIZE(cs42l43_widgets),
2185 .dapm_routes = cs42l43_routes,
2186 .num_dapm_routes = ARRAY_SIZE(cs42l43_routes),
2187};
2188
2189struct cs42l43_irq {
2190 unsigned int irq;
2191 const char *name;
2192 irq_handler_t handler;
2193};
2194
2195static const struct cs42l43_irq cs42l43_irqs[] = {
2196 { CS42L43_PLL_LOST_LOCK, "pll lost lock", cs42l43_pll_lost_lock },
2197 { CS42L43_PLL_READY, "pll ready", cs42l43_pll_ready },
2198 { CS42L43_HP_STARTUP_DONE, "hp startup", cs42l43_hp_startup },
2199 { CS42L43_HP_SHUTDOWN_DONE, "hp shutdown", cs42l43_hp_shutdown },
2200 { CS42L43_HSDET_DONE, "type detect", cs42l43_type_detect },
2201 { CS42L43_TIPSENSE_UNPLUG_PDET, "tip sense unplug", cs42l43_tip_sense },
2202 { CS42L43_TIPSENSE_PLUG_PDET, "tip sense plug", cs42l43_tip_sense },
2203 { CS42L43_DC_DETECT1_TRUE, "button press", cs42l43_button_press },
2204 { CS42L43_DC_DETECT1_FALSE, "button release", cs42l43_button_release },
2205 { CS42L43_HSBIAS_CLAMPED, "hsbias detect clamp", cs42l43_bias_detect_clamp },
2206 { CS42L43_AMP2_CLK_STOP_FAULT, "spkr clock stop", cs42l43_spkr_clock_stop },
2207 { CS42L43_AMP1_CLK_STOP_FAULT, "spkl clock stop", cs42l43_spkl_clock_stop },
2208 { CS42L43_AMP2_VDDSPK_FAULT, "spkr brown out", cs42l43_spkr_brown_out },
2209 { CS42L43_AMP1_VDDSPK_FAULT, "spkl brown out", cs42l43_spkl_brown_out },
2210 { CS42L43_AMP2_SHUTDOWN_DONE, "spkr shutdown", cs42l43_spkr_shutdown },
2211 { CS42L43_AMP1_SHUTDOWN_DONE, "spkl shutdown", cs42l43_spkl_shutdown },
2212 { CS42L43_AMP2_STARTUP_DONE, "spkr startup", cs42l43_spkr_startup },
2213 { CS42L43_AMP1_STARTUP_DONE, "spkl startup", cs42l43_spkl_startup },
2214 { CS42L43_AMP2_THERM_SHDN, "spkr thermal shutdown", cs42l43_spkr_therm_shutdown },
2215 { CS42L43_AMP1_THERM_SHDN, "spkl thermal shutdown", cs42l43_spkl_therm_shutdown },
2216 { CS42L43_AMP2_THERM_WARN, "spkr thermal warning", cs42l43_spkr_therm_warm },
2217 { CS42L43_AMP1_THERM_WARN, "spkl thermal warning", cs42l43_spkl_therm_warm },
2218 { CS42L43_AMP2_SCDET, "spkr short circuit", cs42l43_spkr_sc_detect },
2219 { CS42L43_AMP1_SCDET, "spkl short circuit", cs42l43_spkl_sc_detect },
2220 { CS42L43_HP_ILIMIT, "hp ilimit", cs42l43_hp_ilimit },
2221 { CS42L43_HP_LOADDET_DONE, "load detect done", cs42l43_load_detect },
2222};
2223
2224static int cs42l43_request_irq(struct cs42l43_codec *priv,
2225 struct irq_domain *dom, const char * const name,
2226 unsigned int irq, irq_handler_t handler,
2227 unsigned long flags)
2228{
2229 int ret;
2230
2231 ret = irq_create_mapping(dom, irq);
2232 if (ret < 0)
2233 return dev_err_probe(priv->dev, ret, "Failed to map IRQ %s\n", name);
2234
2235 dev_dbg(priv->dev, "Request IRQ %d for %s\n", ret, name);
2236
2237 ret = devm_request_threaded_irq(priv->dev, ret, NULL, handler,
2238 IRQF_ONESHOT | flags, name, priv);
2239 if (ret)
2240 return dev_err_probe(priv->dev, ret, "Failed to request IRQ %s\n", name);
2241
2242 return 0;
2243}
2244
2245static int cs42l43_shutter_irq(struct cs42l43_codec *priv,
2246 struct irq_domain *dom, unsigned int shutter,
2247 const char * const open_name,
2248 const char * const close_name,
2249 irq_handler_t handler)
2250{
2251 unsigned int open_irq, close_irq;
2252 int ret;
2253
2254 switch (shutter) {
2255 case 0x1:
2256 dev_warn(priv->dev, "Manual shutters, notifications not available\n");
2257 return 0;
2258 case 0x2:
2259 open_irq = CS42L43_GPIO1_RISE;
2260 close_irq = CS42L43_GPIO1_FALL;
2261 break;
2262 case 0x4:
2263 open_irq = CS42L43_GPIO2_RISE;
2264 close_irq = CS42L43_GPIO2_FALL;
2265 break;
2266 case 0x8:
2267 open_irq = CS42L43_GPIO3_RISE;
2268 close_irq = CS42L43_GPIO3_FALL;
2269 break;
2270 default:
2271 return 0;
2272 }
2273
2274 ret = cs42l43_request_irq(priv, dom, close_name, close_irq, handler, IRQF_SHARED);
2275 if (ret)
2276 return ret;
2277
2278 return cs42l43_request_irq(priv, dom, open_name, open_irq, handler, IRQF_SHARED);
2279}
2280
2281static int cs42l43_codec_probe(struct platform_device *pdev)
2282{
2283 struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent);
2284 struct cs42l43_codec *priv;
2285 struct irq_domain *dom;
2286 unsigned int val;
2287 int i, ret;
2288
2289 dom = irq_find_matching_fwnode(dev_fwnode(cs42l43->dev), DOMAIN_BUS_ANY);
2290 if (!dom)
2291 return -EPROBE_DEFER;
2292
2293 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
2294 if (!priv)
2295 return -ENOMEM;
2296
2297 priv->dev = &pdev->dev;
2298 priv->core = cs42l43;
2299
2300 platform_set_drvdata(pdev, priv);
2301
2302 mutex_init(&priv->jack_lock);
2303 mutex_init(&priv->spk_vu_lock);
2304
2305 init_completion(&priv->hp_startup);
2306 init_completion(&priv->hp_shutdown);
2307 init_completion(&priv->spkr_shutdown);
2308 init_completion(&priv->spkl_shutdown);
2309 init_completion(&priv->spkr_startup);
2310 init_completion(&priv->spkl_startup);
2311 init_completion(&priv->pll_ready);
2312 init_completion(&priv->type_detect);
2313 init_completion(&priv->load_detect);
2314
2315 INIT_DELAYED_WORK(&priv->tip_sense_work, cs42l43_tip_sense_work);
2316 INIT_DELAYED_WORK(&priv->bias_sense_timeout, cs42l43_bias_sense_timeout);
2317 INIT_DELAYED_WORK(&priv->button_press_work, cs42l43_button_press_work);
2318 INIT_DELAYED_WORK(&priv->hp_ilimit_clear_work, cs42l43_hp_ilimit_clear_work);
2319 INIT_WORK(&priv->button_release_work, cs42l43_button_release_work);
2320 INIT_WORK(&priv->hp_ilimit_work, cs42l43_hp_ilimit_work);
2321
2322 pm_runtime_set_autosuspend_delay(priv->dev, 100);
2323 pm_runtime_use_autosuspend(priv->dev);
2324 pm_runtime_set_active(priv->dev);
2325 pm_runtime_get_noresume(priv->dev);
2326
2327 ret = devm_pm_runtime_enable(priv->dev);
2328 if (ret)
2329 goto err_pm;
2330
2331 for (i = 0; i < ARRAY_SIZE(cs42l43_irqs); i++) {
2332 ret = cs42l43_request_irq(priv, dom, cs42l43_irqs[i].name,
2333 cs42l43_irqs[i].irq,
2334 cs42l43_irqs[i].handler, 0);
2335 if (ret)
2336 goto err_pm;
2337 }
2338
2339 ret = regmap_read(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, &val);
2340 if (ret) {
2341 dev_err(priv->dev, "Failed to check shutter source: %d\n", ret);
2342 goto err_pm;
2343 }
2344
2345 ret = cs42l43_shutter_irq(priv, dom, val & CS42L43_MIC_SHUTTER_CFG_MASK,
2346 "mic shutter open", "mic shutter close",
2347 cs42l43_mic_shutter);
2348 if (ret)
2349 goto err_pm;
2350
2351 ret = cs42l43_shutter_irq(priv, dom, (val & CS42L43_SPK_SHUTTER_CFG_MASK) >>
2352 CS42L43_SPK_SHUTTER_CFG_SHIFT,
2353 "spk shutter open", "spk shutter close",
2354 cs42l43_spk_shutter);
2355 if (ret)
2356 goto err_pm;
2357
2358 // Don't use devm as we need to get against the MFD device
2359 priv->mclk = clk_get_optional(cs42l43->dev, "mclk");
2360 if (IS_ERR(priv->mclk)) {
2361 ret = PTR_ERR(priv->mclk);
2362 dev_err_probe(priv->dev, ret, "Failed to get mclk\n");
2363 goto err_pm;
2364 }
2365
2366 ret = devm_snd_soc_register_component(priv->dev, &cs42l43_component_drv,
2367 cs42l43_dais, ARRAY_SIZE(cs42l43_dais));
2368 if (ret) {
2369 dev_err_probe(priv->dev, ret, "Failed to register component\n");
2370 goto err_clk;
2371 }
2372
2373 pm_runtime_mark_last_busy(priv->dev);
2374 pm_runtime_put_autosuspend(priv->dev);
2375
2376 return 0;
2377
2378err_clk:
2379 clk_put(priv->mclk);
2380err_pm:
2381 pm_runtime_put_sync(priv->dev);
2382
2383 return ret;
2384}
2385
2386static void cs42l43_codec_remove(struct platform_device *pdev)
2387{
2388 struct cs42l43_codec *priv = platform_get_drvdata(pdev);
2389
2390 clk_put(priv->mclk);
2391}
2392
2393static int cs42l43_codec_runtime_resume(struct device *dev)
2394{
2395 struct cs42l43_codec *priv = dev_get_drvdata(dev);
2396
2397 dev_dbg(priv->dev, "Runtime resume\n");
2398
2399 // Toggle the speaker volume update incase the speaker volume was synced
2400 cs42l43_spk_vu_sync(priv);
2401
2402 return 0;
2403}
2404
2405static const struct dev_pm_ops cs42l43_codec_pm_ops = {
2406 RUNTIME_PM_OPS(NULL, cs42l43_codec_runtime_resume, NULL)
2407 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
2408};
2409
2410static const struct platform_device_id cs42l43_codec_id_table[] = {
2411 { "cs42l43-codec", },
2412 {}
2413};
2414MODULE_DEVICE_TABLE(platform, cs42l43_codec_id_table);
2415
2416static struct platform_driver cs42l43_codec_driver = {
2417 .driver = {
2418 .name = "cs42l43-codec",
2419 .pm = pm_ptr(&cs42l43_codec_pm_ops),
2420 },
2421
2422 .probe = cs42l43_codec_probe,
2423 .remove = cs42l43_codec_remove,
2424 .id_table = cs42l43_codec_id_table,
2425};
2426module_platform_driver(cs42l43_codec_driver);
2427
2428MODULE_IMPORT_NS("SND_SOC_CS42L43");
2429
2430MODULE_DESCRIPTION("CS42L43 CODEC Driver");
2431MODULE_AUTHOR("Charles Keepax <ckeepax@opensource.cirrus.com>");
2432MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0
2//
3// CS42L43 CODEC driver
4//
5// Copyright (C) 2022-2023 Cirrus Logic, Inc. and
6// Cirrus Logic International Semiconductor Ltd.
7
8#include <linux/bitops.h>
9#include <linux/bits.h>
10#include <linux/clk.h>
11#include <linux/device.h>
12#include <linux/err.h>
13#include <linux/errno.h>
14#include <linux/find.h>
15#include <linux/gcd.h>
16#include <linux/irq.h>
17#include <linux/irqdomain.h>
18#include <linux/jiffies.h>
19#include <linux/mfd/cs42l43.h>
20#include <linux/mfd/cs42l43-regs.h>
21#include <linux/mod_devicetable.h>
22#include <linux/module.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/regmap.h>
26#include <linux/string.h>
27#include <linux/workqueue.h>
28#include <sound/control.h>
29#include <sound/cs42l43.h>
30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/soc-component.h>
33#include <sound/soc-dapm.h>
34#include <sound/soc-dai.h>
35#include <sound/soc.h>
36#include <sound/tlv.h>
37
38#include "cs42l43.h"
39
40#define CS42L43_DECL_MUX(name, reg) \
41static SOC_VALUE_ENUM_SINGLE_DECL(cs42l43_##name##_enum, reg, \
42 0, CS42L43_MIXER_SRC_MASK, \
43 cs42l43_mixer_texts, cs42l43_mixer_values); \
44static const struct snd_kcontrol_new cs42l43_##name##_mux = \
45 SOC_DAPM_ENUM("Route", cs42l43_##name##_enum)
46
47#define CS42L43_DECL_MIXER(name, reg) \
48 CS42L43_DECL_MUX(name##_in1, reg); \
49 CS42L43_DECL_MUX(name##_in2, reg + 0x4); \
50 CS42L43_DECL_MUX(name##_in3, reg + 0x8); \
51 CS42L43_DECL_MUX(name##_in4, reg + 0xC)
52
53#define CS42L43_DAPM_MUX(name_str, name) \
54 SND_SOC_DAPM_MUX(name_str " Input", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_mux)
55
56#define CS42L43_DAPM_MIXER(name_str, name) \
57 SND_SOC_DAPM_MUX(name_str " Input 1", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in1_mux), \
58 SND_SOC_DAPM_MUX(name_str " Input 2", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in2_mux), \
59 SND_SOC_DAPM_MUX(name_str " Input 3", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in3_mux), \
60 SND_SOC_DAPM_MUX(name_str " Input 4", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in4_mux), \
61 SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
62
63#define CS42L43_BASE_ROUTES(name_str) \
64 { name_str, "Tone Generator 1", "Tone 1" }, \
65 { name_str, "Tone Generator 2", "Tone 2" }, \
66 { name_str, "Decimator 1", "Decimator 1" }, \
67 { name_str, "Decimator 2", "Decimator 2" }, \
68 { name_str, "Decimator 3", "Decimator 3" }, \
69 { name_str, "Decimator 4", "Decimator 4" }, \
70 { name_str, "ASPRX1", "ASPRX1" }, \
71 { name_str, "ASPRX2", "ASPRX2" }, \
72 { name_str, "ASPRX3", "ASPRX3" }, \
73 { name_str, "ASPRX4", "ASPRX4" }, \
74 { name_str, "ASPRX5", "ASPRX5" }, \
75 { name_str, "ASPRX6", "ASPRX6" }, \
76 { name_str, "DP5RX1", "DP5RX1" }, \
77 { name_str, "DP5RX2", "DP5RX2" }, \
78 { name_str, "DP6RX1", "DP6RX1" }, \
79 { name_str, "DP6RX2", "DP6RX2" }, \
80 { name_str, "DP7RX1", "DP7RX1" }, \
81 { name_str, "DP7RX2", "DP7RX2" }, \
82 { name_str, "ASRC INT1", "ASRC_INT1" }, \
83 { name_str, "ASRC INT2", "ASRC_INT2" }, \
84 { name_str, "ASRC INT3", "ASRC_INT3" }, \
85 { name_str, "ASRC INT4", "ASRC_INT4" }, \
86 { name_str, "ASRC DEC1", "ASRC_DEC1" }, \
87 { name_str, "ASRC DEC2", "ASRC_DEC2" }, \
88 { name_str, "ASRC DEC3", "ASRC_DEC3" }, \
89 { name_str, "ASRC DEC4", "ASRC_DEC4" }, \
90 { name_str, "ISRC1 INT1", "ISRC1INT1" }, \
91 { name_str, "ISRC1 INT2", "ISRC1INT2" }, \
92 { name_str, "ISRC1 DEC1", "ISRC1DEC1" }, \
93 { name_str, "ISRC1 DEC2", "ISRC1DEC2" }, \
94 { name_str, "ISRC2 INT1", "ISRC2INT1" }, \
95 { name_str, "ISRC2 INT2", "ISRC2INT2" }, \
96 { name_str, "ISRC2 DEC1", "ISRC2DEC1" }, \
97 { name_str, "ISRC2 DEC2", "ISRC2DEC2" }, \
98 { name_str, "EQ1", "EQ" }, \
99 { name_str, "EQ2", "EQ" }
100
101#define CS42L43_MUX_ROUTES(name_str, widget) \
102 { widget, NULL, name_str " Input" }, \
103 { name_str " Input", NULL, "Mixer Core" }, \
104 CS42L43_BASE_ROUTES(name_str " Input")
105
106#define CS42L43_MIXER_ROUTES(name_str, widget) \
107 { name_str " Mixer", NULL, name_str " Input 1" }, \
108 { name_str " Mixer", NULL, name_str " Input 2" }, \
109 { name_str " Mixer", NULL, name_str " Input 3" }, \
110 { name_str " Mixer", NULL, name_str " Input 4" }, \
111 { widget, NULL, name_str " Mixer" }, \
112 { name_str " Mixer", NULL, "Mixer Core" }, \
113 CS42L43_BASE_ROUTES(name_str " Input 1"), \
114 CS42L43_BASE_ROUTES(name_str " Input 2"), \
115 CS42L43_BASE_ROUTES(name_str " Input 3"), \
116 CS42L43_BASE_ROUTES(name_str " Input 4")
117
118#define CS42L43_MIXER_VOLUMES(name_str, base) \
119 SOC_SINGLE_RANGE_TLV(name_str " Input 1 Volume", base, \
120 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
121 cs42l43_mixer_tlv), \
122 SOC_SINGLE_RANGE_TLV(name_str " Input 2 Volume", base + 4, \
123 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
124 cs42l43_mixer_tlv), \
125 SOC_SINGLE_RANGE_TLV(name_str " Input 3 Volume", base + 8, \
126 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
127 cs42l43_mixer_tlv), \
128 SOC_SINGLE_RANGE_TLV(name_str " Input 4 Volume", base + 12, \
129 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
130 cs42l43_mixer_tlv)
131
132#define CS42L43_IRQ_ERROR(name) \
133static irqreturn_t cs42l43_##name(int irq, void *data) \
134{ \
135 struct cs42l43_codec *priv = data; \
136 dev_err(priv->dev, "Error " #name " IRQ\n"); \
137 return IRQ_HANDLED; \
138}
139
140CS42L43_IRQ_ERROR(pll_lost_lock)
141CS42L43_IRQ_ERROR(spkr_clock_stop)
142CS42L43_IRQ_ERROR(spkl_clock_stop)
143CS42L43_IRQ_ERROR(spkr_brown_out)
144CS42L43_IRQ_ERROR(spkl_brown_out)
145CS42L43_IRQ_ERROR(spkr_therm_shutdown)
146CS42L43_IRQ_ERROR(spkl_therm_shutdown)
147CS42L43_IRQ_ERROR(spkr_therm_warm)
148CS42L43_IRQ_ERROR(spkl_therm_warm)
149CS42L43_IRQ_ERROR(spkr_sc_detect)
150CS42L43_IRQ_ERROR(spkl_sc_detect)
151
152static void cs42l43_hp_ilimit_clear_work(struct work_struct *work)
153{
154 struct cs42l43_codec *priv = container_of(work, struct cs42l43_codec,
155 hp_ilimit_clear_work.work);
156 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(priv->component);
157
158 snd_soc_dapm_mutex_lock(dapm);
159
160 priv->hp_ilimit_count--;
161
162 if (priv->hp_ilimit_count)
163 queue_delayed_work(system_wq, &priv->hp_ilimit_clear_work,
164 msecs_to_jiffies(CS42L43_HP_ILIMIT_DECAY_MS));
165
166 snd_soc_dapm_mutex_unlock(dapm);
167}
168
169static void cs42l43_hp_ilimit_work(struct work_struct *work)
170{
171 struct cs42l43_codec *priv = container_of(work, struct cs42l43_codec,
172 hp_ilimit_work);
173 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(priv->component);
174 struct cs42l43 *cs42l43 = priv->core;
175
176 snd_soc_dapm_mutex_lock(dapm);
177
178 if (priv->hp_ilimit_count < CS42L43_HP_ILIMIT_MAX_COUNT) {
179 if (!priv->hp_ilimit_count)
180 queue_delayed_work(system_wq, &priv->hp_ilimit_clear_work,
181 msecs_to_jiffies(CS42L43_HP_ILIMIT_DECAY_MS));
182
183 priv->hp_ilimit_count++;
184 snd_soc_dapm_mutex_unlock(dapm);
185 return;
186 }
187
188 dev_err(priv->dev, "Disabling headphone for %dmS, due to frequent current limit\n",
189 CS42L43_HP_ILIMIT_BACKOFF_MS);
190
191 priv->hp_ilimited = true;
192
193 // No need to wait for disable, as just disabling for a period of time
194 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8,
195 CS42L43_HP_EN_MASK, 0);
196
197 snd_soc_dapm_mutex_unlock(dapm);
198
199 msleep(CS42L43_HP_ILIMIT_BACKOFF_MS);
200
201 snd_soc_dapm_mutex_lock(dapm);
202
203 if (priv->hp_ena && !priv->load_detect_running) {
204 unsigned long time_left;
205
206 reinit_completion(&priv->hp_startup);
207
208 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8,
209 CS42L43_HP_EN_MASK, priv->hp_ena);
210
211 time_left = wait_for_completion_timeout(&priv->hp_startup,
212 msecs_to_jiffies(CS42L43_HP_TIMEOUT_MS));
213 if (!time_left)
214 dev_err(priv->dev, "ilimit HP restore timed out\n");
215 }
216
217 priv->hp_ilimited = false;
218
219 snd_soc_dapm_mutex_unlock(dapm);
220}
221
222static irqreturn_t cs42l43_hp_ilimit(int irq, void *data)
223{
224 struct cs42l43_codec *priv = data;
225
226 dev_dbg(priv->dev, "headphone ilimit IRQ\n");
227
228 queue_work(system_long_wq, &priv->hp_ilimit_work);
229
230 return IRQ_HANDLED;
231}
232
233#define CS42L43_IRQ_COMPLETE(name) \
234static irqreturn_t cs42l43_##name(int irq, void *data) \
235{ \
236 struct cs42l43_codec *priv = data; \
237 dev_dbg(priv->dev, #name " completed\n"); \
238 complete(&priv->name); \
239 return IRQ_HANDLED; \
240}
241
242CS42L43_IRQ_COMPLETE(pll_ready)
243CS42L43_IRQ_COMPLETE(hp_startup)
244CS42L43_IRQ_COMPLETE(hp_shutdown)
245CS42L43_IRQ_COMPLETE(type_detect)
246CS42L43_IRQ_COMPLETE(spkr_shutdown)
247CS42L43_IRQ_COMPLETE(spkl_shutdown)
248CS42L43_IRQ_COMPLETE(spkr_startup)
249CS42L43_IRQ_COMPLETE(spkl_startup)
250CS42L43_IRQ_COMPLETE(load_detect)
251
252static irqreturn_t cs42l43_mic_shutter(int irq, void *data)
253{
254 struct cs42l43_codec *priv = data;
255 static const char * const controls[] = {
256 "Decimator 1 Switch",
257 "Decimator 2 Switch",
258 "Decimator 3 Switch",
259 "Decimator 4 Switch",
260 };
261 int i, ret;
262
263 dev_dbg(priv->dev, "Microphone shutter changed\n");
264
265 if (!priv->component)
266 return IRQ_NONE;
267
268 for (i = 0; i < ARRAY_SIZE(controls); i++) {
269 ret = snd_soc_component_notify_control(priv->component,
270 controls[i]);
271 if (ret)
272 return IRQ_NONE;
273 }
274
275 return IRQ_HANDLED;
276}
277
278static irqreturn_t cs42l43_spk_shutter(int irq, void *data)
279{
280 struct cs42l43_codec *priv = data;
281 int ret;
282
283 dev_dbg(priv->dev, "Speaker shutter changed\n");
284
285 if (!priv->component)
286 return IRQ_NONE;
287
288 ret = snd_soc_component_notify_control(priv->component,
289 "Speaker Digital Switch");
290 if (ret)
291 return IRQ_NONE;
292
293 return IRQ_HANDLED;
294}
295
296static const unsigned int cs42l43_sample_rates[] = {
297 8000, 16000, 24000, 32000, 44100, 48000, 96000, 192000,
298};
299
300#define CS42L43_CONSUMER_RATE_MASK 0xFF
301#define CS42L43_PROVIDER_RATE_MASK 0xEF // 44.1k only supported as consumer
302
303static const struct snd_pcm_hw_constraint_list cs42l43_constraint = {
304 .count = ARRAY_SIZE(cs42l43_sample_rates),
305 .list = cs42l43_sample_rates,
306};
307
308static int cs42l43_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
309{
310 struct snd_soc_component *component = dai->component;
311 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
312 struct cs42l43 *cs42l43 = priv->core;
313 int provider = !dai->id || !!regmap_test_bits(cs42l43->regmap,
314 CS42L43_ASP_CLK_CONFIG2,
315 CS42L43_ASP_MASTER_MODE_MASK);
316
317 if (provider)
318 priv->constraint.mask = CS42L43_PROVIDER_RATE_MASK;
319 else
320 priv->constraint.mask = CS42L43_CONSUMER_RATE_MASK;
321
322 return snd_pcm_hw_constraint_list(substream->runtime, 0,
323 SNDRV_PCM_HW_PARAM_RATE,
324 &priv->constraint);
325}
326
327static int cs42l43_convert_sample_rate(unsigned int rate)
328{
329 switch (rate) {
330 case 8000:
331 return 0x11;
332 case 16000:
333 return 0x12;
334 case 24000:
335 return 0x02;
336 case 32000:
337 return 0x13;
338 case 44100:
339 return 0x0B;
340 case 48000:
341 return 0x03;
342 case 96000:
343 return 0x04;
344 case 192000:
345 return 0x05;
346 default:
347 return -EINVAL;
348 }
349}
350
351static int cs42l43_set_sample_rate(struct snd_pcm_substream *substream,
352 struct snd_pcm_hw_params *params,
353 struct snd_soc_dai *dai)
354{
355 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(dai->component);
356 struct cs42l43 *cs42l43 = priv->core;
357 int ret;
358
359 ret = cs42l43_convert_sample_rate(params_rate(params));
360 if (ret < 0) {
361 dev_err(priv->dev, "Failed to convert sample rate: %d\n", ret);
362 return ret;
363 }
364
365 //FIXME: For now lets just set sample rate 1, this needs expanded in the future
366 regmap_update_bits(cs42l43->regmap, CS42L43_SAMPLE_RATE1,
367 CS42L43_SAMPLE_RATE_MASK, ret);
368
369 return 0;
370}
371
372static int cs42l43_asp_hw_params(struct snd_pcm_substream *substream,
373 struct snd_pcm_hw_params *params,
374 struct snd_soc_dai *dai)
375{
376 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(dai->component);
377 struct cs42l43 *cs42l43 = priv->core;
378 int dsp_mode = !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CTRL,
379 CS42L43_ASP_FSYNC_MODE_MASK);
380 int provider = !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2,
381 CS42L43_ASP_MASTER_MODE_MASK);
382 int n_chans = params_channels(params);
383 int data_width = params_width(params);
384 int n_slots = n_chans;
385 int slot_width = data_width;
386 int frame, bclk_target, i;
387 unsigned int reg;
388 int *slots;
389
390 if (priv->n_slots) {
391 n_slots = priv->n_slots;
392 slot_width = priv->slot_width;
393 }
394
395 if (!dsp_mode && (n_slots & 0x1)) {
396 dev_dbg(priv->dev, "Forcing balanced channels on ASP\n");
397 n_slots++;
398 }
399
400 frame = n_slots * slot_width;
401 bclk_target = params_rate(params) * frame;
402
403 if (provider) {
404 unsigned int gcd_nm = gcd(bclk_target, CS42L43_INTERNAL_SYSCLK);
405 int n = bclk_target / gcd_nm;
406 int m = CS42L43_INTERNAL_SYSCLK / gcd_nm;
407
408 if (n > (CS42L43_ASP_BCLK_N_MASK >> CS42L43_ASP_BCLK_N_SHIFT) ||
409 m > CS42L43_ASP_BCLK_M_MASK) {
410 dev_err(priv->dev, "Can't produce %dHz bclk\n", bclk_target);
411 return -EINVAL;
412 }
413
414 dev_dbg(priv->dev, "bclk %d/%d = %dHz, with %dx%d frame\n",
415 n, m, bclk_target, n_slots, slot_width);
416
417 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG1,
418 CS42L43_ASP_BCLK_N_MASK | CS42L43_ASP_BCLK_M_MASK,
419 n << CS42L43_ASP_BCLK_N_SHIFT |
420 m << CS42L43_ASP_BCLK_M_SHIFT);
421 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL1,
422 CS42L43_ASP_FSYNC_M_MASK, frame);
423 }
424
425 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL4,
426 CS42L43_ASP_NUM_BCLKS_PER_FSYNC_MASK,
427 frame << CS42L43_ASP_NUM_BCLKS_PER_FSYNC_SHIFT);
428
429 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
430 reg = CS42L43_ASP_TX_CH1_CTRL;
431 slots = priv->tx_slots;
432 } else {
433 reg = CS42L43_ASP_RX_CH1_CTRL;
434 slots = priv->rx_slots;
435 }
436
437 for (i = 0; i < n_chans; i++, reg += 4) {
438 int slot_phase = dsp_mode | (i & CS42L43_ASP_CH_SLOT_PHASE_MASK);
439 int slot_pos;
440
441 if (dsp_mode)
442 slot_pos = slots[i] * slot_width;
443 else
444 slot_pos = (slots[i] / 2) * slot_width;
445
446 dev_dbg(priv->dev, "Configure channel %d at slot %d (%d,%d)\n",
447 i, slots[i], slot_pos, slot_phase);
448
449 regmap_update_bits(cs42l43->regmap, reg,
450 CS42L43_ASP_CH_WIDTH_MASK |
451 CS42L43_ASP_CH_SLOT_MASK |
452 CS42L43_ASP_CH_SLOT_PHASE_MASK,
453 ((data_width - 1) << CS42L43_ASP_CH_WIDTH_SHIFT) |
454 (slot_pos << CS42L43_ASP_CH_SLOT_SHIFT) |
455 slot_phase);
456 }
457
458 return cs42l43_set_sample_rate(substream, params, dai);
459}
460
461static int cs42l43_asp_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
462{
463 struct snd_soc_component *component = dai->component;
464 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
465 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
466 struct cs42l43 *cs42l43 = priv->core;
467 int provider = regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2,
468 CS42L43_ASP_MASTER_MODE_MASK);
469 struct snd_soc_dapm_route routes[] = {
470 { "BCLK", NULL, "FSYNC" },
471 };
472 unsigned int asp_ctrl = 0;
473 unsigned int data_ctrl = 0;
474 unsigned int fsync_ctrl = 0;
475 unsigned int clk_config = 0;
476
477 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
478 case SND_SOC_DAIFMT_DSP_A:
479 data_ctrl |= 2 << CS42L43_ASP_FSYNC_FRAME_START_DLY_SHIFT;
480 fallthrough;
481 case SND_SOC_DAIFMT_DSP_B:
482 asp_ctrl |= CS42L43_ASP_FSYNC_MODE_MASK;
483 data_ctrl |= CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK;
484 break;
485 case SND_SOC_DAIFMT_I2S:
486 data_ctrl |= 2 << CS42L43_ASP_FSYNC_FRAME_START_DLY_SHIFT;
487 break;
488 case SND_SOC_DAIFMT_LEFT_J:
489 data_ctrl |= CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK;
490 break;
491 default:
492 dev_err(priv->dev, "Unsupported DAI format 0x%x\n",
493 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
494 return -EINVAL;
495 }
496
497 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
498 case SND_SOC_DAIFMT_CBC_CFC:
499 if (provider)
500 snd_soc_dapm_del_routes(dapm, routes, ARRAY_SIZE(routes));
501 break;
502 case SND_SOC_DAIFMT_CBP_CFP:
503 if (!provider)
504 snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes));
505 clk_config |= CS42L43_ASP_MASTER_MODE_MASK;
506 break;
507 default:
508 dev_err(priv->dev, "Unsupported ASP mode 0x%x\n",
509 fmt & SND_SOC_DAIFMT_MASTER_MASK);
510 return -EINVAL;
511 }
512
513 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
514 case SND_SOC_DAIFMT_NB_NF:
515 clk_config |= CS42L43_ASP_BCLK_INV_MASK; /* Yes BCLK_INV = NB */
516 break;
517 case SND_SOC_DAIFMT_IB_NF:
518 break;
519 case SND_SOC_DAIFMT_NB_IF:
520 clk_config |= CS42L43_ASP_BCLK_INV_MASK;
521 fsync_ctrl |= CS42L43_ASP_FSYNC_IN_INV_MASK |
522 CS42L43_ASP_FSYNC_OUT_INV_MASK;
523 break;
524 case SND_SOC_DAIFMT_IB_IF:
525 fsync_ctrl |= CS42L43_ASP_FSYNC_IN_INV_MASK |
526 CS42L43_ASP_FSYNC_OUT_INV_MASK;
527 break;
528 default:
529 dev_err(priv->dev, "Unsupported invert mode 0x%x\n",
530 fmt & SND_SOC_DAIFMT_INV_MASK);
531 return -EINVAL;
532 }
533
534 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CTRL,
535 CS42L43_ASP_FSYNC_MODE_MASK,
536 asp_ctrl);
537 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_DATA_CTRL,
538 CS42L43_ASP_FSYNC_FRAME_START_DLY_MASK |
539 CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK,
540 data_ctrl);
541 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2,
542 CS42L43_ASP_MASTER_MODE_MASK |
543 CS42L43_ASP_BCLK_INV_MASK,
544 clk_config);
545 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL3,
546 CS42L43_ASP_FSYNC_IN_INV_MASK |
547 CS42L43_ASP_FSYNC_OUT_INV_MASK,
548 fsync_ctrl);
549
550 return 0;
551}
552
553static void cs42l43_mask_to_slots(struct cs42l43_codec *priv, unsigned long mask,
554 int *slots, unsigned int nslots)
555{
556 int i = 0;
557 int slot;
558
559 for_each_set_bit(slot, &mask, BITS_PER_TYPE(mask)) {
560 if (i == nslots) {
561 dev_warn(priv->dev, "Too many channels in TDM mask: %lx\n",
562 mask);
563 return;
564 }
565
566 slots[i++] = slot;
567 }
568
569}
570
571static int cs42l43_asp_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
572 unsigned int rx_mask, int slots, int slot_width)
573{
574 struct snd_soc_component *component = dai->component;
575 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
576
577 priv->n_slots = slots;
578 priv->slot_width = slot_width;
579
580 if (!slots) {
581 tx_mask = CS42L43_DEFAULT_SLOTS;
582 rx_mask = CS42L43_DEFAULT_SLOTS;
583 }
584
585 cs42l43_mask_to_slots(priv, tx_mask, priv->tx_slots,
586 ARRAY_SIZE(priv->tx_slots));
587 cs42l43_mask_to_slots(priv, rx_mask, priv->rx_slots,
588 ARRAY_SIZE(priv->rx_slots));
589
590 return 0;
591}
592
593static const struct snd_soc_dai_ops cs42l43_asp_ops = {
594 .startup = cs42l43_startup,
595 .hw_params = cs42l43_asp_hw_params,
596 .set_fmt = cs42l43_asp_set_fmt,
597 .set_tdm_slot = cs42l43_asp_set_tdm_slot,
598};
599
600static int cs42l43_sdw_hw_params(struct snd_pcm_substream *substream,
601 struct snd_pcm_hw_params *params,
602 struct snd_soc_dai *dai)
603{
604 int ret;
605
606 ret = cs42l43_sdw_add_peripheral(substream, params, dai);
607 if (ret)
608 return ret;
609
610 return cs42l43_set_sample_rate(substream, params, dai);
611};
612
613static const struct snd_soc_dai_ops cs42l43_sdw_ops = {
614 .startup = cs42l43_startup,
615 .set_stream = cs42l43_sdw_set_stream,
616 .hw_params = cs42l43_sdw_hw_params,
617 .hw_free = cs42l43_sdw_remove_peripheral,
618};
619
620#define CS42L43_ASP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
621 SNDRV_PCM_FMTBIT_S32_LE)
622#define CS42L43_SDW_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
623
624static struct snd_soc_dai_driver cs42l43_dais[] = {
625 {
626 .name = "cs42l43-asp",
627 .ops = &cs42l43_asp_ops,
628 .symmetric_rate = 1,
629 .capture = {
630 .stream_name = "ASP Capture",
631 .channels_min = 1,
632 .channels_max = CS42L43_ASP_MAX_CHANNELS,
633 .rates = SNDRV_PCM_RATE_KNOT,
634 .formats = CS42L43_ASP_FORMATS,
635 },
636 .playback = {
637 .stream_name = "ASP Playback",
638 .channels_min = 1,
639 .channels_max = CS42L43_ASP_MAX_CHANNELS,
640 .rates = SNDRV_PCM_RATE_KNOT,
641 .formats = CS42L43_ASP_FORMATS,
642 },
643 },
644 {
645 .name = "cs42l43-dp1",
646 .id = 1,
647 .ops = &cs42l43_sdw_ops,
648 .capture = {
649 .stream_name = "DP1 Capture",
650 .channels_min = 1,
651 .channels_max = 4,
652 .rates = SNDRV_PCM_RATE_KNOT,
653 .formats = CS42L43_SDW_FORMATS,
654 },
655 },
656 {
657 .name = "cs42l43-dp2",
658 .id = 2,
659 .ops = &cs42l43_sdw_ops,
660 .capture = {
661 .stream_name = "DP2 Capture",
662 .channels_min = 1,
663 .channels_max = 2,
664 .rates = SNDRV_PCM_RATE_KNOT,
665 .formats = CS42L43_SDW_FORMATS,
666 },
667 },
668 {
669 .name = "cs42l43-dp3",
670 .id = 3,
671 .ops = &cs42l43_sdw_ops,
672 .capture = {
673 .stream_name = "DP3 Capture",
674 .channels_min = 1,
675 .channels_max = 2,
676 .rates = SNDRV_PCM_RATE_KNOT,
677 .formats = CS42L43_SDW_FORMATS,
678 },
679 },
680 {
681 .name = "cs42l43-dp4",
682 .id = 4,
683 .ops = &cs42l43_sdw_ops,
684 .capture = {
685 .stream_name = "DP4 Capture",
686 .channels_min = 1,
687 .channels_max = 2,
688 .rates = SNDRV_PCM_RATE_KNOT,
689 .formats = CS42L43_SDW_FORMATS,
690 },
691 },
692 {
693 .name = "cs42l43-dp5",
694 .id = 5,
695 .ops = &cs42l43_sdw_ops,
696 .playback = {
697 .stream_name = "DP5 Playback",
698 .channels_min = 1,
699 .channels_max = 2,
700 .rates = SNDRV_PCM_RATE_KNOT,
701 .formats = CS42L43_SDW_FORMATS,
702 },
703 },
704 {
705 .name = "cs42l43-dp6",
706 .id = 6,
707 .ops = &cs42l43_sdw_ops,
708 .playback = {
709 .stream_name = "DP6 Playback",
710 .channels_min = 1,
711 .channels_max = 2,
712 .rates = SNDRV_PCM_RATE_KNOT,
713 .formats = CS42L43_SDW_FORMATS,
714 },
715 },
716 {
717 .name = "cs42l43-dp7",
718 .id = 7,
719 .ops = &cs42l43_sdw_ops,
720 .playback = {
721 .stream_name = "DP7 Playback",
722 .channels_min = 1,
723 .channels_max = 2,
724 .rates = SNDRV_PCM_RATE_KNOT,
725 .formats = CS42L43_SDW_FORMATS,
726 },
727 },
728};
729
730static const DECLARE_TLV_DB_SCALE(cs42l43_mixer_tlv, -3200, 100, 0);
731
732static const char * const cs42l43_ramp_text[] = {
733 "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB",
734 "15ms/6dB", "30ms/6dB",
735};
736
737static const char * const cs42l43_adc1_input_text[] = { "IN1", "IN2" };
738
739static SOC_ENUM_SINGLE_DECL(cs42l43_adc1_input, CS42L43_ADC_B_CTRL1,
740 CS42L43_ADC_AIN_SEL_SHIFT,
741 cs42l43_adc1_input_text);
742
743static const struct snd_kcontrol_new cs42l43_adc1_input_ctl =
744 SOC_DAPM_ENUM("ADC1 Input", cs42l43_adc1_input);
745
746static const char * const cs42l43_dec_mode_text[] = { "ADC", "PDM" };
747
748static SOC_ENUM_SINGLE_VIRT_DECL(cs42l43_dec1_mode, cs42l43_dec_mode_text);
749static SOC_ENUM_SINGLE_VIRT_DECL(cs42l43_dec2_mode, cs42l43_dec_mode_text);
750
751static const struct snd_kcontrol_new cs42l43_dec_mode_ctl[] = {
752 SOC_DAPM_ENUM("Decimator 1 Mode", cs42l43_dec1_mode),
753 SOC_DAPM_ENUM("Decimator 2 Mode", cs42l43_dec2_mode),
754};
755
756static const char * const cs42l43_pdm_clk_text[] = {
757 "3.072MHz", "1.536MHz", "768kHz",
758};
759
760static SOC_ENUM_SINGLE_DECL(cs42l43_pdm1_clk, CS42L43_PDM_CONTROL,
761 CS42L43_PDM1_CLK_DIV_SHIFT, cs42l43_pdm_clk_text);
762static SOC_ENUM_SINGLE_DECL(cs42l43_pdm2_clk, CS42L43_PDM_CONTROL,
763 CS42L43_PDM2_CLK_DIV_SHIFT, cs42l43_pdm_clk_text);
764
765static DECLARE_TLV_DB_SCALE(cs42l43_adc_tlv, -600, 600, 0);
766static DECLARE_TLV_DB_SCALE(cs42l43_dec_tlv, -6400, 50, 0);
767
768static const char * const cs42l43_wnf_corner_text[] = {
769 "160Hz", "180Hz", "200Hz", "220Hz", "240Hz", "260Hz", "280Hz", "300Hz",
770};
771
772static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL1,
773 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
774static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL2,
775 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
776static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL3,
777 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
778static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL4,
779 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
780
781static const char * const cs42l43_hpf_corner_text[] = {
782 "3Hz", "12Hz", "48Hz", "96Hz",
783};
784
785static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL1,
786 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
787static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL2,
788 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
789static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL3,
790 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
791static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL4,
792 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
793
794static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_ramp_up, CS42L43_DECIM_VOL_CTRL_CH1_CH2,
795 CS42L43_DECIM1_VI_RAMP_SHIFT, cs42l43_ramp_text);
796static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_ramp_down, CS42L43_DECIM_VOL_CTRL_CH1_CH2,
797 CS42L43_DECIM1_VD_RAMP_SHIFT, cs42l43_ramp_text);
798static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_ramp_up, CS42L43_DECIM_VOL_CTRL_CH1_CH2,
799 CS42L43_DECIM2_VI_RAMP_SHIFT, cs42l43_ramp_text);
800static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_ramp_down, CS42L43_DECIM_VOL_CTRL_CH1_CH2,
801 CS42L43_DECIM2_VD_RAMP_SHIFT, cs42l43_ramp_text);
802static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_ramp_up, CS42L43_DECIM_VOL_CTRL_CH3_CH4,
803 CS42L43_DECIM3_VI_RAMP_SHIFT, cs42l43_ramp_text);
804static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_ramp_down, CS42L43_DECIM_VOL_CTRL_CH3_CH4,
805 CS42L43_DECIM3_VD_RAMP_SHIFT, cs42l43_ramp_text);
806static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_ramp_up, CS42L43_DECIM_VOL_CTRL_CH3_CH4,
807 CS42L43_DECIM4_VI_RAMP_SHIFT, cs42l43_ramp_text);
808static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_ramp_down, CS42L43_DECIM_VOL_CTRL_CH3_CH4,
809 CS42L43_DECIM4_VD_RAMP_SHIFT, cs42l43_ramp_text);
810
811static DECLARE_TLV_DB_SCALE(cs42l43_speaker_tlv, -6400, 50, 0);
812
813static SOC_ENUM_SINGLE_DECL(cs42l43_speaker_ramp_up, CS42L43_AMP1_2_VOL_RAMP,
814 CS42L43_AMP1_2_VI_RAMP_SHIFT, cs42l43_ramp_text);
815
816static SOC_ENUM_SINGLE_DECL(cs42l43_speaker_ramp_down, CS42L43_AMP1_2_VOL_RAMP,
817 CS42L43_AMP1_2_VD_RAMP_SHIFT, cs42l43_ramp_text);
818
819static DECLARE_TLV_DB_SCALE(cs42l43_headphone_tlv, -11450, 50, 1);
820
821static const char * const cs42l43_headphone_ramp_text[] = {
822 "1", "2", "4", "6", "8", "11", "12", "16", "22", "24", "33", "36", "44",
823 "48", "66", "72",
824};
825
826static SOC_ENUM_SINGLE_DECL(cs42l43_headphone_ramp, CS42L43_PGAVOL,
827 CS42L43_HP_PATH_VOL_RAMP_SHIFT,
828 cs42l43_headphone_ramp_text);
829
830static const char * const cs42l43_tone_freq_text[] = {
831 "1kHz", "2kHz", "4kHz", "6kHz", "8kHz",
832};
833
834static SOC_ENUM_SINGLE_DECL(cs42l43_tone1_freq, CS42L43_TONE_CH1_CTRL,
835 CS42L43_TONE_FREQ_SHIFT, cs42l43_tone_freq_text);
836
837static SOC_ENUM_SINGLE_DECL(cs42l43_tone2_freq, CS42L43_TONE_CH2_CTRL,
838 CS42L43_TONE_FREQ_SHIFT, cs42l43_tone_freq_text);
839
840static const char * const cs42l43_mixer_texts[] = {
841 "None",
842 "Tone Generator 1", "Tone Generator 2",
843 "Decimator 1", "Decimator 2", "Decimator 3", "Decimator 4",
844 "ASPRX1", "ASPRX2", "ASPRX3", "ASPRX4", "ASPRX5", "ASPRX6",
845 "DP5RX1", "DP5RX2", "DP6RX1", "DP6RX2", "DP7RX1", "DP7RX2",
846 "ASRC INT1", "ASRC INT2", "ASRC INT3", "ASRC INT4",
847 "ASRC DEC1", "ASRC DEC2", "ASRC DEC3", "ASRC DEC4",
848 "ISRC1 INT1", "ISRC1 INT2",
849 "ISRC1 DEC1", "ISRC1 DEC2",
850 "ISRC2 INT1", "ISRC2 INT2",
851 "ISRC2 DEC1", "ISRC2 DEC2",
852 "EQ1", "EQ2",
853};
854
855static const unsigned int cs42l43_mixer_values[] = {
856 0x00, // None
857 0x04, 0x05, // Tone Generator 1, 2
858 0x10, 0x11, 0x12, 0x13, // Decimator 1, 2, 3, 4
859 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, // ASPRX1,2,3,4,5,6
860 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, // DP5, 6, 7RX1, 2
861 0x40, 0x41, 0x42, 0x43, // ASRC INT1, 2, 3, 4
862 0x44, 0x45, 0x46, 0x47, // ASRC DEC1, 2, 3, 4
863 0x50, 0x51, // ISRC1 INT1, 2
864 0x52, 0x53, // ISRC1 DEC1, 2
865 0x54, 0x55, // ISRC2 INT1, 2
866 0x56, 0x57, // ISRC2 DEC1, 2
867 0x58, 0x59, // EQ1, 2
868};
869
870CS42L43_DECL_MUX(asptx1, CS42L43_ASPTX1_INPUT);
871CS42L43_DECL_MUX(asptx2, CS42L43_ASPTX2_INPUT);
872CS42L43_DECL_MUX(asptx3, CS42L43_ASPTX3_INPUT);
873CS42L43_DECL_MUX(asptx4, CS42L43_ASPTX4_INPUT);
874CS42L43_DECL_MUX(asptx5, CS42L43_ASPTX5_INPUT);
875CS42L43_DECL_MUX(asptx6, CS42L43_ASPTX6_INPUT);
876
877CS42L43_DECL_MUX(dp1tx1, CS42L43_SWIRE_DP1_CH1_INPUT);
878CS42L43_DECL_MUX(dp1tx2, CS42L43_SWIRE_DP1_CH2_INPUT);
879CS42L43_DECL_MUX(dp1tx3, CS42L43_SWIRE_DP1_CH3_INPUT);
880CS42L43_DECL_MUX(dp1tx4, CS42L43_SWIRE_DP1_CH4_INPUT);
881CS42L43_DECL_MUX(dp2tx1, CS42L43_SWIRE_DP2_CH1_INPUT);
882CS42L43_DECL_MUX(dp2tx2, CS42L43_SWIRE_DP2_CH2_INPUT);
883CS42L43_DECL_MUX(dp3tx1, CS42L43_SWIRE_DP3_CH1_INPUT);
884CS42L43_DECL_MUX(dp3tx2, CS42L43_SWIRE_DP3_CH2_INPUT);
885CS42L43_DECL_MUX(dp4tx1, CS42L43_SWIRE_DP4_CH1_INPUT);
886CS42L43_DECL_MUX(dp4tx2, CS42L43_SWIRE_DP4_CH2_INPUT);
887
888CS42L43_DECL_MUX(asrcint1, CS42L43_ASRC_INT1_INPUT1);
889CS42L43_DECL_MUX(asrcint2, CS42L43_ASRC_INT2_INPUT1);
890CS42L43_DECL_MUX(asrcint3, CS42L43_ASRC_INT3_INPUT1);
891CS42L43_DECL_MUX(asrcint4, CS42L43_ASRC_INT4_INPUT1);
892CS42L43_DECL_MUX(asrcdec1, CS42L43_ASRC_DEC1_INPUT1);
893CS42L43_DECL_MUX(asrcdec2, CS42L43_ASRC_DEC2_INPUT1);
894CS42L43_DECL_MUX(asrcdec3, CS42L43_ASRC_DEC3_INPUT1);
895CS42L43_DECL_MUX(asrcdec4, CS42L43_ASRC_DEC4_INPUT1);
896
897CS42L43_DECL_MUX(isrc1int1, CS42L43_ISRC1INT1_INPUT1);
898CS42L43_DECL_MUX(isrc1int2, CS42L43_ISRC1INT2_INPUT1);
899CS42L43_DECL_MUX(isrc1dec1, CS42L43_ISRC1DEC1_INPUT1);
900CS42L43_DECL_MUX(isrc1dec2, CS42L43_ISRC1DEC2_INPUT1);
901CS42L43_DECL_MUX(isrc2int1, CS42L43_ISRC2INT1_INPUT1);
902CS42L43_DECL_MUX(isrc2int2, CS42L43_ISRC2INT2_INPUT1);
903CS42L43_DECL_MUX(isrc2dec1, CS42L43_ISRC2DEC1_INPUT1);
904CS42L43_DECL_MUX(isrc2dec2, CS42L43_ISRC2DEC2_INPUT1);
905
906CS42L43_DECL_MUX(spdif1, CS42L43_SPDIF1_INPUT1);
907CS42L43_DECL_MUX(spdif2, CS42L43_SPDIF2_INPUT1);
908
909CS42L43_DECL_MIXER(eq1, CS42L43_EQ1MIX_INPUT1);
910CS42L43_DECL_MIXER(eq2, CS42L43_EQ2MIX_INPUT1);
911
912CS42L43_DECL_MIXER(amp1, CS42L43_AMP1MIX_INPUT1);
913CS42L43_DECL_MIXER(amp2, CS42L43_AMP2MIX_INPUT1);
914
915CS42L43_DECL_MIXER(amp3, CS42L43_AMP3MIX_INPUT1);
916CS42L43_DECL_MIXER(amp4, CS42L43_AMP4MIX_INPUT1);
917
918static int cs42l43_dapm_get_volsw(struct snd_kcontrol *kcontrol,
919 struct snd_ctl_elem_value *ucontrol)
920{
921 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
922 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
923 int ret;
924
925 snd_soc_dapm_mutex_lock(dapm);
926 ret = snd_soc_get_volsw(kcontrol, ucontrol);
927 snd_soc_dapm_mutex_unlock(dapm);
928
929 return ret;
930}
931
932static int cs42l43_dapm_put_volsw(struct snd_kcontrol *kcontrol,
933 struct snd_ctl_elem_value *ucontrol)
934{
935 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
936 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
937 int ret;
938
939 snd_soc_dapm_mutex_lock(dapm);
940 ret = snd_soc_put_volsw(kcontrol, ucontrol);
941 snd_soc_dapm_mutex_unlock(dapm);
942
943 return ret;
944}
945
946static int cs42l43_dapm_get_enum(struct snd_kcontrol *kcontrol,
947 struct snd_ctl_elem_value *ucontrol)
948{
949 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
950 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
951 int ret;
952
953 snd_soc_dapm_mutex_lock(dapm);
954 ret = snd_soc_get_enum_double(kcontrol, ucontrol);
955 snd_soc_dapm_mutex_unlock(dapm);
956
957 return ret;
958}
959
960static int cs42l43_dapm_put_enum(struct snd_kcontrol *kcontrol,
961 struct snd_ctl_elem_value *ucontrol)
962{
963 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
964 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
965 int ret;
966
967 snd_soc_dapm_mutex_lock(dapm);
968 ret = snd_soc_put_enum_double(kcontrol, ucontrol);
969 snd_soc_dapm_mutex_unlock(dapm);
970
971 return ret;
972}
973
974static int cs42l43_eq_get(struct snd_kcontrol *kcontrol,
975 struct snd_ctl_elem_value *ucontrol)
976{
977 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
978 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
979
980 memcpy(ucontrol->value.integer.value, priv->eq_coeffs, sizeof(priv->eq_coeffs));
981
982 return 0;
983}
984
985static int cs42l43_eq_put(struct snd_kcontrol *kcontrol,
986 struct snd_ctl_elem_value *ucontrol)
987{
988 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
989 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
990 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
991
992 snd_soc_dapm_mutex_lock(dapm);
993
994 memcpy(priv->eq_coeffs, ucontrol->value.integer.value, sizeof(priv->eq_coeffs));
995
996 snd_soc_dapm_mutex_unlock(dapm);
997
998 return 0;
999}
1000
1001static void cs42l43_spk_vu_sync(struct cs42l43_codec *priv)
1002{
1003 struct cs42l43 *cs42l43 = priv->core;
1004
1005 mutex_lock(&priv->spk_vu_lock);
1006
1007 regmap_update_bits(cs42l43->regmap, CS42L43_INTP_VOLUME_CTRL1,
1008 CS42L43_AMP1_2_VU_MASK, CS42L43_AMP1_2_VU_MASK);
1009 regmap_update_bits(cs42l43->regmap, CS42L43_INTP_VOLUME_CTRL1,
1010 CS42L43_AMP1_2_VU_MASK, 0);
1011
1012 mutex_unlock(&priv->spk_vu_lock);
1013}
1014
1015static int cs42l43_shutter_get(struct cs42l43_codec *priv, unsigned int shift)
1016{
1017 struct cs42l43 *cs42l43 = priv->core;
1018 unsigned int val;
1019 int ret;
1020
1021 ret = pm_runtime_resume_and_get(priv->dev);
1022 if (ret) {
1023 dev_err(priv->dev, "Failed to resume for shutters: %d\n", ret);
1024 return ret;
1025 }
1026
1027 /*
1028 * SHUTTER_CONTROL is a mix of volatile and non-volatile bits, so must
1029 * be cached for the non-volatiles, so drop it from the cache here so
1030 * we force a read.
1031 */
1032 ret = regcache_drop_region(cs42l43->regmap, CS42L43_SHUTTER_CONTROL,
1033 CS42L43_SHUTTER_CONTROL);
1034 if (ret) {
1035 dev_err(priv->dev, "Failed to drop shutter from cache: %d\n", ret);
1036 goto error;
1037 }
1038
1039 ret = regmap_read(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, &val);
1040 if (ret) {
1041 dev_err(priv->dev, "Failed to check shutter status: %d\n", ret);
1042 goto error;
1043 }
1044
1045 ret = !(val & BIT(shift));
1046
1047 dev_dbg(priv->dev, "%s shutter is %s\n",
1048 BIT(shift) == CS42L43_STATUS_MIC_SHUTTER_MUTE_MASK ? "Mic" : "Speaker",
1049 ret ? "open" : "closed");
1050
1051error:
1052 pm_runtime_mark_last_busy(priv->dev);
1053 pm_runtime_put_autosuspend(priv->dev);
1054
1055 return ret;
1056}
1057
1058static int cs42l43_decim_get(struct snd_kcontrol *kcontrol,
1059 struct snd_ctl_elem_value *ucontrol)
1060{
1061 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1062 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1063 int ret;
1064
1065 ret = cs42l43_shutter_get(priv, CS42L43_STATUS_MIC_SHUTTER_MUTE_SHIFT);
1066 if (ret > 0)
1067 ret = cs42l43_dapm_get_volsw(kcontrol, ucontrol);
1068 else if (!ret)
1069 ucontrol->value.integer.value[0] = ret;
1070
1071 return ret;
1072}
1073
1074static int cs42l43_spk_get(struct snd_kcontrol *kcontrol,
1075 struct snd_ctl_elem_value *ucontrol)
1076{
1077 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1078 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1079 int ret;
1080
1081 ret = cs42l43_shutter_get(priv, CS42L43_STATUS_SPK_SHUTTER_MUTE_SHIFT);
1082 if (ret > 0)
1083 ret = snd_soc_get_volsw(kcontrol, ucontrol);
1084 else if (!ret)
1085 ucontrol->value.integer.value[0] = ret;
1086
1087 return ret;
1088}
1089
1090static int cs42l43_spk_put(struct snd_kcontrol *kcontrol,
1091 struct snd_ctl_elem_value *ucontrol)
1092{
1093 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1094 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1095 int ret;
1096
1097 ret = snd_soc_put_volsw(kcontrol, ucontrol);
1098 if (ret > 0)
1099 cs42l43_spk_vu_sync(priv);
1100
1101 return ret;
1102}
1103
1104static const struct snd_kcontrol_new cs42l43_controls[] = {
1105 SOC_ENUM_EXT("Jack Override", cs42l43_jack_enum,
1106 cs42l43_jack_get, cs42l43_jack_put),
1107
1108 SOC_DOUBLE_R_SX_TLV("ADC Volume", CS42L43_ADC_B_CTRL1, CS42L43_ADC_B_CTRL2,
1109 CS42L43_ADC_PGA_GAIN_SHIFT,
1110 0xF, 5, cs42l43_adc_tlv),
1111
1112 SOC_DOUBLE("PDM1 Invert Switch", CS42L43_DMIC_PDM_CTRL,
1113 CS42L43_PDM1L_INV_SHIFT, CS42L43_PDM1R_INV_SHIFT, 1, 0),
1114 SOC_DOUBLE("PDM2 Invert Switch", CS42L43_DMIC_PDM_CTRL,
1115 CS42L43_PDM2L_INV_SHIFT, CS42L43_PDM2R_INV_SHIFT, 1, 0),
1116 SOC_ENUM("PDM1 Clock", cs42l43_pdm1_clk),
1117 SOC_ENUM("PDM2 Clock", cs42l43_pdm2_clk),
1118
1119 SOC_SINGLE("Decimator 1 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL1,
1120 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
1121 SOC_SINGLE("Decimator 2 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL2,
1122 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
1123 SOC_SINGLE("Decimator 3 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL3,
1124 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
1125 SOC_SINGLE("Decimator 4 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL4,
1126 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
1127
1128 SOC_ENUM("Decimator 1 WNF Corner Frequency", cs42l43_dec1_wnf_corner),
1129 SOC_ENUM("Decimator 2 WNF Corner Frequency", cs42l43_dec2_wnf_corner),
1130 SOC_ENUM("Decimator 3 WNF Corner Frequency", cs42l43_dec3_wnf_corner),
1131 SOC_ENUM("Decimator 4 WNF Corner Frequency", cs42l43_dec4_wnf_corner),
1132
1133 SOC_SINGLE("Decimator 1 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL1,
1134 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
1135 SOC_SINGLE("Decimator 2 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL2,
1136 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
1137 SOC_SINGLE("Decimator 3 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL3,
1138 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
1139 SOC_SINGLE("Decimator 4 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL4,
1140 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
1141
1142 SOC_ENUM("Decimator 1 HPF Corner Frequency", cs42l43_dec1_hpf_corner),
1143 SOC_ENUM("Decimator 2 HPF Corner Frequency", cs42l43_dec2_hpf_corner),
1144 SOC_ENUM("Decimator 3 HPF Corner Frequency", cs42l43_dec3_hpf_corner),
1145 SOC_ENUM("Decimator 4 HPF Corner Frequency", cs42l43_dec4_hpf_corner),
1146
1147 SOC_SINGLE_TLV("Decimator 1 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2,
1148 CS42L43_DECIM1_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
1149 SOC_SINGLE_EXT("Decimator 1 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2,
1150 CS42L43_DECIM1_MUTE_SHIFT, 1, 1,
1151 cs42l43_decim_get, cs42l43_dapm_put_volsw),
1152 SOC_SINGLE_TLV("Decimator 2 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2,
1153 CS42L43_DECIM2_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
1154 SOC_SINGLE_EXT("Decimator 2 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2,
1155 CS42L43_DECIM2_MUTE_SHIFT, 1, 1,
1156 cs42l43_decim_get, cs42l43_dapm_put_volsw),
1157 SOC_SINGLE_TLV("Decimator 3 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4,
1158 CS42L43_DECIM3_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
1159 SOC_SINGLE_EXT("Decimator 3 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4,
1160 CS42L43_DECIM3_MUTE_SHIFT, 1, 1,
1161 cs42l43_decim_get, cs42l43_dapm_put_volsw),
1162 SOC_SINGLE_TLV("Decimator 4 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4,
1163 CS42L43_DECIM4_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
1164 SOC_SINGLE_EXT("Decimator 4 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4,
1165 CS42L43_DECIM4_MUTE_SHIFT, 1, 1,
1166 cs42l43_decim_get, cs42l43_dapm_put_volsw),
1167
1168 SOC_ENUM_EXT("Decimator 1 Ramp Up", cs42l43_dec1_ramp_up,
1169 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1170 SOC_ENUM_EXT("Decimator 1 Ramp Down", cs42l43_dec1_ramp_down,
1171 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1172 SOC_ENUM_EXT("Decimator 2 Ramp Up", cs42l43_dec2_ramp_up,
1173 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1174 SOC_ENUM_EXT("Decimator 2 Ramp Down", cs42l43_dec2_ramp_down,
1175 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1176 SOC_ENUM_EXT("Decimator 3 Ramp Up", cs42l43_dec3_ramp_up,
1177 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1178 SOC_ENUM_EXT("Decimator 3 Ramp Down", cs42l43_dec3_ramp_down,
1179 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1180 SOC_ENUM_EXT("Decimator 4 Ramp Up", cs42l43_dec4_ramp_up,
1181 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1182 SOC_ENUM_EXT("Decimator 4 Ramp Down", cs42l43_dec4_ramp_down,
1183 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1184
1185 SOC_DOUBLE_R_EXT("Speaker Digital Switch",
1186 CS42L43_INTP_VOLUME_CTRL1, CS42L43_INTP_VOLUME_CTRL2,
1187 CS42L43_AMP_MUTE_SHIFT, 1, 1,
1188 cs42l43_spk_get, cs42l43_spk_put),
1189
1190 SOC_DOUBLE_R_EXT_TLV("Speaker Digital Volume",
1191 CS42L43_INTP_VOLUME_CTRL1, CS42L43_INTP_VOLUME_CTRL2,
1192 CS42L43_AMP_VOL_SHIFT,
1193 0xBF, 0, snd_soc_get_volsw, cs42l43_spk_put,
1194 cs42l43_speaker_tlv),
1195
1196 SOC_ENUM("Speaker Ramp Up", cs42l43_speaker_ramp_up),
1197 SOC_ENUM("Speaker Ramp Down", cs42l43_speaker_ramp_down),
1198
1199 CS42L43_MIXER_VOLUMES("Speaker L", CS42L43_AMP1MIX_INPUT1),
1200 CS42L43_MIXER_VOLUMES("Speaker R", CS42L43_AMP2MIX_INPUT1),
1201
1202 SOC_DOUBLE_SX_TLV("Headphone Digital Volume", CS42L43_HPPATHVOL,
1203 CS42L43_AMP3_PATH_VOL_SHIFT, CS42L43_AMP4_PATH_VOL_SHIFT,
1204 0x11B, 229, cs42l43_headphone_tlv),
1205
1206 SOC_DOUBLE("Headphone Invert Switch", CS42L43_DACCNFG1,
1207 CS42L43_AMP3_INV_SHIFT, CS42L43_AMP4_INV_SHIFT, 1, 0),
1208
1209 SOC_SINGLE("Headphone Zero Cross Switch", CS42L43_PGAVOL,
1210 CS42L43_HP_PATH_VOL_ZC_SHIFT, 1, 0),
1211 SOC_SINGLE("Headphone Ramp Switch", CS42L43_PGAVOL,
1212 CS42L43_HP_PATH_VOL_SFT_SHIFT, 1, 0),
1213 SOC_ENUM("Headphone Ramp Rate", cs42l43_headphone_ramp),
1214
1215 CS42L43_MIXER_VOLUMES("Headphone L", CS42L43_AMP3MIX_INPUT1),
1216 CS42L43_MIXER_VOLUMES("Headphone R", CS42L43_AMP4MIX_INPUT1),
1217
1218 SOC_ENUM("Tone 1 Frequency", cs42l43_tone1_freq),
1219 SOC_ENUM("Tone 2 Frequency", cs42l43_tone2_freq),
1220
1221 SOC_DOUBLE_EXT("EQ Switch",
1222 CS42L43_MUTE_EQ_IN0, CS42L43_MUTE_EQ_CH1_SHIFT,
1223 CS42L43_MUTE_EQ_CH2_SHIFT, 1, 1,
1224 cs42l43_dapm_get_volsw, cs42l43_dapm_put_volsw),
1225
1226 SND_SOC_BYTES_E("EQ Coefficients", 0, CS42L43_N_EQ_COEFFS,
1227 cs42l43_eq_get, cs42l43_eq_put),
1228
1229 CS42L43_MIXER_VOLUMES("EQ1", CS42L43_EQ1MIX_INPUT1),
1230 CS42L43_MIXER_VOLUMES("EQ2", CS42L43_EQ2MIX_INPUT1),
1231};
1232
1233static int cs42l43_eq_ev(struct snd_soc_dapm_widget *w,
1234 struct snd_kcontrol *kcontrol, int event)
1235{
1236 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1237 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1238 struct cs42l43 *cs42l43 = priv->core;
1239 unsigned int val;
1240 int i, ret;
1241
1242 switch (event) {
1243 case SND_SOC_DAPM_PRE_PMU:
1244 regmap_update_bits(cs42l43->regmap, CS42L43_MUTE_EQ_IN0,
1245 CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK,
1246 CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK);
1247
1248 regmap_update_bits(cs42l43->regmap, CS42L43_COEFF_RD_WR0,
1249 CS42L43_WRITE_MODE_MASK, CS42L43_WRITE_MODE_MASK);
1250
1251 for (i = 0; i < CS42L43_N_EQ_COEFFS; i++)
1252 regmap_write(cs42l43->regmap, CS42L43_COEFF_DATA_IN0,
1253 priv->eq_coeffs[i]);
1254
1255 regmap_update_bits(cs42l43->regmap, CS42L43_COEFF_RD_WR0,
1256 CS42L43_WRITE_MODE_MASK, 0);
1257
1258 return 0;
1259 case SND_SOC_DAPM_POST_PMU:
1260 ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_INIT_DONE0,
1261 val, (val & CS42L43_INITIALIZE_DONE_MASK),
1262 2000, 10000);
1263 if (ret)
1264 dev_err(priv->dev, "Failed to start EQs: %d\n", ret);
1265
1266 regmap_update_bits(cs42l43->regmap, CS42L43_MUTE_EQ_IN0,
1267 CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK, 0);
1268 return ret;
1269 default:
1270 return 0;
1271 }
1272}
1273
1274struct cs42l43_pll_config {
1275 unsigned int freq;
1276
1277 unsigned int div;
1278 unsigned int mode;
1279 unsigned int cal;
1280};
1281
1282static const struct cs42l43_pll_config cs42l43_pll_configs[] = {
1283 { 2400000, 0x50000000, 0x1, 0xA4 },
1284 { 3000000, 0x40000000, 0x1, 0x83 },
1285 { 3072000, 0x40000000, 0x3, 0x80 },
1286};
1287
1288static int cs42l43_set_pll(struct cs42l43_codec *priv, unsigned int src,
1289 unsigned int freq)
1290{
1291 struct cs42l43 *cs42l43 = priv->core;
1292
1293 lockdep_assert_held(&cs42l43->pll_lock);
1294
1295 if (priv->refclk_src == src && priv->refclk_freq == freq)
1296 return 0;
1297
1298 if (regmap_test_bits(cs42l43->regmap, CS42L43_CTRL_REG, CS42L43_PLL_EN_MASK)) {
1299 dev_err(priv->dev, "PLL active, can't change configuration\n");
1300 return -EBUSY;
1301 }
1302
1303 switch (src) {
1304 case CS42L43_SYSCLK_MCLK:
1305 case CS42L43_SYSCLK_SDW:
1306 dev_dbg(priv->dev, "Source PLL from %s at %uHz\n",
1307 src ? "SoundWire" : "MCLK", freq);
1308
1309 priv->refclk_src = src;
1310 priv->refclk_freq = freq;
1311
1312 return 0;
1313 default:
1314 dev_err(priv->dev, "Invalid PLL source: 0x%x\n", src);
1315 return -EINVAL;
1316 }
1317}
1318
1319static int cs42l43_enable_pll(struct cs42l43_codec *priv)
1320{
1321 static const struct reg_sequence enable_seq[] = {
1322 { CS42L43_OSC_DIV_SEL, 0x0, },
1323 { CS42L43_MCLK_SRC_SEL, CS42L43_OSC_PLL_MCLK_SEL_MASK, 5, },
1324 };
1325 struct cs42l43 *cs42l43 = priv->core;
1326 const struct cs42l43_pll_config *config = NULL;
1327 unsigned int div = 0;
1328 unsigned int freq = priv->refclk_freq;
1329 unsigned long time_left;
1330
1331 lockdep_assert_held(&cs42l43->pll_lock);
1332
1333 if (priv->refclk_src == CS42L43_SYSCLK_SDW) {
1334 if (!freq)
1335 freq = cs42l43->sdw_freq;
1336 else if (!cs42l43->sdw_freq)
1337 cs42l43->sdw_freq = freq;
1338 }
1339
1340 dev_dbg(priv->dev, "Enabling PLL at %uHz\n", freq);
1341
1342 div = fls(freq) -
1343 fls(cs42l43_pll_configs[ARRAY_SIZE(cs42l43_pll_configs) - 1].freq);
1344 freq >>= div;
1345
1346 if (div <= CS42L43_PLL_REFCLK_DIV_MASK) {
1347 int i;
1348
1349 for (i = 0; i < ARRAY_SIZE(cs42l43_pll_configs); i++) {
1350 if (freq == cs42l43_pll_configs[i].freq) {
1351 config = &cs42l43_pll_configs[i];
1352 break;
1353 }
1354 }
1355 }
1356
1357 if (!config) {
1358 dev_err(priv->dev, "No suitable PLL config: 0x%x, %uHz\n", div, freq);
1359 return -EINVAL;
1360 }
1361
1362 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
1363 CS42L43_PLL_REFCLK_DIV_MASK | CS42L43_PLL_REFCLK_SRC_MASK,
1364 div << CS42L43_PLL_REFCLK_DIV_SHIFT |
1365 priv->refclk_src << CS42L43_PLL_REFCLK_SRC_SHIFT);
1366 regmap_write(cs42l43->regmap, CS42L43_FDIV_FRAC, config->div);
1367 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG,
1368 CS42L43_PLL_MODE_BYPASS_500_MASK |
1369 CS42L43_PLL_MODE_BYPASS_1029_MASK,
1370 config->mode << CS42L43_PLL_MODE_BYPASS_1029_SHIFT);
1371 regmap_update_bits(cs42l43->regmap, CS42L43_CAL_RATIO,
1372 CS42L43_PLL_CAL_RATIO_MASK, config->cal);
1373 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
1374 CS42L43_PLL_REFCLK_EN_MASK, CS42L43_PLL_REFCLK_EN_MASK);
1375
1376 reinit_completion(&priv->pll_ready);
1377
1378 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG,
1379 CS42L43_PLL_EN_MASK, CS42L43_PLL_EN_MASK);
1380
1381 time_left = wait_for_completion_timeout(&priv->pll_ready,
1382 msecs_to_jiffies(CS42L43_PLL_TIMEOUT_MS));
1383 if (!time_left) {
1384 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG,
1385 CS42L43_PLL_EN_MASK, 0);
1386 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
1387 CS42L43_PLL_REFCLK_EN_MASK, 0);
1388
1389 dev_err(priv->dev, "Timeout out waiting for PLL\n");
1390 return -ETIMEDOUT;
1391 }
1392
1393 if (priv->refclk_src == CS42L43_SYSCLK_SDW)
1394 cs42l43->sdw_pll_active = true;
1395
1396 dev_dbg(priv->dev, "PLL locked in %ums\n", 200 - jiffies_to_msecs(time_left));
1397
1398 /*
1399 * Reads are not allowed over Soundwire without OSC_DIV2_EN or the PLL,
1400 * but you can not change to PLL with OSC_DIV2_EN set. So ensure the whole
1401 * change over happens under the regmap lock to prevent any reads.
1402 */
1403 regmap_multi_reg_write(cs42l43->regmap, enable_seq, ARRAY_SIZE(enable_seq));
1404
1405 return 0;
1406}
1407
1408static int cs42l43_disable_pll(struct cs42l43_codec *priv)
1409{
1410 static const struct reg_sequence disable_seq[] = {
1411 { CS42L43_MCLK_SRC_SEL, 0x0, 5, },
1412 { CS42L43_OSC_DIV_SEL, CS42L43_OSC_DIV2_EN_MASK, },
1413 };
1414 struct cs42l43 *cs42l43 = priv->core;
1415
1416 dev_dbg(priv->dev, "Disabling PLL\n");
1417
1418 lockdep_assert_held(&cs42l43->pll_lock);
1419
1420 regmap_multi_reg_write(cs42l43->regmap, disable_seq, ARRAY_SIZE(disable_seq));
1421 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG, CS42L43_PLL_EN_MASK, 0);
1422 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
1423 CS42L43_PLL_REFCLK_EN_MASK, 0);
1424
1425 cs42l43->sdw_pll_active = false;
1426
1427 return 0;
1428}
1429
1430static int cs42l43_pll_ev(struct snd_soc_dapm_widget *w,
1431 struct snd_kcontrol *kcontrol, int event)
1432{
1433 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1434 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1435 struct cs42l43 *cs42l43 = priv->core;
1436 int ret;
1437
1438 mutex_lock(&cs42l43->pll_lock);
1439
1440 switch (event) {
1441 case SND_SOC_DAPM_PRE_PMU:
1442 if (priv->refclk_src == CS42L43_SYSCLK_MCLK) {
1443 ret = clk_prepare_enable(priv->mclk);
1444 if (ret) {
1445 dev_err(priv->dev, "Failed to enable MCLK: %d\n", ret);
1446 break;
1447 }
1448 }
1449
1450 ret = cs42l43_enable_pll(priv);
1451 break;
1452 case SND_SOC_DAPM_POST_PMD:
1453 ret = cs42l43_disable_pll(priv);
1454
1455 if (priv->refclk_src == CS42L43_SYSCLK_MCLK)
1456 clk_disable_unprepare(priv->mclk);
1457 break;
1458 default:
1459 ret = 0;
1460 break;
1461 }
1462
1463 mutex_unlock(&cs42l43->pll_lock);
1464
1465 return ret;
1466}
1467
1468static int cs42l43_dapm_wait_completion(struct completion *pmu, struct completion *pmd,
1469 int event, int timeout_ms)
1470{
1471 unsigned long time_left;
1472
1473 switch (event) {
1474 case SND_SOC_DAPM_PRE_PMU:
1475 reinit_completion(pmu);
1476 return 0;
1477 case SND_SOC_DAPM_PRE_PMD:
1478 reinit_completion(pmd);
1479 return 0;
1480 case SND_SOC_DAPM_POST_PMU:
1481 time_left = wait_for_completion_timeout(pmu, msecs_to_jiffies(timeout_ms));
1482 break;
1483 case SND_SOC_DAPM_POST_PMD:
1484 time_left = wait_for_completion_timeout(pmd, msecs_to_jiffies(timeout_ms));
1485 break;
1486 default:
1487 return 0;
1488 }
1489
1490 if (!time_left)
1491 return -ETIMEDOUT;
1492 else
1493 return 0;
1494}
1495
1496static int cs42l43_spkr_ev(struct snd_soc_dapm_widget *w,
1497 struct snd_kcontrol *kcontrol, int event)
1498{
1499 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1500 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1501
1502 return cs42l43_dapm_wait_completion(&priv->spkr_startup,
1503 &priv->spkr_shutdown, event,
1504 CS42L43_SPK_TIMEOUT_MS);
1505}
1506
1507static int cs42l43_spkl_ev(struct snd_soc_dapm_widget *w,
1508 struct snd_kcontrol *kcontrol, int event)
1509{
1510 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1511 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1512
1513 return cs42l43_dapm_wait_completion(&priv->spkl_startup,
1514 &priv->spkl_shutdown, event,
1515 CS42L43_SPK_TIMEOUT_MS);
1516}
1517
1518static int cs42l43_hp_ev(struct snd_soc_dapm_widget *w,
1519 struct snd_kcontrol *kcontrol, int event)
1520{
1521 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1522 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1523 struct cs42l43 *cs42l43 = priv->core;
1524 unsigned int mask = 1 << w->shift;
1525 unsigned int val = 0;
1526 int ret;
1527
1528 switch (event) {
1529 case SND_SOC_DAPM_PRE_PMU:
1530 val = mask;
1531 fallthrough;
1532 case SND_SOC_DAPM_PRE_PMD:
1533 priv->hp_ena &= ~mask;
1534 priv->hp_ena |= val;
1535
1536 ret = cs42l43_dapm_wait_completion(&priv->hp_startup,
1537 &priv->hp_shutdown, event,
1538 CS42L43_HP_TIMEOUT_MS);
1539 if (ret)
1540 return ret;
1541
1542 if (!priv->load_detect_running && !priv->hp_ilimited)
1543 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8,
1544 mask, val);
1545 break;
1546 case SND_SOC_DAPM_POST_PMU:
1547 case SND_SOC_DAPM_POST_PMD:
1548 if (priv->load_detect_running || priv->hp_ilimited)
1549 break;
1550
1551 ret = cs42l43_dapm_wait_completion(&priv->hp_startup,
1552 &priv->hp_shutdown, event,
1553 CS42L43_HP_TIMEOUT_MS);
1554 if (ret)
1555 return ret;
1556 break;
1557 default:
1558 break;
1559 }
1560
1561 return 0;
1562}
1563
1564static int cs42l43_mic_ev(struct snd_soc_dapm_widget *w,
1565 struct snd_kcontrol *kcontrol, int event)
1566{
1567 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1568 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1569 struct cs42l43 *cs42l43 = priv->core;
1570 unsigned int reg, ramp, mute;
1571 unsigned int *val;
1572 int ret;
1573
1574 switch (w->shift) {
1575 case CS42L43_ADC1_EN_SHIFT:
1576 case CS42L43_PDM1_DIN_L_EN_SHIFT:
1577 reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2;
1578 ramp = CS42L43_DECIM1_VD_RAMP_MASK;
1579 mute = CS42L43_DECIM1_MUTE_MASK;
1580 val = &priv->decim_cache[0];
1581 break;
1582 case CS42L43_ADC2_EN_SHIFT:
1583 case CS42L43_PDM1_DIN_R_EN_SHIFT:
1584 reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2;
1585 ramp = CS42L43_DECIM2_VD_RAMP_MASK;
1586 mute = CS42L43_DECIM2_MUTE_MASK;
1587 val = &priv->decim_cache[1];
1588 break;
1589 case CS42L43_PDM2_DIN_L_EN_SHIFT:
1590 reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4;
1591 ramp = CS42L43_DECIM3_VD_RAMP_MASK;
1592 mute = CS42L43_DECIM3_MUTE_MASK;
1593 val = &priv->decim_cache[2];
1594 break;
1595 case CS42L43_PDM2_DIN_R_EN_SHIFT:
1596 reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4;
1597 ramp = CS42L43_DECIM4_VD_RAMP_MASK;
1598 mute = CS42L43_DECIM4_MUTE_MASK;
1599 val = &priv->decim_cache[3];
1600 break;
1601 default:
1602 dev_err(priv->dev, "Invalid microphone shift: %d\n", w->shift);
1603 return -EINVAL;
1604 }
1605
1606 switch (event) {
1607 case SND_SOC_DAPM_PRE_PMU:
1608 ret = regmap_read(cs42l43->regmap, reg, val);
1609 if (ret) {
1610 dev_err(priv->dev,
1611 "Failed to cache decimator settings: %d\n",
1612 ret);
1613 return ret;
1614 }
1615
1616 regmap_update_bits(cs42l43->regmap, reg, mute | ramp, mute);
1617 break;
1618 case SND_SOC_DAPM_POST_PMU:
1619 regmap_update_bits(cs42l43->regmap, reg, mute | ramp, *val);
1620 break;
1621 default:
1622 break;
1623 }
1624
1625 return 0;
1626}
1627
1628static int cs42l43_adc_ev(struct snd_soc_dapm_widget *w,
1629 struct snd_kcontrol *kcontrol, int event)
1630{
1631 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1632 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1633 struct cs42l43 *cs42l43 = priv->core;
1634 unsigned int mask = 1 << w->shift;
1635 unsigned int val = 0;
1636 int ret;
1637
1638 ret = cs42l43_mic_ev(w, kcontrol, event);
1639 if (ret)
1640 return ret;
1641
1642 switch (event) {
1643 case SND_SOC_DAPM_PRE_PMU:
1644 val = mask;
1645 fallthrough;
1646 case SND_SOC_DAPM_PRE_PMD:
1647 priv->adc_ena &= ~mask;
1648 priv->adc_ena |= val;
1649
1650 if (!priv->load_detect_running)
1651 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN3,
1652 mask, val);
1653 fallthrough;
1654 default:
1655 return 0;
1656 }
1657}
1658
1659static const struct snd_soc_dapm_widget cs42l43_widgets[] = {
1660 SND_SOC_DAPM_SUPPLY("PLL", SND_SOC_NOPM, 0, 0, cs42l43_pll_ev,
1661 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1662
1663 SND_SOC_DAPM_INPUT("ADC1_IN1_P"),
1664 SND_SOC_DAPM_INPUT("ADC1_IN1_N"),
1665 SND_SOC_DAPM_INPUT("ADC1_IN2_P"),
1666 SND_SOC_DAPM_INPUT("ADC1_IN2_N"),
1667 SND_SOC_DAPM_INPUT("ADC2_IN_P"),
1668 SND_SOC_DAPM_INPUT("ADC2_IN_N"),
1669
1670 SND_SOC_DAPM_INPUT("PDM1_DIN"),
1671 SND_SOC_DAPM_INPUT("PDM2_DIN"),
1672
1673 SND_SOC_DAPM_MUX("ADC1 Input", SND_SOC_NOPM, 0, 0, &cs42l43_adc1_input_ctl),
1674
1675 SND_SOC_DAPM_PGA_E("ADC1", SND_SOC_NOPM, CS42L43_ADC1_EN_SHIFT, 0, NULL, 0,
1676 cs42l43_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1677 SND_SOC_DAPM_PRE_PMD),
1678 SND_SOC_DAPM_PGA_E("ADC2", SND_SOC_NOPM, CS42L43_ADC2_EN_SHIFT, 0, NULL, 0,
1679 cs42l43_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1680 SND_SOC_DAPM_PRE_PMD),
1681
1682 SND_SOC_DAPM_PGA_E("PDM1L", CS42L43_BLOCK_EN3, CS42L43_PDM1_DIN_L_EN_SHIFT,
1683 0, NULL, 0, cs42l43_mic_ev,
1684 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1685 SND_SOC_DAPM_PGA_E("PDM1R", CS42L43_BLOCK_EN3, CS42L43_PDM1_DIN_R_EN_SHIFT,
1686 0, NULL, 0, cs42l43_mic_ev,
1687 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1688 SND_SOC_DAPM_PGA_E("PDM2L", CS42L43_BLOCK_EN3, CS42L43_PDM2_DIN_L_EN_SHIFT,
1689 0, NULL, 0, cs42l43_mic_ev,
1690 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1691 SND_SOC_DAPM_PGA_E("PDM2R", CS42L43_BLOCK_EN3, CS42L43_PDM2_DIN_R_EN_SHIFT,
1692 0, NULL, 0, cs42l43_mic_ev,
1693 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1694
1695 SND_SOC_DAPM_MUX("Decimator 1 Mode", SND_SOC_NOPM, 0, 0,
1696 &cs42l43_dec_mode_ctl[0]),
1697 SND_SOC_DAPM_MUX("Decimator 2 Mode", SND_SOC_NOPM, 0, 0,
1698 &cs42l43_dec_mode_ctl[1]),
1699
1700 SND_SOC_DAPM_PGA("Decimator 1", SND_SOC_NOPM, 0, 0, NULL, 0),
1701 SND_SOC_DAPM_PGA("Decimator 2", SND_SOC_NOPM, 0, 0, NULL, 0),
1702 SND_SOC_DAPM_PGA("Decimator 3", SND_SOC_NOPM, 0, 0, NULL, 0),
1703 SND_SOC_DAPM_PGA("Decimator 4", SND_SOC_NOPM, 0, 0, NULL, 0),
1704
1705 SND_SOC_DAPM_SUPPLY_S("FSYNC", 0, CS42L43_ASP_CTRL, CS42L43_ASP_FSYNC_EN_SHIFT,
1706 0, NULL, 0),
1707 SND_SOC_DAPM_SUPPLY_S("BCLK", 1, CS42L43_ASP_CTRL, CS42L43_ASP_BCLK_EN_SHIFT,
1708 0, NULL, 0),
1709
1710 SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0,
1711 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH1_EN_SHIFT, 0),
1712 SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 1,
1713 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH2_EN_SHIFT, 0),
1714 SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 2,
1715 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH3_EN_SHIFT, 0),
1716 SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 3,
1717 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH4_EN_SHIFT, 0),
1718 SND_SOC_DAPM_AIF_OUT("ASPTX5", NULL, 4,
1719 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH5_EN_SHIFT, 0),
1720 SND_SOC_DAPM_AIF_OUT("ASPTX6", NULL, 5,
1721 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH6_EN_SHIFT, 0),
1722
1723 SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0,
1724 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH1_EN_SHIFT, 0),
1725 SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 1,
1726 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH2_EN_SHIFT, 0),
1727 SND_SOC_DAPM_AIF_IN("ASPRX3", NULL, 2,
1728 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH3_EN_SHIFT, 0),
1729 SND_SOC_DAPM_AIF_IN("ASPRX4", NULL, 3,
1730 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH4_EN_SHIFT, 0),
1731 SND_SOC_DAPM_AIF_IN("ASPRX5", NULL, 4,
1732 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH5_EN_SHIFT, 0),
1733 SND_SOC_DAPM_AIF_IN("ASPRX6", NULL, 5,
1734 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH6_EN_SHIFT, 0),
1735
1736 SND_SOC_DAPM_AIF_OUT("DP1TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1737 SND_SOC_DAPM_AIF_OUT("DP1TX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1738 SND_SOC_DAPM_AIF_OUT("DP1TX3", NULL, 2, SND_SOC_NOPM, 0, 0),
1739 SND_SOC_DAPM_AIF_OUT("DP1TX4", NULL, 3, SND_SOC_NOPM, 0, 0),
1740
1741 SND_SOC_DAPM_AIF_OUT("DP2TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1742 SND_SOC_DAPM_AIF_OUT("DP2TX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1743
1744 SND_SOC_DAPM_AIF_OUT("DP3TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1745 SND_SOC_DAPM_AIF_OUT("DP3TX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1746
1747 SND_SOC_DAPM_AIF_OUT("DP4TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1748 SND_SOC_DAPM_AIF_OUT("DP4TX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1749
1750 SND_SOC_DAPM_AIF_IN("DP5RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1751 SND_SOC_DAPM_AIF_IN("DP5RX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1752
1753 SND_SOC_DAPM_AIF_IN("DP6RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1754 SND_SOC_DAPM_AIF_IN("DP6RX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1755
1756 SND_SOC_DAPM_AIF_IN("DP7RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1757 SND_SOC_DAPM_AIF_IN("DP7RX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1758
1759 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-amp", 0, 0),
1760
1761 SND_SOC_DAPM_PGA_E("AMP1", CS42L43_BLOCK_EN10, CS42L43_AMP1_EN_SHIFT, 0, NULL, 0,
1762 cs42l43_spkl_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1763 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1764 SND_SOC_DAPM_PGA_E("AMP2", CS42L43_BLOCK_EN10, CS42L43_AMP2_EN_SHIFT, 0, NULL, 0,
1765 cs42l43_spkr_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1766 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1767
1768 SND_SOC_DAPM_OUTPUT("AMP1_OUT_P"),
1769 SND_SOC_DAPM_OUTPUT("AMP1_OUT_N"),
1770 SND_SOC_DAPM_OUTPUT("AMP2_OUT_P"),
1771 SND_SOC_DAPM_OUTPUT("AMP2_OUT_N"),
1772
1773 SND_SOC_DAPM_PGA("SPDIF", CS42L43_BLOCK_EN11, CS42L43_SPDIF_EN_SHIFT,
1774 0, NULL, 0),
1775 SND_SOC_DAPM_OUTPUT("SPDIF_TX"),
1776
1777 SND_SOC_DAPM_PGA_E("HP", SND_SOC_NOPM, CS42L43_HP_EN_SHIFT, 0, NULL, 0,
1778 cs42l43_hp_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1779 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1780 SND_SOC_DAPM_OUTPUT("AMP3_OUT"),
1781 SND_SOC_DAPM_OUTPUT("AMP4_OUT"),
1782
1783 SND_SOC_DAPM_SIGGEN("Tone"),
1784 SND_SOC_DAPM_SUPPLY("Tone Generator", CS42L43_BLOCK_EN9, CS42L43_TONE_EN_SHIFT,
1785 0, NULL, 0),
1786 SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Tone 1", CS42L43_TONE_CH1_CTRL,
1787 CS42L43_TONE_SEL_SHIFT, CS42L43_TONE_SEL_MASK, 0xA, 0),
1788 SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Tone 2", CS42L43_TONE_CH2_CTRL,
1789 CS42L43_TONE_SEL_SHIFT, CS42L43_TONE_SEL_MASK, 0xA, 0),
1790
1791 SND_SOC_DAPM_SUPPLY("ISRC1", CS42L43_BLOCK_EN5, CS42L43_ISRC1_BANK_EN_SHIFT,
1792 0, NULL, 0),
1793 SND_SOC_DAPM_SUPPLY("ISRC2", CS42L43_BLOCK_EN5, CS42L43_ISRC2_BANK_EN_SHIFT,
1794 0, NULL, 0),
1795
1796 SND_SOC_DAPM_PGA("ISRC1INT2", CS42L43_ISRC1_CTRL,
1797 CS42L43_ISRC_INT2_EN_SHIFT, 0, NULL, 0),
1798 SND_SOC_DAPM_PGA("ISRC1INT1", CS42L43_ISRC1_CTRL,
1799 CS42L43_ISRC_INT1_EN_SHIFT, 0, NULL, 0),
1800 SND_SOC_DAPM_PGA("ISRC1DEC2", CS42L43_ISRC1_CTRL,
1801 CS42L43_ISRC_DEC2_EN_SHIFT, 0, NULL, 0),
1802 SND_SOC_DAPM_PGA("ISRC1DEC1", CS42L43_ISRC1_CTRL,
1803 CS42L43_ISRC_DEC1_EN_SHIFT, 0, NULL, 0),
1804
1805 SND_SOC_DAPM_PGA("ISRC2INT2", CS42L43_ISRC2_CTRL,
1806 CS42L43_ISRC_INT2_EN_SHIFT, 0, NULL, 0),
1807 SND_SOC_DAPM_PGA("ISRC2INT1", CS42L43_ISRC2_CTRL,
1808 CS42L43_ISRC_INT1_EN_SHIFT, 0, NULL, 0),
1809 SND_SOC_DAPM_PGA("ISRC2DEC2", CS42L43_ISRC2_CTRL,
1810 CS42L43_ISRC_DEC2_EN_SHIFT, 0, NULL, 0),
1811 SND_SOC_DAPM_PGA("ISRC2DEC1", CS42L43_ISRC2_CTRL,
1812 CS42L43_ISRC_DEC1_EN_SHIFT, 0, NULL, 0),
1813
1814 SND_SOC_DAPM_SUPPLY("ASRC_INT", CS42L43_BLOCK_EN4,
1815 CS42L43_ASRC_INT_BANK_EN_SHIFT, 0, NULL, 0),
1816 SND_SOC_DAPM_SUPPLY("ASRC_DEC", CS42L43_BLOCK_EN4,
1817 CS42L43_ASRC_DEC_BANK_EN_SHIFT, 0, NULL, 0),
1818
1819 SND_SOC_DAPM_PGA("ASRC_INT1", CS42L43_ASRC_INT_ENABLES,
1820 CS42L43_ASRC_INT1_EN_SHIFT, 0, NULL, 0),
1821 SND_SOC_DAPM_PGA("ASRC_INT2", CS42L43_ASRC_INT_ENABLES,
1822 CS42L43_ASRC_INT2_EN_SHIFT, 0, NULL, 0),
1823 SND_SOC_DAPM_PGA("ASRC_INT3", CS42L43_ASRC_INT_ENABLES,
1824 CS42L43_ASRC_INT3_EN_SHIFT, 0, NULL, 0),
1825 SND_SOC_DAPM_PGA("ASRC_INT4", CS42L43_ASRC_INT_ENABLES,
1826 CS42L43_ASRC_INT4_EN_SHIFT, 0, NULL, 0),
1827 SND_SOC_DAPM_PGA("ASRC_DEC1", CS42L43_ASRC_DEC_ENABLES,
1828 CS42L43_ASRC_DEC1_EN_SHIFT, 0, NULL, 0),
1829 SND_SOC_DAPM_PGA("ASRC_DEC2", CS42L43_ASRC_DEC_ENABLES,
1830 CS42L43_ASRC_DEC2_EN_SHIFT, 0, NULL, 0),
1831 SND_SOC_DAPM_PGA("ASRC_DEC3", CS42L43_ASRC_DEC_ENABLES,
1832 CS42L43_ASRC_DEC3_EN_SHIFT, 0, NULL, 0),
1833 SND_SOC_DAPM_PGA("ASRC_DEC4", CS42L43_ASRC_DEC_ENABLES,
1834 CS42L43_ASRC_DEC4_EN_SHIFT, 0, NULL, 0),
1835
1836 SND_SOC_DAPM_SUPPLY("EQ Clock", CS42L43_BLOCK_EN7, CS42L43_EQ_EN_SHIFT,
1837 0, NULL, 0),
1838 SND_SOC_DAPM_PGA_E("EQ", CS42L43_START_EQZ0, CS42L43_START_FILTER_SHIFT,
1839 0, NULL, 0, cs42l43_eq_ev,
1840 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1841
1842 SND_SOC_DAPM_SUPPLY("Mixer Core", CS42L43_BLOCK_EN6, CS42L43_MIXER_EN_SHIFT,
1843 0, NULL, 0),
1844 CS42L43_DAPM_MUX("ASPTX1", asptx1),
1845 CS42L43_DAPM_MUX("ASPTX2", asptx2),
1846 CS42L43_DAPM_MUX("ASPTX3", asptx3),
1847 CS42L43_DAPM_MUX("ASPTX4", asptx4),
1848 CS42L43_DAPM_MUX("ASPTX5", asptx5),
1849 CS42L43_DAPM_MUX("ASPTX6", asptx6),
1850
1851 CS42L43_DAPM_MUX("DP1TX1", dp1tx1),
1852 CS42L43_DAPM_MUX("DP1TX2", dp1tx2),
1853 CS42L43_DAPM_MUX("DP1TX3", dp1tx3),
1854 CS42L43_DAPM_MUX("DP1TX4", dp1tx4),
1855 CS42L43_DAPM_MUX("DP2TX1", dp2tx1),
1856 CS42L43_DAPM_MUX("DP2TX2", dp2tx2),
1857 CS42L43_DAPM_MUX("DP3TX1", dp3tx1),
1858 CS42L43_DAPM_MUX("DP3TX2", dp3tx2),
1859 CS42L43_DAPM_MUX("DP4TX1", dp4tx1),
1860 CS42L43_DAPM_MUX("DP4TX2", dp4tx2),
1861
1862 CS42L43_DAPM_MUX("ASRC INT1", asrcint1),
1863 CS42L43_DAPM_MUX("ASRC INT2", asrcint2),
1864 CS42L43_DAPM_MUX("ASRC INT3", asrcint3),
1865 CS42L43_DAPM_MUX("ASRC INT4", asrcint4),
1866 CS42L43_DAPM_MUX("ASRC DEC1", asrcdec1),
1867 CS42L43_DAPM_MUX("ASRC DEC2", asrcdec2),
1868 CS42L43_DAPM_MUX("ASRC DEC3", asrcdec3),
1869 CS42L43_DAPM_MUX("ASRC DEC4", asrcdec4),
1870
1871 CS42L43_DAPM_MUX("ISRC1INT1", isrc1int1),
1872 CS42L43_DAPM_MUX("ISRC1INT2", isrc1int2),
1873 CS42L43_DAPM_MUX("ISRC1DEC1", isrc1dec1),
1874 CS42L43_DAPM_MUX("ISRC1DEC2", isrc1dec2),
1875 CS42L43_DAPM_MUX("ISRC2INT1", isrc2int1),
1876 CS42L43_DAPM_MUX("ISRC2INT2", isrc2int2),
1877 CS42L43_DAPM_MUX("ISRC2DEC1", isrc2dec1),
1878 CS42L43_DAPM_MUX("ISRC2DEC2", isrc2dec2),
1879
1880 CS42L43_DAPM_MUX("SPDIF1", spdif1),
1881 CS42L43_DAPM_MUX("SPDIF2", spdif2),
1882
1883 CS42L43_DAPM_MIXER("EQ1", eq1),
1884 CS42L43_DAPM_MIXER("EQ2", eq2),
1885
1886 CS42L43_DAPM_MIXER("Speaker L", amp1),
1887 CS42L43_DAPM_MIXER("Speaker R", amp2),
1888
1889 CS42L43_DAPM_MIXER("Headphone L", amp3),
1890 CS42L43_DAPM_MIXER("Headphone R", amp4),
1891};
1892
1893static const struct snd_soc_dapm_route cs42l43_routes[] = {
1894 { "ADC1_IN1_P", NULL, "PLL" },
1895 { "ADC1_IN1_N", NULL, "PLL" },
1896 { "ADC1_IN2_P", NULL, "PLL" },
1897 { "ADC1_IN2_N", NULL, "PLL" },
1898 { "ADC2_IN_P", NULL, "PLL" },
1899 { "ADC2_IN_N", NULL, "PLL" },
1900 { "PDM1_DIN", NULL, "PLL" },
1901 { "PDM2_DIN", NULL, "PLL" },
1902 { "AMP1_OUT_P", NULL, "PLL" },
1903 { "AMP1_OUT_N", NULL, "PLL" },
1904 { "AMP2_OUT_P", NULL, "PLL" },
1905 { "AMP2_OUT_N", NULL, "PLL" },
1906 { "SPDIF_TX", NULL, "PLL" },
1907 { "HP", NULL, "PLL" },
1908 { "AMP3_OUT", NULL, "PLL" },
1909 { "AMP4_OUT", NULL, "PLL" },
1910 { "Tone 1", NULL, "PLL" },
1911 { "Tone 2", NULL, "PLL" },
1912 { "ASP Playback", NULL, "PLL" },
1913 { "ASP Capture", NULL, "PLL" },
1914 { "DP1 Capture", NULL, "PLL" },
1915 { "DP2 Capture", NULL, "PLL" },
1916 { "DP3 Capture", NULL, "PLL" },
1917 { "DP4 Capture", NULL, "PLL" },
1918 { "DP5 Playback", NULL, "PLL" },
1919 { "DP6 Playback", NULL, "PLL" },
1920 { "DP7 Playback", NULL, "PLL" },
1921
1922 { "ADC1 Input", "IN1", "ADC1_IN1_P" },
1923 { "ADC1 Input", "IN1", "ADC1_IN1_N" },
1924 { "ADC1 Input", "IN2", "ADC1_IN2_P" },
1925 { "ADC1 Input", "IN2", "ADC1_IN2_N" },
1926
1927 { "ADC1", NULL, "ADC1 Input" },
1928 { "ADC2", NULL, "ADC2_IN_P" },
1929 { "ADC2", NULL, "ADC2_IN_N" },
1930
1931 { "PDM1L", NULL, "PDM1_DIN" },
1932 { "PDM1R", NULL, "PDM1_DIN" },
1933 { "PDM2L", NULL, "PDM2_DIN" },
1934 { "PDM2R", NULL, "PDM2_DIN" },
1935
1936 { "Decimator 1 Mode", "PDM", "PDM1L" },
1937 { "Decimator 1 Mode", "ADC", "ADC1" },
1938 { "Decimator 2 Mode", "PDM", "PDM1R" },
1939 { "Decimator 2 Mode", "ADC", "ADC2" },
1940
1941 { "Decimator 1", NULL, "Decimator 1 Mode" },
1942 { "Decimator 2", NULL, "Decimator 2 Mode" },
1943 { "Decimator 3", NULL, "PDM2L" },
1944 { "Decimator 4", NULL, "PDM2R" },
1945
1946 { "ASP Capture", NULL, "ASPTX1" },
1947 { "ASP Capture", NULL, "ASPTX2" },
1948 { "ASP Capture", NULL, "ASPTX3" },
1949 { "ASP Capture", NULL, "ASPTX4" },
1950 { "ASP Capture", NULL, "ASPTX5" },
1951 { "ASP Capture", NULL, "ASPTX6" },
1952 { "ASPTX1", NULL, "BCLK" },
1953 { "ASPTX2", NULL, "BCLK" },
1954 { "ASPTX3", NULL, "BCLK" },
1955 { "ASPTX4", NULL, "BCLK" },
1956 { "ASPTX5", NULL, "BCLK" },
1957 { "ASPTX6", NULL, "BCLK" },
1958
1959 { "ASPRX1", NULL, "ASP Playback" },
1960 { "ASPRX2", NULL, "ASP Playback" },
1961 { "ASPRX3", NULL, "ASP Playback" },
1962 { "ASPRX4", NULL, "ASP Playback" },
1963 { "ASPRX5", NULL, "ASP Playback" },
1964 { "ASPRX6", NULL, "ASP Playback" },
1965 { "ASPRX1", NULL, "BCLK" },
1966 { "ASPRX2", NULL, "BCLK" },
1967 { "ASPRX3", NULL, "BCLK" },
1968 { "ASPRX4", NULL, "BCLK" },
1969 { "ASPRX5", NULL, "BCLK" },
1970 { "ASPRX6", NULL, "BCLK" },
1971
1972 { "DP1 Capture", NULL, "DP1TX1" },
1973 { "DP1 Capture", NULL, "DP1TX2" },
1974 { "DP1 Capture", NULL, "DP1TX3" },
1975 { "DP1 Capture", NULL, "DP1TX4" },
1976
1977 { "DP2 Capture", NULL, "DP2TX1" },
1978 { "DP2 Capture", NULL, "DP2TX2" },
1979
1980 { "DP3 Capture", NULL, "DP3TX1" },
1981 { "DP3 Capture", NULL, "DP3TX2" },
1982
1983 { "DP4 Capture", NULL, "DP4TX1" },
1984 { "DP4 Capture", NULL, "DP4TX2" },
1985
1986 { "DP5RX1", NULL, "DP5 Playback" },
1987 { "DP5RX2", NULL, "DP5 Playback" },
1988
1989 { "DP6RX1", NULL, "DP6 Playback" },
1990 { "DP6RX2", NULL, "DP6 Playback" },
1991
1992 { "DP7RX1", NULL, "DP7 Playback" },
1993 { "DP7RX2", NULL, "DP7 Playback" },
1994
1995 { "AMP1", NULL, "vdd-amp" },
1996 { "AMP2", NULL, "vdd-amp" },
1997
1998 { "AMP1_OUT_P", NULL, "AMP1" },
1999 { "AMP1_OUT_N", NULL, "AMP1" },
2000 { "AMP2_OUT_P", NULL, "AMP2" },
2001 { "AMP2_OUT_N", NULL, "AMP2" },
2002
2003 { "SPDIF_TX", NULL, "SPDIF" },
2004
2005 { "AMP3_OUT", NULL, "HP" },
2006 { "AMP4_OUT", NULL, "HP" },
2007
2008 { "Tone 1", NULL, "Tone" },
2009 { "Tone 1", NULL, "Tone Generator" },
2010 { "Tone 2", NULL, "Tone" },
2011 { "Tone 2", NULL, "Tone Generator" },
2012
2013 { "ISRC1INT2", NULL, "ISRC1" },
2014 { "ISRC1INT1", NULL, "ISRC1" },
2015 { "ISRC1DEC2", NULL, "ISRC1" },
2016 { "ISRC1DEC1", NULL, "ISRC1" },
2017
2018 { "ISRC2INT2", NULL, "ISRC2" },
2019 { "ISRC2INT1", NULL, "ISRC2" },
2020 { "ISRC2DEC2", NULL, "ISRC2" },
2021 { "ISRC2DEC1", NULL, "ISRC2" },
2022
2023 { "ASRC_INT1", NULL, "ASRC_INT" },
2024 { "ASRC_INT2", NULL, "ASRC_INT" },
2025 { "ASRC_INT3", NULL, "ASRC_INT" },
2026 { "ASRC_INT4", NULL, "ASRC_INT" },
2027 { "ASRC_DEC1", NULL, "ASRC_DEC" },
2028 { "ASRC_DEC2", NULL, "ASRC_DEC" },
2029 { "ASRC_DEC3", NULL, "ASRC_DEC" },
2030 { "ASRC_DEC4", NULL, "ASRC_DEC" },
2031
2032 { "EQ", NULL, "EQ Clock" },
2033
2034 CS42L43_MUX_ROUTES("ASPTX1", "ASPTX1"),
2035 CS42L43_MUX_ROUTES("ASPTX2", "ASPTX2"),
2036 CS42L43_MUX_ROUTES("ASPTX3", "ASPTX3"),
2037 CS42L43_MUX_ROUTES("ASPTX4", "ASPTX4"),
2038 CS42L43_MUX_ROUTES("ASPTX5", "ASPTX5"),
2039 CS42L43_MUX_ROUTES("ASPTX6", "ASPTX6"),
2040
2041 CS42L43_MUX_ROUTES("DP1TX1", "DP1TX1"),
2042 CS42L43_MUX_ROUTES("DP1TX2", "DP1TX2"),
2043 CS42L43_MUX_ROUTES("DP1TX3", "DP1TX3"),
2044 CS42L43_MUX_ROUTES("DP1TX4", "DP1TX4"),
2045 CS42L43_MUX_ROUTES("DP2TX1", "DP2TX1"),
2046 CS42L43_MUX_ROUTES("DP2TX2", "DP2TX2"),
2047 CS42L43_MUX_ROUTES("DP3TX1", "DP3TX1"),
2048 CS42L43_MUX_ROUTES("DP3TX2", "DP3TX2"),
2049 CS42L43_MUX_ROUTES("DP4TX1", "DP4TX1"),
2050 CS42L43_MUX_ROUTES("DP4TX2", "DP4TX2"),
2051
2052 CS42L43_MUX_ROUTES("ASRC INT1", "ASRC_INT1"),
2053 CS42L43_MUX_ROUTES("ASRC INT2", "ASRC_INT2"),
2054 CS42L43_MUX_ROUTES("ASRC INT3", "ASRC_INT3"),
2055 CS42L43_MUX_ROUTES("ASRC INT4", "ASRC_INT4"),
2056 CS42L43_MUX_ROUTES("ASRC DEC1", "ASRC_DEC1"),
2057 CS42L43_MUX_ROUTES("ASRC DEC2", "ASRC_DEC2"),
2058 CS42L43_MUX_ROUTES("ASRC DEC3", "ASRC_DEC3"),
2059 CS42L43_MUX_ROUTES("ASRC DEC4", "ASRC_DEC4"),
2060
2061 CS42L43_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"),
2062 CS42L43_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"),
2063 CS42L43_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"),
2064 CS42L43_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"),
2065 CS42L43_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"),
2066 CS42L43_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"),
2067 CS42L43_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"),
2068 CS42L43_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"),
2069
2070 CS42L43_MUX_ROUTES("SPDIF1", "SPDIF"),
2071 CS42L43_MUX_ROUTES("SPDIF2", "SPDIF"),
2072
2073 CS42L43_MIXER_ROUTES("EQ1", "EQ"),
2074 CS42L43_MIXER_ROUTES("EQ2", "EQ"),
2075
2076 CS42L43_MIXER_ROUTES("Speaker L", "AMP1"),
2077 CS42L43_MIXER_ROUTES("Speaker R", "AMP2"),
2078
2079 CS42L43_MIXER_ROUTES("Headphone L", "HP"),
2080 CS42L43_MIXER_ROUTES("Headphone R", "HP"),
2081};
2082
2083static int cs42l43_set_sysclk(struct snd_soc_component *component, int clk_id,
2084 int src, unsigned int freq, int dir)
2085{
2086 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
2087 struct cs42l43 *cs42l43 = priv->core;
2088 int ret;
2089
2090 mutex_lock(&cs42l43->pll_lock);
2091 ret = cs42l43_set_pll(priv, src, freq);
2092 mutex_unlock(&cs42l43->pll_lock);
2093
2094 return ret;
2095}
2096
2097static int cs42l43_component_probe(struct snd_soc_component *component)
2098{
2099 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
2100 struct cs42l43 *cs42l43 = priv->core;
2101
2102 snd_soc_component_init_regmap(component, cs42l43->regmap);
2103
2104 cs42l43_mask_to_slots(priv, CS42L43_DEFAULT_SLOTS, priv->tx_slots,
2105 ARRAY_SIZE(priv->tx_slots));
2106 cs42l43_mask_to_slots(priv, CS42L43_DEFAULT_SLOTS, priv->rx_slots,
2107 ARRAY_SIZE(priv->rx_slots));
2108
2109 priv->component = component;
2110 priv->constraint = cs42l43_constraint;
2111
2112 return 0;
2113}
2114
2115static void cs42l43_component_remove(struct snd_soc_component *component)
2116{
2117 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
2118
2119 cs42l43_set_jack(priv->component, NULL, NULL);
2120
2121 cancel_delayed_work_sync(&priv->bias_sense_timeout);
2122 cancel_delayed_work_sync(&priv->tip_sense_work);
2123 cancel_delayed_work_sync(&priv->button_press_work);
2124 cancel_work_sync(&priv->button_release_work);
2125
2126 cancel_work_sync(&priv->hp_ilimit_work);
2127 cancel_delayed_work_sync(&priv->hp_ilimit_clear_work);
2128
2129 priv->component = NULL;
2130}
2131
2132static const struct snd_soc_component_driver cs42l43_component_drv = {
2133 .name = "cs42l43-codec",
2134
2135 .probe = cs42l43_component_probe,
2136 .remove = cs42l43_component_remove,
2137 .set_sysclk = cs42l43_set_sysclk,
2138 .set_jack = cs42l43_set_jack,
2139
2140 .endianness = 1,
2141
2142 .controls = cs42l43_controls,
2143 .num_controls = ARRAY_SIZE(cs42l43_controls),
2144 .dapm_widgets = cs42l43_widgets,
2145 .num_dapm_widgets = ARRAY_SIZE(cs42l43_widgets),
2146 .dapm_routes = cs42l43_routes,
2147 .num_dapm_routes = ARRAY_SIZE(cs42l43_routes),
2148};
2149
2150struct cs42l43_irq {
2151 unsigned int irq;
2152 const char *name;
2153 irq_handler_t handler;
2154};
2155
2156static const struct cs42l43_irq cs42l43_irqs[] = {
2157 { CS42L43_PLL_LOST_LOCK, "pll lost lock", cs42l43_pll_lost_lock },
2158 { CS42L43_PLL_READY, "pll ready", cs42l43_pll_ready },
2159 { CS42L43_HP_STARTUP_DONE, "hp startup", cs42l43_hp_startup },
2160 { CS42L43_HP_SHUTDOWN_DONE, "hp shutdown", cs42l43_hp_shutdown },
2161 { CS42L43_HSDET_DONE, "type detect", cs42l43_type_detect },
2162 { CS42L43_TIPSENSE_UNPLUG_PDET, "tip sense unplug", cs42l43_tip_sense },
2163 { CS42L43_TIPSENSE_PLUG_PDET, "tip sense plug", cs42l43_tip_sense },
2164 { CS42L43_DC_DETECT1_TRUE, "button press", cs42l43_button_press },
2165 { CS42L43_DC_DETECT1_FALSE, "button release", cs42l43_button_release },
2166 { CS42L43_HSBIAS_CLAMPED, "hsbias detect clamp", cs42l43_bias_detect_clamp },
2167 { CS42L43_AMP2_CLK_STOP_FAULT, "spkr clock stop", cs42l43_spkr_clock_stop },
2168 { CS42L43_AMP1_CLK_STOP_FAULT, "spkl clock stop", cs42l43_spkl_clock_stop },
2169 { CS42L43_AMP2_VDDSPK_FAULT, "spkr brown out", cs42l43_spkr_brown_out },
2170 { CS42L43_AMP1_VDDSPK_FAULT, "spkl brown out", cs42l43_spkl_brown_out },
2171 { CS42L43_AMP2_SHUTDOWN_DONE, "spkr shutdown", cs42l43_spkr_shutdown },
2172 { CS42L43_AMP1_SHUTDOWN_DONE, "spkl shutdown", cs42l43_spkl_shutdown },
2173 { CS42L43_AMP2_STARTUP_DONE, "spkr startup", cs42l43_spkr_startup },
2174 { CS42L43_AMP1_STARTUP_DONE, "spkl startup", cs42l43_spkl_startup },
2175 { CS42L43_AMP2_THERM_SHDN, "spkr thermal shutdown", cs42l43_spkr_therm_shutdown },
2176 { CS42L43_AMP1_THERM_SHDN, "spkl thermal shutdown", cs42l43_spkl_therm_shutdown },
2177 { CS42L43_AMP2_THERM_WARN, "spkr thermal warning", cs42l43_spkr_therm_warm },
2178 { CS42L43_AMP1_THERM_WARN, "spkl thermal warning", cs42l43_spkl_therm_warm },
2179 { CS42L43_AMP2_SCDET, "spkr short circuit", cs42l43_spkr_sc_detect },
2180 { CS42L43_AMP1_SCDET, "spkl short circuit", cs42l43_spkl_sc_detect },
2181 { CS42L43_HP_ILIMIT, "hp ilimit", cs42l43_hp_ilimit },
2182 { CS42L43_HP_LOADDET_DONE, "load detect done", cs42l43_load_detect },
2183};
2184
2185static int cs42l43_request_irq(struct cs42l43_codec *priv,
2186 struct irq_domain *dom, const char * const name,
2187 unsigned int irq, irq_handler_t handler,
2188 unsigned long flags)
2189{
2190 int ret;
2191
2192 ret = irq_create_mapping(dom, irq);
2193 if (ret < 0)
2194 return dev_err_probe(priv->dev, ret, "Failed to map IRQ %s\n", name);
2195
2196 dev_dbg(priv->dev, "Request IRQ %d for %s\n", ret, name);
2197
2198 ret = devm_request_threaded_irq(priv->dev, ret, NULL, handler,
2199 IRQF_ONESHOT | flags, name, priv);
2200 if (ret)
2201 return dev_err_probe(priv->dev, ret, "Failed to request IRQ %s\n", name);
2202
2203 return 0;
2204}
2205
2206static int cs42l43_shutter_irq(struct cs42l43_codec *priv,
2207 struct irq_domain *dom, unsigned int shutter,
2208 const char * const open_name,
2209 const char * const close_name,
2210 irq_handler_t handler)
2211{
2212 unsigned int open_irq, close_irq;
2213 int ret;
2214
2215 switch (shutter) {
2216 case 0x1:
2217 dev_warn(priv->dev, "Manual shutters, notifications not available\n");
2218 return 0;
2219 case 0x2:
2220 open_irq = CS42L43_GPIO1_RISE;
2221 close_irq = CS42L43_GPIO1_FALL;
2222 break;
2223 case 0x4:
2224 open_irq = CS42L43_GPIO2_RISE;
2225 close_irq = CS42L43_GPIO2_FALL;
2226 break;
2227 case 0x8:
2228 open_irq = CS42L43_GPIO3_RISE;
2229 close_irq = CS42L43_GPIO3_FALL;
2230 break;
2231 default:
2232 return 0;
2233 }
2234
2235 ret = cs42l43_request_irq(priv, dom, close_name, close_irq, handler, IRQF_SHARED);
2236 if (ret)
2237 return ret;
2238
2239 return cs42l43_request_irq(priv, dom, open_name, open_irq, handler, IRQF_SHARED);
2240}
2241
2242static int cs42l43_codec_probe(struct platform_device *pdev)
2243{
2244 struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent);
2245 struct cs42l43_codec *priv;
2246 struct irq_domain *dom;
2247 unsigned int val;
2248 int i, ret;
2249
2250 dom = irq_find_matching_fwnode(dev_fwnode(cs42l43->dev), DOMAIN_BUS_ANY);
2251 if (!dom)
2252 return -EPROBE_DEFER;
2253
2254 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
2255 if (!priv)
2256 return -ENOMEM;
2257
2258 priv->dev = &pdev->dev;
2259 priv->core = cs42l43;
2260
2261 platform_set_drvdata(pdev, priv);
2262
2263 mutex_init(&priv->jack_lock);
2264 mutex_init(&priv->spk_vu_lock);
2265
2266 init_completion(&priv->hp_startup);
2267 init_completion(&priv->hp_shutdown);
2268 init_completion(&priv->spkr_shutdown);
2269 init_completion(&priv->spkl_shutdown);
2270 init_completion(&priv->spkr_startup);
2271 init_completion(&priv->spkl_startup);
2272 init_completion(&priv->pll_ready);
2273 init_completion(&priv->type_detect);
2274 init_completion(&priv->load_detect);
2275
2276 INIT_DELAYED_WORK(&priv->tip_sense_work, cs42l43_tip_sense_work);
2277 INIT_DELAYED_WORK(&priv->bias_sense_timeout, cs42l43_bias_sense_timeout);
2278 INIT_DELAYED_WORK(&priv->button_press_work, cs42l43_button_press_work);
2279 INIT_DELAYED_WORK(&priv->hp_ilimit_clear_work, cs42l43_hp_ilimit_clear_work);
2280 INIT_WORK(&priv->button_release_work, cs42l43_button_release_work);
2281 INIT_WORK(&priv->hp_ilimit_work, cs42l43_hp_ilimit_work);
2282
2283 pm_runtime_set_autosuspend_delay(priv->dev, 100);
2284 pm_runtime_use_autosuspend(priv->dev);
2285 pm_runtime_set_active(priv->dev);
2286 pm_runtime_get_noresume(priv->dev);
2287
2288 ret = devm_pm_runtime_enable(priv->dev);
2289 if (ret)
2290 goto err_pm;
2291
2292 for (i = 0; i < ARRAY_SIZE(cs42l43_irqs); i++) {
2293 ret = cs42l43_request_irq(priv, dom, cs42l43_irqs[i].name,
2294 cs42l43_irqs[i].irq,
2295 cs42l43_irqs[i].handler, 0);
2296 if (ret)
2297 goto err_pm;
2298 }
2299
2300 ret = regmap_read(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, &val);
2301 if (ret) {
2302 dev_err(priv->dev, "Failed to check shutter source: %d\n", ret);
2303 goto err_pm;
2304 }
2305
2306 ret = cs42l43_shutter_irq(priv, dom, val & CS42L43_MIC_SHUTTER_CFG_MASK,
2307 "mic shutter open", "mic shutter close",
2308 cs42l43_mic_shutter);
2309 if (ret)
2310 goto err_pm;
2311
2312 ret = cs42l43_shutter_irq(priv, dom, (val & CS42L43_SPK_SHUTTER_CFG_MASK) >>
2313 CS42L43_SPK_SHUTTER_CFG_SHIFT,
2314 "spk shutter open", "spk shutter close",
2315 cs42l43_spk_shutter);
2316 if (ret)
2317 goto err_pm;
2318
2319 // Don't use devm as we need to get against the MFD device
2320 priv->mclk = clk_get_optional(cs42l43->dev, "mclk");
2321 if (IS_ERR(priv->mclk)) {
2322 ret = PTR_ERR(priv->mclk);
2323 dev_err_probe(priv->dev, ret, "Failed to get mclk\n");
2324 goto err_pm;
2325 }
2326
2327 ret = devm_snd_soc_register_component(priv->dev, &cs42l43_component_drv,
2328 cs42l43_dais, ARRAY_SIZE(cs42l43_dais));
2329 if (ret) {
2330 dev_err_probe(priv->dev, ret, "Failed to register component\n");
2331 goto err_clk;
2332 }
2333
2334 pm_runtime_mark_last_busy(priv->dev);
2335 pm_runtime_put_autosuspend(priv->dev);
2336
2337 return 0;
2338
2339err_clk:
2340 clk_put(priv->mclk);
2341err_pm:
2342 pm_runtime_put_sync(priv->dev);
2343
2344 return ret;
2345}
2346
2347static void cs42l43_codec_remove(struct platform_device *pdev)
2348{
2349 struct cs42l43_codec *priv = platform_get_drvdata(pdev);
2350
2351 clk_put(priv->mclk);
2352}
2353
2354static int cs42l43_codec_runtime_resume(struct device *dev)
2355{
2356 struct cs42l43_codec *priv = dev_get_drvdata(dev);
2357
2358 dev_dbg(priv->dev, "Runtime resume\n");
2359
2360 // Toggle the speaker volume update incase the speaker volume was synced
2361 cs42l43_spk_vu_sync(priv);
2362
2363 return 0;
2364}
2365
2366static int cs42l43_codec_suspend(struct device *dev)
2367{
2368 struct cs42l43_codec *priv = dev_get_drvdata(dev);
2369 struct cs42l43 *cs42l43 = priv->core;
2370
2371 disable_irq(cs42l43->irq);
2372
2373 return 0;
2374}
2375
2376static int cs42l43_codec_suspend_noirq(struct device *dev)
2377{
2378 struct cs42l43_codec *priv = dev_get_drvdata(dev);
2379 struct cs42l43 *cs42l43 = priv->core;
2380
2381 enable_irq(cs42l43->irq);
2382
2383 return 0;
2384}
2385
2386static int cs42l43_codec_resume(struct device *dev)
2387{
2388 struct cs42l43_codec *priv = dev_get_drvdata(dev);
2389 struct cs42l43 *cs42l43 = priv->core;
2390
2391 enable_irq(cs42l43->irq);
2392
2393 return 0;
2394}
2395
2396static int cs42l43_codec_resume_noirq(struct device *dev)
2397{
2398 struct cs42l43_codec *priv = dev_get_drvdata(dev);
2399 struct cs42l43 *cs42l43 = priv->core;
2400
2401 disable_irq(cs42l43->irq);
2402
2403 return 0;
2404}
2405
2406static const struct dev_pm_ops cs42l43_codec_pm_ops = {
2407 SYSTEM_SLEEP_PM_OPS(cs42l43_codec_suspend, cs42l43_codec_resume)
2408 NOIRQ_SYSTEM_SLEEP_PM_OPS(cs42l43_codec_suspend_noirq, cs42l43_codec_resume_noirq)
2409 RUNTIME_PM_OPS(NULL, cs42l43_codec_runtime_resume, NULL)
2410};
2411
2412static const struct platform_device_id cs42l43_codec_id_table[] = {
2413 { "cs42l43-codec", },
2414 {}
2415};
2416MODULE_DEVICE_TABLE(platform, cs42l43_codec_id_table);
2417
2418static struct platform_driver cs42l43_codec_driver = {
2419 .driver = {
2420 .name = "cs42l43-codec",
2421 .pm = pm_ptr(&cs42l43_codec_pm_ops),
2422 },
2423
2424 .probe = cs42l43_codec_probe,
2425 .remove_new = cs42l43_codec_remove,
2426 .id_table = cs42l43_codec_id_table,
2427};
2428module_platform_driver(cs42l43_codec_driver);
2429
2430MODULE_IMPORT_NS(SND_SOC_CS42L43);
2431
2432MODULE_DESCRIPTION("CS42L43 CODEC Driver");
2433MODULE_AUTHOR("Charles Keepax <ckeepax@opensource.cirrus.com>");
2434MODULE_LICENSE("GPL");