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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2018-2019 NXP.
4 *
5 * Limitations:
6 * - The TPM counter and period counter are shared between
7 * multiple channels, so all channels should use same period
8 * settings.
9 * - Changes to polarity cannot be latched at the time of the
10 * next period start.
11 * - Changing period and duty cycle together isn't atomic,
12 * with the wrong timing it might happen that a period is
13 * produced with old duty cycle but new period settings.
14 */
15
16#include <linux/bitfield.h>
17#include <linux/bitops.h>
18#include <linux/clk.h>
19#include <linux/err.h>
20#include <linux/io.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/pinctrl/consumer.h>
24#include <linux/platform_device.h>
25#include <linux/pwm.h>
26#include <linux/slab.h>
27
28#define PWM_IMX_TPM_PARAM 0x4
29#define PWM_IMX_TPM_GLOBAL 0x8
30#define PWM_IMX_TPM_SC 0x10
31#define PWM_IMX_TPM_CNT 0x14
32#define PWM_IMX_TPM_MOD 0x18
33#define PWM_IMX_TPM_CnSC(n) (0x20 + (n) * 0x8)
34#define PWM_IMX_TPM_CnV(n) (0x24 + (n) * 0x8)
35
36#define PWM_IMX_TPM_PARAM_CHAN GENMASK(7, 0)
37
38#define PWM_IMX_TPM_SC_PS GENMASK(2, 0)
39#define PWM_IMX_TPM_SC_CMOD GENMASK(4, 3)
40#define PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK FIELD_PREP(PWM_IMX_TPM_SC_CMOD, 1)
41#define PWM_IMX_TPM_SC_CPWMS BIT(5)
42
43#define PWM_IMX_TPM_CnSC_CHF BIT(7)
44#define PWM_IMX_TPM_CnSC_MSB BIT(5)
45#define PWM_IMX_TPM_CnSC_MSA BIT(4)
46
47/*
48 * The reference manual describes this field as two separate bits. The
49 * semantic of the two bits isn't orthogonal though, so they are treated
50 * together as a 2-bit field here.
51 */
52#define PWM_IMX_TPM_CnSC_ELS GENMASK(3, 2)
53#define PWM_IMX_TPM_CnSC_ELS_INVERSED FIELD_PREP(PWM_IMX_TPM_CnSC_ELS, 1)
54#define PWM_IMX_TPM_CnSC_ELS_NORMAL FIELD_PREP(PWM_IMX_TPM_CnSC_ELS, 2)
55
56
57#define PWM_IMX_TPM_MOD_WIDTH 16
58#define PWM_IMX_TPM_MOD_MOD GENMASK(PWM_IMX_TPM_MOD_WIDTH - 1, 0)
59
60struct imx_tpm_pwm_chip {
61 struct clk *clk;
62 void __iomem *base;
63 struct mutex lock;
64 u32 user_count;
65 u32 enable_count;
66 u32 real_period;
67};
68
69struct imx_tpm_pwm_param {
70 u8 prescale;
71 u32 mod;
72 u32 val;
73};
74
75static inline struct imx_tpm_pwm_chip *
76to_imx_tpm_pwm_chip(struct pwm_chip *chip)
77{
78 return pwmchip_get_drvdata(chip);
79}
80
81/*
82 * This function determines for a given pwm_state *state that a consumer
83 * might request the pwm_state *real_state that eventually is implemented
84 * by the hardware and the necessary register values (in *p) to achieve
85 * this.
86 */
87static int pwm_imx_tpm_round_state(struct pwm_chip *chip,
88 struct imx_tpm_pwm_param *p,
89 struct pwm_state *real_state,
90 const struct pwm_state *state)
91{
92 struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
93 u32 rate, prescale, period_count, clock_unit;
94 u64 tmp;
95
96 rate = clk_get_rate(tpm->clk);
97 tmp = (u64)state->period * rate;
98 clock_unit = DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC);
99 if (clock_unit <= PWM_IMX_TPM_MOD_MOD)
100 prescale = 0;
101 else
102 prescale = ilog2(clock_unit) + 1 - PWM_IMX_TPM_MOD_WIDTH;
103
104 if ((!FIELD_FIT(PWM_IMX_TPM_SC_PS, prescale)))
105 return -ERANGE;
106 p->prescale = prescale;
107
108 period_count = (clock_unit + ((1 << prescale) >> 1)) >> prescale;
109 if (period_count == 0)
110 return -EINVAL;
111 p->mod = period_count - 1;
112
113 /* calculate real period HW can support */
114 tmp = (u64)period_count << prescale;
115 tmp *= NSEC_PER_SEC;
116 real_state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate);
117
118 /*
119 * if eventually the PWM output is inactive, either
120 * duty cycle is 0 or status is disabled, need to
121 * make sure the output pin is inactive.
122 */
123 if (!state->enabled)
124 real_state->duty_cycle = 0;
125 else
126 real_state->duty_cycle = state->duty_cycle;
127
128 tmp = (u64)p->mod * real_state->duty_cycle;
129 p->val = DIV64_U64_ROUND_CLOSEST(tmp, real_state->period);
130
131 real_state->polarity = state->polarity;
132 real_state->enabled = state->enabled;
133
134 return 0;
135}
136
137static int pwm_imx_tpm_get_state(struct pwm_chip *chip,
138 struct pwm_device *pwm,
139 struct pwm_state *state)
140{
141 struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
142 u32 rate, val, prescale;
143 u64 tmp;
144
145 /* get period */
146 state->period = tpm->real_period;
147
148 /* get duty cycle */
149 rate = clk_get_rate(tpm->clk);
150 val = readl(tpm->base + PWM_IMX_TPM_SC);
151 prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val);
152 tmp = readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm));
153 tmp = (tmp << prescale) * NSEC_PER_SEC;
154 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate);
155
156 /* get polarity */
157 val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
158 if ((val & PWM_IMX_TPM_CnSC_ELS) == PWM_IMX_TPM_CnSC_ELS_INVERSED)
159 state->polarity = PWM_POLARITY_INVERSED;
160 else
161 /*
162 * Assume reserved values (2b00 and 2b11) to yield
163 * normal polarity.
164 */
165 state->polarity = PWM_POLARITY_NORMAL;
166
167 /* get channel status */
168 state->enabled = FIELD_GET(PWM_IMX_TPM_CnSC_ELS, val) ? true : false;
169
170 return 0;
171}
172
173/* this function is supposed to be called with mutex hold */
174static int pwm_imx_tpm_apply_hw(struct pwm_chip *chip,
175 struct imx_tpm_pwm_param *p,
176 struct pwm_state *state,
177 struct pwm_device *pwm)
178{
179 struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
180 bool period_update = false;
181 bool duty_update = false;
182 u32 val, cmod, cur_prescale;
183 unsigned long timeout;
184 struct pwm_state c;
185
186 if (state->period != tpm->real_period) {
187 /*
188 * TPM counter is shared by multiple channels, so
189 * prescale and period can NOT be modified when
190 * there are multiple channels in use with different
191 * period settings.
192 */
193 if (tpm->user_count > 1)
194 return -EBUSY;
195
196 val = readl(tpm->base + PWM_IMX_TPM_SC);
197 cmod = FIELD_GET(PWM_IMX_TPM_SC_CMOD, val);
198 cur_prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val);
199 if (cmod && cur_prescale != p->prescale)
200 return -EBUSY;
201
202 /* set TPM counter prescale */
203 val &= ~PWM_IMX_TPM_SC_PS;
204 val |= FIELD_PREP(PWM_IMX_TPM_SC_PS, p->prescale);
205 writel(val, tpm->base + PWM_IMX_TPM_SC);
206
207 /*
208 * set period count:
209 * if the PWM is disabled (CMOD[1:0] = 2b00), then MOD register
210 * is updated when MOD register is written.
211 *
212 * if the PWM is enabled (CMOD[1:0] ≠2b00), the period length
213 * is latched into hardware when the next period starts.
214 */
215 writel(p->mod, tpm->base + PWM_IMX_TPM_MOD);
216 tpm->real_period = state->period;
217 period_update = true;
218 }
219
220 pwm_imx_tpm_get_state(chip, pwm, &c);
221
222 /* polarity is NOT allowed to be changed if PWM is active */
223 if (c.enabled && c.polarity != state->polarity)
224 return -EBUSY;
225
226 if (state->duty_cycle != c.duty_cycle) {
227 /*
228 * set channel value:
229 * if the PWM is disabled (CMOD[1:0] = 2b00), then CnV register
230 * is updated when CnV register is written.
231 *
232 * if the PWM is enabled (CMOD[1:0] ≠2b00), the duty length
233 * is latched into hardware when the next period starts.
234 */
235 writel(p->val, tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm));
236 duty_update = true;
237 }
238
239 /* make sure MOD & CnV registers are updated */
240 if (period_update || duty_update) {
241 timeout = jiffies + msecs_to_jiffies(tpm->real_period /
242 NSEC_PER_MSEC + 1);
243 while (readl(tpm->base + PWM_IMX_TPM_MOD) != p->mod
244 || readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm))
245 != p->val) {
246 if (time_after(jiffies, timeout))
247 return -ETIME;
248 cpu_relax();
249 }
250 }
251
252 /*
253 * polarity settings will enabled/disable output status
254 * immediately, so if the channel is disabled, need to
255 * make sure MSA/MSB/ELS are set to 0 which means channel
256 * disabled.
257 */
258 val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
259 val &= ~(PWM_IMX_TPM_CnSC_ELS | PWM_IMX_TPM_CnSC_MSA |
260 PWM_IMX_TPM_CnSC_MSB);
261 if (state->enabled) {
262 /*
263 * set polarity (for edge-aligned PWM modes)
264 *
265 * ELS[1:0] = 2b10 yields normal polarity behaviour,
266 * ELS[1:0] = 2b01 yields inversed polarity.
267 * The other values are reserved.
268 */
269 val |= PWM_IMX_TPM_CnSC_MSB;
270 val |= (state->polarity == PWM_POLARITY_NORMAL) ?
271 PWM_IMX_TPM_CnSC_ELS_NORMAL :
272 PWM_IMX_TPM_CnSC_ELS_INVERSED;
273 }
274 writel(val, tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
275
276 /* control the counter status */
277 if (state->enabled != c.enabled) {
278 val = readl(tpm->base + PWM_IMX_TPM_SC);
279 if (state->enabled) {
280 if (++tpm->enable_count == 1)
281 val |= PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK;
282 } else {
283 if (--tpm->enable_count == 0)
284 val &= ~PWM_IMX_TPM_SC_CMOD;
285 }
286 writel(val, tpm->base + PWM_IMX_TPM_SC);
287 }
288
289 return 0;
290}
291
292static int pwm_imx_tpm_apply(struct pwm_chip *chip,
293 struct pwm_device *pwm,
294 const struct pwm_state *state)
295{
296 struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
297 struct imx_tpm_pwm_param param;
298 struct pwm_state real_state;
299 int ret;
300
301 ret = pwm_imx_tpm_round_state(chip, ¶m, &real_state, state);
302 if (ret)
303 return ret;
304
305 mutex_lock(&tpm->lock);
306 ret = pwm_imx_tpm_apply_hw(chip, ¶m, &real_state, pwm);
307 mutex_unlock(&tpm->lock);
308
309 return ret;
310}
311
312static int pwm_imx_tpm_request(struct pwm_chip *chip, struct pwm_device *pwm)
313{
314 struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
315
316 mutex_lock(&tpm->lock);
317 tpm->user_count++;
318 mutex_unlock(&tpm->lock);
319
320 return 0;
321}
322
323static void pwm_imx_tpm_free(struct pwm_chip *chip, struct pwm_device *pwm)
324{
325 struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
326
327 mutex_lock(&tpm->lock);
328 tpm->user_count--;
329 mutex_unlock(&tpm->lock);
330}
331
332static const struct pwm_ops imx_tpm_pwm_ops = {
333 .request = pwm_imx_tpm_request,
334 .free = pwm_imx_tpm_free,
335 .get_state = pwm_imx_tpm_get_state,
336 .apply = pwm_imx_tpm_apply,
337};
338
339static int pwm_imx_tpm_probe(struct platform_device *pdev)
340{
341 struct pwm_chip *chip;
342 struct imx_tpm_pwm_chip *tpm;
343 struct clk *clk;
344 void __iomem *base;
345 int ret;
346 unsigned int npwm;
347 u32 val;
348
349 base = devm_platform_ioremap_resource(pdev, 0);
350 if (IS_ERR(base))
351 return PTR_ERR(base);
352
353 clk = devm_clk_get_enabled(&pdev->dev, NULL);
354 if (IS_ERR(clk))
355 return dev_err_probe(&pdev->dev, PTR_ERR(clk),
356 "failed to get PWM clock\n");
357
358 /* get number of channels */
359 val = readl(base + PWM_IMX_TPM_PARAM);
360 npwm = FIELD_GET(PWM_IMX_TPM_PARAM_CHAN, val);
361
362 chip = devm_pwmchip_alloc(&pdev->dev, npwm, sizeof(*tpm));
363 if (IS_ERR(chip))
364 return PTR_ERR(chip);
365 tpm = to_imx_tpm_pwm_chip(chip);
366
367 platform_set_drvdata(pdev, tpm);
368
369 tpm->base = base;
370 tpm->clk = clk;
371
372 chip->ops = &imx_tpm_pwm_ops;
373
374 mutex_init(&tpm->lock);
375
376 ret = devm_pwmchip_add(&pdev->dev, chip);
377 if (ret)
378 return dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n");
379
380 return 0;
381}
382
383static int pwm_imx_tpm_suspend(struct device *dev)
384{
385 struct imx_tpm_pwm_chip *tpm = dev_get_drvdata(dev);
386 int ret;
387
388 if (tpm->enable_count > 0)
389 return -EBUSY;
390
391 /*
392 * Force 'real_period' to be zero to force period update code
393 * can be executed after system resume back, since suspend causes
394 * the period related registers to become their reset values.
395 */
396 tpm->real_period = 0;
397
398 clk_disable_unprepare(tpm->clk);
399
400 ret = pinctrl_pm_select_sleep_state(dev);
401 if (ret)
402 clk_prepare_enable(tpm->clk);
403
404 return ret;
405}
406
407static int pwm_imx_tpm_resume(struct device *dev)
408{
409 struct imx_tpm_pwm_chip *tpm = dev_get_drvdata(dev);
410 int ret = 0;
411
412 ret = pinctrl_pm_select_default_state(dev);
413 if (ret)
414 return ret;
415
416 ret = clk_prepare_enable(tpm->clk);
417 if (ret) {
418 dev_err(dev, "failed to prepare or enable clock: %d\n", ret);
419 pinctrl_pm_select_sleep_state(dev);
420 }
421
422 return ret;
423}
424
425static DEFINE_SIMPLE_DEV_PM_OPS(imx_tpm_pwm_pm,
426 pwm_imx_tpm_suspend, pwm_imx_tpm_resume);
427
428static const struct of_device_id imx_tpm_pwm_dt_ids[] = {
429 { .compatible = "fsl,imx7ulp-pwm", },
430 { /* sentinel */ }
431};
432MODULE_DEVICE_TABLE(of, imx_tpm_pwm_dt_ids);
433
434static struct platform_driver imx_tpm_pwm_driver = {
435 .driver = {
436 .name = "imx7ulp-tpm-pwm",
437 .of_match_table = imx_tpm_pwm_dt_ids,
438 .pm = pm_ptr(&imx_tpm_pwm_pm),
439 },
440 .probe = pwm_imx_tpm_probe,
441};
442module_platform_driver(imx_tpm_pwm_driver);
443
444MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
445MODULE_DESCRIPTION("i.MX TPM PWM Driver");
446MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2018-2019 NXP.
4 *
5 * Limitations:
6 * - The TPM counter and period counter are shared between
7 * multiple channels, so all channels should use same period
8 * settings.
9 * - Changes to polarity cannot be latched at the time of the
10 * next period start.
11 * - Changing period and duty cycle together isn't atomic,
12 * with the wrong timing it might happen that a period is
13 * produced with old duty cycle but new period settings.
14 */
15
16#include <linux/bitfield.h>
17#include <linux/bitops.h>
18#include <linux/clk.h>
19#include <linux/err.h>
20#include <linux/io.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/platform_device.h>
24#include <linux/pwm.h>
25#include <linux/slab.h>
26
27#define PWM_IMX_TPM_PARAM 0x4
28#define PWM_IMX_TPM_GLOBAL 0x8
29#define PWM_IMX_TPM_SC 0x10
30#define PWM_IMX_TPM_CNT 0x14
31#define PWM_IMX_TPM_MOD 0x18
32#define PWM_IMX_TPM_CnSC(n) (0x20 + (n) * 0x8)
33#define PWM_IMX_TPM_CnV(n) (0x24 + (n) * 0x8)
34
35#define PWM_IMX_TPM_PARAM_CHAN GENMASK(7, 0)
36
37#define PWM_IMX_TPM_SC_PS GENMASK(2, 0)
38#define PWM_IMX_TPM_SC_CMOD GENMASK(4, 3)
39#define PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK FIELD_PREP(PWM_IMX_TPM_SC_CMOD, 1)
40#define PWM_IMX_TPM_SC_CPWMS BIT(5)
41
42#define PWM_IMX_TPM_CnSC_CHF BIT(7)
43#define PWM_IMX_TPM_CnSC_MSB BIT(5)
44#define PWM_IMX_TPM_CnSC_MSA BIT(4)
45
46/*
47 * The reference manual describes this field as two separate bits. The
48 * semantic of the two bits isn't orthogonal though, so they are treated
49 * together as a 2-bit field here.
50 */
51#define PWM_IMX_TPM_CnSC_ELS GENMASK(3, 2)
52#define PWM_IMX_TPM_CnSC_ELS_INVERSED FIELD_PREP(PWM_IMX_TPM_CnSC_ELS, 1)
53#define PWM_IMX_TPM_CnSC_ELS_NORMAL FIELD_PREP(PWM_IMX_TPM_CnSC_ELS, 2)
54
55
56#define PWM_IMX_TPM_MOD_WIDTH 16
57#define PWM_IMX_TPM_MOD_MOD GENMASK(PWM_IMX_TPM_MOD_WIDTH - 1, 0)
58
59struct imx_tpm_pwm_chip {
60 struct clk *clk;
61 void __iomem *base;
62 struct mutex lock;
63 u32 user_count;
64 u32 enable_count;
65 u32 real_period;
66};
67
68struct imx_tpm_pwm_param {
69 u8 prescale;
70 u32 mod;
71 u32 val;
72};
73
74static inline struct imx_tpm_pwm_chip *
75to_imx_tpm_pwm_chip(struct pwm_chip *chip)
76{
77 return pwmchip_get_drvdata(chip);
78}
79
80/*
81 * This function determines for a given pwm_state *state that a consumer
82 * might request the pwm_state *real_state that eventually is implemented
83 * by the hardware and the necessary register values (in *p) to achieve
84 * this.
85 */
86static int pwm_imx_tpm_round_state(struct pwm_chip *chip,
87 struct imx_tpm_pwm_param *p,
88 struct pwm_state *real_state,
89 const struct pwm_state *state)
90{
91 struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
92 u32 rate, prescale, period_count, clock_unit;
93 u64 tmp;
94
95 rate = clk_get_rate(tpm->clk);
96 tmp = (u64)state->period * rate;
97 clock_unit = DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC);
98 if (clock_unit <= PWM_IMX_TPM_MOD_MOD)
99 prescale = 0;
100 else
101 prescale = ilog2(clock_unit) + 1 - PWM_IMX_TPM_MOD_WIDTH;
102
103 if ((!FIELD_FIT(PWM_IMX_TPM_SC_PS, prescale)))
104 return -ERANGE;
105 p->prescale = prescale;
106
107 period_count = (clock_unit + ((1 << prescale) >> 1)) >> prescale;
108 p->mod = period_count;
109
110 /* calculate real period HW can support */
111 tmp = (u64)period_count << prescale;
112 tmp *= NSEC_PER_SEC;
113 real_state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate);
114
115 /*
116 * if eventually the PWM output is inactive, either
117 * duty cycle is 0 or status is disabled, need to
118 * make sure the output pin is inactive.
119 */
120 if (!state->enabled)
121 real_state->duty_cycle = 0;
122 else
123 real_state->duty_cycle = state->duty_cycle;
124
125 tmp = (u64)p->mod * real_state->duty_cycle;
126 p->val = DIV64_U64_ROUND_CLOSEST(tmp, real_state->period);
127
128 real_state->polarity = state->polarity;
129 real_state->enabled = state->enabled;
130
131 return 0;
132}
133
134static int pwm_imx_tpm_get_state(struct pwm_chip *chip,
135 struct pwm_device *pwm,
136 struct pwm_state *state)
137{
138 struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
139 u32 rate, val, prescale;
140 u64 tmp;
141
142 /* get period */
143 state->period = tpm->real_period;
144
145 /* get duty cycle */
146 rate = clk_get_rate(tpm->clk);
147 val = readl(tpm->base + PWM_IMX_TPM_SC);
148 prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val);
149 tmp = readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm));
150 tmp = (tmp << prescale) * NSEC_PER_SEC;
151 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate);
152
153 /* get polarity */
154 val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
155 if ((val & PWM_IMX_TPM_CnSC_ELS) == PWM_IMX_TPM_CnSC_ELS_INVERSED)
156 state->polarity = PWM_POLARITY_INVERSED;
157 else
158 /*
159 * Assume reserved values (2b00 and 2b11) to yield
160 * normal polarity.
161 */
162 state->polarity = PWM_POLARITY_NORMAL;
163
164 /* get channel status */
165 state->enabled = FIELD_GET(PWM_IMX_TPM_CnSC_ELS, val) ? true : false;
166
167 return 0;
168}
169
170/* this function is supposed to be called with mutex hold */
171static int pwm_imx_tpm_apply_hw(struct pwm_chip *chip,
172 struct imx_tpm_pwm_param *p,
173 struct pwm_state *state,
174 struct pwm_device *pwm)
175{
176 struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
177 bool period_update = false;
178 bool duty_update = false;
179 u32 val, cmod, cur_prescale;
180 unsigned long timeout;
181 struct pwm_state c;
182
183 if (state->period != tpm->real_period) {
184 /*
185 * TPM counter is shared by multiple channels, so
186 * prescale and period can NOT be modified when
187 * there are multiple channels in use with different
188 * period settings.
189 */
190 if (tpm->user_count > 1)
191 return -EBUSY;
192
193 val = readl(tpm->base + PWM_IMX_TPM_SC);
194 cmod = FIELD_GET(PWM_IMX_TPM_SC_CMOD, val);
195 cur_prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val);
196 if (cmod && cur_prescale != p->prescale)
197 return -EBUSY;
198
199 /* set TPM counter prescale */
200 val &= ~PWM_IMX_TPM_SC_PS;
201 val |= FIELD_PREP(PWM_IMX_TPM_SC_PS, p->prescale);
202 writel(val, tpm->base + PWM_IMX_TPM_SC);
203
204 /*
205 * set period count:
206 * if the PWM is disabled (CMOD[1:0] = 2b00), then MOD register
207 * is updated when MOD register is written.
208 *
209 * if the PWM is enabled (CMOD[1:0] ≠2b00), the period length
210 * is latched into hardware when the next period starts.
211 */
212 writel(p->mod, tpm->base + PWM_IMX_TPM_MOD);
213 tpm->real_period = state->period;
214 period_update = true;
215 }
216
217 pwm_imx_tpm_get_state(chip, pwm, &c);
218
219 /* polarity is NOT allowed to be changed if PWM is active */
220 if (c.enabled && c.polarity != state->polarity)
221 return -EBUSY;
222
223 if (state->duty_cycle != c.duty_cycle) {
224 /*
225 * set channel value:
226 * if the PWM is disabled (CMOD[1:0] = 2b00), then CnV register
227 * is updated when CnV register is written.
228 *
229 * if the PWM is enabled (CMOD[1:0] ≠2b00), the duty length
230 * is latched into hardware when the next period starts.
231 */
232 writel(p->val, tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm));
233 duty_update = true;
234 }
235
236 /* make sure MOD & CnV registers are updated */
237 if (period_update || duty_update) {
238 timeout = jiffies + msecs_to_jiffies(tpm->real_period /
239 NSEC_PER_MSEC + 1);
240 while (readl(tpm->base + PWM_IMX_TPM_MOD) != p->mod
241 || readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm))
242 != p->val) {
243 if (time_after(jiffies, timeout))
244 return -ETIME;
245 cpu_relax();
246 }
247 }
248
249 /*
250 * polarity settings will enabled/disable output status
251 * immediately, so if the channel is disabled, need to
252 * make sure MSA/MSB/ELS are set to 0 which means channel
253 * disabled.
254 */
255 val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
256 val &= ~(PWM_IMX_TPM_CnSC_ELS | PWM_IMX_TPM_CnSC_MSA |
257 PWM_IMX_TPM_CnSC_MSB);
258 if (state->enabled) {
259 /*
260 * set polarity (for edge-aligned PWM modes)
261 *
262 * ELS[1:0] = 2b10 yields normal polarity behaviour,
263 * ELS[1:0] = 2b01 yields inversed polarity.
264 * The other values are reserved.
265 */
266 val |= PWM_IMX_TPM_CnSC_MSB;
267 val |= (state->polarity == PWM_POLARITY_NORMAL) ?
268 PWM_IMX_TPM_CnSC_ELS_NORMAL :
269 PWM_IMX_TPM_CnSC_ELS_INVERSED;
270 }
271 writel(val, tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
272
273 /* control the counter status */
274 if (state->enabled != c.enabled) {
275 val = readl(tpm->base + PWM_IMX_TPM_SC);
276 if (state->enabled) {
277 if (++tpm->enable_count == 1)
278 val |= PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK;
279 } else {
280 if (--tpm->enable_count == 0)
281 val &= ~PWM_IMX_TPM_SC_CMOD;
282 }
283 writel(val, tpm->base + PWM_IMX_TPM_SC);
284 }
285
286 return 0;
287}
288
289static int pwm_imx_tpm_apply(struct pwm_chip *chip,
290 struct pwm_device *pwm,
291 const struct pwm_state *state)
292{
293 struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
294 struct imx_tpm_pwm_param param;
295 struct pwm_state real_state;
296 int ret;
297
298 ret = pwm_imx_tpm_round_state(chip, ¶m, &real_state, state);
299 if (ret)
300 return ret;
301
302 mutex_lock(&tpm->lock);
303 ret = pwm_imx_tpm_apply_hw(chip, ¶m, &real_state, pwm);
304 mutex_unlock(&tpm->lock);
305
306 return ret;
307}
308
309static int pwm_imx_tpm_request(struct pwm_chip *chip, struct pwm_device *pwm)
310{
311 struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
312
313 mutex_lock(&tpm->lock);
314 tpm->user_count++;
315 mutex_unlock(&tpm->lock);
316
317 return 0;
318}
319
320static void pwm_imx_tpm_free(struct pwm_chip *chip, struct pwm_device *pwm)
321{
322 struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
323
324 mutex_lock(&tpm->lock);
325 tpm->user_count--;
326 mutex_unlock(&tpm->lock);
327}
328
329static const struct pwm_ops imx_tpm_pwm_ops = {
330 .request = pwm_imx_tpm_request,
331 .free = pwm_imx_tpm_free,
332 .get_state = pwm_imx_tpm_get_state,
333 .apply = pwm_imx_tpm_apply,
334};
335
336static int pwm_imx_tpm_probe(struct platform_device *pdev)
337{
338 struct pwm_chip *chip;
339 struct imx_tpm_pwm_chip *tpm;
340 struct clk *clk;
341 void __iomem *base;
342 int ret;
343 unsigned int npwm;
344 u32 val;
345
346 base = devm_platform_ioremap_resource(pdev, 0);
347 if (IS_ERR(base))
348 return PTR_ERR(base);
349
350 clk = devm_clk_get_enabled(&pdev->dev, NULL);
351 if (IS_ERR(clk))
352 return dev_err_probe(&pdev->dev, PTR_ERR(clk),
353 "failed to get PWM clock\n");
354
355 /* get number of channels */
356 val = readl(base + PWM_IMX_TPM_PARAM);
357 npwm = FIELD_GET(PWM_IMX_TPM_PARAM_CHAN, val);
358
359 chip = devm_pwmchip_alloc(&pdev->dev, npwm, sizeof(*tpm));
360 if (IS_ERR(chip))
361 return PTR_ERR(chip);
362 tpm = to_imx_tpm_pwm_chip(chip);
363
364 platform_set_drvdata(pdev, tpm);
365
366 tpm->base = base;
367 tpm->clk = clk;
368
369 chip->ops = &imx_tpm_pwm_ops;
370
371 mutex_init(&tpm->lock);
372
373 ret = devm_pwmchip_add(&pdev->dev, chip);
374 if (ret)
375 return dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n");
376
377 return 0;
378}
379
380static int pwm_imx_tpm_suspend(struct device *dev)
381{
382 struct imx_tpm_pwm_chip *tpm = dev_get_drvdata(dev);
383
384 if (tpm->enable_count > 0)
385 return -EBUSY;
386
387 /*
388 * Force 'real_period' to be zero to force period update code
389 * can be executed after system resume back, since suspend causes
390 * the period related registers to become their reset values.
391 */
392 tpm->real_period = 0;
393
394 clk_disable_unprepare(tpm->clk);
395
396 return 0;
397}
398
399static int pwm_imx_tpm_resume(struct device *dev)
400{
401 struct imx_tpm_pwm_chip *tpm = dev_get_drvdata(dev);
402 int ret = 0;
403
404 ret = clk_prepare_enable(tpm->clk);
405 if (ret)
406 dev_err(dev, "failed to prepare or enable clock: %d\n", ret);
407
408 return ret;
409}
410
411static DEFINE_SIMPLE_DEV_PM_OPS(imx_tpm_pwm_pm,
412 pwm_imx_tpm_suspend, pwm_imx_tpm_resume);
413
414static const struct of_device_id imx_tpm_pwm_dt_ids[] = {
415 { .compatible = "fsl,imx7ulp-pwm", },
416 { /* sentinel */ }
417};
418MODULE_DEVICE_TABLE(of, imx_tpm_pwm_dt_ids);
419
420static struct platform_driver imx_tpm_pwm_driver = {
421 .driver = {
422 .name = "imx7ulp-tpm-pwm",
423 .of_match_table = imx_tpm_pwm_dt_ids,
424 .pm = pm_ptr(&imx_tpm_pwm_pm),
425 },
426 .probe = pwm_imx_tpm_probe,
427};
428module_platform_driver(imx_tpm_pwm_driver);
429
430MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
431MODULE_DESCRIPTION("i.MX TPM PWM Driver");
432MODULE_LICENSE("GPL v2");