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1// SPDX-License-Identifier: GPL-2.0+
2/* drivers/net/phy/realtek.c
3 *
4 * Driver for Realtek PHYs
5 *
6 * Author: Johnson Leung <r58129@freescale.com>
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 */
10#include <linux/bitops.h>
11#include <linux/of.h>
12#include <linux/phy.h>
13#include <linux/module.h>
14#include <linux/delay.h>
15#include <linux/clk.h>
16
17#define RTL821x_PHYSR 0x11
18#define RTL821x_PHYSR_DUPLEX BIT(13)
19#define RTL821x_PHYSR_SPEED GENMASK(15, 14)
20
21#define RTL821x_INER 0x12
22#define RTL8211B_INER_INIT 0x6400
23#define RTL8211E_INER_LINK_STATUS BIT(10)
24#define RTL8211F_INER_LINK_STATUS BIT(4)
25
26#define RTL821x_INSR 0x13
27
28#define RTL821x_EXT_PAGE_SELECT 0x1e
29#define RTL821x_PAGE_SELECT 0x1f
30
31#define RTL8211F_PHYCR1 0x18
32#define RTL8211F_PHYCR2 0x19
33#define RTL8211F_INSR 0x1d
34
35#define RTL8211F_LEDCR 0x10
36#define RTL8211F_LEDCR_MODE BIT(15)
37#define RTL8211F_LEDCR_ACT_TXRX BIT(4)
38#define RTL8211F_LEDCR_LINK_1000 BIT(3)
39#define RTL8211F_LEDCR_LINK_100 BIT(1)
40#define RTL8211F_LEDCR_LINK_10 BIT(0)
41#define RTL8211F_LEDCR_MASK GENMASK(4, 0)
42#define RTL8211F_LEDCR_SHIFT 5
43
44#define RTL8211F_TX_DELAY BIT(8)
45#define RTL8211F_RX_DELAY BIT(3)
46
47#define RTL8211F_ALDPS_PLL_OFF BIT(1)
48#define RTL8211F_ALDPS_ENABLE BIT(2)
49#define RTL8211F_ALDPS_XTAL_OFF BIT(12)
50
51#define RTL8211E_CTRL_DELAY BIT(13)
52#define RTL8211E_TX_DELAY BIT(12)
53#define RTL8211E_RX_DELAY BIT(11)
54
55#define RTL8211F_CLKOUT_EN BIT(0)
56
57#define RTL8201F_ISR 0x1e
58#define RTL8201F_ISR_ANERR BIT(15)
59#define RTL8201F_ISR_DUPLEX BIT(13)
60#define RTL8201F_ISR_LINK BIT(11)
61#define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \
62 RTL8201F_ISR_DUPLEX | \
63 RTL8201F_ISR_LINK)
64#define RTL8201F_IER 0x13
65
66#define RTL822X_VND1_SERDES_OPTION 0x697a
67#define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0)
68#define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0
69#define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2
70
71#define RTL822X_VND1_SERDES_CTRL3 0x7580
72#define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0)
73#define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02
74#define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16
75
76/* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45
77 * is set, they cannot be accessed by C45-over-C22.
78 */
79#define RTL822X_VND2_GBCR 0xa412
80
81#define RTL822X_VND2_GANLPAR 0xa414
82
83#define RTL8366RB_POWER_SAVE 0x15
84#define RTL8366RB_POWER_SAVE_ON BIT(12)
85
86#define RTL9000A_GINMR 0x14
87#define RTL9000A_GINMR_LINK_STATUS BIT(4)
88
89#define RTL_VND2_PHYSR 0xa434
90#define RTL_VND2_PHYSR_DUPLEX BIT(3)
91#define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4)
92#define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9)
93#define RTL_VND2_PHYSR_MASTER BIT(11)
94#define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH)
95
96#define RTL_GENERIC_PHYID 0x001cc800
97#define RTL_8211FVD_PHYID 0x001cc878
98#define RTL_8221B 0x001cc840
99#define RTL_8221B_VB_CG 0x001cc849
100#define RTL_8221B_VN_CG 0x001cc84a
101#define RTL_8251B 0x001cc862
102
103#define RTL8211F_LED_COUNT 3
104
105MODULE_DESCRIPTION("Realtek PHY driver");
106MODULE_AUTHOR("Johnson Leung");
107MODULE_LICENSE("GPL");
108
109struct rtl821x_priv {
110 u16 phycr1;
111 u16 phycr2;
112 bool has_phycr2;
113 struct clk *clk;
114};
115
116static int rtl821x_read_page(struct phy_device *phydev)
117{
118 return __phy_read(phydev, RTL821x_PAGE_SELECT);
119}
120
121static int rtl821x_write_page(struct phy_device *phydev, int page)
122{
123 return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
124}
125
126static int rtl821x_probe(struct phy_device *phydev)
127{
128 struct device *dev = &phydev->mdio.dev;
129 struct rtl821x_priv *priv;
130 u32 phy_id = phydev->drv->phy_id;
131 int ret;
132
133 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
134 if (!priv)
135 return -ENOMEM;
136
137 priv->clk = devm_clk_get_optional_enabled(dev, NULL);
138 if (IS_ERR(priv->clk))
139 return dev_err_probe(dev, PTR_ERR(priv->clk),
140 "failed to get phy clock\n");
141
142 ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR1);
143 if (ret < 0)
144 return ret;
145
146 priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF);
147 if (of_property_read_bool(dev->of_node, "realtek,aldps-enable"))
148 priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF;
149
150 priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID);
151 if (priv->has_phycr2) {
152 ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR2);
153 if (ret < 0)
154 return ret;
155
156 priv->phycr2 = ret & RTL8211F_CLKOUT_EN;
157 if (of_property_read_bool(dev->of_node, "realtek,clkout-disable"))
158 priv->phycr2 &= ~RTL8211F_CLKOUT_EN;
159 }
160
161 phydev->priv = priv;
162
163 return 0;
164}
165
166static int rtl8201_ack_interrupt(struct phy_device *phydev)
167{
168 int err;
169
170 err = phy_read(phydev, RTL8201F_ISR);
171
172 return (err < 0) ? err : 0;
173}
174
175static int rtl821x_ack_interrupt(struct phy_device *phydev)
176{
177 int err;
178
179 err = phy_read(phydev, RTL821x_INSR);
180
181 return (err < 0) ? err : 0;
182}
183
184static int rtl8211f_ack_interrupt(struct phy_device *phydev)
185{
186 int err;
187
188 err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
189
190 return (err < 0) ? err : 0;
191}
192
193static int rtl8201_config_intr(struct phy_device *phydev)
194{
195 u16 val;
196 int err;
197
198 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
199 err = rtl8201_ack_interrupt(phydev);
200 if (err)
201 return err;
202
203 val = BIT(13) | BIT(12) | BIT(11);
204 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
205 } else {
206 val = 0;
207 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
208 if (err)
209 return err;
210
211 err = rtl8201_ack_interrupt(phydev);
212 }
213
214 return err;
215}
216
217static int rtl8211b_config_intr(struct phy_device *phydev)
218{
219 int err;
220
221 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
222 err = rtl821x_ack_interrupt(phydev);
223 if (err)
224 return err;
225
226 err = phy_write(phydev, RTL821x_INER,
227 RTL8211B_INER_INIT);
228 } else {
229 err = phy_write(phydev, RTL821x_INER, 0);
230 if (err)
231 return err;
232
233 err = rtl821x_ack_interrupt(phydev);
234 }
235
236 return err;
237}
238
239static int rtl8211e_config_intr(struct phy_device *phydev)
240{
241 int err;
242
243 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
244 err = rtl821x_ack_interrupt(phydev);
245 if (err)
246 return err;
247
248 err = phy_write(phydev, RTL821x_INER,
249 RTL8211E_INER_LINK_STATUS);
250 } else {
251 err = phy_write(phydev, RTL821x_INER, 0);
252 if (err)
253 return err;
254
255 err = rtl821x_ack_interrupt(phydev);
256 }
257
258 return err;
259}
260
261static int rtl8211f_config_intr(struct phy_device *phydev)
262{
263 u16 val;
264 int err;
265
266 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
267 err = rtl8211f_ack_interrupt(phydev);
268 if (err)
269 return err;
270
271 val = RTL8211F_INER_LINK_STATUS;
272 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
273 } else {
274 val = 0;
275 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
276 if (err)
277 return err;
278
279 err = rtl8211f_ack_interrupt(phydev);
280 }
281
282 return err;
283}
284
285static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev)
286{
287 int irq_status;
288
289 irq_status = phy_read(phydev, RTL8201F_ISR);
290 if (irq_status < 0) {
291 phy_error(phydev);
292 return IRQ_NONE;
293 }
294
295 if (!(irq_status & RTL8201F_ISR_MASK))
296 return IRQ_NONE;
297
298 phy_trigger_machine(phydev);
299
300 return IRQ_HANDLED;
301}
302
303static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev)
304{
305 int irq_status, irq_enabled;
306
307 irq_status = phy_read(phydev, RTL821x_INSR);
308 if (irq_status < 0) {
309 phy_error(phydev);
310 return IRQ_NONE;
311 }
312
313 irq_enabled = phy_read(phydev, RTL821x_INER);
314 if (irq_enabled < 0) {
315 phy_error(phydev);
316 return IRQ_NONE;
317 }
318
319 if (!(irq_status & irq_enabled))
320 return IRQ_NONE;
321
322 phy_trigger_machine(phydev);
323
324 return IRQ_HANDLED;
325}
326
327static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev)
328{
329 int irq_status;
330
331 irq_status = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
332 if (irq_status < 0) {
333 phy_error(phydev);
334 return IRQ_NONE;
335 }
336
337 if (!(irq_status & RTL8211F_INER_LINK_STATUS))
338 return IRQ_NONE;
339
340 phy_trigger_machine(phydev);
341
342 return IRQ_HANDLED;
343}
344
345static int rtl8211_config_aneg(struct phy_device *phydev)
346{
347 int ret;
348
349 ret = genphy_config_aneg(phydev);
350 if (ret < 0)
351 return ret;
352
353 /* Quirk was copied from vendor driver. Unfortunately it includes no
354 * description of the magic numbers.
355 */
356 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
357 phy_write(phydev, 0x17, 0x2138);
358 phy_write(phydev, 0x0e, 0x0260);
359 } else {
360 phy_write(phydev, 0x17, 0x2108);
361 phy_write(phydev, 0x0e, 0x0000);
362 }
363
364 return 0;
365}
366
367static int rtl8211c_config_init(struct phy_device *phydev)
368{
369 /* RTL8211C has an issue when operating in Gigabit slave mode */
370 return phy_set_bits(phydev, MII_CTRL1000,
371 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
372}
373
374static int rtl8211f_config_init(struct phy_device *phydev)
375{
376 struct rtl821x_priv *priv = phydev->priv;
377 struct device *dev = &phydev->mdio.dev;
378 u16 val_txdly, val_rxdly;
379 int ret;
380
381 ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1,
382 RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF,
383 priv->phycr1);
384 if (ret < 0) {
385 dev_err(dev, "aldps mode configuration failed: %pe\n",
386 ERR_PTR(ret));
387 return ret;
388 }
389
390 switch (phydev->interface) {
391 case PHY_INTERFACE_MODE_RGMII:
392 val_txdly = 0;
393 val_rxdly = 0;
394 break;
395
396 case PHY_INTERFACE_MODE_RGMII_RXID:
397 val_txdly = 0;
398 val_rxdly = RTL8211F_RX_DELAY;
399 break;
400
401 case PHY_INTERFACE_MODE_RGMII_TXID:
402 val_txdly = RTL8211F_TX_DELAY;
403 val_rxdly = 0;
404 break;
405
406 case PHY_INTERFACE_MODE_RGMII_ID:
407 val_txdly = RTL8211F_TX_DELAY;
408 val_rxdly = RTL8211F_RX_DELAY;
409 break;
410
411 default: /* the rest of the modes imply leaving delay as is. */
412 return 0;
413 }
414
415 ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
416 val_txdly);
417 if (ret < 0) {
418 dev_err(dev, "Failed to update the TX delay register\n");
419 return ret;
420 } else if (ret) {
421 dev_dbg(dev,
422 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
423 val_txdly ? "Enabling" : "Disabling");
424 } else {
425 dev_dbg(dev,
426 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
427 val_txdly ? "enabled" : "disabled");
428 }
429
430 ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY,
431 val_rxdly);
432 if (ret < 0) {
433 dev_err(dev, "Failed to update the RX delay register\n");
434 return ret;
435 } else if (ret) {
436 dev_dbg(dev,
437 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
438 val_rxdly ? "Enabling" : "Disabling");
439 } else {
440 dev_dbg(dev,
441 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
442 val_rxdly ? "enabled" : "disabled");
443 }
444
445 if (priv->has_phycr2) {
446 ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2,
447 RTL8211F_CLKOUT_EN, priv->phycr2);
448 if (ret < 0) {
449 dev_err(dev, "clkout configuration failed: %pe\n",
450 ERR_PTR(ret));
451 return ret;
452 }
453
454 return genphy_soft_reset(phydev);
455 }
456
457 return 0;
458}
459
460static int rtl821x_suspend(struct phy_device *phydev)
461{
462 struct rtl821x_priv *priv = phydev->priv;
463 int ret = 0;
464
465 if (!phydev->wol_enabled) {
466 ret = genphy_suspend(phydev);
467
468 if (ret)
469 return ret;
470
471 clk_disable_unprepare(priv->clk);
472 }
473
474 return ret;
475}
476
477static int rtl821x_resume(struct phy_device *phydev)
478{
479 struct rtl821x_priv *priv = phydev->priv;
480 int ret;
481
482 if (!phydev->wol_enabled)
483 clk_prepare_enable(priv->clk);
484
485 ret = genphy_resume(phydev);
486 if (ret < 0)
487 return ret;
488
489 msleep(20);
490
491 return 0;
492}
493
494static int rtl8211f_led_hw_is_supported(struct phy_device *phydev, u8 index,
495 unsigned long rules)
496{
497 const unsigned long mask = BIT(TRIGGER_NETDEV_LINK_10) |
498 BIT(TRIGGER_NETDEV_LINK_100) |
499 BIT(TRIGGER_NETDEV_LINK_1000) |
500 BIT(TRIGGER_NETDEV_RX) |
501 BIT(TRIGGER_NETDEV_TX);
502
503 /* The RTL8211F PHY supports these LED settings on up to three LEDs:
504 * - Link: Configurable subset of 10/100/1000 link rates
505 * - Active: Blink on activity, RX or TX is not differentiated
506 * The Active option has two modes, A and B:
507 * - A: Link and Active indication at configurable, but matching,
508 * subset of 10/100/1000 link rates
509 * - B: Link indication at configurable subset of 10/100/1000 link
510 * rates and Active indication always at all three 10+100+1000
511 * link rates.
512 * This code currently uses mode B only.
513 */
514
515 if (index >= RTL8211F_LED_COUNT)
516 return -EINVAL;
517
518 /* Filter out any other unsupported triggers. */
519 if (rules & ~mask)
520 return -EOPNOTSUPP;
521
522 /* RX and TX are not differentiated, either both are set or not set. */
523 if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX)))
524 return -EOPNOTSUPP;
525
526 return 0;
527}
528
529static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index,
530 unsigned long *rules)
531{
532 int val;
533
534 if (index >= RTL8211F_LED_COUNT)
535 return -EINVAL;
536
537 val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR);
538 if (val < 0)
539 return val;
540
541 val >>= RTL8211F_LEDCR_SHIFT * index;
542 val &= RTL8211F_LEDCR_MASK;
543
544 if (val & RTL8211F_LEDCR_LINK_10)
545 set_bit(TRIGGER_NETDEV_LINK_10, rules);
546
547 if (val & RTL8211F_LEDCR_LINK_100)
548 set_bit(TRIGGER_NETDEV_LINK_100, rules);
549
550 if (val & RTL8211F_LEDCR_LINK_1000)
551 set_bit(TRIGGER_NETDEV_LINK_1000, rules);
552
553 if (val & RTL8211F_LEDCR_ACT_TXRX) {
554 set_bit(TRIGGER_NETDEV_RX, rules);
555 set_bit(TRIGGER_NETDEV_TX, rules);
556 }
557
558 return 0;
559}
560
561static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index,
562 unsigned long rules)
563{
564 const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index);
565 u16 reg = 0;
566
567 if (index >= RTL8211F_LED_COUNT)
568 return -EINVAL;
569
570 if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
571 reg |= RTL8211F_LEDCR_LINK_10;
572
573 if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
574 reg |= RTL8211F_LEDCR_LINK_100;
575
576 if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
577 reg |= RTL8211F_LEDCR_LINK_1000;
578
579 if (test_bit(TRIGGER_NETDEV_RX, &rules) ||
580 test_bit(TRIGGER_NETDEV_TX, &rules)) {
581 reg |= RTL8211F_LEDCR_ACT_TXRX;
582 }
583
584 reg <<= RTL8211F_LEDCR_SHIFT * index;
585 reg |= RTL8211F_LEDCR_MODE; /* Mode B */
586
587 return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg);
588}
589
590static int rtl8211e_config_init(struct phy_device *phydev)
591{
592 int ret = 0, oldpage;
593 u16 val;
594
595 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
596 switch (phydev->interface) {
597 case PHY_INTERFACE_MODE_RGMII:
598 val = RTL8211E_CTRL_DELAY | 0;
599 break;
600 case PHY_INTERFACE_MODE_RGMII_ID:
601 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
602 break;
603 case PHY_INTERFACE_MODE_RGMII_RXID:
604 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY;
605 break;
606 case PHY_INTERFACE_MODE_RGMII_TXID:
607 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY;
608 break;
609 default: /* the rest of the modes imply leaving delays as is. */
610 return 0;
611 }
612
613 /* According to a sample driver there is a 0x1c config register on the
614 * 0xa4 extension page (0x7) layout. It can be used to disable/enable
615 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins.
616 * The configuration register definition:
617 * 14 = reserved
618 * 13 = Force Tx RX Delay controlled by bit12 bit11,
619 * 12 = RX Delay, 11 = TX Delay
620 * 10:0 = Test && debug settings reserved by realtek
621 */
622 oldpage = phy_select_page(phydev, 0x7);
623 if (oldpage < 0)
624 goto err_restore_page;
625
626 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
627 if (ret)
628 goto err_restore_page;
629
630 ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY
631 | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
632 val);
633
634err_restore_page:
635 return phy_restore_page(phydev, oldpage, ret);
636}
637
638static int rtl8211b_suspend(struct phy_device *phydev)
639{
640 phy_write(phydev, MII_MMD_DATA, BIT(9));
641
642 return genphy_suspend(phydev);
643}
644
645static int rtl8211b_resume(struct phy_device *phydev)
646{
647 phy_write(phydev, MII_MMD_DATA, 0);
648
649 return genphy_resume(phydev);
650}
651
652static int rtl8366rb_config_init(struct phy_device *phydev)
653{
654 int ret;
655
656 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
657 RTL8366RB_POWER_SAVE_ON);
658 if (ret) {
659 dev_err(&phydev->mdio.dev,
660 "error enabling power management\n");
661 }
662
663 return ret;
664}
665
666/* get actual speed to cover the downshift case */
667static void rtlgen_decode_physr(struct phy_device *phydev, int val)
668{
669 /* bit 3
670 * 0: Half Duplex
671 * 1: Full Duplex
672 */
673 if (val & RTL_VND2_PHYSR_DUPLEX)
674 phydev->duplex = DUPLEX_FULL;
675 else
676 phydev->duplex = DUPLEX_HALF;
677
678 switch (val & RTL_VND2_PHYSR_SPEED_MASK) {
679 case 0x0000:
680 phydev->speed = SPEED_10;
681 break;
682 case 0x0010:
683 phydev->speed = SPEED_100;
684 break;
685 case 0x0020:
686 phydev->speed = SPEED_1000;
687 break;
688 case 0x0200:
689 phydev->speed = SPEED_10000;
690 break;
691 case 0x0210:
692 phydev->speed = SPEED_2500;
693 break;
694 case 0x0220:
695 phydev->speed = SPEED_5000;
696 break;
697 default:
698 break;
699 }
700
701 /* bit 11
702 * 0: Slave Mode
703 * 1: Master Mode
704 */
705 if (phydev->speed >= 1000) {
706 if (val & RTL_VND2_PHYSR_MASTER)
707 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
708 else
709 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
710 } else {
711 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
712 }
713}
714
715static int rtlgen_read_status(struct phy_device *phydev)
716{
717 int ret, val;
718
719 ret = genphy_read_status(phydev);
720 if (ret < 0)
721 return ret;
722
723 if (!phydev->link)
724 return 0;
725
726 val = phy_read_paged(phydev, 0xa43, 0x12);
727 if (val < 0)
728 return val;
729
730 rtlgen_decode_physr(phydev, val);
731
732 return 0;
733}
734
735static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
736{
737 int ret;
738
739 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
740 rtl821x_write_page(phydev, 0xa5c);
741 ret = __phy_read(phydev, 0x12);
742 rtl821x_write_page(phydev, 0);
743 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
744 rtl821x_write_page(phydev, 0xa5d);
745 ret = __phy_read(phydev, 0x10);
746 rtl821x_write_page(phydev, 0);
747 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
748 rtl821x_write_page(phydev, 0xa5d);
749 ret = __phy_read(phydev, 0x11);
750 rtl821x_write_page(phydev, 0);
751 } else {
752 ret = -EOPNOTSUPP;
753 }
754
755 return ret;
756}
757
758static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
759 u16 val)
760{
761 int ret;
762
763 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
764 rtl821x_write_page(phydev, 0xa5d);
765 ret = __phy_write(phydev, 0x10, val);
766 rtl821x_write_page(phydev, 0);
767 } else {
768 ret = -EOPNOTSUPP;
769 }
770
771 return ret;
772}
773
774static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
775{
776 int ret = rtlgen_read_mmd(phydev, devnum, regnum);
777
778 if (ret != -EOPNOTSUPP)
779 return ret;
780
781 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
782 rtl821x_write_page(phydev, 0xa6e);
783 ret = __phy_read(phydev, 0x16);
784 rtl821x_write_page(phydev, 0);
785 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
786 rtl821x_write_page(phydev, 0xa6d);
787 ret = __phy_read(phydev, 0x12);
788 rtl821x_write_page(phydev, 0);
789 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
790 rtl821x_write_page(phydev, 0xa6d);
791 ret = __phy_read(phydev, 0x10);
792 rtl821x_write_page(phydev, 0);
793 }
794
795 return ret;
796}
797
798static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
799 u16 val)
800{
801 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
802
803 if (ret != -EOPNOTSUPP)
804 return ret;
805
806 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
807 rtl821x_write_page(phydev, 0xa6d);
808 ret = __phy_write(phydev, 0x12, val);
809 rtl821x_write_page(phydev, 0);
810 }
811
812 return ret;
813}
814
815static int rtl822xb_config_init(struct phy_device *phydev)
816{
817 bool has_2500, has_sgmii;
818 u16 mode;
819 int ret;
820
821 has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX,
822 phydev->host_interfaces) ||
823 phydev->interface == PHY_INTERFACE_MODE_2500BASEX;
824
825 has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII,
826 phydev->host_interfaces) ||
827 phydev->interface == PHY_INTERFACE_MODE_SGMII;
828
829 /* fill in possible interfaces */
830 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces,
831 has_2500);
832 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces,
833 has_sgmii);
834
835 if (!has_2500 && !has_sgmii)
836 return 0;
837
838 /* determine SerDes option mode */
839 if (has_2500 && !has_sgmii) {
840 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX;
841 phydev->rate_matching = RATE_MATCH_PAUSE;
842 } else {
843 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII;
844 phydev->rate_matching = RATE_MATCH_NONE;
845 }
846
847 /* the following sequence with magic numbers sets up the SerDes
848 * option mode
849 */
850 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0);
851 if (ret < 0)
852 return ret;
853
854 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1,
855 RTL822X_VND1_SERDES_OPTION,
856 RTL822X_VND1_SERDES_OPTION_MODE_MASK,
857 mode);
858 if (ret < 0)
859 return ret;
860
861 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503);
862 if (ret < 0)
863 return ret;
864
865 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455);
866 if (ret < 0)
867 return ret;
868
869 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020);
870}
871
872static int rtl822xb_get_rate_matching(struct phy_device *phydev,
873 phy_interface_t iface)
874{
875 int val;
876
877 /* Only rate matching at 2500base-x */
878 if (iface != PHY_INTERFACE_MODE_2500BASEX)
879 return RATE_MATCH_NONE;
880
881 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION);
882 if (val < 0)
883 return val;
884
885 if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) ==
886 RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX)
887 return RATE_MATCH_PAUSE;
888
889 /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */
890 return RATE_MATCH_NONE;
891}
892
893static int rtl822x_get_features(struct phy_device *phydev)
894{
895 int val;
896
897 val = phy_read_paged(phydev, 0xa61, 0x13);
898 if (val < 0)
899 return val;
900
901 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
902 phydev->supported, val & MDIO_PMA_SPEED_2_5G);
903 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
904 phydev->supported, val & MDIO_PMA_SPEED_5G);
905 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
906 phydev->supported, val & MDIO_SPEED_10G);
907
908 return genphy_read_abilities(phydev);
909}
910
911static int rtl822x_config_aneg(struct phy_device *phydev)
912{
913 int ret = 0;
914
915 if (phydev->autoneg == AUTONEG_ENABLE) {
916 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
917
918 ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
919 MDIO_AN_10GBT_CTRL_ADV2_5G |
920 MDIO_AN_10GBT_CTRL_ADV5G,
921 adv);
922 if (ret < 0)
923 return ret;
924 }
925
926 return __genphy_config_aneg(phydev, ret);
927}
928
929static void rtl822xb_update_interface(struct phy_device *phydev)
930{
931 int val;
932
933 if (!phydev->link)
934 return;
935
936 /* Change interface according to serdes mode */
937 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3);
938 if (val < 0)
939 return;
940
941 switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) {
942 case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX:
943 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
944 break;
945 case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII:
946 phydev->interface = PHY_INTERFACE_MODE_SGMII;
947 break;
948 }
949}
950
951static int rtl822x_read_status(struct phy_device *phydev)
952{
953 int lpadv, ret;
954
955 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
956
957 ret = rtlgen_read_status(phydev);
958 if (ret < 0)
959 return ret;
960
961 if (phydev->autoneg == AUTONEG_DISABLE ||
962 !phydev->autoneg_complete)
963 return 0;
964
965 lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
966 if (lpadv < 0)
967 return lpadv;
968
969 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv);
970
971 return 0;
972}
973
974static int rtl822xb_read_status(struct phy_device *phydev)
975{
976 int ret;
977
978 ret = rtl822x_read_status(phydev);
979 if (ret < 0)
980 return ret;
981
982 rtl822xb_update_interface(phydev);
983
984 return 0;
985}
986
987static int rtl822x_c45_get_features(struct phy_device *phydev)
988{
989 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
990 phydev->supported);
991
992 return genphy_c45_pma_read_abilities(phydev);
993}
994
995static int rtl822x_c45_config_aneg(struct phy_device *phydev)
996{
997 bool changed = false;
998 int ret, val;
999
1000 if (phydev->autoneg == AUTONEG_DISABLE)
1001 return genphy_c45_pma_setup_forced(phydev);
1002
1003 ret = genphy_c45_an_config_aneg(phydev);
1004 if (ret < 0)
1005 return ret;
1006 if (ret > 0)
1007 changed = true;
1008
1009 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
1010
1011 /* Vendor register as C45 has no standardized support for 1000BaseT */
1012 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, RTL822X_VND2_GBCR,
1013 ADVERTISE_1000FULL, val);
1014 if (ret < 0)
1015 return ret;
1016 if (ret > 0)
1017 changed = true;
1018
1019 return genphy_c45_check_and_restart_aneg(phydev, changed);
1020}
1021
1022static int rtl822x_c45_read_status(struct phy_device *phydev)
1023{
1024 int ret, val;
1025
1026 /* Vendor register as C45 has no standardized support for 1000BaseT */
1027 if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) {
1028 val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1029 RTL822X_VND2_GANLPAR);
1030 if (val < 0)
1031 return val;
1032 } else {
1033 val = 0;
1034 }
1035 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
1036
1037 ret = genphy_c45_read_status(phydev);
1038 if (ret < 0)
1039 return ret;
1040
1041 if (!phydev->link) {
1042 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
1043 return 0;
1044 }
1045
1046 /* Read actual speed from vendor register. */
1047 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR);
1048 if (val < 0)
1049 return val;
1050
1051 rtlgen_decode_physr(phydev, val);
1052
1053 return 0;
1054}
1055
1056static int rtl822xb_c45_read_status(struct phy_device *phydev)
1057{
1058 int ret;
1059
1060 ret = rtl822x_c45_read_status(phydev);
1061 if (ret < 0)
1062 return ret;
1063
1064 rtl822xb_update_interface(phydev);
1065
1066 return 0;
1067}
1068
1069static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
1070{
1071 int val;
1072
1073 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
1074 val = phy_read(phydev, 0x13);
1075 phy_write(phydev, RTL821x_PAGE_SELECT, 0);
1076
1077 return val >= 0 && val & MDIO_PMA_SPEED_2_5G;
1078}
1079
1080/* On internal PHY's MMD reads over C22 always return 0.
1081 * Check a MMD register which is known to be non-zero.
1082 */
1083static bool rtlgen_supports_mmd(struct phy_device *phydev)
1084{
1085 int val;
1086
1087 phy_lock_mdio_bus(phydev);
1088 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS);
1089 __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE);
1090 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR);
1091 val = __phy_read(phydev, MII_MMD_DATA);
1092 phy_unlock_mdio_bus(phydev);
1093
1094 return val > 0;
1095}
1096
1097static int rtlgen_match_phy_device(struct phy_device *phydev)
1098{
1099 return phydev->phy_id == RTL_GENERIC_PHYID &&
1100 !rtlgen_supports_2_5gbps(phydev);
1101}
1102
1103static int rtl8226_match_phy_device(struct phy_device *phydev)
1104{
1105 return phydev->phy_id == RTL_GENERIC_PHYID &&
1106 rtlgen_supports_2_5gbps(phydev) &&
1107 rtlgen_supports_mmd(phydev);
1108}
1109
1110static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id,
1111 bool is_c45)
1112{
1113 if (phydev->is_c45)
1114 return is_c45 && (id == phydev->c45_ids.device_ids[1]);
1115 else
1116 return !is_c45 && (id == phydev->phy_id);
1117}
1118
1119static int rtl8221b_match_phy_device(struct phy_device *phydev)
1120{
1121 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev);
1122}
1123
1124static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev)
1125{
1126 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false);
1127}
1128
1129static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev)
1130{
1131 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true);
1132}
1133
1134static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev)
1135{
1136 return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, false);
1137}
1138
1139static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev)
1140{
1141 return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true);
1142}
1143
1144static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev)
1145{
1146 if (phydev->is_c45)
1147 return false;
1148
1149 switch (phydev->phy_id) {
1150 case RTL_GENERIC_PHYID:
1151 case RTL_8221B:
1152 case RTL_8251B:
1153 case 0x001cc841:
1154 break;
1155 default:
1156 return false;
1157 }
1158
1159 return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev);
1160}
1161
1162static int rtl8251b_c45_match_phy_device(struct phy_device *phydev)
1163{
1164 return rtlgen_is_c45_match(phydev, RTL_8251B, true);
1165}
1166
1167static int rtlgen_resume(struct phy_device *phydev)
1168{
1169 int ret = genphy_resume(phydev);
1170
1171 /* Internal PHY's from RTL8168h up may not be instantly ready */
1172 msleep(20);
1173
1174 return ret;
1175}
1176
1177static int rtlgen_c45_resume(struct phy_device *phydev)
1178{
1179 int ret = genphy_c45_pma_resume(phydev);
1180
1181 msleep(20);
1182
1183 return ret;
1184}
1185
1186static int rtl9000a_config_init(struct phy_device *phydev)
1187{
1188 phydev->autoneg = AUTONEG_DISABLE;
1189 phydev->speed = SPEED_100;
1190 phydev->duplex = DUPLEX_FULL;
1191
1192 return 0;
1193}
1194
1195static int rtl9000a_config_aneg(struct phy_device *phydev)
1196{
1197 int ret;
1198 u16 ctl = 0;
1199
1200 switch (phydev->master_slave_set) {
1201 case MASTER_SLAVE_CFG_MASTER_FORCE:
1202 ctl |= CTL1000_AS_MASTER;
1203 break;
1204 case MASTER_SLAVE_CFG_SLAVE_FORCE:
1205 break;
1206 case MASTER_SLAVE_CFG_UNKNOWN:
1207 case MASTER_SLAVE_CFG_UNSUPPORTED:
1208 return 0;
1209 default:
1210 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
1211 return -EOPNOTSUPP;
1212 }
1213
1214 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);
1215 if (ret == 1)
1216 ret = genphy_soft_reset(phydev);
1217
1218 return ret;
1219}
1220
1221static int rtl9000a_read_status(struct phy_device *phydev)
1222{
1223 int ret;
1224
1225 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
1226 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
1227
1228 ret = genphy_update_link(phydev);
1229 if (ret)
1230 return ret;
1231
1232 ret = phy_read(phydev, MII_CTRL1000);
1233 if (ret < 0)
1234 return ret;
1235 if (ret & CTL1000_AS_MASTER)
1236 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
1237 else
1238 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
1239
1240 ret = phy_read(phydev, MII_STAT1000);
1241 if (ret < 0)
1242 return ret;
1243 if (ret & LPA_1000MSRES)
1244 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
1245 else
1246 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
1247
1248 return 0;
1249}
1250
1251static int rtl9000a_ack_interrupt(struct phy_device *phydev)
1252{
1253 int err;
1254
1255 err = phy_read(phydev, RTL8211F_INSR);
1256
1257 return (err < 0) ? err : 0;
1258}
1259
1260static int rtl9000a_config_intr(struct phy_device *phydev)
1261{
1262 u16 val;
1263 int err;
1264
1265 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1266 err = rtl9000a_ack_interrupt(phydev);
1267 if (err)
1268 return err;
1269
1270 val = (u16)~RTL9000A_GINMR_LINK_STATUS;
1271 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1272 } else {
1273 val = ~0;
1274 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1275 if (err)
1276 return err;
1277
1278 err = rtl9000a_ack_interrupt(phydev);
1279 }
1280
1281 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1282}
1283
1284static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev)
1285{
1286 int irq_status;
1287
1288 irq_status = phy_read(phydev, RTL8211F_INSR);
1289 if (irq_status < 0) {
1290 phy_error(phydev);
1291 return IRQ_NONE;
1292 }
1293
1294 if (!(irq_status & RTL8211F_INER_LINK_STATUS))
1295 return IRQ_NONE;
1296
1297 phy_trigger_machine(phydev);
1298
1299 return IRQ_HANDLED;
1300}
1301
1302static struct phy_driver realtek_drvs[] = {
1303 {
1304 PHY_ID_MATCH_EXACT(0x00008201),
1305 .name = "RTL8201CP Ethernet",
1306 .read_page = rtl821x_read_page,
1307 .write_page = rtl821x_write_page,
1308 }, {
1309 PHY_ID_MATCH_EXACT(0x001cc816),
1310 .name = "RTL8201F Fast Ethernet",
1311 .config_intr = &rtl8201_config_intr,
1312 .handle_interrupt = rtl8201_handle_interrupt,
1313 .suspend = genphy_suspend,
1314 .resume = genphy_resume,
1315 .read_page = rtl821x_read_page,
1316 .write_page = rtl821x_write_page,
1317 }, {
1318 PHY_ID_MATCH_MODEL(0x001cc880),
1319 .name = "RTL8208 Fast Ethernet",
1320 .read_mmd = genphy_read_mmd_unsupported,
1321 .write_mmd = genphy_write_mmd_unsupported,
1322 .suspend = genphy_suspend,
1323 .resume = genphy_resume,
1324 .read_page = rtl821x_read_page,
1325 .write_page = rtl821x_write_page,
1326 }, {
1327 PHY_ID_MATCH_EXACT(0x001cc910),
1328 .name = "RTL8211 Gigabit Ethernet",
1329 .config_aneg = rtl8211_config_aneg,
1330 .read_mmd = &genphy_read_mmd_unsupported,
1331 .write_mmd = &genphy_write_mmd_unsupported,
1332 .read_page = rtl821x_read_page,
1333 .write_page = rtl821x_write_page,
1334 }, {
1335 PHY_ID_MATCH_EXACT(0x001cc912),
1336 .name = "RTL8211B Gigabit Ethernet",
1337 .config_intr = &rtl8211b_config_intr,
1338 .handle_interrupt = rtl821x_handle_interrupt,
1339 .read_mmd = &genphy_read_mmd_unsupported,
1340 .write_mmd = &genphy_write_mmd_unsupported,
1341 .suspend = rtl8211b_suspend,
1342 .resume = rtl8211b_resume,
1343 .read_page = rtl821x_read_page,
1344 .write_page = rtl821x_write_page,
1345 }, {
1346 PHY_ID_MATCH_EXACT(0x001cc913),
1347 .name = "RTL8211C Gigabit Ethernet",
1348 .config_init = rtl8211c_config_init,
1349 .read_mmd = &genphy_read_mmd_unsupported,
1350 .write_mmd = &genphy_write_mmd_unsupported,
1351 .read_page = rtl821x_read_page,
1352 .write_page = rtl821x_write_page,
1353 }, {
1354 PHY_ID_MATCH_EXACT(0x001cc914),
1355 .name = "RTL8211DN Gigabit Ethernet",
1356 .config_intr = rtl8211e_config_intr,
1357 .handle_interrupt = rtl821x_handle_interrupt,
1358 .suspend = genphy_suspend,
1359 .resume = genphy_resume,
1360 .read_page = rtl821x_read_page,
1361 .write_page = rtl821x_write_page,
1362 }, {
1363 PHY_ID_MATCH_EXACT(0x001cc915),
1364 .name = "RTL8211E Gigabit Ethernet",
1365 .config_init = &rtl8211e_config_init,
1366 .config_intr = &rtl8211e_config_intr,
1367 .handle_interrupt = rtl821x_handle_interrupt,
1368 .suspend = genphy_suspend,
1369 .resume = genphy_resume,
1370 .read_page = rtl821x_read_page,
1371 .write_page = rtl821x_write_page,
1372 }, {
1373 PHY_ID_MATCH_EXACT(0x001cc916),
1374 .name = "RTL8211F Gigabit Ethernet",
1375 .probe = rtl821x_probe,
1376 .config_init = &rtl8211f_config_init,
1377 .read_status = rtlgen_read_status,
1378 .config_intr = &rtl8211f_config_intr,
1379 .handle_interrupt = rtl8211f_handle_interrupt,
1380 .suspend = rtl821x_suspend,
1381 .resume = rtl821x_resume,
1382 .read_page = rtl821x_read_page,
1383 .write_page = rtl821x_write_page,
1384 .flags = PHY_ALWAYS_CALL_SUSPEND,
1385 .led_hw_is_supported = rtl8211f_led_hw_is_supported,
1386 .led_hw_control_get = rtl8211f_led_hw_control_get,
1387 .led_hw_control_set = rtl8211f_led_hw_control_set,
1388 }, {
1389 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID),
1390 .name = "RTL8211F-VD Gigabit Ethernet",
1391 .probe = rtl821x_probe,
1392 .config_init = &rtl8211f_config_init,
1393 .read_status = rtlgen_read_status,
1394 .config_intr = &rtl8211f_config_intr,
1395 .handle_interrupt = rtl8211f_handle_interrupt,
1396 .suspend = rtl821x_suspend,
1397 .resume = rtl821x_resume,
1398 .read_page = rtl821x_read_page,
1399 .write_page = rtl821x_write_page,
1400 .flags = PHY_ALWAYS_CALL_SUSPEND,
1401 }, {
1402 .name = "Generic FE-GE Realtek PHY",
1403 .match_phy_device = rtlgen_match_phy_device,
1404 .read_status = rtlgen_read_status,
1405 .suspend = genphy_suspend,
1406 .resume = rtlgen_resume,
1407 .read_page = rtl821x_read_page,
1408 .write_page = rtl821x_write_page,
1409 .read_mmd = rtlgen_read_mmd,
1410 .write_mmd = rtlgen_write_mmd,
1411 }, {
1412 .name = "RTL8226 2.5Gbps PHY",
1413 .match_phy_device = rtl8226_match_phy_device,
1414 .get_features = rtl822x_get_features,
1415 .config_aneg = rtl822x_config_aneg,
1416 .read_status = rtl822x_read_status,
1417 .suspend = genphy_suspend,
1418 .resume = rtlgen_resume,
1419 .read_page = rtl821x_read_page,
1420 .write_page = rtl821x_write_page,
1421 }, {
1422 .match_phy_device = rtl8221b_match_phy_device,
1423 .name = "RTL8226B_RTL8221B 2.5Gbps PHY",
1424 .get_features = rtl822x_get_features,
1425 .config_aneg = rtl822x_config_aneg,
1426 .config_init = rtl822xb_config_init,
1427 .get_rate_matching = rtl822xb_get_rate_matching,
1428 .read_status = rtl822xb_read_status,
1429 .suspend = genphy_suspend,
1430 .resume = rtlgen_resume,
1431 .read_page = rtl821x_read_page,
1432 .write_page = rtl821x_write_page,
1433 }, {
1434 PHY_ID_MATCH_EXACT(0x001cc838),
1435 .name = "RTL8226-CG 2.5Gbps PHY",
1436 .get_features = rtl822x_get_features,
1437 .config_aneg = rtl822x_config_aneg,
1438 .read_status = rtl822x_read_status,
1439 .suspend = genphy_suspend,
1440 .resume = rtlgen_resume,
1441 .read_page = rtl821x_read_page,
1442 .write_page = rtl821x_write_page,
1443 }, {
1444 PHY_ID_MATCH_EXACT(0x001cc848),
1445 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
1446 .get_features = rtl822x_get_features,
1447 .config_aneg = rtl822x_config_aneg,
1448 .config_init = rtl822xb_config_init,
1449 .get_rate_matching = rtl822xb_get_rate_matching,
1450 .read_status = rtl822xb_read_status,
1451 .suspend = genphy_suspend,
1452 .resume = rtlgen_resume,
1453 .read_page = rtl821x_read_page,
1454 .write_page = rtl821x_write_page,
1455 }, {
1456 .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device,
1457 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
1458 .get_features = rtl822x_get_features,
1459 .config_aneg = rtl822x_config_aneg,
1460 .config_init = rtl822xb_config_init,
1461 .get_rate_matching = rtl822xb_get_rate_matching,
1462 .read_status = rtl822xb_read_status,
1463 .suspend = genphy_suspend,
1464 .resume = rtlgen_resume,
1465 .read_page = rtl821x_read_page,
1466 .write_page = rtl821x_write_page,
1467 }, {
1468 .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device,
1469 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)",
1470 .config_init = rtl822xb_config_init,
1471 .get_rate_matching = rtl822xb_get_rate_matching,
1472 .get_features = rtl822x_c45_get_features,
1473 .config_aneg = rtl822x_c45_config_aneg,
1474 .read_status = rtl822xb_c45_read_status,
1475 .suspend = genphy_c45_pma_suspend,
1476 .resume = rtlgen_c45_resume,
1477 }, {
1478 .match_phy_device = rtl8221b_vn_cg_c22_match_phy_device,
1479 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)",
1480 .get_features = rtl822x_get_features,
1481 .config_aneg = rtl822x_config_aneg,
1482 .config_init = rtl822xb_config_init,
1483 .get_rate_matching = rtl822xb_get_rate_matching,
1484 .read_status = rtl822xb_read_status,
1485 .suspend = genphy_suspend,
1486 .resume = rtlgen_resume,
1487 .read_page = rtl821x_read_page,
1488 .write_page = rtl821x_write_page,
1489 }, {
1490 .match_phy_device = rtl8221b_vn_cg_c45_match_phy_device,
1491 .name = "RTL8221B-VN-CG 2.5Gbps PHY (C45)",
1492 .config_init = rtl822xb_config_init,
1493 .get_rate_matching = rtl822xb_get_rate_matching,
1494 .get_features = rtl822x_c45_get_features,
1495 .config_aneg = rtl822x_c45_config_aneg,
1496 .read_status = rtl822xb_c45_read_status,
1497 .suspend = genphy_c45_pma_suspend,
1498 .resume = rtlgen_c45_resume,
1499 }, {
1500 .match_phy_device = rtl8251b_c45_match_phy_device,
1501 .name = "RTL8251B 5Gbps PHY",
1502 .get_features = rtl822x_get_features,
1503 .config_aneg = rtl822x_config_aneg,
1504 .read_status = rtl822x_read_status,
1505 .suspend = genphy_suspend,
1506 .resume = rtlgen_resume,
1507 .read_page = rtl821x_read_page,
1508 .write_page = rtl821x_write_page,
1509 }, {
1510 .match_phy_device = rtl_internal_nbaset_match_phy_device,
1511 .name = "Realtek Internal NBASE-T PHY",
1512 .flags = PHY_IS_INTERNAL,
1513 .get_features = rtl822x_get_features,
1514 .config_aneg = rtl822x_config_aneg,
1515 .read_status = rtl822x_read_status,
1516 .suspend = genphy_suspend,
1517 .resume = rtlgen_resume,
1518 .read_page = rtl821x_read_page,
1519 .write_page = rtl821x_write_page,
1520 .read_mmd = rtl822x_read_mmd,
1521 .write_mmd = rtl822x_write_mmd,
1522 }, {
1523 PHY_ID_MATCH_EXACT(0x001ccad0),
1524 .name = "RTL8224 2.5Gbps PHY",
1525 .get_features = rtl822x_c45_get_features,
1526 .config_aneg = rtl822x_c45_config_aneg,
1527 .read_status = rtl822x_c45_read_status,
1528 .suspend = genphy_c45_pma_suspend,
1529 .resume = rtlgen_c45_resume,
1530 }, {
1531 PHY_ID_MATCH_EXACT(0x001cc961),
1532 .name = "RTL8366RB Gigabit Ethernet",
1533 .config_init = &rtl8366rb_config_init,
1534 /* These interrupts are handled by the irq controller
1535 * embedded inside the RTL8366RB, they get unmasked when the
1536 * irq is requested and ACKed by reading the status register,
1537 * which is done by the irqchip code.
1538 */
1539 .config_intr = genphy_no_config_intr,
1540 .handle_interrupt = genphy_handle_interrupt_no_ack,
1541 .suspend = genphy_suspend,
1542 .resume = genphy_resume,
1543 }, {
1544 PHY_ID_MATCH_EXACT(0x001ccb00),
1545 .name = "RTL9000AA_RTL9000AN Ethernet",
1546 .features = PHY_BASIC_T1_FEATURES,
1547 .config_init = rtl9000a_config_init,
1548 .config_aneg = rtl9000a_config_aneg,
1549 .read_status = rtl9000a_read_status,
1550 .config_intr = rtl9000a_config_intr,
1551 .handle_interrupt = rtl9000a_handle_interrupt,
1552 .suspend = genphy_suspend,
1553 .resume = genphy_resume,
1554 .read_page = rtl821x_read_page,
1555 .write_page = rtl821x_write_page,
1556 }, {
1557 PHY_ID_MATCH_EXACT(0x001cc942),
1558 .name = "RTL8365MB-VC Gigabit Ethernet",
1559 /* Interrupt handling analogous to RTL8366RB */
1560 .config_intr = genphy_no_config_intr,
1561 .handle_interrupt = genphy_handle_interrupt_no_ack,
1562 .suspend = genphy_suspend,
1563 .resume = genphy_resume,
1564 }, {
1565 PHY_ID_MATCH_EXACT(0x001cc960),
1566 .name = "RTL8366S Gigabit Ethernet",
1567 .suspend = genphy_suspend,
1568 .resume = genphy_resume,
1569 .read_mmd = genphy_read_mmd_unsupported,
1570 .write_mmd = genphy_write_mmd_unsupported,
1571 },
1572};
1573
1574module_phy_driver(realtek_drvs);
1575
1576static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
1577 { PHY_ID_MATCH_VENDOR(0x001cc800) },
1578 { }
1579};
1580
1581MODULE_DEVICE_TABLE(mdio, realtek_tbl);
1// SPDX-License-Identifier: GPL-2.0+
2/* drivers/net/phy/realtek.c
3 *
4 * Driver for Realtek PHYs
5 *
6 * Author: Johnson Leung <r58129@freescale.com>
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 */
10#include <linux/bitops.h>
11#include <linux/of.h>
12#include <linux/phy.h>
13#include <linux/module.h>
14#include <linux/delay.h>
15#include <linux/clk.h>
16
17#define RTL821x_PHYSR 0x11
18#define RTL821x_PHYSR_DUPLEX BIT(13)
19#define RTL821x_PHYSR_SPEED GENMASK(15, 14)
20
21#define RTL821x_INER 0x12
22#define RTL8211B_INER_INIT 0x6400
23#define RTL8211E_INER_LINK_STATUS BIT(10)
24#define RTL8211F_INER_LINK_STATUS BIT(4)
25
26#define RTL821x_INSR 0x13
27
28#define RTL821x_EXT_PAGE_SELECT 0x1e
29#define RTL821x_PAGE_SELECT 0x1f
30
31#define RTL8211F_PHYCR1 0x18
32#define RTL8211F_PHYCR2 0x19
33#define RTL8211F_INSR 0x1d
34
35#define RTL8211F_TX_DELAY BIT(8)
36#define RTL8211F_RX_DELAY BIT(3)
37
38#define RTL8211F_ALDPS_PLL_OFF BIT(1)
39#define RTL8211F_ALDPS_ENABLE BIT(2)
40#define RTL8211F_ALDPS_XTAL_OFF BIT(12)
41
42#define RTL8211E_CTRL_DELAY BIT(13)
43#define RTL8211E_TX_DELAY BIT(12)
44#define RTL8211E_RX_DELAY BIT(11)
45
46#define RTL8211F_CLKOUT_EN BIT(0)
47
48#define RTL8201F_ISR 0x1e
49#define RTL8201F_ISR_ANERR BIT(15)
50#define RTL8201F_ISR_DUPLEX BIT(13)
51#define RTL8201F_ISR_LINK BIT(11)
52#define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \
53 RTL8201F_ISR_DUPLEX | \
54 RTL8201F_ISR_LINK)
55#define RTL8201F_IER 0x13
56
57#define RTL8366RB_POWER_SAVE 0x15
58#define RTL8366RB_POWER_SAVE_ON BIT(12)
59
60#define RTL9000A_GINMR 0x14
61#define RTL9000A_GINMR_LINK_STATUS BIT(4)
62
63#define RTLGEN_SPEED_MASK 0x0630
64
65#define RTL_GENERIC_PHYID 0x001cc800
66#define RTL_8211FVD_PHYID 0x001cc878
67
68MODULE_DESCRIPTION("Realtek PHY driver");
69MODULE_AUTHOR("Johnson Leung");
70MODULE_LICENSE("GPL");
71
72struct rtl821x_priv {
73 u16 phycr1;
74 u16 phycr2;
75 bool has_phycr2;
76 struct clk *clk;
77};
78
79static int rtl821x_read_page(struct phy_device *phydev)
80{
81 return __phy_read(phydev, RTL821x_PAGE_SELECT);
82}
83
84static int rtl821x_write_page(struct phy_device *phydev, int page)
85{
86 return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
87}
88
89static int rtl821x_probe(struct phy_device *phydev)
90{
91 struct device *dev = &phydev->mdio.dev;
92 struct rtl821x_priv *priv;
93 u32 phy_id = phydev->drv->phy_id;
94 int ret;
95
96 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
97 if (!priv)
98 return -ENOMEM;
99
100 priv->clk = devm_clk_get_optional_enabled(dev, NULL);
101 if (IS_ERR(priv->clk))
102 return dev_err_probe(dev, PTR_ERR(priv->clk),
103 "failed to get phy clock\n");
104
105 ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR1);
106 if (ret < 0)
107 return ret;
108
109 priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF);
110 if (of_property_read_bool(dev->of_node, "realtek,aldps-enable"))
111 priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF;
112
113 priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID);
114 if (priv->has_phycr2) {
115 ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR2);
116 if (ret < 0)
117 return ret;
118
119 priv->phycr2 = ret & RTL8211F_CLKOUT_EN;
120 if (of_property_read_bool(dev->of_node, "realtek,clkout-disable"))
121 priv->phycr2 &= ~RTL8211F_CLKOUT_EN;
122 }
123
124 phydev->priv = priv;
125
126 return 0;
127}
128
129static int rtl8201_ack_interrupt(struct phy_device *phydev)
130{
131 int err;
132
133 err = phy_read(phydev, RTL8201F_ISR);
134
135 return (err < 0) ? err : 0;
136}
137
138static int rtl821x_ack_interrupt(struct phy_device *phydev)
139{
140 int err;
141
142 err = phy_read(phydev, RTL821x_INSR);
143
144 return (err < 0) ? err : 0;
145}
146
147static int rtl8211f_ack_interrupt(struct phy_device *phydev)
148{
149 int err;
150
151 err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
152
153 return (err < 0) ? err : 0;
154}
155
156static int rtl8201_config_intr(struct phy_device *phydev)
157{
158 u16 val;
159 int err;
160
161 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
162 err = rtl8201_ack_interrupt(phydev);
163 if (err)
164 return err;
165
166 val = BIT(13) | BIT(12) | BIT(11);
167 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
168 } else {
169 val = 0;
170 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
171 if (err)
172 return err;
173
174 err = rtl8201_ack_interrupt(phydev);
175 }
176
177 return err;
178}
179
180static int rtl8211b_config_intr(struct phy_device *phydev)
181{
182 int err;
183
184 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
185 err = rtl821x_ack_interrupt(phydev);
186 if (err)
187 return err;
188
189 err = phy_write(phydev, RTL821x_INER,
190 RTL8211B_INER_INIT);
191 } else {
192 err = phy_write(phydev, RTL821x_INER, 0);
193 if (err)
194 return err;
195
196 err = rtl821x_ack_interrupt(phydev);
197 }
198
199 return err;
200}
201
202static int rtl8211e_config_intr(struct phy_device *phydev)
203{
204 int err;
205
206 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
207 err = rtl821x_ack_interrupt(phydev);
208 if (err)
209 return err;
210
211 err = phy_write(phydev, RTL821x_INER,
212 RTL8211E_INER_LINK_STATUS);
213 } else {
214 err = phy_write(phydev, RTL821x_INER, 0);
215 if (err)
216 return err;
217
218 err = rtl821x_ack_interrupt(phydev);
219 }
220
221 return err;
222}
223
224static int rtl8211f_config_intr(struct phy_device *phydev)
225{
226 u16 val;
227 int err;
228
229 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
230 err = rtl8211f_ack_interrupt(phydev);
231 if (err)
232 return err;
233
234 val = RTL8211F_INER_LINK_STATUS;
235 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
236 } else {
237 val = 0;
238 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
239 if (err)
240 return err;
241
242 err = rtl8211f_ack_interrupt(phydev);
243 }
244
245 return err;
246}
247
248static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev)
249{
250 int irq_status;
251
252 irq_status = phy_read(phydev, RTL8201F_ISR);
253 if (irq_status < 0) {
254 phy_error(phydev);
255 return IRQ_NONE;
256 }
257
258 if (!(irq_status & RTL8201F_ISR_MASK))
259 return IRQ_NONE;
260
261 phy_trigger_machine(phydev);
262
263 return IRQ_HANDLED;
264}
265
266static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev)
267{
268 int irq_status, irq_enabled;
269
270 irq_status = phy_read(phydev, RTL821x_INSR);
271 if (irq_status < 0) {
272 phy_error(phydev);
273 return IRQ_NONE;
274 }
275
276 irq_enabled = phy_read(phydev, RTL821x_INER);
277 if (irq_enabled < 0) {
278 phy_error(phydev);
279 return IRQ_NONE;
280 }
281
282 if (!(irq_status & irq_enabled))
283 return IRQ_NONE;
284
285 phy_trigger_machine(phydev);
286
287 return IRQ_HANDLED;
288}
289
290static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev)
291{
292 int irq_status;
293
294 irq_status = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
295 if (irq_status < 0) {
296 phy_error(phydev);
297 return IRQ_NONE;
298 }
299
300 if (!(irq_status & RTL8211F_INER_LINK_STATUS))
301 return IRQ_NONE;
302
303 phy_trigger_machine(phydev);
304
305 return IRQ_HANDLED;
306}
307
308static int rtl8211_config_aneg(struct phy_device *phydev)
309{
310 int ret;
311
312 ret = genphy_config_aneg(phydev);
313 if (ret < 0)
314 return ret;
315
316 /* Quirk was copied from vendor driver. Unfortunately it includes no
317 * description of the magic numbers.
318 */
319 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
320 phy_write(phydev, 0x17, 0x2138);
321 phy_write(phydev, 0x0e, 0x0260);
322 } else {
323 phy_write(phydev, 0x17, 0x2108);
324 phy_write(phydev, 0x0e, 0x0000);
325 }
326
327 return 0;
328}
329
330static int rtl8211c_config_init(struct phy_device *phydev)
331{
332 /* RTL8211C has an issue when operating in Gigabit slave mode */
333 return phy_set_bits(phydev, MII_CTRL1000,
334 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
335}
336
337static int rtl8211f_config_init(struct phy_device *phydev)
338{
339 struct rtl821x_priv *priv = phydev->priv;
340 struct device *dev = &phydev->mdio.dev;
341 u16 val_txdly, val_rxdly;
342 int ret;
343
344 ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1,
345 RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF,
346 priv->phycr1);
347 if (ret < 0) {
348 dev_err(dev, "aldps mode configuration failed: %pe\n",
349 ERR_PTR(ret));
350 return ret;
351 }
352
353 switch (phydev->interface) {
354 case PHY_INTERFACE_MODE_RGMII:
355 val_txdly = 0;
356 val_rxdly = 0;
357 break;
358
359 case PHY_INTERFACE_MODE_RGMII_RXID:
360 val_txdly = 0;
361 val_rxdly = RTL8211F_RX_DELAY;
362 break;
363
364 case PHY_INTERFACE_MODE_RGMII_TXID:
365 val_txdly = RTL8211F_TX_DELAY;
366 val_rxdly = 0;
367 break;
368
369 case PHY_INTERFACE_MODE_RGMII_ID:
370 val_txdly = RTL8211F_TX_DELAY;
371 val_rxdly = RTL8211F_RX_DELAY;
372 break;
373
374 default: /* the rest of the modes imply leaving delay as is. */
375 return 0;
376 }
377
378 ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
379 val_txdly);
380 if (ret < 0) {
381 dev_err(dev, "Failed to update the TX delay register\n");
382 return ret;
383 } else if (ret) {
384 dev_dbg(dev,
385 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
386 val_txdly ? "Enabling" : "Disabling");
387 } else {
388 dev_dbg(dev,
389 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
390 val_txdly ? "enabled" : "disabled");
391 }
392
393 ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY,
394 val_rxdly);
395 if (ret < 0) {
396 dev_err(dev, "Failed to update the RX delay register\n");
397 return ret;
398 } else if (ret) {
399 dev_dbg(dev,
400 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
401 val_rxdly ? "Enabling" : "Disabling");
402 } else {
403 dev_dbg(dev,
404 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
405 val_rxdly ? "enabled" : "disabled");
406 }
407
408 if (priv->has_phycr2) {
409 ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2,
410 RTL8211F_CLKOUT_EN, priv->phycr2);
411 if (ret < 0) {
412 dev_err(dev, "clkout configuration failed: %pe\n",
413 ERR_PTR(ret));
414 return ret;
415 }
416
417 return genphy_soft_reset(phydev);
418 }
419
420 return 0;
421}
422
423static int rtl821x_suspend(struct phy_device *phydev)
424{
425 struct rtl821x_priv *priv = phydev->priv;
426 int ret = 0;
427
428 if (!phydev->wol_enabled) {
429 ret = genphy_suspend(phydev);
430
431 if (ret)
432 return ret;
433
434 clk_disable_unprepare(priv->clk);
435 }
436
437 return ret;
438}
439
440static int rtl821x_resume(struct phy_device *phydev)
441{
442 struct rtl821x_priv *priv = phydev->priv;
443 int ret;
444
445 if (!phydev->wol_enabled)
446 clk_prepare_enable(priv->clk);
447
448 ret = genphy_resume(phydev);
449 if (ret < 0)
450 return ret;
451
452 msleep(20);
453
454 return 0;
455}
456
457static int rtl8211e_config_init(struct phy_device *phydev)
458{
459 int ret = 0, oldpage;
460 u16 val;
461
462 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
463 switch (phydev->interface) {
464 case PHY_INTERFACE_MODE_RGMII:
465 val = RTL8211E_CTRL_DELAY | 0;
466 break;
467 case PHY_INTERFACE_MODE_RGMII_ID:
468 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
469 break;
470 case PHY_INTERFACE_MODE_RGMII_RXID:
471 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY;
472 break;
473 case PHY_INTERFACE_MODE_RGMII_TXID:
474 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY;
475 break;
476 default: /* the rest of the modes imply leaving delays as is. */
477 return 0;
478 }
479
480 /* According to a sample driver there is a 0x1c config register on the
481 * 0xa4 extension page (0x7) layout. It can be used to disable/enable
482 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins.
483 * The configuration register definition:
484 * 14 = reserved
485 * 13 = Force Tx RX Delay controlled by bit12 bit11,
486 * 12 = RX Delay, 11 = TX Delay
487 * 10:0 = Test && debug settings reserved by realtek
488 */
489 oldpage = phy_select_page(phydev, 0x7);
490 if (oldpage < 0)
491 goto err_restore_page;
492
493 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
494 if (ret)
495 goto err_restore_page;
496
497 ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY
498 | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
499 val);
500
501err_restore_page:
502 return phy_restore_page(phydev, oldpage, ret);
503}
504
505static int rtl8211b_suspend(struct phy_device *phydev)
506{
507 phy_write(phydev, MII_MMD_DATA, BIT(9));
508
509 return genphy_suspend(phydev);
510}
511
512static int rtl8211b_resume(struct phy_device *phydev)
513{
514 phy_write(phydev, MII_MMD_DATA, 0);
515
516 return genphy_resume(phydev);
517}
518
519static int rtl8366rb_config_init(struct phy_device *phydev)
520{
521 int ret;
522
523 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
524 RTL8366RB_POWER_SAVE_ON);
525 if (ret) {
526 dev_err(&phydev->mdio.dev,
527 "error enabling power management\n");
528 }
529
530 return ret;
531}
532
533/* get actual speed to cover the downshift case */
534static int rtlgen_get_speed(struct phy_device *phydev)
535{
536 int val;
537
538 if (!phydev->link)
539 return 0;
540
541 val = phy_read_paged(phydev, 0xa43, 0x12);
542 if (val < 0)
543 return val;
544
545 switch (val & RTLGEN_SPEED_MASK) {
546 case 0x0000:
547 phydev->speed = SPEED_10;
548 break;
549 case 0x0010:
550 phydev->speed = SPEED_100;
551 break;
552 case 0x0020:
553 phydev->speed = SPEED_1000;
554 break;
555 case 0x0200:
556 phydev->speed = SPEED_10000;
557 break;
558 case 0x0210:
559 phydev->speed = SPEED_2500;
560 break;
561 case 0x0220:
562 phydev->speed = SPEED_5000;
563 break;
564 default:
565 break;
566 }
567
568 return 0;
569}
570
571static int rtlgen_read_status(struct phy_device *phydev)
572{
573 int ret;
574
575 ret = genphy_read_status(phydev);
576 if (ret < 0)
577 return ret;
578
579 return rtlgen_get_speed(phydev);
580}
581
582static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
583{
584 int ret;
585
586 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
587 rtl821x_write_page(phydev, 0xa5c);
588 ret = __phy_read(phydev, 0x12);
589 rtl821x_write_page(phydev, 0);
590 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
591 rtl821x_write_page(phydev, 0xa5d);
592 ret = __phy_read(phydev, 0x10);
593 rtl821x_write_page(phydev, 0);
594 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
595 rtl821x_write_page(phydev, 0xa5d);
596 ret = __phy_read(phydev, 0x11);
597 rtl821x_write_page(phydev, 0);
598 } else {
599 ret = -EOPNOTSUPP;
600 }
601
602 return ret;
603}
604
605static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
606 u16 val)
607{
608 int ret;
609
610 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
611 rtl821x_write_page(phydev, 0xa5d);
612 ret = __phy_write(phydev, 0x10, val);
613 rtl821x_write_page(phydev, 0);
614 } else {
615 ret = -EOPNOTSUPP;
616 }
617
618 return ret;
619}
620
621static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
622{
623 int ret = rtlgen_read_mmd(phydev, devnum, regnum);
624
625 if (ret != -EOPNOTSUPP)
626 return ret;
627
628 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
629 rtl821x_write_page(phydev, 0xa6e);
630 ret = __phy_read(phydev, 0x16);
631 rtl821x_write_page(phydev, 0);
632 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
633 rtl821x_write_page(phydev, 0xa6d);
634 ret = __phy_read(phydev, 0x12);
635 rtl821x_write_page(phydev, 0);
636 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
637 rtl821x_write_page(phydev, 0xa6d);
638 ret = __phy_read(phydev, 0x10);
639 rtl821x_write_page(phydev, 0);
640 }
641
642 return ret;
643}
644
645static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
646 u16 val)
647{
648 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
649
650 if (ret != -EOPNOTSUPP)
651 return ret;
652
653 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
654 rtl821x_write_page(phydev, 0xa6d);
655 ret = __phy_write(phydev, 0x12, val);
656 rtl821x_write_page(phydev, 0);
657 }
658
659 return ret;
660}
661
662static int rtl822x_get_features(struct phy_device *phydev)
663{
664 int val;
665
666 val = phy_read_paged(phydev, 0xa61, 0x13);
667 if (val < 0)
668 return val;
669
670 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
671 phydev->supported, val & MDIO_PMA_SPEED_2_5G);
672 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
673 phydev->supported, val & MDIO_PMA_SPEED_5G);
674 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
675 phydev->supported, val & MDIO_SPEED_10G);
676
677 return genphy_read_abilities(phydev);
678}
679
680static int rtl822x_config_aneg(struct phy_device *phydev)
681{
682 int ret = 0;
683
684 if (phydev->autoneg == AUTONEG_ENABLE) {
685 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
686
687 ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
688 MDIO_AN_10GBT_CTRL_ADV2_5G |
689 MDIO_AN_10GBT_CTRL_ADV5G,
690 adv);
691 if (ret < 0)
692 return ret;
693 }
694
695 return __genphy_config_aneg(phydev, ret);
696}
697
698static int rtl822x_read_status(struct phy_device *phydev)
699{
700 int ret;
701
702 if (phydev->autoneg == AUTONEG_ENABLE) {
703 int lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
704
705 if (lpadv < 0)
706 return lpadv;
707
708 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising,
709 lpadv);
710 }
711
712 ret = genphy_read_status(phydev);
713 if (ret < 0)
714 return ret;
715
716 return rtlgen_get_speed(phydev);
717}
718
719static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
720{
721 int val;
722
723 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
724 val = phy_read(phydev, 0x13);
725 phy_write(phydev, RTL821x_PAGE_SELECT, 0);
726
727 return val >= 0 && val & MDIO_PMA_SPEED_2_5G;
728}
729
730static int rtlgen_match_phy_device(struct phy_device *phydev)
731{
732 return phydev->phy_id == RTL_GENERIC_PHYID &&
733 !rtlgen_supports_2_5gbps(phydev);
734}
735
736static int rtl8226_match_phy_device(struct phy_device *phydev)
737{
738 return phydev->phy_id == RTL_GENERIC_PHYID &&
739 rtlgen_supports_2_5gbps(phydev);
740}
741
742static int rtlgen_resume(struct phy_device *phydev)
743{
744 int ret = genphy_resume(phydev);
745
746 /* Internal PHY's from RTL8168h up may not be instantly ready */
747 msleep(20);
748
749 return ret;
750}
751
752static int rtl9000a_config_init(struct phy_device *phydev)
753{
754 phydev->autoneg = AUTONEG_DISABLE;
755 phydev->speed = SPEED_100;
756 phydev->duplex = DUPLEX_FULL;
757
758 return 0;
759}
760
761static int rtl9000a_config_aneg(struct phy_device *phydev)
762{
763 int ret;
764 u16 ctl = 0;
765
766 switch (phydev->master_slave_set) {
767 case MASTER_SLAVE_CFG_MASTER_FORCE:
768 ctl |= CTL1000_AS_MASTER;
769 break;
770 case MASTER_SLAVE_CFG_SLAVE_FORCE:
771 break;
772 case MASTER_SLAVE_CFG_UNKNOWN:
773 case MASTER_SLAVE_CFG_UNSUPPORTED:
774 return 0;
775 default:
776 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
777 return -EOPNOTSUPP;
778 }
779
780 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);
781 if (ret == 1)
782 ret = genphy_soft_reset(phydev);
783
784 return ret;
785}
786
787static int rtl9000a_read_status(struct phy_device *phydev)
788{
789 int ret;
790
791 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
792 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
793
794 ret = genphy_update_link(phydev);
795 if (ret)
796 return ret;
797
798 ret = phy_read(phydev, MII_CTRL1000);
799 if (ret < 0)
800 return ret;
801 if (ret & CTL1000_AS_MASTER)
802 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
803 else
804 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
805
806 ret = phy_read(phydev, MII_STAT1000);
807 if (ret < 0)
808 return ret;
809 if (ret & LPA_1000MSRES)
810 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
811 else
812 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
813
814 return 0;
815}
816
817static int rtl9000a_ack_interrupt(struct phy_device *phydev)
818{
819 int err;
820
821 err = phy_read(phydev, RTL8211F_INSR);
822
823 return (err < 0) ? err : 0;
824}
825
826static int rtl9000a_config_intr(struct phy_device *phydev)
827{
828 u16 val;
829 int err;
830
831 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
832 err = rtl9000a_ack_interrupt(phydev);
833 if (err)
834 return err;
835
836 val = (u16)~RTL9000A_GINMR_LINK_STATUS;
837 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
838 } else {
839 val = ~0;
840 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
841 if (err)
842 return err;
843
844 err = rtl9000a_ack_interrupt(phydev);
845 }
846
847 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
848}
849
850static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev)
851{
852 int irq_status;
853
854 irq_status = phy_read(phydev, RTL8211F_INSR);
855 if (irq_status < 0) {
856 phy_error(phydev);
857 return IRQ_NONE;
858 }
859
860 if (!(irq_status & RTL8211F_INER_LINK_STATUS))
861 return IRQ_NONE;
862
863 phy_trigger_machine(phydev);
864
865 return IRQ_HANDLED;
866}
867
868static struct phy_driver realtek_drvs[] = {
869 {
870 PHY_ID_MATCH_EXACT(0x00008201),
871 .name = "RTL8201CP Ethernet",
872 .read_page = rtl821x_read_page,
873 .write_page = rtl821x_write_page,
874 }, {
875 PHY_ID_MATCH_EXACT(0x001cc816),
876 .name = "RTL8201F Fast Ethernet",
877 .config_intr = &rtl8201_config_intr,
878 .handle_interrupt = rtl8201_handle_interrupt,
879 .suspend = genphy_suspend,
880 .resume = genphy_resume,
881 .read_page = rtl821x_read_page,
882 .write_page = rtl821x_write_page,
883 }, {
884 PHY_ID_MATCH_MODEL(0x001cc880),
885 .name = "RTL8208 Fast Ethernet",
886 .read_mmd = genphy_read_mmd_unsupported,
887 .write_mmd = genphy_write_mmd_unsupported,
888 .suspend = genphy_suspend,
889 .resume = genphy_resume,
890 .read_page = rtl821x_read_page,
891 .write_page = rtl821x_write_page,
892 }, {
893 PHY_ID_MATCH_EXACT(0x001cc910),
894 .name = "RTL8211 Gigabit Ethernet",
895 .config_aneg = rtl8211_config_aneg,
896 .read_mmd = &genphy_read_mmd_unsupported,
897 .write_mmd = &genphy_write_mmd_unsupported,
898 .read_page = rtl821x_read_page,
899 .write_page = rtl821x_write_page,
900 }, {
901 PHY_ID_MATCH_EXACT(0x001cc912),
902 .name = "RTL8211B Gigabit Ethernet",
903 .config_intr = &rtl8211b_config_intr,
904 .handle_interrupt = rtl821x_handle_interrupt,
905 .read_mmd = &genphy_read_mmd_unsupported,
906 .write_mmd = &genphy_write_mmd_unsupported,
907 .suspend = rtl8211b_suspend,
908 .resume = rtl8211b_resume,
909 .read_page = rtl821x_read_page,
910 .write_page = rtl821x_write_page,
911 }, {
912 PHY_ID_MATCH_EXACT(0x001cc913),
913 .name = "RTL8211C Gigabit Ethernet",
914 .config_init = rtl8211c_config_init,
915 .read_mmd = &genphy_read_mmd_unsupported,
916 .write_mmd = &genphy_write_mmd_unsupported,
917 .read_page = rtl821x_read_page,
918 .write_page = rtl821x_write_page,
919 }, {
920 PHY_ID_MATCH_EXACT(0x001cc914),
921 .name = "RTL8211DN Gigabit Ethernet",
922 .config_intr = rtl8211e_config_intr,
923 .handle_interrupt = rtl821x_handle_interrupt,
924 .suspend = genphy_suspend,
925 .resume = genphy_resume,
926 .read_page = rtl821x_read_page,
927 .write_page = rtl821x_write_page,
928 }, {
929 PHY_ID_MATCH_EXACT(0x001cc915),
930 .name = "RTL8211E Gigabit Ethernet",
931 .config_init = &rtl8211e_config_init,
932 .config_intr = &rtl8211e_config_intr,
933 .handle_interrupt = rtl821x_handle_interrupt,
934 .suspend = genphy_suspend,
935 .resume = genphy_resume,
936 .read_page = rtl821x_read_page,
937 .write_page = rtl821x_write_page,
938 }, {
939 PHY_ID_MATCH_EXACT(0x001cc916),
940 .name = "RTL8211F Gigabit Ethernet",
941 .probe = rtl821x_probe,
942 .config_init = &rtl8211f_config_init,
943 .read_status = rtlgen_read_status,
944 .config_intr = &rtl8211f_config_intr,
945 .handle_interrupt = rtl8211f_handle_interrupt,
946 .suspend = rtl821x_suspend,
947 .resume = rtl821x_resume,
948 .read_page = rtl821x_read_page,
949 .write_page = rtl821x_write_page,
950 .flags = PHY_ALWAYS_CALL_SUSPEND,
951 }, {
952 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID),
953 .name = "RTL8211F-VD Gigabit Ethernet",
954 .probe = rtl821x_probe,
955 .config_init = &rtl8211f_config_init,
956 .read_status = rtlgen_read_status,
957 .config_intr = &rtl8211f_config_intr,
958 .handle_interrupt = rtl8211f_handle_interrupt,
959 .suspend = rtl821x_suspend,
960 .resume = rtl821x_resume,
961 .read_page = rtl821x_read_page,
962 .write_page = rtl821x_write_page,
963 .flags = PHY_ALWAYS_CALL_SUSPEND,
964 }, {
965 .name = "Generic FE-GE Realtek PHY",
966 .match_phy_device = rtlgen_match_phy_device,
967 .read_status = rtlgen_read_status,
968 .suspend = genphy_suspend,
969 .resume = rtlgen_resume,
970 .read_page = rtl821x_read_page,
971 .write_page = rtl821x_write_page,
972 .read_mmd = rtlgen_read_mmd,
973 .write_mmd = rtlgen_write_mmd,
974 }, {
975 .name = "RTL8226 2.5Gbps PHY",
976 .match_phy_device = rtl8226_match_phy_device,
977 .get_features = rtl822x_get_features,
978 .config_aneg = rtl822x_config_aneg,
979 .read_status = rtl822x_read_status,
980 .suspend = genphy_suspend,
981 .resume = rtlgen_resume,
982 .read_page = rtl821x_read_page,
983 .write_page = rtl821x_write_page,
984 .read_mmd = rtl822x_read_mmd,
985 .write_mmd = rtl822x_write_mmd,
986 }, {
987 PHY_ID_MATCH_EXACT(0x001cc840),
988 .name = "RTL8226B_RTL8221B 2.5Gbps PHY",
989 .get_features = rtl822x_get_features,
990 .config_aneg = rtl822x_config_aneg,
991 .read_status = rtl822x_read_status,
992 .suspend = genphy_suspend,
993 .resume = rtlgen_resume,
994 .read_page = rtl821x_read_page,
995 .write_page = rtl821x_write_page,
996 .read_mmd = rtl822x_read_mmd,
997 .write_mmd = rtl822x_write_mmd,
998 }, {
999 PHY_ID_MATCH_EXACT(0x001cc838),
1000 .name = "RTL8226-CG 2.5Gbps PHY",
1001 .get_features = rtl822x_get_features,
1002 .config_aneg = rtl822x_config_aneg,
1003 .read_status = rtl822x_read_status,
1004 .suspend = genphy_suspend,
1005 .resume = rtlgen_resume,
1006 .read_page = rtl821x_read_page,
1007 .write_page = rtl821x_write_page,
1008 }, {
1009 PHY_ID_MATCH_EXACT(0x001cc848),
1010 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
1011 .get_features = rtl822x_get_features,
1012 .config_aneg = rtl822x_config_aneg,
1013 .read_status = rtl822x_read_status,
1014 .suspend = genphy_suspend,
1015 .resume = rtlgen_resume,
1016 .read_page = rtl821x_read_page,
1017 .write_page = rtl821x_write_page,
1018 }, {
1019 PHY_ID_MATCH_EXACT(0x001cc849),
1020 .name = "RTL8221B-VB-CG 2.5Gbps PHY",
1021 .get_features = rtl822x_get_features,
1022 .config_aneg = rtl822x_config_aneg,
1023 .read_status = rtl822x_read_status,
1024 .suspend = genphy_suspend,
1025 .resume = rtlgen_resume,
1026 .read_page = rtl821x_read_page,
1027 .write_page = rtl821x_write_page,
1028 }, {
1029 PHY_ID_MATCH_EXACT(0x001cc84a),
1030 .name = "RTL8221B-VM-CG 2.5Gbps PHY",
1031 .get_features = rtl822x_get_features,
1032 .config_aneg = rtl822x_config_aneg,
1033 .read_status = rtl822x_read_status,
1034 .suspend = genphy_suspend,
1035 .resume = rtlgen_resume,
1036 .read_page = rtl821x_read_page,
1037 .write_page = rtl821x_write_page,
1038 }, {
1039 PHY_ID_MATCH_EXACT(0x001cc862),
1040 .name = "RTL8251B 5Gbps PHY",
1041 .get_features = rtl822x_get_features,
1042 .config_aneg = rtl822x_config_aneg,
1043 .read_status = rtl822x_read_status,
1044 .suspend = genphy_suspend,
1045 .resume = rtlgen_resume,
1046 .read_page = rtl821x_read_page,
1047 .write_page = rtl821x_write_page,
1048 }, {
1049 PHY_ID_MATCH_EXACT(0x001cc961),
1050 .name = "RTL8366RB Gigabit Ethernet",
1051 .config_init = &rtl8366rb_config_init,
1052 /* These interrupts are handled by the irq controller
1053 * embedded inside the RTL8366RB, they get unmasked when the
1054 * irq is requested and ACKed by reading the status register,
1055 * which is done by the irqchip code.
1056 */
1057 .config_intr = genphy_no_config_intr,
1058 .handle_interrupt = genphy_handle_interrupt_no_ack,
1059 .suspend = genphy_suspend,
1060 .resume = genphy_resume,
1061 }, {
1062 PHY_ID_MATCH_EXACT(0x001ccb00),
1063 .name = "RTL9000AA_RTL9000AN Ethernet",
1064 .features = PHY_BASIC_T1_FEATURES,
1065 .config_init = rtl9000a_config_init,
1066 .config_aneg = rtl9000a_config_aneg,
1067 .read_status = rtl9000a_read_status,
1068 .config_intr = rtl9000a_config_intr,
1069 .handle_interrupt = rtl9000a_handle_interrupt,
1070 .suspend = genphy_suspend,
1071 .resume = genphy_resume,
1072 .read_page = rtl821x_read_page,
1073 .write_page = rtl821x_write_page,
1074 }, {
1075 PHY_ID_MATCH_EXACT(0x001cc942),
1076 .name = "RTL8365MB-VC Gigabit Ethernet",
1077 /* Interrupt handling analogous to RTL8366RB */
1078 .config_intr = genphy_no_config_intr,
1079 .handle_interrupt = genphy_handle_interrupt_no_ack,
1080 .suspend = genphy_suspend,
1081 .resume = genphy_resume,
1082 },
1083};
1084
1085module_phy_driver(realtek_drvs);
1086
1087static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
1088 { PHY_ID_MATCH_VENDOR(0x001cc800) },
1089 { }
1090};
1091
1092MODULE_DEVICE_TABLE(mdio, realtek_tbl);