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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Marvell 88E6xxx Switch Port Registers support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9 */
10
11#include <linux/bitfield.h>
12#include <linux/if_bridge.h>
13#include <linux/phy.h>
14#include <linux/phylink.h>
15#include <linux/property.h>
16
17#include "chip.h"
18#include "global2.h"
19#include "port.h"
20#include "serdes.h"
21
22int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
23 u16 *val)
24{
25 int addr = chip->info->port_base_addr + port;
26
27 return mv88e6xxx_read(chip, addr, reg, val);
28}
29
30int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg,
31 int bit, int val)
32{
33 int addr = chip->info->port_base_addr + port;
34
35 return mv88e6xxx_wait_bit(chip, addr, reg, bit, val);
36}
37
38int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
39 u16 val)
40{
41 int addr = chip->info->port_base_addr + port;
42
43 return mv88e6xxx_write(chip, addr, reg, val);
44}
45
46/* Offset 0x00: MAC (or PCS or Physical) Status Register
47 *
48 * For most devices, this is read only. However the 6185 has the MyPause
49 * bit read/write.
50 */
51int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port,
52 int pause)
53{
54 u16 reg;
55 int err;
56
57 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
58 if (err)
59 return err;
60
61 if (pause)
62 reg |= MV88E6XXX_PORT_STS_MY_PAUSE;
63 else
64 reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE;
65
66 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
67}
68
69/* Offset 0x01: MAC (or PCS or Physical) Control Register
70 *
71 * Link, Duplex and Flow Control have one force bit, one value bit.
72 *
73 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value.
74 * Alternative values require the 200BASE (or AltSpeed) bit 12 set.
75 * Newer chips need a ForcedSpd bit 13 set to consider the value.
76 */
77
78static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
79 phy_interface_t mode)
80{
81 u16 reg;
82 int err;
83
84 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
85 if (err)
86 return err;
87
88 reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
89 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK);
90
91 switch (mode) {
92 case PHY_INTERFACE_MODE_RGMII_RXID:
93 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK;
94 break;
95 case PHY_INTERFACE_MODE_RGMII_TXID:
96 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
97 break;
98 case PHY_INTERFACE_MODE_RGMII_ID:
99 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
100 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
101 break;
102 case PHY_INTERFACE_MODE_RGMII:
103 break;
104 default:
105 return 0;
106 }
107
108 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
109 if (err)
110 return err;
111
112 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port,
113 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no",
114 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no");
115
116 return 0;
117}
118
119int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
120 phy_interface_t mode)
121{
122 if (port < 5)
123 return -EOPNOTSUPP;
124
125 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
126}
127
128int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
129 phy_interface_t mode)
130{
131 if (port != 0)
132 return -EOPNOTSUPP;
133
134 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
135}
136
137int mv88e6320_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
138 phy_interface_t mode)
139{
140 if (port != 2 && port != 5 && port != 6)
141 return -EOPNOTSUPP;
142
143 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
144}
145
146int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link)
147{
148 u16 reg;
149 int err;
150
151 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
152 if (err)
153 return err;
154
155 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
156 MV88E6XXX_PORT_MAC_CTL_LINK_UP);
157
158 switch (link) {
159 case LINK_FORCED_DOWN:
160 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK;
161 break;
162 case LINK_FORCED_UP:
163 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
164 MV88E6XXX_PORT_MAC_CTL_LINK_UP;
165 break;
166 case LINK_UNFORCED:
167 /* normal link detection */
168 break;
169 default:
170 return -EINVAL;
171 }
172
173 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
174 if (err)
175 return err;
176
177 dev_dbg(chip->dev, "p%d: %s link %s\n", port,
178 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce",
179 reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down");
180
181 return 0;
182}
183
184int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup)
185{
186 const struct mv88e6xxx_ops *ops = chip->info->ops;
187 int err = 0;
188 int link;
189
190 if (isup)
191 link = LINK_FORCED_UP;
192 else
193 link = LINK_FORCED_DOWN;
194
195 if (ops->port_set_link)
196 err = ops->port_set_link(chip, port, link);
197
198 return err;
199}
200
201int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup)
202{
203 const struct mv88e6xxx_ops *ops = chip->info->ops;
204 int err = 0;
205 int link;
206
207 if (mode == MLO_AN_INBAND)
208 link = LINK_UNFORCED;
209 else if (isup)
210 link = LINK_FORCED_UP;
211 else
212 link = LINK_FORCED_DOWN;
213
214 if (ops->port_set_link)
215 err = ops->port_set_link(chip, port, link);
216
217 return err;
218}
219
220static int mv88e6xxx_port_set_speed_duplex(struct mv88e6xxx_chip *chip,
221 int port, int speed, bool alt_bit,
222 bool force_bit, int duplex)
223{
224 u16 reg, ctrl;
225 int err;
226
227 switch (speed) {
228 case 10:
229 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10;
230 break;
231 case 100:
232 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100;
233 break;
234 case 200:
235 if (alt_bit)
236 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 |
237 MV88E6390_PORT_MAC_CTL_ALTSPEED;
238 else
239 ctrl = MV88E6065_PORT_MAC_CTL_SPEED_200;
240 break;
241 case 1000:
242 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000;
243 break;
244 case 2500:
245 if (alt_bit)
246 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 |
247 MV88E6390_PORT_MAC_CTL_ALTSPEED;
248 else
249 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000;
250 break;
251 case 10000:
252 /* all bits set, fall through... */
253 case SPEED_UNFORCED:
254 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED;
255 break;
256 default:
257 return -EOPNOTSUPP;
258 }
259
260 switch (duplex) {
261 case DUPLEX_HALF:
262 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX;
263 break;
264 case DUPLEX_FULL:
265 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
266 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL;
267 break;
268 case DUPLEX_UNFORCED:
269 /* normal duplex detection */
270 break;
271 default:
272 return -EOPNOTSUPP;
273 }
274
275 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
276 if (err)
277 return err;
278
279 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK |
280 MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
281 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL);
282
283 if (alt_bit)
284 reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED;
285 if (force_bit) {
286 reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
287 if (speed != SPEED_UNFORCED)
288 ctrl |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
289 }
290 reg |= ctrl;
291
292 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
293 if (err)
294 return err;
295
296 if (speed != SPEED_UNFORCED)
297 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed);
298 else
299 dev_dbg(chip->dev, "p%d: Speed unforced\n", port);
300 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port,
301 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce",
302 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half");
303
304 return 0;
305}
306
307/* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */
308int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
309 int speed, int duplex)
310{
311 if (speed == 200 || speed > 1000)
312 return -EOPNOTSUPP;
313
314 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false,
315 duplex);
316}
317
318/* Support 10, 100 Mbps (e.g. 88E6250 family) */
319int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
320 int speed, int duplex)
321{
322 if (speed > 100)
323 return -EOPNOTSUPP;
324
325 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false,
326 duplex);
327}
328
329/* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6341) */
330int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
331 int speed, int duplex)
332{
333 if (speed > 2500)
334 return -EOPNOTSUPP;
335
336 if (speed == 200 && port != 0)
337 return -EOPNOTSUPP;
338
339 if (speed == 2500 && port < 5)
340 return -EOPNOTSUPP;
341
342 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, !port, true,
343 duplex);
344}
345
346phy_interface_t mv88e6341_port_max_speed_mode(struct mv88e6xxx_chip *chip,
347 int port)
348{
349 if (port == 5)
350 return PHY_INTERFACE_MODE_2500BASEX;
351
352 return PHY_INTERFACE_MODE_NA;
353}
354
355/* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */
356int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
357 int speed, int duplex)
358{
359 if (speed > 1000)
360 return -EOPNOTSUPP;
361
362 if (speed == 200 && port < 5)
363 return -EOPNOTSUPP;
364
365 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, false,
366 duplex);
367}
368
369/* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */
370int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
371 int speed, int duplex)
372{
373 if (speed > 2500)
374 return -EOPNOTSUPP;
375
376 if (speed == 200 && port != 0)
377 return -EOPNOTSUPP;
378
379 if (speed == 2500 && port < 9)
380 return -EOPNOTSUPP;
381
382 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true,
383 duplex);
384}
385
386phy_interface_t mv88e6390_port_max_speed_mode(struct mv88e6xxx_chip *chip,
387 int port)
388{
389 if (port == 9 || port == 10)
390 return PHY_INTERFACE_MODE_2500BASEX;
391
392 return PHY_INTERFACE_MODE_NA;
393}
394
395/* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */
396int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
397 int speed, int duplex)
398{
399 if (speed == 200 && port != 0)
400 return -EOPNOTSUPP;
401
402 if (speed >= 2500 && port < 9)
403 return -EOPNOTSUPP;
404
405 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true,
406 duplex);
407}
408
409phy_interface_t mv88e6390x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
410 int port)
411{
412 if (port == 9 || port == 10)
413 return PHY_INTERFACE_MODE_XAUI;
414
415 return PHY_INTERFACE_MODE_NA;
416}
417
418/* Support 10, 100, 200, 1000, 2500, 5000, 10000 Mbps (e.g. 88E6393X)
419 * Function mv88e6xxx_port_set_speed_duplex() can't be used as the register
420 * values for speeds 2500 & 5000 conflict.
421 */
422int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
423 int speed, int duplex)
424{
425 u16 reg, ctrl;
426 int err;
427
428 if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361 &&
429 speed > 2500)
430 return -EOPNOTSUPP;
431
432 if (speed == 200 && port != 0)
433 return -EOPNOTSUPP;
434
435 if (speed >= 2500 && port > 0 && port < 9)
436 return -EOPNOTSUPP;
437
438 switch (speed) {
439 case 10:
440 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10;
441 break;
442 case 100:
443 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100;
444 break;
445 case 200:
446 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 |
447 MV88E6390_PORT_MAC_CTL_ALTSPEED;
448 break;
449 case 1000:
450 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000;
451 break;
452 case 2500:
453 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000 |
454 MV88E6390_PORT_MAC_CTL_ALTSPEED;
455 break;
456 case 5000:
457 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 |
458 MV88E6390_PORT_MAC_CTL_ALTSPEED;
459 break;
460 case 10000:
461 case SPEED_UNFORCED:
462 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED;
463 break;
464 default:
465 return -EOPNOTSUPP;
466 }
467
468 switch (duplex) {
469 case DUPLEX_HALF:
470 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX;
471 break;
472 case DUPLEX_FULL:
473 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
474 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL;
475 break;
476 case DUPLEX_UNFORCED:
477 /* normal duplex detection */
478 break;
479 default:
480 return -EOPNOTSUPP;
481 }
482
483 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
484 if (err)
485 return err;
486
487 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK |
488 MV88E6390_PORT_MAC_CTL_ALTSPEED |
489 MV88E6390_PORT_MAC_CTL_FORCE_SPEED);
490
491 if (speed != SPEED_UNFORCED)
492 reg |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
493
494 reg |= ctrl;
495
496 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
497 if (err)
498 return err;
499
500 if (speed != SPEED_UNFORCED)
501 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed);
502 else
503 dev_dbg(chip->dev, "p%d: Speed unforced\n", port);
504 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port,
505 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce",
506 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half");
507
508 return 0;
509}
510
511phy_interface_t mv88e6393x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
512 int port)
513{
514
515 if (port != 0 && port != 9 && port != 10)
516 return PHY_INTERFACE_MODE_NA;
517
518 if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361)
519 return PHY_INTERFACE_MODE_2500BASEX;
520
521 return PHY_INTERFACE_MODE_10GBASER;
522}
523
524static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
525 phy_interface_t mode, bool force)
526{
527 u16 cmode;
528 u16 reg;
529 int err;
530
531 /* Default to a slow mode, so freeing up SERDES interfaces for
532 * other ports which might use them for SFPs.
533 */
534 if (mode == PHY_INTERFACE_MODE_NA)
535 mode = PHY_INTERFACE_MODE_1000BASEX;
536
537 switch (mode) {
538 case PHY_INTERFACE_MODE_RMII:
539 cmode = MV88E6XXX_PORT_STS_CMODE_RMII;
540 break;
541 case PHY_INTERFACE_MODE_RGMII:
542 case PHY_INTERFACE_MODE_RGMII_ID:
543 case PHY_INTERFACE_MODE_RGMII_RXID:
544 case PHY_INTERFACE_MODE_RGMII_TXID:
545 cmode = MV88E6XXX_PORT_STS_CMODE_RGMII;
546 break;
547 case PHY_INTERFACE_MODE_1000BASEX:
548 cmode = MV88E6XXX_PORT_STS_CMODE_1000BASEX;
549 break;
550 case PHY_INTERFACE_MODE_SGMII:
551 cmode = MV88E6XXX_PORT_STS_CMODE_SGMII;
552 break;
553 case PHY_INTERFACE_MODE_2500BASEX:
554 cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX;
555 break;
556 case PHY_INTERFACE_MODE_5GBASER:
557 cmode = MV88E6393X_PORT_STS_CMODE_5GBASER;
558 break;
559 case PHY_INTERFACE_MODE_XGMII:
560 case PHY_INTERFACE_MODE_XAUI:
561 cmode = MV88E6XXX_PORT_STS_CMODE_XAUI;
562 break;
563 case PHY_INTERFACE_MODE_RXAUI:
564 cmode = MV88E6XXX_PORT_STS_CMODE_RXAUI;
565 break;
566 case PHY_INTERFACE_MODE_10GBASER:
567 cmode = MV88E6393X_PORT_STS_CMODE_10GBASER;
568 break;
569 case PHY_INTERFACE_MODE_USXGMII:
570 cmode = MV88E6393X_PORT_STS_CMODE_USXGMII;
571 break;
572 default:
573 cmode = 0;
574 }
575
576 /* cmode doesn't change, nothing to do for us unless forced */
577 if (cmode == chip->ports[port].cmode && !force)
578 return 0;
579
580 chip->ports[port].cmode = 0;
581
582 if (cmode) {
583 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
584 if (err)
585 return err;
586
587 reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK;
588 reg |= cmode;
589
590 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
591 if (err)
592 return err;
593
594 chip->ports[port].cmode = cmode;
595 }
596
597 return 0;
598}
599
600int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
601 phy_interface_t mode)
602{
603 if (port != 9 && port != 10)
604 return -EOPNOTSUPP;
605
606 return mv88e6xxx_port_set_cmode(chip, port, mode, false);
607}
608
609int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
610 phy_interface_t mode)
611{
612 if (port != 9 && port != 10)
613 return -EOPNOTSUPP;
614
615 switch (mode) {
616 case PHY_INTERFACE_MODE_NA:
617 return 0;
618 case PHY_INTERFACE_MODE_XGMII:
619 case PHY_INTERFACE_MODE_XAUI:
620 case PHY_INTERFACE_MODE_RXAUI:
621 return -EINVAL;
622 default:
623 break;
624 }
625
626 return mv88e6xxx_port_set_cmode(chip, port, mode, false);
627}
628
629int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
630 phy_interface_t mode)
631{
632 int err;
633 u16 reg;
634
635 if (port != 0 && port != 9 && port != 10)
636 return -EOPNOTSUPP;
637
638 if (port == 9 || port == 10) {
639 switch (mode) {
640 case PHY_INTERFACE_MODE_RMII:
641 case PHY_INTERFACE_MODE_RGMII:
642 case PHY_INTERFACE_MODE_RGMII_ID:
643 case PHY_INTERFACE_MODE_RGMII_RXID:
644 case PHY_INTERFACE_MODE_RGMII_TXID:
645 return -EINVAL;
646 default:
647 break;
648 }
649 }
650
651 /* mv88e6393x errata 4.5: EEE should be disabled on SERDES ports */
652 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
653 if (err)
654 return err;
655
656 reg &= ~MV88E6XXX_PORT_MAC_CTL_EEE;
657 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_EEE;
658 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
659 if (err)
660 return err;
661
662 return mv88e6xxx_port_set_cmode(chip, port, mode, false);
663}
664
665static int mv88e6341_port_set_cmode_writable(struct mv88e6xxx_chip *chip,
666 int port)
667{
668 int err, addr;
669 u16 reg, bits;
670
671 if (port != 5)
672 return -EOPNOTSUPP;
673
674 addr = chip->info->port_base_addr + port;
675
676 err = mv88e6xxx_port_hidden_read(chip, 0x7, addr, 0, ®);
677 if (err)
678 return err;
679
680 bits = MV88E6341_PORT_RESERVED_1A_FORCE_CMODE |
681 MV88E6341_PORT_RESERVED_1A_SGMII_AN;
682
683 if ((reg & bits) == bits)
684 return 0;
685
686 reg |= bits;
687 return mv88e6xxx_port_hidden_write(chip, 0x7, addr, 0, reg);
688}
689
690int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
691 phy_interface_t mode)
692{
693 int err;
694
695 if (port != 5)
696 return -EOPNOTSUPP;
697
698 switch (mode) {
699 case PHY_INTERFACE_MODE_NA:
700 return 0;
701 case PHY_INTERFACE_MODE_XGMII:
702 case PHY_INTERFACE_MODE_XAUI:
703 case PHY_INTERFACE_MODE_RXAUI:
704 return -EINVAL;
705 default:
706 break;
707 }
708
709 err = mv88e6341_port_set_cmode_writable(chip, port);
710 if (err)
711 return err;
712
713 return mv88e6xxx_port_set_cmode(chip, port, mode, true);
714}
715
716int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
717{
718 int err;
719 u16 reg;
720
721 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
722 if (err)
723 return err;
724
725 *cmode = reg & MV88E6185_PORT_STS_CMODE_MASK;
726
727 return 0;
728}
729
730int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
731{
732 int err;
733 u16 reg;
734
735 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
736 if (err)
737 return err;
738
739 *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK;
740
741 return 0;
742}
743
744/* Offset 0x02: Jamming Control
745 *
746 * Do not limit the period of time that this port can be paused for by
747 * the remote end or the period of time that this port can pause the
748 * remote end.
749 */
750int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
751 u8 out)
752{
753 return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL,
754 out << 8 | in);
755}
756
757int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
758 u8 out)
759{
760 int err;
761
762 err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
763 MV88E6390_PORT_FLOW_CTL_UPDATE |
764 MV88E6390_PORT_FLOW_CTL_LIMIT_IN | in);
765 if (err)
766 return err;
767
768 return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
769 MV88E6390_PORT_FLOW_CTL_UPDATE |
770 MV88E6390_PORT_FLOW_CTL_LIMIT_OUT | out);
771}
772
773/* Offset 0x04: Port Control Register */
774
775static const char * const mv88e6xxx_port_state_names[] = {
776 [MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled",
777 [MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening",
778 [MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning",
779 [MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding",
780};
781
782int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state)
783{
784 u16 reg;
785 int err;
786
787 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
788 if (err)
789 return err;
790
791 reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK;
792
793 switch (state) {
794 case BR_STATE_DISABLED:
795 state = MV88E6XXX_PORT_CTL0_STATE_DISABLED;
796 break;
797 case BR_STATE_BLOCKING:
798 case BR_STATE_LISTENING:
799 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
800 break;
801 case BR_STATE_LEARNING:
802 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
803 break;
804 case BR_STATE_FORWARDING:
805 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
806 break;
807 default:
808 return -EINVAL;
809 }
810
811 reg |= state;
812
813 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
814 if (err)
815 return err;
816
817 dev_dbg(chip->dev, "p%d: PortState set to %s\n", port,
818 mv88e6xxx_port_state_names[state]);
819
820 return 0;
821}
822
823int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
824 enum mv88e6xxx_egress_mode mode)
825{
826 int err;
827 u16 reg;
828
829 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
830 if (err)
831 return err;
832
833 reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK;
834
835 switch (mode) {
836 case MV88E6XXX_EGRESS_MODE_UNMODIFIED:
837 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED;
838 break;
839 case MV88E6XXX_EGRESS_MODE_UNTAGGED:
840 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED;
841 break;
842 case MV88E6XXX_EGRESS_MODE_TAGGED:
843 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED;
844 break;
845 case MV88E6XXX_EGRESS_MODE_ETHERTYPE:
846 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA;
847 break;
848 default:
849 return -EINVAL;
850 }
851
852 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
853}
854
855int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
856 enum mv88e6xxx_frame_mode mode)
857{
858 int err;
859 u16 reg;
860
861 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
862 if (err)
863 return err;
864
865 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
866
867 switch (mode) {
868 case MV88E6XXX_FRAME_MODE_NORMAL:
869 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
870 break;
871 case MV88E6XXX_FRAME_MODE_DSA:
872 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
873 break;
874 default:
875 return -EINVAL;
876 }
877
878 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
879}
880
881int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
882 enum mv88e6xxx_frame_mode mode)
883{
884 int err;
885 u16 reg;
886
887 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
888 if (err)
889 return err;
890
891 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
892
893 switch (mode) {
894 case MV88E6XXX_FRAME_MODE_NORMAL:
895 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
896 break;
897 case MV88E6XXX_FRAME_MODE_DSA:
898 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
899 break;
900 case MV88E6XXX_FRAME_MODE_PROVIDER:
901 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER;
902 break;
903 case MV88E6XXX_FRAME_MODE_ETHERTYPE:
904 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA;
905 break;
906 default:
907 return -EINVAL;
908 }
909
910 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
911}
912
913int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip,
914 int port, bool unicast)
915{
916 int err;
917 u16 reg;
918
919 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
920 if (err)
921 return err;
922
923 if (unicast)
924 reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
925 else
926 reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
927
928 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
929}
930
931int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port,
932 bool unicast)
933{
934 int err;
935 u16 reg;
936
937 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
938 if (err)
939 return err;
940
941 if (unicast)
942 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC;
943 else
944 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC;
945
946 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
947}
948
949int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port,
950 bool multicast)
951{
952 int err;
953 u16 reg;
954
955 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
956 if (err)
957 return err;
958
959 if (multicast)
960 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC;
961 else
962 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC;
963
964 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
965}
966
967/* Offset 0x05: Port Control 1 */
968
969int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
970 bool message_port)
971{
972 u16 val;
973 int err;
974
975 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
976 if (err)
977 return err;
978
979 if (message_port)
980 val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
981 else
982 val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
983
984 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
985}
986
987int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port,
988 bool trunk, u8 id)
989{
990 u16 val;
991 int err;
992
993 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
994 if (err)
995 return err;
996
997 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK;
998
999 if (trunk)
1000 val |= MV88E6XXX_PORT_CTL1_TRUNK_PORT |
1001 (id << MV88E6XXX_PORT_CTL1_TRUNK_ID_SHIFT);
1002 else
1003 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_PORT;
1004
1005 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
1006}
1007
1008/* Offset 0x06: Port Based VLAN Map */
1009
1010int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map)
1011{
1012 const u16 mask = mv88e6xxx_port_mask(chip);
1013 u16 reg;
1014 int err;
1015
1016 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
1017 if (err)
1018 return err;
1019
1020 reg &= ~mask;
1021 reg |= map & mask;
1022
1023 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
1024 if (err)
1025 return err;
1026
1027 dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map);
1028
1029 return 0;
1030}
1031
1032int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid)
1033{
1034 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
1035 u16 reg;
1036 int err;
1037
1038 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
1039 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
1040 if (err)
1041 return err;
1042
1043 *fid = (reg & 0xf000) >> 12;
1044
1045 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
1046 if (upper_mask) {
1047 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
1048 ®);
1049 if (err)
1050 return err;
1051
1052 *fid |= (reg & upper_mask) << 4;
1053 }
1054
1055 return 0;
1056}
1057
1058int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid)
1059{
1060 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
1061 u16 reg;
1062 int err;
1063
1064 if (fid >= mv88e6xxx_num_databases(chip))
1065 return -EINVAL;
1066
1067 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
1068 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
1069 if (err)
1070 return err;
1071
1072 reg &= 0x0fff;
1073 reg |= (fid & 0x000f) << 12;
1074
1075 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
1076 if (err)
1077 return err;
1078
1079 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
1080 if (upper_mask) {
1081 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
1082 ®);
1083 if (err)
1084 return err;
1085
1086 reg &= ~upper_mask;
1087 reg |= (fid >> 4) & upper_mask;
1088
1089 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1,
1090 reg);
1091 if (err)
1092 return err;
1093 }
1094
1095 dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid);
1096
1097 return 0;
1098}
1099
1100/* Offset 0x07: Default Port VLAN ID & Priority */
1101
1102int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid)
1103{
1104 u16 reg;
1105 int err;
1106
1107 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1108 ®);
1109 if (err)
1110 return err;
1111
1112 *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1113
1114 return 0;
1115}
1116
1117int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid)
1118{
1119 u16 reg;
1120 int err;
1121
1122 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1123 ®);
1124 if (err)
1125 return err;
1126
1127 reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1128 reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1129
1130 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1131 reg);
1132 if (err)
1133 return err;
1134
1135 dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid);
1136
1137 return 0;
1138}
1139
1140/* Offset 0x08: Port Control 2 Register */
1141
1142static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1143 [MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled",
1144 [MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback",
1145 [MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check",
1146 [MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure",
1147};
1148
1149int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip,
1150 int port, bool multicast)
1151{
1152 int err;
1153 u16 reg;
1154
1155 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1156 if (err)
1157 return err;
1158
1159 if (multicast)
1160 reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
1161 else
1162 reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
1163
1164 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1165}
1166
1167int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
1168 int upstream_port)
1169{
1170 int err;
1171 u16 reg;
1172
1173 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1174 if (err)
1175 return err;
1176
1177 reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK;
1178 reg |= upstream_port;
1179
1180 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1181}
1182
1183int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port,
1184 enum mv88e6xxx_egress_direction direction,
1185 bool mirror)
1186{
1187 bool *mirror_port;
1188 u16 reg;
1189 u16 bit;
1190 int err;
1191
1192 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1193 if (err)
1194 return err;
1195
1196 switch (direction) {
1197 case MV88E6XXX_EGRESS_DIR_INGRESS:
1198 bit = MV88E6XXX_PORT_CTL2_INGRESS_MONITOR;
1199 mirror_port = &chip->ports[port].mirror_ingress;
1200 break;
1201 case MV88E6XXX_EGRESS_DIR_EGRESS:
1202 bit = MV88E6XXX_PORT_CTL2_EGRESS_MONITOR;
1203 mirror_port = &chip->ports[port].mirror_egress;
1204 break;
1205 default:
1206 return -EINVAL;
1207 }
1208
1209 reg &= ~bit;
1210 if (mirror)
1211 reg |= bit;
1212
1213 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1214 if (!err)
1215 *mirror_port = mirror;
1216
1217 return err;
1218}
1219
1220int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port,
1221 bool locked)
1222{
1223 u16 reg;
1224 int err;
1225
1226 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
1227 if (err)
1228 return err;
1229
1230 reg &= ~MV88E6XXX_PORT_CTL0_SA_FILT_MASK;
1231 if (locked)
1232 reg |= MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_LOCK;
1233
1234 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
1235 if (err)
1236 return err;
1237
1238 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, ®);
1239 if (err)
1240 return err;
1241
1242 reg &= ~MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT;
1243 if (locked)
1244 reg |= MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT;
1245
1246 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, reg);
1247}
1248
1249int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
1250 u16 mode)
1251{
1252 u16 reg;
1253 int err;
1254
1255 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1256 if (err)
1257 return err;
1258
1259 reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
1260 reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
1261
1262 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1263 if (err)
1264 return err;
1265
1266 dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port,
1267 mv88e6xxx_port_8021q_mode_names[mode]);
1268
1269 return 0;
1270}
1271
1272int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port,
1273 bool drop_untagged)
1274{
1275 u16 old, new;
1276 int err;
1277
1278 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &old);
1279 if (err)
1280 return err;
1281
1282 if (drop_untagged)
1283 new = old | MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED;
1284 else
1285 new = old & ~MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED;
1286
1287 if (new == old)
1288 return 0;
1289
1290 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, new);
1291}
1292
1293int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map)
1294{
1295 u16 reg;
1296 int err;
1297
1298 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1299 if (err)
1300 return err;
1301
1302 if (map)
1303 reg |= MV88E6XXX_PORT_CTL2_MAP_DA;
1304 else
1305 reg &= ~MV88E6XXX_PORT_CTL2_MAP_DA;
1306
1307 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1308}
1309
1310int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
1311 size_t size)
1312{
1313 u16 reg;
1314 int err;
1315
1316 size += VLAN_ETH_HLEN + ETH_FCS_LEN;
1317
1318 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1319 if (err)
1320 return err;
1321
1322 reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK;
1323
1324 if (size <= 1522)
1325 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522;
1326 else if (size <= 2048)
1327 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048;
1328 else if (size <= 10240)
1329 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240;
1330 else
1331 return -ERANGE;
1332
1333 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1334}
1335
1336/* Offset 0x09: Port Rate Control */
1337
1338int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
1339{
1340 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
1341 0x0000);
1342}
1343
1344int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
1345{
1346 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
1347 0x0001);
1348}
1349
1350/* Offset 0x0B: Port Association Vector */
1351
1352int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port,
1353 u16 pav)
1354{
1355 u16 reg, mask;
1356 int err;
1357
1358 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
1359 ®);
1360 if (err)
1361 return err;
1362
1363 mask = mv88e6xxx_port_mask(chip);
1364 reg &= ~mask;
1365 reg |= pav & mask;
1366
1367 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
1368 reg);
1369}
1370
1371/* Offset 0x0C: Port ATU Control */
1372
1373int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port)
1374{
1375 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0);
1376}
1377
1378/* Offset 0x0D: (Priority) Override Register */
1379
1380int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port)
1381{
1382 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0);
1383}
1384
1385/* Offset 0x0E: Policy & MGMT Control Register for FAMILY 6191X 6193X 6393X */
1386
1387static int mv88e6393x_port_policy_read(struct mv88e6xxx_chip *chip, int port,
1388 u16 pointer, u8 *data)
1389{
1390 u16 reg;
1391 int err;
1392
1393 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL,
1394 pointer);
1395 if (err)
1396 return err;
1397
1398 err = mv88e6xxx_port_read(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL,
1399 ®);
1400 if (err)
1401 return err;
1402
1403 *data = reg;
1404
1405 return 0;
1406}
1407
1408static int mv88e6393x_port_policy_write(struct mv88e6xxx_chip *chip, int port,
1409 u16 pointer, u8 data)
1410{
1411 u16 reg;
1412
1413 reg = MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE | pointer | data;
1414
1415 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL,
1416 reg);
1417}
1418
1419static int mv88e6393x_port_policy_write_all(struct mv88e6xxx_chip *chip,
1420 u16 pointer, u8 data)
1421{
1422 int err, port;
1423
1424 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1425 if (dsa_is_unused_port(chip->ds, port))
1426 continue;
1427
1428 err = mv88e6393x_port_policy_write(chip, port, pointer, data);
1429 if (err)
1430 return err;
1431 }
1432
1433 return 0;
1434}
1435
1436int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip,
1437 enum mv88e6xxx_egress_direction direction,
1438 int port)
1439{
1440 u16 ptr;
1441 int err;
1442
1443 switch (direction) {
1444 case MV88E6XXX_EGRESS_DIR_INGRESS:
1445 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_INGRESS_DEST;
1446 err = mv88e6393x_port_policy_write_all(chip, ptr, port);
1447 if (err)
1448 return err;
1449 break;
1450 case MV88E6XXX_EGRESS_DIR_EGRESS:
1451 ptr = MV88E6393X_G2_EGRESS_MONITOR_DEST;
1452 err = mv88e6xxx_g2_write(chip, ptr, port);
1453 if (err)
1454 return err;
1455 break;
1456 }
1457
1458 return 0;
1459}
1460
1461int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
1462 int upstream_port)
1463{
1464 u16 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_CPU_DEST;
1465 u8 data = MV88E6393X_PORT_POLICY_MGMT_CTL_CPU_DEST_MGMTPRI |
1466 upstream_port;
1467
1468 return mv88e6393x_port_policy_write(chip, port, ptr, data);
1469}
1470
1471int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
1472{
1473 u16 ptr;
1474 int err;
1475
1476 /* Consider the frames with reserved multicast destination
1477 * addresses matching 01:80:c2:00:00:00 and
1478 * 01:80:c2:00:00:02 as MGMT.
1479 */
1480 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO;
1481 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff);
1482 if (err)
1483 return err;
1484
1485 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI;
1486 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff);
1487 if (err)
1488 return err;
1489
1490 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO;
1491 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff);
1492 if (err)
1493 return err;
1494
1495 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI;
1496 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff);
1497 if (err)
1498 return err;
1499
1500 return 0;
1501}
1502
1503/* Offset 0x10 & 0x11: EPC */
1504
1505static int mv88e6393x_port_epc_wait_ready(struct mv88e6xxx_chip *chip, int port)
1506{
1507 int bit = __bf_shf(MV88E6393X_PORT_EPC_CMD_BUSY);
1508
1509 return mv88e6xxx_port_wait_bit(chip, port, MV88E6393X_PORT_EPC_CMD, bit, 0);
1510}
1511
1512/* Port Ether type for 6393X family */
1513
1514int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
1515 u16 etype)
1516{
1517 u16 val;
1518 int err;
1519
1520 err = mv88e6393x_port_epc_wait_ready(chip, port);
1521 if (err)
1522 return err;
1523
1524 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_DATA, etype);
1525 if (err)
1526 return err;
1527
1528 val = MV88E6393X_PORT_EPC_CMD_BUSY |
1529 MV88E6393X_PORT_EPC_CMD_WRITE |
1530 MV88E6393X_PORT_EPC_INDEX_PORT_ETYPE;
1531
1532 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_CMD, val);
1533}
1534
1535/* Offset 0x0f: Port Ether type */
1536
1537int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
1538 u16 etype)
1539{
1540 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype);
1541}
1542
1543/* Offset 0x18: Port IEEE Priority Remapping Registers [0-3]
1544 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7]
1545 */
1546
1547int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
1548{
1549 int err;
1550
1551 /* Use a direct priority mapping for all IEEE tagged frames */
1552 err = mv88e6xxx_port_write(chip, port,
1553 MV88E6095_PORT_IEEE_PRIO_REMAP_0123,
1554 0x3210);
1555 if (err)
1556 return err;
1557
1558 return mv88e6xxx_port_write(chip, port,
1559 MV88E6095_PORT_IEEE_PRIO_REMAP_4567,
1560 0x7654);
1561}
1562
1563static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip,
1564 int port, u16 table, u8 ptr, u16 data)
1565{
1566 u16 reg;
1567
1568 reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table |
1569 (ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)) |
1570 (data & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK);
1571
1572 return mv88e6xxx_port_write(chip, port,
1573 MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg);
1574}
1575
1576int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
1577{
1578 int err, i;
1579 u16 table;
1580
1581 for (i = 0; i <= 7; i++) {
1582 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP;
1583 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i,
1584 (i | i << 4));
1585 if (err)
1586 return err;
1587
1588 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP;
1589 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1590 if (err)
1591 return err;
1592
1593 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP;
1594 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1595 if (err)
1596 return err;
1597
1598 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP;
1599 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1600 if (err)
1601 return err;
1602 }
1603
1604 return 0;
1605}
1606
1607/* Offset 0x0E: Policy Control Register */
1608
1609static int
1610mv88e6xxx_port_policy_mapping_get_pos(enum mv88e6xxx_policy_mapping mapping,
1611 enum mv88e6xxx_policy_action action,
1612 u16 *mask, u16 *val, int *shift)
1613{
1614 switch (mapping) {
1615 case MV88E6XXX_POLICY_MAPPING_DA:
1616 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_DA_MASK);
1617 *mask = MV88E6XXX_PORT_POLICY_CTL_DA_MASK;
1618 break;
1619 case MV88E6XXX_POLICY_MAPPING_SA:
1620 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_SA_MASK);
1621 *mask = MV88E6XXX_PORT_POLICY_CTL_SA_MASK;
1622 break;
1623 case MV88E6XXX_POLICY_MAPPING_VTU:
1624 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VTU_MASK);
1625 *mask = MV88E6XXX_PORT_POLICY_CTL_VTU_MASK;
1626 break;
1627 case MV88E6XXX_POLICY_MAPPING_ETYPE:
1628 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK);
1629 *mask = MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK;
1630 break;
1631 case MV88E6XXX_POLICY_MAPPING_PPPOE:
1632 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK);
1633 *mask = MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK;
1634 break;
1635 case MV88E6XXX_POLICY_MAPPING_VBAS:
1636 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK);
1637 *mask = MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK;
1638 break;
1639 case MV88E6XXX_POLICY_MAPPING_OPT82:
1640 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK);
1641 *mask = MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK;
1642 break;
1643 case MV88E6XXX_POLICY_MAPPING_UDP:
1644 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_UDP_MASK);
1645 *mask = MV88E6XXX_PORT_POLICY_CTL_UDP_MASK;
1646 break;
1647 default:
1648 return -EOPNOTSUPP;
1649 }
1650
1651 switch (action) {
1652 case MV88E6XXX_POLICY_ACTION_NORMAL:
1653 *val = MV88E6XXX_PORT_POLICY_CTL_NORMAL;
1654 break;
1655 case MV88E6XXX_POLICY_ACTION_MIRROR:
1656 *val = MV88E6XXX_PORT_POLICY_CTL_MIRROR;
1657 break;
1658 case MV88E6XXX_POLICY_ACTION_TRAP:
1659 *val = MV88E6XXX_PORT_POLICY_CTL_TRAP;
1660 break;
1661 case MV88E6XXX_POLICY_ACTION_DISCARD:
1662 *val = MV88E6XXX_PORT_POLICY_CTL_DISCARD;
1663 break;
1664 default:
1665 return -EOPNOTSUPP;
1666 }
1667
1668 return 0;
1669}
1670
1671int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port,
1672 enum mv88e6xxx_policy_mapping mapping,
1673 enum mv88e6xxx_policy_action action)
1674{
1675 u16 reg, mask, val;
1676 int shift;
1677 int err;
1678
1679 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask,
1680 &val, &shift);
1681 if (err)
1682 return err;
1683
1684 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_POLICY_CTL, ®);
1685 if (err)
1686 return err;
1687
1688 reg &= ~mask;
1689 reg |= (val << shift) & mask;
1690
1691 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg);
1692}
1693
1694int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port,
1695 enum mv88e6xxx_policy_mapping mapping,
1696 enum mv88e6xxx_policy_action action)
1697{
1698 u16 mask, val;
1699 int shift;
1700 int err;
1701 u16 ptr;
1702 u8 reg;
1703
1704 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask,
1705 &val, &shift);
1706 if (err)
1707 return err;
1708
1709 /* The 16-bit Port Policy CTL register from older chips is on 6393x
1710 * changed to Port Policy MGMT CTL, which can access more data, but
1711 * indirectly. The original 16-bit value is divided into two 8-bit
1712 * registers.
1713 */
1714 ptr = shift / 8;
1715 shift %= 8;
1716 mask >>= ptr * 8;
1717 ptr <<= 8;
1718
1719 err = mv88e6393x_port_policy_read(chip, port, ptr, ®);
1720 if (err)
1721 return err;
1722
1723 reg &= ~mask;
1724 reg |= (val << shift) & mask;
1725
1726 return mv88e6393x_port_policy_write(chip, port, ptr, reg);
1727}
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Marvell 88E6xxx Switch Port Registers support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9 */
10
11#include <linux/bitfield.h>
12#include <linux/if_bridge.h>
13#include <linux/phy.h>
14#include <linux/phylink.h>
15
16#include "chip.h"
17#include "global2.h"
18#include "port.h"
19#include "serdes.h"
20
21int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
22 u16 *val)
23{
24 int addr = chip->info->port_base_addr + port;
25
26 return mv88e6xxx_read(chip, addr, reg, val);
27}
28
29int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg,
30 int bit, int val)
31{
32 int addr = chip->info->port_base_addr + port;
33
34 return mv88e6xxx_wait_bit(chip, addr, reg, bit, val);
35}
36
37int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
38 u16 val)
39{
40 int addr = chip->info->port_base_addr + port;
41
42 return mv88e6xxx_write(chip, addr, reg, val);
43}
44
45/* Offset 0x00: MAC (or PCS or Physical) Status Register
46 *
47 * For most devices, this is read only. However the 6185 has the MyPause
48 * bit read/write.
49 */
50int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port,
51 int pause)
52{
53 u16 reg;
54 int err;
55
56 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
57 if (err)
58 return err;
59
60 if (pause)
61 reg |= MV88E6XXX_PORT_STS_MY_PAUSE;
62 else
63 reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE;
64
65 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
66}
67
68/* Offset 0x01: MAC (or PCS or Physical) Control Register
69 *
70 * Link, Duplex and Flow Control have one force bit, one value bit.
71 *
72 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value.
73 * Alternative values require the 200BASE (or AltSpeed) bit 12 set.
74 * Newer chips need a ForcedSpd bit 13 set to consider the value.
75 */
76
77static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
78 phy_interface_t mode)
79{
80 u16 reg;
81 int err;
82
83 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
84 if (err)
85 return err;
86
87 reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
88 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK);
89
90 switch (mode) {
91 case PHY_INTERFACE_MODE_RGMII_RXID:
92 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK;
93 break;
94 case PHY_INTERFACE_MODE_RGMII_TXID:
95 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
96 break;
97 case PHY_INTERFACE_MODE_RGMII_ID:
98 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
99 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
100 break;
101 case PHY_INTERFACE_MODE_RGMII:
102 break;
103 default:
104 return 0;
105 }
106
107 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
108 if (err)
109 return err;
110
111 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port,
112 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no",
113 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no");
114
115 return 0;
116}
117
118int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
119 phy_interface_t mode)
120{
121 if (port < 5)
122 return -EOPNOTSUPP;
123
124 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
125}
126
127int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
128 phy_interface_t mode)
129{
130 if (port != 0)
131 return -EOPNOTSUPP;
132
133 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
134}
135
136int mv88e6320_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
137 phy_interface_t mode)
138{
139 if (port != 2 && port != 5 && port != 6)
140 return -EOPNOTSUPP;
141
142 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
143}
144
145int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link)
146{
147 u16 reg;
148 int err;
149
150 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
151 if (err)
152 return err;
153
154 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
155 MV88E6XXX_PORT_MAC_CTL_LINK_UP);
156
157 switch (link) {
158 case LINK_FORCED_DOWN:
159 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK;
160 break;
161 case LINK_FORCED_UP:
162 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
163 MV88E6XXX_PORT_MAC_CTL_LINK_UP;
164 break;
165 case LINK_UNFORCED:
166 /* normal link detection */
167 break;
168 default:
169 return -EINVAL;
170 }
171
172 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
173 if (err)
174 return err;
175
176 dev_dbg(chip->dev, "p%d: %s link %s\n", port,
177 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce",
178 reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down");
179
180 return 0;
181}
182
183int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup)
184{
185 const struct mv88e6xxx_ops *ops = chip->info->ops;
186 int err = 0;
187 int link;
188
189 if (isup)
190 link = LINK_FORCED_UP;
191 else
192 link = LINK_FORCED_DOWN;
193
194 if (ops->port_set_link)
195 err = ops->port_set_link(chip, port, link);
196
197 return err;
198}
199
200int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup)
201{
202 const struct mv88e6xxx_ops *ops = chip->info->ops;
203 int err = 0;
204 int link;
205
206 if (mode == MLO_AN_INBAND)
207 link = LINK_UNFORCED;
208 else if (isup)
209 link = LINK_FORCED_UP;
210 else
211 link = LINK_FORCED_DOWN;
212
213 if (ops->port_set_link)
214 err = ops->port_set_link(chip, port, link);
215
216 return err;
217}
218
219static int mv88e6xxx_port_set_speed_duplex(struct mv88e6xxx_chip *chip,
220 int port, int speed, bool alt_bit,
221 bool force_bit, int duplex)
222{
223 u16 reg, ctrl;
224 int err;
225
226 switch (speed) {
227 case 10:
228 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10;
229 break;
230 case 100:
231 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100;
232 break;
233 case 200:
234 if (alt_bit)
235 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 |
236 MV88E6390_PORT_MAC_CTL_ALTSPEED;
237 else
238 ctrl = MV88E6065_PORT_MAC_CTL_SPEED_200;
239 break;
240 case 1000:
241 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000;
242 break;
243 case 2500:
244 if (alt_bit)
245 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 |
246 MV88E6390_PORT_MAC_CTL_ALTSPEED;
247 else
248 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000;
249 break;
250 case 10000:
251 /* all bits set, fall through... */
252 case SPEED_UNFORCED:
253 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED;
254 break;
255 default:
256 return -EOPNOTSUPP;
257 }
258
259 switch (duplex) {
260 case DUPLEX_HALF:
261 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX;
262 break;
263 case DUPLEX_FULL:
264 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
265 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL;
266 break;
267 case DUPLEX_UNFORCED:
268 /* normal duplex detection */
269 break;
270 default:
271 return -EOPNOTSUPP;
272 }
273
274 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
275 if (err)
276 return err;
277
278 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK |
279 MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
280 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL);
281
282 if (alt_bit)
283 reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED;
284 if (force_bit) {
285 reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
286 if (speed != SPEED_UNFORCED)
287 ctrl |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
288 }
289 reg |= ctrl;
290
291 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
292 if (err)
293 return err;
294
295 if (speed != SPEED_UNFORCED)
296 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed);
297 else
298 dev_dbg(chip->dev, "p%d: Speed unforced\n", port);
299 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port,
300 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce",
301 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half");
302
303 return 0;
304}
305
306/* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */
307int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
308 int speed, int duplex)
309{
310 if (speed == 200 || speed > 1000)
311 return -EOPNOTSUPP;
312
313 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false,
314 duplex);
315}
316
317/* Support 10, 100 Mbps (e.g. 88E6250 family) */
318int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
319 int speed, int duplex)
320{
321 if (speed > 100)
322 return -EOPNOTSUPP;
323
324 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false,
325 duplex);
326}
327
328/* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6341) */
329int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
330 int speed, int duplex)
331{
332 if (speed > 2500)
333 return -EOPNOTSUPP;
334
335 if (speed == 200 && port != 0)
336 return -EOPNOTSUPP;
337
338 if (speed == 2500 && port < 5)
339 return -EOPNOTSUPP;
340
341 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, !port, true,
342 duplex);
343}
344
345phy_interface_t mv88e6341_port_max_speed_mode(struct mv88e6xxx_chip *chip,
346 int port)
347{
348 if (port == 5)
349 return PHY_INTERFACE_MODE_2500BASEX;
350
351 return PHY_INTERFACE_MODE_NA;
352}
353
354/* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */
355int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
356 int speed, int duplex)
357{
358 if (speed > 1000)
359 return -EOPNOTSUPP;
360
361 if (speed == 200 && port < 5)
362 return -EOPNOTSUPP;
363
364 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, false,
365 duplex);
366}
367
368/* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */
369int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
370 int speed, int duplex)
371{
372 if (speed > 2500)
373 return -EOPNOTSUPP;
374
375 if (speed == 200 && port != 0)
376 return -EOPNOTSUPP;
377
378 if (speed == 2500 && port < 9)
379 return -EOPNOTSUPP;
380
381 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true,
382 duplex);
383}
384
385phy_interface_t mv88e6390_port_max_speed_mode(struct mv88e6xxx_chip *chip,
386 int port)
387{
388 if (port == 9 || port == 10)
389 return PHY_INTERFACE_MODE_2500BASEX;
390
391 return PHY_INTERFACE_MODE_NA;
392}
393
394/* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */
395int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
396 int speed, int duplex)
397{
398 if (speed == 200 && port != 0)
399 return -EOPNOTSUPP;
400
401 if (speed >= 2500 && port < 9)
402 return -EOPNOTSUPP;
403
404 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true,
405 duplex);
406}
407
408phy_interface_t mv88e6390x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
409 int port)
410{
411 if (port == 9 || port == 10)
412 return PHY_INTERFACE_MODE_XAUI;
413
414 return PHY_INTERFACE_MODE_NA;
415}
416
417/* Support 10, 100, 200, 1000, 2500, 5000, 10000 Mbps (e.g. 88E6393X)
418 * Function mv88e6xxx_port_set_speed_duplex() can't be used as the register
419 * values for speeds 2500 & 5000 conflict.
420 */
421int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
422 int speed, int duplex)
423{
424 u16 reg, ctrl;
425 int err;
426
427 if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361 &&
428 speed > 2500)
429 return -EOPNOTSUPP;
430
431 if (speed == 200 && port != 0)
432 return -EOPNOTSUPP;
433
434 if (speed >= 2500 && port > 0 && port < 9)
435 return -EOPNOTSUPP;
436
437 switch (speed) {
438 case 10:
439 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10;
440 break;
441 case 100:
442 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100;
443 break;
444 case 200:
445 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 |
446 MV88E6390_PORT_MAC_CTL_ALTSPEED;
447 break;
448 case 1000:
449 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000;
450 break;
451 case 2500:
452 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000 |
453 MV88E6390_PORT_MAC_CTL_ALTSPEED;
454 break;
455 case 5000:
456 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 |
457 MV88E6390_PORT_MAC_CTL_ALTSPEED;
458 break;
459 case 10000:
460 case SPEED_UNFORCED:
461 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED;
462 break;
463 default:
464 return -EOPNOTSUPP;
465 }
466
467 switch (duplex) {
468 case DUPLEX_HALF:
469 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX;
470 break;
471 case DUPLEX_FULL:
472 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
473 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL;
474 break;
475 case DUPLEX_UNFORCED:
476 /* normal duplex detection */
477 break;
478 default:
479 return -EOPNOTSUPP;
480 }
481
482 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
483 if (err)
484 return err;
485
486 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK |
487 MV88E6390_PORT_MAC_CTL_ALTSPEED |
488 MV88E6390_PORT_MAC_CTL_FORCE_SPEED);
489
490 if (speed != SPEED_UNFORCED)
491 reg |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
492
493 reg |= ctrl;
494
495 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
496 if (err)
497 return err;
498
499 if (speed != SPEED_UNFORCED)
500 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed);
501 else
502 dev_dbg(chip->dev, "p%d: Speed unforced\n", port);
503 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port,
504 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce",
505 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half");
506
507 return 0;
508}
509
510phy_interface_t mv88e6393x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
511 int port)
512{
513
514 if (port != 0 && port != 9 && port != 10)
515 return PHY_INTERFACE_MODE_NA;
516
517 if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361)
518 return PHY_INTERFACE_MODE_2500BASEX;
519
520 return PHY_INTERFACE_MODE_10GBASER;
521}
522
523static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
524 phy_interface_t mode, bool force)
525{
526 u16 cmode;
527 u16 reg;
528 int err;
529
530 /* Default to a slow mode, so freeing up SERDES interfaces for
531 * other ports which might use them for SFPs.
532 */
533 if (mode == PHY_INTERFACE_MODE_NA)
534 mode = PHY_INTERFACE_MODE_1000BASEX;
535
536 switch (mode) {
537 case PHY_INTERFACE_MODE_RMII:
538 cmode = MV88E6XXX_PORT_STS_CMODE_RMII;
539 break;
540 case PHY_INTERFACE_MODE_RGMII:
541 case PHY_INTERFACE_MODE_RGMII_ID:
542 case PHY_INTERFACE_MODE_RGMII_RXID:
543 case PHY_INTERFACE_MODE_RGMII_TXID:
544 cmode = MV88E6XXX_PORT_STS_CMODE_RGMII;
545 break;
546 case PHY_INTERFACE_MODE_1000BASEX:
547 cmode = MV88E6XXX_PORT_STS_CMODE_1000BASEX;
548 break;
549 case PHY_INTERFACE_MODE_SGMII:
550 cmode = MV88E6XXX_PORT_STS_CMODE_SGMII;
551 break;
552 case PHY_INTERFACE_MODE_2500BASEX:
553 cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX;
554 break;
555 case PHY_INTERFACE_MODE_5GBASER:
556 cmode = MV88E6393X_PORT_STS_CMODE_5GBASER;
557 break;
558 case PHY_INTERFACE_MODE_XGMII:
559 case PHY_INTERFACE_MODE_XAUI:
560 cmode = MV88E6XXX_PORT_STS_CMODE_XAUI;
561 break;
562 case PHY_INTERFACE_MODE_RXAUI:
563 cmode = MV88E6XXX_PORT_STS_CMODE_RXAUI;
564 break;
565 case PHY_INTERFACE_MODE_10GBASER:
566 cmode = MV88E6393X_PORT_STS_CMODE_10GBASER;
567 break;
568 case PHY_INTERFACE_MODE_USXGMII:
569 cmode = MV88E6393X_PORT_STS_CMODE_USXGMII;
570 break;
571 default:
572 cmode = 0;
573 }
574
575 /* cmode doesn't change, nothing to do for us unless forced */
576 if (cmode == chip->ports[port].cmode && !force)
577 return 0;
578
579 chip->ports[port].cmode = 0;
580
581 if (cmode) {
582 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
583 if (err)
584 return err;
585
586 reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK;
587 reg |= cmode;
588
589 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
590 if (err)
591 return err;
592
593 chip->ports[port].cmode = cmode;
594 }
595
596 return 0;
597}
598
599int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
600 phy_interface_t mode)
601{
602 if (port != 9 && port != 10)
603 return -EOPNOTSUPP;
604
605 return mv88e6xxx_port_set_cmode(chip, port, mode, false);
606}
607
608int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
609 phy_interface_t mode)
610{
611 if (port != 9 && port != 10)
612 return -EOPNOTSUPP;
613
614 switch (mode) {
615 case PHY_INTERFACE_MODE_NA:
616 return 0;
617 case PHY_INTERFACE_MODE_XGMII:
618 case PHY_INTERFACE_MODE_XAUI:
619 case PHY_INTERFACE_MODE_RXAUI:
620 return -EINVAL;
621 default:
622 break;
623 }
624
625 return mv88e6xxx_port_set_cmode(chip, port, mode, false);
626}
627
628int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
629 phy_interface_t mode)
630{
631 int err;
632 u16 reg;
633
634 if (port != 0 && port != 9 && port != 10)
635 return -EOPNOTSUPP;
636
637 if (port == 9 || port == 10) {
638 switch (mode) {
639 case PHY_INTERFACE_MODE_RMII:
640 case PHY_INTERFACE_MODE_RGMII:
641 case PHY_INTERFACE_MODE_RGMII_ID:
642 case PHY_INTERFACE_MODE_RGMII_RXID:
643 case PHY_INTERFACE_MODE_RGMII_TXID:
644 return -EINVAL;
645 default:
646 break;
647 }
648 }
649
650 /* mv88e6393x errata 4.5: EEE should be disabled on SERDES ports */
651 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
652 if (err)
653 return err;
654
655 reg &= ~MV88E6XXX_PORT_MAC_CTL_EEE;
656 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_EEE;
657 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
658 if (err)
659 return err;
660
661 return mv88e6xxx_port_set_cmode(chip, port, mode, false);
662}
663
664static int mv88e6341_port_set_cmode_writable(struct mv88e6xxx_chip *chip,
665 int port)
666{
667 int err, addr;
668 u16 reg, bits;
669
670 if (port != 5)
671 return -EOPNOTSUPP;
672
673 addr = chip->info->port_base_addr + port;
674
675 err = mv88e6xxx_port_hidden_read(chip, 0x7, addr, 0, ®);
676 if (err)
677 return err;
678
679 bits = MV88E6341_PORT_RESERVED_1A_FORCE_CMODE |
680 MV88E6341_PORT_RESERVED_1A_SGMII_AN;
681
682 if ((reg & bits) == bits)
683 return 0;
684
685 reg |= bits;
686 return mv88e6xxx_port_hidden_write(chip, 0x7, addr, 0, reg);
687}
688
689int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
690 phy_interface_t mode)
691{
692 int err;
693
694 if (port != 5)
695 return -EOPNOTSUPP;
696
697 switch (mode) {
698 case PHY_INTERFACE_MODE_NA:
699 return 0;
700 case PHY_INTERFACE_MODE_XGMII:
701 case PHY_INTERFACE_MODE_XAUI:
702 case PHY_INTERFACE_MODE_RXAUI:
703 return -EINVAL;
704 default:
705 break;
706 }
707
708 err = mv88e6341_port_set_cmode_writable(chip, port);
709 if (err)
710 return err;
711
712 return mv88e6xxx_port_set_cmode(chip, port, mode, true);
713}
714
715int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
716{
717 int err;
718 u16 reg;
719
720 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
721 if (err)
722 return err;
723
724 *cmode = reg & MV88E6185_PORT_STS_CMODE_MASK;
725
726 return 0;
727}
728
729int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
730{
731 int err;
732 u16 reg;
733
734 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
735 if (err)
736 return err;
737
738 *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK;
739
740 return 0;
741}
742
743/* Offset 0x02: Jamming Control
744 *
745 * Do not limit the period of time that this port can be paused for by
746 * the remote end or the period of time that this port can pause the
747 * remote end.
748 */
749int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
750 u8 out)
751{
752 return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL,
753 out << 8 | in);
754}
755
756int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
757 u8 out)
758{
759 int err;
760
761 err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
762 MV88E6390_PORT_FLOW_CTL_UPDATE |
763 MV88E6390_PORT_FLOW_CTL_LIMIT_IN | in);
764 if (err)
765 return err;
766
767 return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
768 MV88E6390_PORT_FLOW_CTL_UPDATE |
769 MV88E6390_PORT_FLOW_CTL_LIMIT_OUT | out);
770}
771
772/* Offset 0x04: Port Control Register */
773
774static const char * const mv88e6xxx_port_state_names[] = {
775 [MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled",
776 [MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening",
777 [MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning",
778 [MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding",
779};
780
781int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state)
782{
783 u16 reg;
784 int err;
785
786 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
787 if (err)
788 return err;
789
790 reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK;
791
792 switch (state) {
793 case BR_STATE_DISABLED:
794 state = MV88E6XXX_PORT_CTL0_STATE_DISABLED;
795 break;
796 case BR_STATE_BLOCKING:
797 case BR_STATE_LISTENING:
798 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
799 break;
800 case BR_STATE_LEARNING:
801 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
802 break;
803 case BR_STATE_FORWARDING:
804 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
805 break;
806 default:
807 return -EINVAL;
808 }
809
810 reg |= state;
811
812 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
813 if (err)
814 return err;
815
816 dev_dbg(chip->dev, "p%d: PortState set to %s\n", port,
817 mv88e6xxx_port_state_names[state]);
818
819 return 0;
820}
821
822int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
823 enum mv88e6xxx_egress_mode mode)
824{
825 int err;
826 u16 reg;
827
828 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
829 if (err)
830 return err;
831
832 reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK;
833
834 switch (mode) {
835 case MV88E6XXX_EGRESS_MODE_UNMODIFIED:
836 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED;
837 break;
838 case MV88E6XXX_EGRESS_MODE_UNTAGGED:
839 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED;
840 break;
841 case MV88E6XXX_EGRESS_MODE_TAGGED:
842 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED;
843 break;
844 case MV88E6XXX_EGRESS_MODE_ETHERTYPE:
845 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA;
846 break;
847 default:
848 return -EINVAL;
849 }
850
851 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
852}
853
854int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
855 enum mv88e6xxx_frame_mode mode)
856{
857 int err;
858 u16 reg;
859
860 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
861 if (err)
862 return err;
863
864 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
865
866 switch (mode) {
867 case MV88E6XXX_FRAME_MODE_NORMAL:
868 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
869 break;
870 case MV88E6XXX_FRAME_MODE_DSA:
871 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
872 break;
873 default:
874 return -EINVAL;
875 }
876
877 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
878}
879
880int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
881 enum mv88e6xxx_frame_mode mode)
882{
883 int err;
884 u16 reg;
885
886 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
887 if (err)
888 return err;
889
890 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
891
892 switch (mode) {
893 case MV88E6XXX_FRAME_MODE_NORMAL:
894 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
895 break;
896 case MV88E6XXX_FRAME_MODE_DSA:
897 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
898 break;
899 case MV88E6XXX_FRAME_MODE_PROVIDER:
900 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER;
901 break;
902 case MV88E6XXX_FRAME_MODE_ETHERTYPE:
903 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA;
904 break;
905 default:
906 return -EINVAL;
907 }
908
909 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
910}
911
912int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip,
913 int port, bool unicast)
914{
915 int err;
916 u16 reg;
917
918 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
919 if (err)
920 return err;
921
922 if (unicast)
923 reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
924 else
925 reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
926
927 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
928}
929
930int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port,
931 bool unicast)
932{
933 int err;
934 u16 reg;
935
936 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
937 if (err)
938 return err;
939
940 if (unicast)
941 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC;
942 else
943 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC;
944
945 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
946}
947
948int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port,
949 bool multicast)
950{
951 int err;
952 u16 reg;
953
954 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
955 if (err)
956 return err;
957
958 if (multicast)
959 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC;
960 else
961 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC;
962
963 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
964}
965
966/* Offset 0x05: Port Control 1 */
967
968int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
969 bool message_port)
970{
971 u16 val;
972 int err;
973
974 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
975 if (err)
976 return err;
977
978 if (message_port)
979 val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
980 else
981 val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
982
983 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
984}
985
986int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port,
987 bool trunk, u8 id)
988{
989 u16 val;
990 int err;
991
992 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
993 if (err)
994 return err;
995
996 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK;
997
998 if (trunk)
999 val |= MV88E6XXX_PORT_CTL1_TRUNK_PORT |
1000 (id << MV88E6XXX_PORT_CTL1_TRUNK_ID_SHIFT);
1001 else
1002 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_PORT;
1003
1004 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
1005}
1006
1007/* Offset 0x06: Port Based VLAN Map */
1008
1009int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map)
1010{
1011 const u16 mask = mv88e6xxx_port_mask(chip);
1012 u16 reg;
1013 int err;
1014
1015 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
1016 if (err)
1017 return err;
1018
1019 reg &= ~mask;
1020 reg |= map & mask;
1021
1022 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
1023 if (err)
1024 return err;
1025
1026 dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map);
1027
1028 return 0;
1029}
1030
1031int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid)
1032{
1033 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
1034 u16 reg;
1035 int err;
1036
1037 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
1038 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
1039 if (err)
1040 return err;
1041
1042 *fid = (reg & 0xf000) >> 12;
1043
1044 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
1045 if (upper_mask) {
1046 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
1047 ®);
1048 if (err)
1049 return err;
1050
1051 *fid |= (reg & upper_mask) << 4;
1052 }
1053
1054 return 0;
1055}
1056
1057int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid)
1058{
1059 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
1060 u16 reg;
1061 int err;
1062
1063 if (fid >= mv88e6xxx_num_databases(chip))
1064 return -EINVAL;
1065
1066 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
1067 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
1068 if (err)
1069 return err;
1070
1071 reg &= 0x0fff;
1072 reg |= (fid & 0x000f) << 12;
1073
1074 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
1075 if (err)
1076 return err;
1077
1078 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
1079 if (upper_mask) {
1080 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
1081 ®);
1082 if (err)
1083 return err;
1084
1085 reg &= ~upper_mask;
1086 reg |= (fid >> 4) & upper_mask;
1087
1088 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1,
1089 reg);
1090 if (err)
1091 return err;
1092 }
1093
1094 dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid);
1095
1096 return 0;
1097}
1098
1099/* Offset 0x07: Default Port VLAN ID & Priority */
1100
1101int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid)
1102{
1103 u16 reg;
1104 int err;
1105
1106 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1107 ®);
1108 if (err)
1109 return err;
1110
1111 *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1112
1113 return 0;
1114}
1115
1116int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid)
1117{
1118 u16 reg;
1119 int err;
1120
1121 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1122 ®);
1123 if (err)
1124 return err;
1125
1126 reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1127 reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1128
1129 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1130 reg);
1131 if (err)
1132 return err;
1133
1134 dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid);
1135
1136 return 0;
1137}
1138
1139/* Offset 0x08: Port Control 2 Register */
1140
1141static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1142 [MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled",
1143 [MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback",
1144 [MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check",
1145 [MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure",
1146};
1147
1148int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip,
1149 int port, bool multicast)
1150{
1151 int err;
1152 u16 reg;
1153
1154 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1155 if (err)
1156 return err;
1157
1158 if (multicast)
1159 reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
1160 else
1161 reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
1162
1163 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1164}
1165
1166int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
1167 int upstream_port)
1168{
1169 int err;
1170 u16 reg;
1171
1172 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1173 if (err)
1174 return err;
1175
1176 reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK;
1177 reg |= upstream_port;
1178
1179 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1180}
1181
1182int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port,
1183 enum mv88e6xxx_egress_direction direction,
1184 bool mirror)
1185{
1186 bool *mirror_port;
1187 u16 reg;
1188 u16 bit;
1189 int err;
1190
1191 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1192 if (err)
1193 return err;
1194
1195 switch (direction) {
1196 case MV88E6XXX_EGRESS_DIR_INGRESS:
1197 bit = MV88E6XXX_PORT_CTL2_INGRESS_MONITOR;
1198 mirror_port = &chip->ports[port].mirror_ingress;
1199 break;
1200 case MV88E6XXX_EGRESS_DIR_EGRESS:
1201 bit = MV88E6XXX_PORT_CTL2_EGRESS_MONITOR;
1202 mirror_port = &chip->ports[port].mirror_egress;
1203 break;
1204 default:
1205 return -EINVAL;
1206 }
1207
1208 reg &= ~bit;
1209 if (mirror)
1210 reg |= bit;
1211
1212 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1213 if (!err)
1214 *mirror_port = mirror;
1215
1216 return err;
1217}
1218
1219int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port,
1220 bool locked)
1221{
1222 u16 reg;
1223 int err;
1224
1225 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
1226 if (err)
1227 return err;
1228
1229 reg &= ~MV88E6XXX_PORT_CTL0_SA_FILT_MASK;
1230 if (locked)
1231 reg |= MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_LOCK;
1232
1233 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
1234 if (err)
1235 return err;
1236
1237 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, ®);
1238 if (err)
1239 return err;
1240
1241 reg &= ~MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT;
1242 if (locked)
1243 reg |= MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT;
1244
1245 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, reg);
1246}
1247
1248int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
1249 u16 mode)
1250{
1251 u16 reg;
1252 int err;
1253
1254 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1255 if (err)
1256 return err;
1257
1258 reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
1259 reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
1260
1261 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1262 if (err)
1263 return err;
1264
1265 dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port,
1266 mv88e6xxx_port_8021q_mode_names[mode]);
1267
1268 return 0;
1269}
1270
1271int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port,
1272 bool drop_untagged)
1273{
1274 u16 old, new;
1275 int err;
1276
1277 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &old);
1278 if (err)
1279 return err;
1280
1281 if (drop_untagged)
1282 new = old | MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED;
1283 else
1284 new = old & ~MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED;
1285
1286 if (new == old)
1287 return 0;
1288
1289 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, new);
1290}
1291
1292int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map)
1293{
1294 u16 reg;
1295 int err;
1296
1297 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1298 if (err)
1299 return err;
1300
1301 if (map)
1302 reg |= MV88E6XXX_PORT_CTL2_MAP_DA;
1303 else
1304 reg &= ~MV88E6XXX_PORT_CTL2_MAP_DA;
1305
1306 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1307}
1308
1309int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
1310 size_t size)
1311{
1312 u16 reg;
1313 int err;
1314
1315 size += VLAN_ETH_HLEN + ETH_FCS_LEN;
1316
1317 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1318 if (err)
1319 return err;
1320
1321 reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK;
1322
1323 if (size <= 1522)
1324 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522;
1325 else if (size <= 2048)
1326 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048;
1327 else if (size <= 10240)
1328 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240;
1329 else
1330 return -ERANGE;
1331
1332 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1333}
1334
1335/* Offset 0x09: Port Rate Control */
1336
1337int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
1338{
1339 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
1340 0x0000);
1341}
1342
1343int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
1344{
1345 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
1346 0x0001);
1347}
1348
1349/* Offset 0x0B: Port Association Vector */
1350
1351int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port,
1352 u16 pav)
1353{
1354 u16 reg, mask;
1355 int err;
1356
1357 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
1358 ®);
1359 if (err)
1360 return err;
1361
1362 mask = mv88e6xxx_port_mask(chip);
1363 reg &= ~mask;
1364 reg |= pav & mask;
1365
1366 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
1367 reg);
1368}
1369
1370/* Offset 0x0C: Port ATU Control */
1371
1372int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port)
1373{
1374 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0);
1375}
1376
1377/* Offset 0x0D: (Priority) Override Register */
1378
1379int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port)
1380{
1381 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0);
1382}
1383
1384/* Offset 0x0E: Policy & MGMT Control Register for FAMILY 6191X 6193X 6393X */
1385
1386static int mv88e6393x_port_policy_read(struct mv88e6xxx_chip *chip, int port,
1387 u16 pointer, u8 *data)
1388{
1389 u16 reg;
1390 int err;
1391
1392 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL,
1393 pointer);
1394 if (err)
1395 return err;
1396
1397 err = mv88e6xxx_port_read(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL,
1398 ®);
1399 if (err)
1400 return err;
1401
1402 *data = reg;
1403
1404 return 0;
1405}
1406
1407static int mv88e6393x_port_policy_write(struct mv88e6xxx_chip *chip, int port,
1408 u16 pointer, u8 data)
1409{
1410 u16 reg;
1411
1412 reg = MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE | pointer | data;
1413
1414 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL,
1415 reg);
1416}
1417
1418static int mv88e6393x_port_policy_write_all(struct mv88e6xxx_chip *chip,
1419 u16 pointer, u8 data)
1420{
1421 int err, port;
1422
1423 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1424 if (dsa_is_unused_port(chip->ds, port))
1425 continue;
1426
1427 err = mv88e6393x_port_policy_write(chip, port, pointer, data);
1428 if (err)
1429 return err;
1430 }
1431
1432 return 0;
1433}
1434
1435int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip,
1436 enum mv88e6xxx_egress_direction direction,
1437 int port)
1438{
1439 u16 ptr;
1440 int err;
1441
1442 switch (direction) {
1443 case MV88E6XXX_EGRESS_DIR_INGRESS:
1444 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_INGRESS_DEST;
1445 err = mv88e6393x_port_policy_write_all(chip, ptr, port);
1446 if (err)
1447 return err;
1448 break;
1449 case MV88E6XXX_EGRESS_DIR_EGRESS:
1450 ptr = MV88E6393X_G2_EGRESS_MONITOR_DEST;
1451 err = mv88e6xxx_g2_write(chip, ptr, port);
1452 if (err)
1453 return err;
1454 break;
1455 }
1456
1457 return 0;
1458}
1459
1460int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
1461 int upstream_port)
1462{
1463 u16 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_CPU_DEST;
1464 u8 data = MV88E6393X_PORT_POLICY_MGMT_CTL_CPU_DEST_MGMTPRI |
1465 upstream_port;
1466
1467 return mv88e6393x_port_policy_write(chip, port, ptr, data);
1468}
1469
1470int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
1471{
1472 u16 ptr;
1473 int err;
1474
1475 /* Consider the frames with reserved multicast destination
1476 * addresses matching 01:80:c2:00:00:00 and
1477 * 01:80:c2:00:00:02 as MGMT.
1478 */
1479 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO;
1480 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff);
1481 if (err)
1482 return err;
1483
1484 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI;
1485 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff);
1486 if (err)
1487 return err;
1488
1489 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO;
1490 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff);
1491 if (err)
1492 return err;
1493
1494 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI;
1495 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff);
1496 if (err)
1497 return err;
1498
1499 return 0;
1500}
1501
1502/* Offset 0x10 & 0x11: EPC */
1503
1504static int mv88e6393x_port_epc_wait_ready(struct mv88e6xxx_chip *chip, int port)
1505{
1506 int bit = __bf_shf(MV88E6393X_PORT_EPC_CMD_BUSY);
1507
1508 return mv88e6xxx_port_wait_bit(chip, port, MV88E6393X_PORT_EPC_CMD, bit, 0);
1509}
1510
1511/* Port Ether type for 6393X family */
1512
1513int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
1514 u16 etype)
1515{
1516 u16 val;
1517 int err;
1518
1519 err = mv88e6393x_port_epc_wait_ready(chip, port);
1520 if (err)
1521 return err;
1522
1523 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_DATA, etype);
1524 if (err)
1525 return err;
1526
1527 val = MV88E6393X_PORT_EPC_CMD_BUSY |
1528 MV88E6393X_PORT_EPC_CMD_WRITE |
1529 MV88E6393X_PORT_EPC_INDEX_PORT_ETYPE;
1530
1531 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_CMD, val);
1532}
1533
1534/* Offset 0x0f: Port Ether type */
1535
1536int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
1537 u16 etype)
1538{
1539 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype);
1540}
1541
1542/* Offset 0x18: Port IEEE Priority Remapping Registers [0-3]
1543 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7]
1544 */
1545
1546int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
1547{
1548 int err;
1549
1550 /* Use a direct priority mapping for all IEEE tagged frames */
1551 err = mv88e6xxx_port_write(chip, port,
1552 MV88E6095_PORT_IEEE_PRIO_REMAP_0123,
1553 0x3210);
1554 if (err)
1555 return err;
1556
1557 return mv88e6xxx_port_write(chip, port,
1558 MV88E6095_PORT_IEEE_PRIO_REMAP_4567,
1559 0x7654);
1560}
1561
1562static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip,
1563 int port, u16 table, u8 ptr, u16 data)
1564{
1565 u16 reg;
1566
1567 reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table |
1568 (ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)) |
1569 (data & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK);
1570
1571 return mv88e6xxx_port_write(chip, port,
1572 MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg);
1573}
1574
1575int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
1576{
1577 int err, i;
1578 u16 table;
1579
1580 for (i = 0; i <= 7; i++) {
1581 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP;
1582 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i,
1583 (i | i << 4));
1584 if (err)
1585 return err;
1586
1587 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP;
1588 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1589 if (err)
1590 return err;
1591
1592 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP;
1593 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1594 if (err)
1595 return err;
1596
1597 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP;
1598 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1599 if (err)
1600 return err;
1601 }
1602
1603 return 0;
1604}
1605
1606/* Offset 0x0E: Policy Control Register */
1607
1608static int
1609mv88e6xxx_port_policy_mapping_get_pos(enum mv88e6xxx_policy_mapping mapping,
1610 enum mv88e6xxx_policy_action action,
1611 u16 *mask, u16 *val, int *shift)
1612{
1613 switch (mapping) {
1614 case MV88E6XXX_POLICY_MAPPING_DA:
1615 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_DA_MASK);
1616 *mask = MV88E6XXX_PORT_POLICY_CTL_DA_MASK;
1617 break;
1618 case MV88E6XXX_POLICY_MAPPING_SA:
1619 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_SA_MASK);
1620 *mask = MV88E6XXX_PORT_POLICY_CTL_SA_MASK;
1621 break;
1622 case MV88E6XXX_POLICY_MAPPING_VTU:
1623 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VTU_MASK);
1624 *mask = MV88E6XXX_PORT_POLICY_CTL_VTU_MASK;
1625 break;
1626 case MV88E6XXX_POLICY_MAPPING_ETYPE:
1627 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK);
1628 *mask = MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK;
1629 break;
1630 case MV88E6XXX_POLICY_MAPPING_PPPOE:
1631 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK);
1632 *mask = MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK;
1633 break;
1634 case MV88E6XXX_POLICY_MAPPING_VBAS:
1635 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK);
1636 *mask = MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK;
1637 break;
1638 case MV88E6XXX_POLICY_MAPPING_OPT82:
1639 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK);
1640 *mask = MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK;
1641 break;
1642 case MV88E6XXX_POLICY_MAPPING_UDP:
1643 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_UDP_MASK);
1644 *mask = MV88E6XXX_PORT_POLICY_CTL_UDP_MASK;
1645 break;
1646 default:
1647 return -EOPNOTSUPP;
1648 }
1649
1650 switch (action) {
1651 case MV88E6XXX_POLICY_ACTION_NORMAL:
1652 *val = MV88E6XXX_PORT_POLICY_CTL_NORMAL;
1653 break;
1654 case MV88E6XXX_POLICY_ACTION_MIRROR:
1655 *val = MV88E6XXX_PORT_POLICY_CTL_MIRROR;
1656 break;
1657 case MV88E6XXX_POLICY_ACTION_TRAP:
1658 *val = MV88E6XXX_PORT_POLICY_CTL_TRAP;
1659 break;
1660 case MV88E6XXX_POLICY_ACTION_DISCARD:
1661 *val = MV88E6XXX_PORT_POLICY_CTL_DISCARD;
1662 break;
1663 default:
1664 return -EOPNOTSUPP;
1665 }
1666
1667 return 0;
1668}
1669
1670int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port,
1671 enum mv88e6xxx_policy_mapping mapping,
1672 enum mv88e6xxx_policy_action action)
1673{
1674 u16 reg, mask, val;
1675 int shift;
1676 int err;
1677
1678 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask,
1679 &val, &shift);
1680 if (err)
1681 return err;
1682
1683 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_POLICY_CTL, ®);
1684 if (err)
1685 return err;
1686
1687 reg &= ~mask;
1688 reg |= (val << shift) & mask;
1689
1690 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg);
1691}
1692
1693int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port,
1694 enum mv88e6xxx_policy_mapping mapping,
1695 enum mv88e6xxx_policy_action action)
1696{
1697 u16 mask, val;
1698 int shift;
1699 int err;
1700 u16 ptr;
1701 u8 reg;
1702
1703 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask,
1704 &val, &shift);
1705 if (err)
1706 return err;
1707
1708 /* The 16-bit Port Policy CTL register from older chips is on 6393x
1709 * changed to Port Policy MGMT CTL, which can access more data, but
1710 * indirectly. The original 16-bit value is divided into two 8-bit
1711 * registers.
1712 */
1713 ptr = shift / 8;
1714 shift %= 8;
1715 mask >>= ptr * 8;
1716
1717 err = mv88e6393x_port_policy_read(chip, port, ptr, ®);
1718 if (err)
1719 return err;
1720
1721 reg &= ~mask;
1722 reg |= (val << shift) & mask;
1723
1724 return mv88e6393x_port_policy_write(chip, port, ptr, reg);
1725}