1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * DRM driver for Solomon SSD13xx OLED displays
   4 *
   5 * Copyright 2022 Red Hat Inc.
   6 * Author: Javier Martinez Canillas <javierm@redhat.com>
   7 *
   8 * Based on drivers/video/fbdev/ssd1307fb.c
   9 * Copyright 2012 Free Electrons
  10 */
  11
  12#include <linux/backlight.h>
  13#include <linux/bitfield.h>
  14#include <linux/bits.h>
  15#include <linux/delay.h>
  16#include <linux/gpio/consumer.h>
  17#include <linux/property.h>
  18#include <linux/pwm.h>
  19#include <linux/regulator/consumer.h>
  20
  21#include <drm/drm_atomic.h>
  22#include <drm/drm_atomic_helper.h>
  23#include <drm/drm_client_setup.h>
  24#include <drm/drm_crtc_helper.h>
  25#include <drm/drm_damage_helper.h>
  26#include <drm/drm_edid.h>
  27#include <drm/drm_fbdev_shmem.h>
  28#include <drm/drm_format_helper.h>
  29#include <drm/drm_framebuffer.h>
  30#include <drm/drm_gem_atomic_helper.h>
  31#include <drm/drm_gem_framebuffer_helper.h>
  32#include <drm/drm_gem_shmem_helper.h>
  33#include <drm/drm_managed.h>
  34#include <drm/drm_modes.h>
  35#include <drm/drm_rect.h>
  36#include <drm/drm_probe_helper.h>
  37
  38#include "ssd130x.h"
  39
  40#define DRIVER_NAME	"ssd130x"
  41#define DRIVER_DESC	"DRM driver for Solomon SSD13xx OLED displays"
  42#define DRIVER_DATE	"20220131"
  43#define DRIVER_MAJOR	1
  44#define DRIVER_MINOR	0
  45
  46#define SSD130X_PAGE_HEIGHT 8
  47
  48#define SSD132X_SEGMENT_WIDTH 2
  49
  50/* ssd13xx commands */
  51#define SSD13XX_CONTRAST			0x81
  52#define SSD13XX_SET_SEG_REMAP			0xa0
  53#define SSD13XX_SET_MULTIPLEX_RATIO		0xa8
  54#define SSD13XX_DISPLAY_OFF			0xae
  55#define SSD13XX_DISPLAY_ON			0xaf
  56
  57#define SSD13XX_SET_SEG_REMAP_MASK		GENMASK(0, 0)
  58#define SSD13XX_SET_SEG_REMAP_SET(val)		FIELD_PREP(SSD13XX_SET_SEG_REMAP_MASK, (val))
  59
  60/* ssd130x commands */
  61#define SSD130X_PAGE_COL_START_LOW		0x00
  62#define SSD130X_PAGE_COL_START_HIGH		0x10
  63#define SSD130X_SET_ADDRESS_MODE		0x20
  64#define SSD130X_SET_COL_RANGE			0x21
  65#define SSD130X_SET_PAGE_RANGE			0x22
  66#define SSD130X_SET_LOOKUP_TABLE		0x91
  67#define SSD130X_CHARGE_PUMP			0x8d
  68#define SSD130X_START_PAGE_ADDRESS		0xb0
  69#define SSD130X_SET_COM_SCAN_DIR		0xc0
  70#define SSD130X_SET_DISPLAY_OFFSET		0xd3
  71#define SSD130X_SET_CLOCK_FREQ			0xd5
  72#define SSD130X_SET_AREA_COLOR_MODE		0xd8
  73#define SSD130X_SET_PRECHARGE_PERIOD		0xd9
  74#define SSD130X_SET_COM_PINS_CONFIG		0xda
  75#define SSD130X_SET_VCOMH			0xdb
  76
  77/* ssd130x commands accessors */
  78#define SSD130X_PAGE_COL_START_MASK		GENMASK(3, 0)
  79#define SSD130X_PAGE_COL_START_HIGH_SET(val)	FIELD_PREP(SSD130X_PAGE_COL_START_MASK, (val) >> 4)
  80#define SSD130X_PAGE_COL_START_LOW_SET(val)	FIELD_PREP(SSD130X_PAGE_COL_START_MASK, (val))
  81#define SSD130X_START_PAGE_ADDRESS_MASK		GENMASK(2, 0)
  82#define SSD130X_START_PAGE_ADDRESS_SET(val)	FIELD_PREP(SSD130X_START_PAGE_ADDRESS_MASK, (val))
  83#define SSD130X_SET_COM_SCAN_DIR_MASK		GENMASK(3, 3)
  84#define SSD130X_SET_COM_SCAN_DIR_SET(val)	FIELD_PREP(SSD130X_SET_COM_SCAN_DIR_MASK, (val))
  85#define SSD130X_SET_CLOCK_DIV_MASK		GENMASK(3, 0)
  86#define SSD130X_SET_CLOCK_DIV_SET(val)		FIELD_PREP(SSD130X_SET_CLOCK_DIV_MASK, (val))
  87#define SSD130X_SET_CLOCK_FREQ_MASK		GENMASK(7, 4)
  88#define SSD130X_SET_CLOCK_FREQ_SET(val)		FIELD_PREP(SSD130X_SET_CLOCK_FREQ_MASK, (val))
  89#define SSD130X_SET_PRECHARGE_PERIOD1_MASK	GENMASK(3, 0)
  90#define SSD130X_SET_PRECHARGE_PERIOD1_SET(val)	FIELD_PREP(SSD130X_SET_PRECHARGE_PERIOD1_MASK, (val))
  91#define SSD130X_SET_PRECHARGE_PERIOD2_MASK	GENMASK(7, 4)
  92#define SSD130X_SET_PRECHARGE_PERIOD2_SET(val)	FIELD_PREP(SSD130X_SET_PRECHARGE_PERIOD2_MASK, (val))
  93#define SSD130X_SET_COM_PINS_CONFIG1_MASK	GENMASK(4, 4)
  94#define SSD130X_SET_COM_PINS_CONFIG1_SET(val)	FIELD_PREP(SSD130X_SET_COM_PINS_CONFIG1_MASK, (val))
  95#define SSD130X_SET_COM_PINS_CONFIG2_MASK	GENMASK(5, 5)
  96#define SSD130X_SET_COM_PINS_CONFIG2_SET(val)	FIELD_PREP(SSD130X_SET_COM_PINS_CONFIG2_MASK, (val))
  97
  98#define SSD130X_SET_ADDRESS_MODE_HORIZONTAL	0x00
  99#define SSD130X_SET_ADDRESS_MODE_VERTICAL	0x01
 100#define SSD130X_SET_ADDRESS_MODE_PAGE		0x02
 101
 102#define SSD130X_SET_AREA_COLOR_MODE_ENABLE	0x1e
 103#define SSD130X_SET_AREA_COLOR_MODE_LOW_POWER	0x05
 104
 105/* ssd132x commands */
 106#define SSD132X_SET_COL_RANGE			0x15
 107#define SSD132X_SET_DEACTIVATE_SCROLL		0x2e
 108#define SSD132X_SET_ROW_RANGE			0x75
 109#define SSD132X_SET_DISPLAY_START		0xa1
 110#define SSD132X_SET_DISPLAY_OFFSET		0xa2
 111#define SSD132X_SET_DISPLAY_NORMAL		0xa4
 112#define SSD132X_SET_FUNCTION_SELECT_A		0xab
 113#define SSD132X_SET_PHASE_LENGTH		0xb1
 114#define SSD132X_SET_CLOCK_FREQ			0xb3
 115#define SSD132X_SET_GPIO			0xb5
 116#define SSD132X_SET_PRECHARGE_PERIOD		0xb6
 117#define SSD132X_SET_GRAY_SCALE_TABLE		0xb8
 118#define SSD132X_SELECT_DEFAULT_TABLE		0xb9
 119#define SSD132X_SET_PRECHARGE_VOLTAGE		0xbc
 120#define SSD130X_SET_VCOMH_VOLTAGE		0xbe
 121#define SSD132X_SET_FUNCTION_SELECT_B		0xd5
 122
 123/* ssd133x commands */
 124#define SSD133X_SET_COL_RANGE			0x15
 125#define SSD133X_SET_ROW_RANGE			0x75
 126#define SSD133X_CONTRAST_A			0x81
 127#define SSD133X_CONTRAST_B			0x82
 128#define SSD133X_CONTRAST_C			0x83
 129#define SSD133X_SET_MASTER_CURRENT		0x87
 130#define SSD132X_SET_PRECHARGE_A			0x8a
 131#define SSD132X_SET_PRECHARGE_B			0x8b
 132#define SSD132X_SET_PRECHARGE_C			0x8c
 133#define SSD133X_SET_DISPLAY_START		0xa1
 134#define SSD133X_SET_DISPLAY_OFFSET		0xa2
 135#define SSD133X_SET_DISPLAY_NORMAL		0xa4
 136#define SSD133X_SET_MASTER_CONFIG		0xad
 137#define SSD133X_POWER_SAVE_MODE			0xb0
 138#define SSD133X_PHASES_PERIOD			0xb1
 139#define SSD133X_SET_CLOCK_FREQ			0xb3
 140#define SSD133X_SET_PRECHARGE_VOLTAGE		0xbb
 141#define SSD133X_SET_VCOMH_VOLTAGE		0xbe
 142
 143#define MAX_CONTRAST 255
 144
 145const struct ssd130x_deviceinfo ssd130x_variants[] = {
 146	[SH1106_ID] = {
 147		.default_vcomh = 0x40,
 148		.default_dclk_div = 1,
 149		.default_dclk_frq = 5,
 150		.default_width = 132,
 151		.default_height = 64,
 152		.page_mode_only = 1,
 153		.family_id = SSD130X_FAMILY,
 154	},
 155	[SSD1305_ID] = {
 156		.default_vcomh = 0x34,
 157		.default_dclk_div = 1,
 158		.default_dclk_frq = 7,
 159		.default_width = 132,
 160		.default_height = 64,
 161		.family_id = SSD130X_FAMILY,
 162	},
 163	[SSD1306_ID] = {
 164		.default_vcomh = 0x20,
 165		.default_dclk_div = 1,
 166		.default_dclk_frq = 8,
 167		.need_chargepump = 1,
 168		.default_width = 128,
 169		.default_height = 64,
 170		.family_id = SSD130X_FAMILY,
 171	},
 172	[SSD1307_ID] = {
 173		.default_vcomh = 0x20,
 174		.default_dclk_div = 2,
 175		.default_dclk_frq = 12,
 176		.need_pwm = 1,
 177		.default_width = 128,
 178		.default_height = 39,
 179		.family_id = SSD130X_FAMILY,
 180	},
 181	[SSD1309_ID] = {
 182		.default_vcomh = 0x34,
 183		.default_dclk_div = 1,
 184		.default_dclk_frq = 10,
 185		.default_width = 128,
 186		.default_height = 64,
 187		.family_id = SSD130X_FAMILY,
 188	},
 189	/* ssd132x family */
 190	[SSD1322_ID] = {
 191		.default_width = 480,
 192		.default_height = 128,
 193		.family_id = SSD132X_FAMILY,
 194	},
 195	[SSD1325_ID] = {
 196		.default_width = 128,
 197		.default_height = 80,
 198		.family_id = SSD132X_FAMILY,
 199	},
 200	[SSD1327_ID] = {
 201		.default_width = 128,
 202		.default_height = 128,
 203		.family_id = SSD132X_FAMILY,
 204	},
 205	/* ssd133x family */
 206	[SSD1331_ID] = {
 207		.default_width = 96,
 208		.default_height = 64,
 209		.family_id = SSD133X_FAMILY,
 210	}
 211};
 212EXPORT_SYMBOL_NS_GPL(ssd130x_variants, "DRM_SSD130X");
 213
 214struct ssd130x_crtc_state {
 215	struct drm_crtc_state base;
 216	/* Buffer to store pixels in HW format and written to the panel */
 217	u8 *data_array;
 218};
 219
 220struct ssd130x_plane_state {
 221	struct drm_shadow_plane_state base;
 222	/* Intermediate buffer to convert pixels from XRGB8888 to HW format */
 223	u8 *buffer;
 224};
 225
 226static inline struct ssd130x_crtc_state *to_ssd130x_crtc_state(struct drm_crtc_state *state)
 227{
 228	return container_of(state, struct ssd130x_crtc_state, base);
 229}
 230
 231static inline struct ssd130x_plane_state *to_ssd130x_plane_state(struct drm_plane_state *state)
 232{
 233	return container_of(state, struct ssd130x_plane_state, base.base);
 234}
 235
 236static inline struct ssd130x_device *drm_to_ssd130x(struct drm_device *drm)
 237{
 238	return container_of(drm, struct ssd130x_device, drm);
 239}
 240
 241/*
 242 * Helper to write data (SSD13XX_DATA) to the device.
 243 */
 244static int ssd130x_write_data(struct ssd130x_device *ssd130x, u8 *values, int count)
 245{
 246	return regmap_bulk_write(ssd130x->regmap, SSD13XX_DATA, values, count);
 247}
 248
 249/*
 250 * Helper to write command (SSD13XX_COMMAND). The fist variadic argument
 251 * is the command to write and the following are the command options.
 252 *
 253 * Note that the ssd13xx protocol requires each command and option to be
 254 * written as a SSD13XX_COMMAND device register value. That is why a call
 255 * to regmap_write(..., SSD13XX_COMMAND, ...) is done for each argument.
 256 */
 257static int ssd130x_write_cmd(struct ssd130x_device *ssd130x, int count,
 258			     /* u8 cmd, u8 option, ... */...)
 259{
 260	va_list ap;
 261	u8 value;
 262	int ret;
 263
 264	va_start(ap, count);
 265
 266	do {
 267		value = va_arg(ap, int);
 268		ret = regmap_write(ssd130x->regmap, SSD13XX_COMMAND, value);
 269		if (ret)
 270			goto out_end;
 271	} while (--count);
 272
 273out_end:
 274	va_end(ap);
 275
 276	return ret;
 277}
 278
 279/* Set address range for horizontal/vertical addressing modes */
 280static int ssd130x_set_col_range(struct ssd130x_device *ssd130x,
 281				 u8 col_start, u8 cols)
 282{
 283	u8 col_end = col_start + cols - 1;
 284	int ret;
 285
 286	if (col_start == ssd130x->col_start && col_end == ssd130x->col_end)
 287		return 0;
 288
 289	ret = ssd130x_write_cmd(ssd130x, 3, SSD130X_SET_COL_RANGE, col_start, col_end);
 290	if (ret < 0)
 291		return ret;
 292
 293	ssd130x->col_start = col_start;
 294	ssd130x->col_end = col_end;
 295	return 0;
 296}
 297
 298static int ssd130x_set_page_range(struct ssd130x_device *ssd130x,
 299				  u8 page_start, u8 pages)
 300{
 301	u8 page_end = page_start + pages - 1;
 302	int ret;
 303
 304	if (page_start == ssd130x->page_start && page_end == ssd130x->page_end)
 305		return 0;
 306
 307	ret = ssd130x_write_cmd(ssd130x, 3, SSD130X_SET_PAGE_RANGE, page_start, page_end);
 308	if (ret < 0)
 309		return ret;
 310
 311	ssd130x->page_start = page_start;
 312	ssd130x->page_end = page_end;
 313	return 0;
 314}
 315
 316/* Set page and column start address for page addressing mode */
 317static int ssd130x_set_page_pos(struct ssd130x_device *ssd130x,
 318				u8 page_start, u8 col_start)
 319{
 320	int ret;
 321	u32 page, col_low, col_high;
 322
 323	page = SSD130X_START_PAGE_ADDRESS |
 324	       SSD130X_START_PAGE_ADDRESS_SET(page_start);
 325	col_low = SSD130X_PAGE_COL_START_LOW |
 326		  SSD130X_PAGE_COL_START_LOW_SET(col_start);
 327	col_high = SSD130X_PAGE_COL_START_HIGH |
 328		   SSD130X_PAGE_COL_START_HIGH_SET(col_start);
 329	ret = ssd130x_write_cmd(ssd130x, 3, page, col_low, col_high);
 330	if (ret < 0)
 331		return ret;
 332
 333	return 0;
 334}
 335
 336static int ssd130x_pwm_enable(struct ssd130x_device *ssd130x)
 337{
 338	struct device *dev = ssd130x->dev;
 339	struct pwm_state pwmstate;
 340
 341	ssd130x->pwm = pwm_get(dev, NULL);
 342	if (IS_ERR(ssd130x->pwm)) {
 343		dev_err(dev, "Could not get PWM from firmware description!\n");
 344		return PTR_ERR(ssd130x->pwm);
 345	}
 346
 347	pwm_init_state(ssd130x->pwm, &pwmstate);
 348	pwm_set_relative_duty_cycle(&pwmstate, 50, 100);
 349	pwm_apply_might_sleep(ssd130x->pwm, &pwmstate);
 350
 351	/* Enable the PWM */
 352	pwm_enable(ssd130x->pwm);
 353
 354	dev_dbg(dev, "Using PWM %s with a %lluns period.\n",
 355		ssd130x->pwm->label, pwm_get_period(ssd130x->pwm));
 356
 357	return 0;
 358}
 359
 360static void ssd130x_reset(struct ssd130x_device *ssd130x)
 361{
 362	if (!ssd130x->reset)
 363		return;
 364
 365	/* Reset the screen */
 366	gpiod_set_value_cansleep(ssd130x->reset, 1);
 367	udelay(4);
 368	gpiod_set_value_cansleep(ssd130x->reset, 0);
 369	udelay(4);
 370}
 371
 372static int ssd130x_power_on(struct ssd130x_device *ssd130x)
 373{
 374	struct device *dev = ssd130x->dev;
 375	int ret;
 376
 377	ssd130x_reset(ssd130x);
 378
 379	ret = regulator_enable(ssd130x->vcc_reg);
 380	if (ret) {
 381		dev_err(dev, "Failed to enable VCC: %d\n", ret);
 382		return ret;
 383	}
 384
 385	if (ssd130x->device_info->need_pwm) {
 386		ret = ssd130x_pwm_enable(ssd130x);
 387		if (ret) {
 388			dev_err(dev, "Failed to enable PWM: %d\n", ret);
 389			regulator_disable(ssd130x->vcc_reg);
 390			return ret;
 391		}
 392	}
 393
 394	return 0;
 395}
 396
 397static void ssd130x_power_off(struct ssd130x_device *ssd130x)
 398{
 399	pwm_disable(ssd130x->pwm);
 400	pwm_put(ssd130x->pwm);
 401
 402	regulator_disable(ssd130x->vcc_reg);
 403}
 404
 405static int ssd130x_init(struct ssd130x_device *ssd130x)
 406{
 407	u32 precharge, dclk, com_invdir, compins, chargepump, seg_remap;
 408	bool scan_mode;
 409	int ret;
 410
 411	/* Set initial contrast */
 412	ret = ssd130x_write_cmd(ssd130x, 2, SSD13XX_CONTRAST, ssd130x->contrast);
 413	if (ret < 0)
 414		return ret;
 415
 416	/* Set segment re-map */
 417	seg_remap = (SSD13XX_SET_SEG_REMAP |
 418		     SSD13XX_SET_SEG_REMAP_SET(ssd130x->seg_remap));
 419	ret = ssd130x_write_cmd(ssd130x, 1, seg_remap);
 420	if (ret < 0)
 421		return ret;
 422
 423	/* Set COM direction */
 424	com_invdir = (SSD130X_SET_COM_SCAN_DIR |
 425		      SSD130X_SET_COM_SCAN_DIR_SET(ssd130x->com_invdir));
 426	ret = ssd130x_write_cmd(ssd130x,  1, com_invdir);
 427	if (ret < 0)
 428		return ret;
 429
 430	/* Set multiplex ratio value */
 431	ret = ssd130x_write_cmd(ssd130x, 2, SSD13XX_SET_MULTIPLEX_RATIO, ssd130x->height - 1);
 432	if (ret < 0)
 433		return ret;
 434
 435	/* set display offset value */
 436	ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_DISPLAY_OFFSET, ssd130x->com_offset);
 437	if (ret < 0)
 438		return ret;
 439
 440	/* Set clock frequency */
 441	dclk = (SSD130X_SET_CLOCK_DIV_SET(ssd130x->dclk_div - 1) |
 442		SSD130X_SET_CLOCK_FREQ_SET(ssd130x->dclk_frq));
 443	ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_CLOCK_FREQ, dclk);
 444	if (ret < 0)
 445		return ret;
 446
 447	/* Set Area Color Mode ON/OFF & Low Power Display Mode */
 448	if (ssd130x->area_color_enable || ssd130x->low_power) {
 449		u32 mode = 0;
 450
 451		if (ssd130x->area_color_enable)
 452			mode |= SSD130X_SET_AREA_COLOR_MODE_ENABLE;
 453
 454		if (ssd130x->low_power)
 455			mode |= SSD130X_SET_AREA_COLOR_MODE_LOW_POWER;
 456
 457		ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_AREA_COLOR_MODE, mode);
 458		if (ret < 0)
 459			return ret;
 460	}
 461
 462	/* Set precharge period in number of ticks from the internal clock */
 463	precharge = (SSD130X_SET_PRECHARGE_PERIOD1_SET(ssd130x->prechargep1) |
 464		     SSD130X_SET_PRECHARGE_PERIOD2_SET(ssd130x->prechargep2));
 465	ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_PRECHARGE_PERIOD, precharge);
 466	if (ret < 0)
 467		return ret;
 468
 469	/* Set COM pins configuration */
 470	compins = BIT(1);
 471	/*
 472	 * The COM scan mode field values are the inverse of the boolean DT
 473	 * property "solomon,com-seq". The value 0b means scan from COM0 to
 474	 * COM[N - 1] while 1b means scan from COM[N - 1] to COM0.
 475	 */
 476	scan_mode = !ssd130x->com_seq;
 477	compins |= (SSD130X_SET_COM_PINS_CONFIG1_SET(scan_mode) |
 478		    SSD130X_SET_COM_PINS_CONFIG2_SET(ssd130x->com_lrremap));
 479	ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_COM_PINS_CONFIG, compins);
 480	if (ret < 0)
 481		return ret;
 482
 483	/* Set VCOMH */
 484	ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_VCOMH, ssd130x->vcomh);
 485	if (ret < 0)
 486		return ret;
 487
 488	/* Turn on the DC-DC Charge Pump */
 489	chargepump = BIT(4);
 490
 491	if (ssd130x->device_info->need_chargepump)
 492		chargepump |= BIT(2);
 493
 494	ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_CHARGE_PUMP, chargepump);
 495	if (ret < 0)
 496		return ret;
 497
 498	/* Set lookup table */
 499	if (ssd130x->lookup_table_set) {
 500		int i;
 501
 502		ret = ssd130x_write_cmd(ssd130x, 1, SSD130X_SET_LOOKUP_TABLE);
 503		if (ret < 0)
 504			return ret;
 505
 506		for (i = 0; i < ARRAY_SIZE(ssd130x->lookup_table); i++) {
 507			u8 val = ssd130x->lookup_table[i];
 508
 509			if (val < 31 || val > 63)
 510				dev_warn(ssd130x->dev,
 511					 "lookup table index %d value out of range 31 <= %d <= 63\n",
 512					 i, val);
 513			ret = ssd130x_write_cmd(ssd130x, 1, val);
 514			if (ret < 0)
 515				return ret;
 516		}
 517	}
 518
 519	/* Switch to page addressing mode */
 520	if (ssd130x->page_address_mode)
 521		return ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_ADDRESS_MODE,
 522					 SSD130X_SET_ADDRESS_MODE_PAGE);
 523
 524	/* Switch to horizontal addressing mode */
 525	return ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_ADDRESS_MODE,
 526				 SSD130X_SET_ADDRESS_MODE_HORIZONTAL);
 527}
 528
 529static int ssd132x_init(struct ssd130x_device *ssd130x)
 530{
 531	int ret;
 532
 533	/* Set initial contrast */
 534	ret = ssd130x_write_cmd(ssd130x, 2, SSD13XX_CONTRAST, 0x80);
 535	if (ret < 0)
 536		return ret;
 537
 538	/* Set column start and end */
 539	ret = ssd130x_write_cmd(ssd130x, 3, SSD132X_SET_COL_RANGE, 0x00,
 540				ssd130x->width / SSD132X_SEGMENT_WIDTH - 1);
 541	if (ret < 0)
 542		return ret;
 543
 544	/* Set row start and end */
 545	ret = ssd130x_write_cmd(ssd130x, 3, SSD132X_SET_ROW_RANGE, 0x00, ssd130x->height - 1);
 546	if (ret < 0)
 547		return ret;
 548	/*
 549	 * Horizontal Address Increment
 550	 * Re-map for Column Address, Nibble and COM
 551	 * COM Split Odd Even
 552	 */
 553	ret = ssd130x_write_cmd(ssd130x, 2, SSD13XX_SET_SEG_REMAP, 0x53);
 554	if (ret < 0)
 555		return ret;
 556
 557	/* Set display start and offset */
 558	ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_DISPLAY_START, 0x00);
 559	if (ret < 0)
 560		return ret;
 561
 562	ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_DISPLAY_OFFSET, 0x00);
 563	if (ret < 0)
 564		return ret;
 565
 566	/* Set display mode normal */
 567	ret = ssd130x_write_cmd(ssd130x, 1, SSD132X_SET_DISPLAY_NORMAL);
 568	if (ret < 0)
 569		return ret;
 570
 571	/* Set multiplex ratio value */
 572	ret = ssd130x_write_cmd(ssd130x, 2, SSD13XX_SET_MULTIPLEX_RATIO, ssd130x->height - 1);
 573	if (ret < 0)
 574		return ret;
 575
 576	/* Set phase length */
 577	ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_PHASE_LENGTH, 0x55);
 578	if (ret < 0)
 579		return ret;
 580
 581	/* Select default linear gray scale table */
 582	ret = ssd130x_write_cmd(ssd130x, 1, SSD132X_SELECT_DEFAULT_TABLE);
 583	if (ret < 0)
 584		return ret;
 585
 586	/* Set clock frequency */
 587	ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_CLOCK_FREQ, 0x01);
 588	if (ret < 0)
 589		return ret;
 590
 591	/* Enable internal VDD regulator */
 592	ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_FUNCTION_SELECT_A, 0x1);
 593	if (ret < 0)
 594		return ret;
 595
 596	/* Set pre-charge period */
 597	ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_PRECHARGE_PERIOD, 0x01);
 598	if (ret < 0)
 599		return ret;
 600
 601	/* Set pre-charge voltage */
 602	ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_PRECHARGE_VOLTAGE, 0x08);
 603	if (ret < 0)
 604		return ret;
 605
 606	/* Set VCOMH voltage */
 607	ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_VCOMH_VOLTAGE, 0x07);
 608	if (ret < 0)
 609		return ret;
 610
 611	/* Enable second pre-charge and internal VSL */
 612	ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_FUNCTION_SELECT_B, 0x62);
 613	if (ret < 0)
 614		return ret;
 615
 616	return 0;
 617}
 618
 619static int ssd133x_init(struct ssd130x_device *ssd130x)
 620{
 621	int ret;
 622
 623	/* Set color A contrast */
 624	ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_CONTRAST_A, 0x91);
 625	if (ret < 0)
 626		return ret;
 627
 628	/* Set color B contrast */
 629	ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_CONTRAST_B, 0x50);
 630	if (ret < 0)
 631		return ret;
 632
 633	/* Set color C contrast */
 634	ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_CONTRAST_C, 0x7d);
 635	if (ret < 0)
 636		return ret;
 637
 638	/* Set master current */
 639	ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_SET_MASTER_CURRENT, 0x06);
 640	if (ret < 0)
 641		return ret;
 642
 643	/* Set column start and end */
 644	ret = ssd130x_write_cmd(ssd130x, 3, SSD133X_SET_COL_RANGE, 0x00, ssd130x->width - 1);
 645	if (ret < 0)
 646		return ret;
 647
 648	/* Set row start and end */
 649	ret = ssd130x_write_cmd(ssd130x, 3, SSD133X_SET_ROW_RANGE, 0x00, ssd130x->height - 1);
 650	if (ret < 0)
 651		return ret;
 652
 653	/*
 654	 * Horizontal Address Increment
 655	 * Normal order SA,SB,SC (e.g. RGB)
 656	 * COM Split Odd Even
 657	 * 256 color format
 658	 */
 659	ret = ssd130x_write_cmd(ssd130x, 2, SSD13XX_SET_SEG_REMAP, 0x20);
 660	if (ret < 0)
 661		return ret;
 662
 663	/* Set display start and offset */
 664	ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_SET_DISPLAY_START, 0x00);
 665	if (ret < 0)
 666		return ret;
 667
 668	ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_SET_DISPLAY_OFFSET, 0x00);
 669	if (ret < 0)
 670		return ret;
 671
 672	/* Set display mode normal */
 673	ret = ssd130x_write_cmd(ssd130x, 1, SSD133X_SET_DISPLAY_NORMAL);
 674	if (ret < 0)
 675		return ret;
 676
 677	/* Set multiplex ratio value */
 678	ret = ssd130x_write_cmd(ssd130x, 2, SSD13XX_SET_MULTIPLEX_RATIO, ssd130x->height - 1);
 679	if (ret < 0)
 680		return ret;
 681
 682	/* Set master configuration */
 683	ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_SET_MASTER_CONFIG, 0x8e);
 684	if (ret < 0)
 685		return ret;
 686
 687	/* Set power mode */
 688	ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_POWER_SAVE_MODE, 0x0b);
 689	if (ret < 0)
 690		return ret;
 691
 692	/* Set Phase 1 and 2 period */
 693	ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_PHASES_PERIOD, 0x31);
 694	if (ret < 0)
 695		return ret;
 696
 697	/* Set clock divider */
 698	ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_SET_CLOCK_FREQ, 0xf0);
 699	if (ret < 0)
 700		return ret;
 701
 702	/* Set pre-charge A */
 703	ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_PRECHARGE_A, 0x64);
 704	if (ret < 0)
 705		return ret;
 706
 707	/* Set pre-charge B */
 708	ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_PRECHARGE_B, 0x78);
 709	if (ret < 0)
 710		return ret;
 711
 712	/* Set pre-charge C */
 713	ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_PRECHARGE_C, 0x64);
 714	if (ret < 0)
 715		return ret;
 716
 717	/* Set pre-charge level */
 718	ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_SET_PRECHARGE_VOLTAGE, 0x3a);
 719	if (ret < 0)
 720		return ret;
 721
 722	/* Set VCOMH voltage */
 723	ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_SET_VCOMH_VOLTAGE, 0x3e);
 724	if (ret < 0)
 725		return ret;
 726
 727	return 0;
 728}
 729
 730static int ssd130x_update_rect(struct ssd130x_device *ssd130x,
 731			       struct drm_rect *rect, u8 *buf,
 732			       u8 *data_array)
 733{
 734	unsigned int x = rect->x1;
 735	unsigned int y = rect->y1;
 736	unsigned int width = drm_rect_width(rect);
 737	unsigned int height = drm_rect_height(rect);
 738	unsigned int line_length = DIV_ROUND_UP(width, 8);
 739	unsigned int page_height = SSD130X_PAGE_HEIGHT;
 740	unsigned int pages = DIV_ROUND_UP(height, page_height);
 741	struct drm_device *drm = &ssd130x->drm;
 742	u32 array_idx = 0;
 743	int ret, i, j, k;
 744
 745	drm_WARN_ONCE(drm, y % page_height != 0, "y must be aligned to screen page\n");
 746
 747	/*
 748	 * The screen is divided in pages, each having a height of 8
 749	 * pixels, and the width of the screen. When sending a byte of
 750	 * data to the controller, it gives the 8 bits for the current
 751	 * column. I.e, the first byte are the 8 bits of the first
 752	 * column, then the 8 bits for the second column, etc.
 753	 *
 754	 *
 755	 * Representation of the screen, assuming it is 5 bits
 756	 * wide. Each letter-number combination is a bit that controls
 757	 * one pixel.
 758	 *
 759	 * A0 A1 A2 A3 A4
 760	 * B0 B1 B2 B3 B4
 761	 * C0 C1 C2 C3 C4
 762	 * D0 D1 D2 D3 D4
 763	 * E0 E1 E2 E3 E4
 764	 * F0 F1 F2 F3 F4
 765	 * G0 G1 G2 G3 G4
 766	 * H0 H1 H2 H3 H4
 767	 *
 768	 * If you want to update this screen, you need to send 5 bytes:
 769	 *  (1) A0 B0 C0 D0 E0 F0 G0 H0
 770	 *  (2) A1 B1 C1 D1 E1 F1 G1 H1
 771	 *  (3) A2 B2 C2 D2 E2 F2 G2 H2
 772	 *  (4) A3 B3 C3 D3 E3 F3 G3 H3
 773	 *  (5) A4 B4 C4 D4 E4 F4 G4 H4
 774	 */
 775
 776	if (!ssd130x->page_address_mode) {
 777		u8 page_start;
 778
 779		/* Set address range for horizontal addressing mode */
 780		ret = ssd130x_set_col_range(ssd130x, ssd130x->col_offset + x, width);
 781		if (ret < 0)
 782			return ret;
 783
 784		page_start = ssd130x->page_offset + y / page_height;
 785		ret = ssd130x_set_page_range(ssd130x, page_start, pages);
 786		if (ret < 0)
 787			return ret;
 788	}
 789
 790	for (i = 0; i < pages; i++) {
 791		int m = page_height;
 792
 793		/* Last page may be partial */
 794		if (page_height * (y / page_height + i + 1) > ssd130x->height)
 795			m = ssd130x->height % page_height;
 796
 797		for (j = 0; j < width; j++) {
 798			u8 data = 0;
 799
 800			for (k = 0; k < m; k++) {
 801				u32 idx = (page_height * i + k) * line_length + j / 8;
 802				u8 byte = buf[idx];
 803				u8 bit = (byte >> (j % 8)) & 1;
 804
 805				data |= bit << k;
 806			}
 807			data_array[array_idx++] = data;
 808		}
 809
 810		/*
 811		 * In page addressing mode, the start address needs to be reset,
 812		 * and each page then needs to be written out separately.
 813		 */
 814		if (ssd130x->page_address_mode) {
 815			ret = ssd130x_set_page_pos(ssd130x,
 816						   ssd130x->page_offset + i,
 817						   ssd130x->col_offset + x);
 818			if (ret < 0)
 819				return ret;
 820
 821			ret = ssd130x_write_data(ssd130x, data_array, width);
 822			if (ret < 0)
 823				return ret;
 824
 825			array_idx = 0;
 826		}
 827	}
 828
 829	/* Write out update in one go if we aren't using page addressing mode */
 830	if (!ssd130x->page_address_mode)
 831		ret = ssd130x_write_data(ssd130x, data_array, width * pages);
 832
 833	return ret;
 834}
 835
 836static int ssd132x_update_rect(struct ssd130x_device *ssd130x,
 837			       struct drm_rect *rect, u8 *buf,
 838			       u8 *data_array)
 839{
 840	unsigned int x = rect->x1;
 841	unsigned int y = rect->y1;
 842	unsigned int segment_width = SSD132X_SEGMENT_WIDTH;
 843	unsigned int width = drm_rect_width(rect);
 844	unsigned int height = drm_rect_height(rect);
 845	unsigned int columns = DIV_ROUND_UP(width, segment_width);
 846	unsigned int rows = height;
 847	struct drm_device *drm = &ssd130x->drm;
 848	u32 array_idx = 0;
 849	unsigned int i, j;
 850	int ret;
 851
 852	drm_WARN_ONCE(drm, x % segment_width != 0, "x must be aligned to screen segment\n");
 853
 854	/*
 855	 * The screen is divided in Segment and Common outputs, where
 856	 * COM0 to COM[N - 1] are the rows and SEG0 to SEG[M - 1] are
 857	 * the columns.
 858	 *
 859	 * Each Segment has a 4-bit pixel and each Common output has a
 860	 * row of pixels. When using the (default) horizontal address
 861	 * increment mode, each byte of data sent to the controller has
 862	 * two Segments (e.g: SEG0 and SEG1) that are stored in the lower
 863	 * and higher nibbles of a single byte representing one column.
 864	 * That is, the first byte are SEG0 (D0[3:0]) and SEG1 (D0[7:4]),
 865	 * the second byte are SEG2 (D1[3:0]) and SEG3 (D1[7:4]) and so on.
 866	 */
 867
 868	/* Set column start and end */
 869	ret = ssd130x_write_cmd(ssd130x, 3, SSD132X_SET_COL_RANGE, x / segment_width, columns - 1);
 870	if (ret < 0)
 871		return ret;
 872
 873	/* Set row start and end */
 874	ret = ssd130x_write_cmd(ssd130x, 3, SSD132X_SET_ROW_RANGE, y, rows - 1);
 875	if (ret < 0)
 876		return ret;
 877
 878	for (i = 0; i < height; i++) {
 879		/* Process pair of pixels and combine them into a single byte */
 880		for (j = 0; j < width; j += segment_width) {
 881			u8 n1 = buf[i * width + j];
 882			u8 n2 = buf[i * width + j + 1];
 883
 884			data_array[array_idx++] = (n2 << 4) | n1;
 885		}
 886	}
 887
 888	/* Write out update in one go since horizontal addressing mode is used */
 889	ret = ssd130x_write_data(ssd130x, data_array, columns * rows);
 890
 891	return ret;
 892}
 893
 894static int ssd133x_update_rect(struct ssd130x_device *ssd130x,
 895			       struct drm_rect *rect, u8 *data_array,
 896			       unsigned int pitch)
 897{
 898	unsigned int x = rect->x1;
 899	unsigned int y = rect->y1;
 900	unsigned int columns = drm_rect_width(rect);
 901	unsigned int rows = drm_rect_height(rect);
 902	int ret;
 903
 904	/*
 905	 * The screen is divided in Segment and Common outputs, where
 906	 * COM0 to COM[N - 1] are the rows and SEG0 to SEG[M - 1] are
 907	 * the columns.
 908	 *
 909	 * Each Segment has a 8-bit pixel and each Common output has a
 910	 * row of pixels. When using the (default) horizontal address
 911	 * increment mode, each byte of data sent to the controller has
 912	 * a Segment (e.g: SEG0).
 913	 *
 914	 * When using the 256 color depth format, each pixel contains 3
 915	 * sub-pixels for color A, B and C. These have 3 bit, 3 bit and
 916	 * 2 bits respectively.
 917	 */
 918
 919	/* Set column start and end */
 920	ret = ssd130x_write_cmd(ssd130x, 3, SSD133X_SET_COL_RANGE, x, columns - 1);
 921	if (ret < 0)
 922		return ret;
 923
 924	/* Set row start and end */
 925	ret = ssd130x_write_cmd(ssd130x, 3, SSD133X_SET_ROW_RANGE, y, rows - 1);
 926	if (ret < 0)
 927		return ret;
 928
 929	/* Write out update in one go since horizontal addressing mode is used */
 930	ret = ssd130x_write_data(ssd130x, data_array, pitch * rows);
 931
 932	return ret;
 933}
 934
 935static void ssd130x_clear_screen(struct ssd130x_device *ssd130x, u8 *data_array)
 936{
 937	unsigned int pages = DIV_ROUND_UP(ssd130x->height, SSD130X_PAGE_HEIGHT);
 938	unsigned int width = ssd130x->width;
 939	int ret, i;
 940
 941	if (!ssd130x->page_address_mode) {
 942		memset(data_array, 0, width * pages);
 943
 944		/* Set address range for horizontal addressing mode */
 945		ret = ssd130x_set_col_range(ssd130x, ssd130x->col_offset, width);
 946		if (ret < 0)
 947			return;
 948
 949		ret = ssd130x_set_page_range(ssd130x, ssd130x->page_offset, pages);
 950		if (ret < 0)
 951			return;
 952
 953		/* Write out update in one go if we aren't using page addressing mode */
 954		ssd130x_write_data(ssd130x, data_array, width * pages);
 955	} else {
 956		/*
 957		 * In page addressing mode, the start address needs to be reset,
 958		 * and each page then needs to be written out separately.
 959		 */
 960		memset(data_array, 0, width);
 961
 962		for (i = 0; i < pages; i++) {
 963			ret = ssd130x_set_page_pos(ssd130x,
 964						   ssd130x->page_offset + i,
 965						   ssd130x->col_offset);
 966			if (ret < 0)
 967				return;
 968
 969			ret = ssd130x_write_data(ssd130x, data_array, width);
 970			if (ret < 0)
 971				return;
 972		}
 973	}
 974}
 975
 976static void ssd132x_clear_screen(struct ssd130x_device *ssd130x, u8 *data_array)
 977{
 978	unsigned int columns = DIV_ROUND_UP(ssd130x->height, SSD132X_SEGMENT_WIDTH);
 979	unsigned int height = ssd130x->height;
 980
 981	memset(data_array, 0, columns * height);
 982
 983	/* Write out update in one go since horizontal addressing mode is used */
 984	ssd130x_write_data(ssd130x, data_array, columns * height);
 985}
 986
 987static void ssd133x_clear_screen(struct ssd130x_device *ssd130x, u8 *data_array)
 988{
 989	const struct drm_format_info *fi = drm_format_info(DRM_FORMAT_RGB332);
 990	unsigned int pitch;
 991
 992	if (!fi)
 993		return;
 994
 995	pitch = drm_format_info_min_pitch(fi, 0, ssd130x->width);
 996
 997	memset(data_array, 0, pitch * ssd130x->height);
 998
 999	/* Write out update in one go since horizontal addressing mode is used */
1000	ssd130x_write_data(ssd130x, data_array, pitch * ssd130x->height);
1001}
1002
1003static int ssd130x_fb_blit_rect(struct drm_framebuffer *fb,
1004				const struct iosys_map *vmap,
1005				struct drm_rect *rect,
1006				u8 *buf, u8 *data_array,
1007				struct drm_format_conv_state *fmtcnv_state)
1008{
1009	struct ssd130x_device *ssd130x = drm_to_ssd130x(fb->dev);
1010	struct iosys_map dst;
1011	unsigned int dst_pitch;
1012	int ret = 0;
1013
1014	/* Align y to display page boundaries */
1015	rect->y1 = round_down(rect->y1, SSD130X_PAGE_HEIGHT);
1016	rect->y2 = min_t(unsigned int, round_up(rect->y2, SSD130X_PAGE_HEIGHT), ssd130x->height);
1017
1018	dst_pitch = DIV_ROUND_UP(drm_rect_width(rect), 8);
1019
1020	ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE);
1021	if (ret)
1022		return ret;
1023
1024	iosys_map_set_vaddr(&dst, buf);
1025	drm_fb_xrgb8888_to_mono(&dst, &dst_pitch, vmap, fb, rect, fmtcnv_state);
1026
1027	drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE);
1028
1029	ssd130x_update_rect(ssd130x, rect, buf, data_array);
1030
1031	return ret;
1032}
1033
1034static int ssd132x_fb_blit_rect(struct drm_framebuffer *fb,
1035				const struct iosys_map *vmap,
1036				struct drm_rect *rect, u8 *buf,
1037				u8 *data_array,
1038				struct drm_format_conv_state *fmtcnv_state)
1039{
1040	struct ssd130x_device *ssd130x = drm_to_ssd130x(fb->dev);
1041	unsigned int dst_pitch = drm_rect_width(rect);
1042	struct iosys_map dst;
1043	int ret = 0;
1044
1045	/* Align x to display segment boundaries */
1046	rect->x1 = round_down(rect->x1, SSD132X_SEGMENT_WIDTH);
1047	rect->x2 = min_t(unsigned int, round_up(rect->x2, SSD132X_SEGMENT_WIDTH),
1048			 ssd130x->width);
1049
1050	ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE);
1051	if (ret)
1052		return ret;
1053
1054	iosys_map_set_vaddr(&dst, buf);
1055	drm_fb_xrgb8888_to_gray8(&dst, &dst_pitch, vmap, fb, rect, fmtcnv_state);
1056
1057	drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE);
1058
1059	ssd132x_update_rect(ssd130x, rect, buf, data_array);
1060
1061	return ret;
1062}
1063
1064static int ssd133x_fb_blit_rect(struct drm_framebuffer *fb,
1065				const struct iosys_map *vmap,
1066				struct drm_rect *rect, u8 *data_array,
1067				struct drm_format_conv_state *fmtcnv_state)
1068{
1069	struct ssd130x_device *ssd130x = drm_to_ssd130x(fb->dev);
1070	const struct drm_format_info *fi = drm_format_info(DRM_FORMAT_RGB332);
1071	unsigned int dst_pitch;
1072	struct iosys_map dst;
1073	int ret = 0;
1074
1075	if (!fi)
1076		return -EINVAL;
1077
1078	dst_pitch = drm_format_info_min_pitch(fi, 0, drm_rect_width(rect));
1079
1080	ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE);
1081	if (ret)
1082		return ret;
1083
1084	iosys_map_set_vaddr(&dst, data_array);
1085	drm_fb_xrgb8888_to_rgb332(&dst, &dst_pitch, vmap, fb, rect, fmtcnv_state);
1086
1087	drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE);
1088
1089	ssd133x_update_rect(ssd130x, rect, data_array, dst_pitch);
1090
1091	return ret;
1092}
1093
1094static int ssd130x_primary_plane_atomic_check(struct drm_plane *plane,
1095					      struct drm_atomic_state *state)
1096{
1097	struct drm_device *drm = plane->dev;
1098	struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
1099	struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);
1100	struct ssd130x_plane_state *ssd130x_state = to_ssd130x_plane_state(plane_state);
1101	struct drm_shadow_plane_state *shadow_plane_state = &ssd130x_state->base;
1102	struct drm_crtc *crtc = plane_state->crtc;
1103	struct drm_crtc_state *crtc_state = NULL;
1104	const struct drm_format_info *fi;
1105	unsigned int pitch;
1106	int ret;
1107
1108	if (crtc)
1109		crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
1110
1111	ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,
1112						  DRM_PLANE_NO_SCALING,
1113						  DRM_PLANE_NO_SCALING,
1114						  false, false);
1115	if (ret)
1116		return ret;
1117	else if (!plane_state->visible)
1118		return 0;
1119
1120	fi = drm_format_info(DRM_FORMAT_R1);
1121	if (!fi)
1122		return -EINVAL;
1123
1124	pitch = drm_format_info_min_pitch(fi, 0, ssd130x->width);
1125
1126	if (plane_state->fb->format != fi) {
1127		void *buf;
1128
1129		/* format conversion necessary; reserve buffer */
1130		buf = drm_format_conv_state_reserve(&shadow_plane_state->fmtcnv_state,
1131						    pitch, GFP_KERNEL);
1132		if (!buf)
1133			return -ENOMEM;
1134	}
1135
1136	ssd130x_state->buffer = kcalloc(pitch, ssd130x->height, GFP_KERNEL);
1137	if (!ssd130x_state->buffer)
1138		return -ENOMEM;
1139
1140	return 0;
1141}
1142
1143static int ssd132x_primary_plane_atomic_check(struct drm_plane *plane,
1144					      struct drm_atomic_state *state)
1145{
1146	struct drm_device *drm = plane->dev;
1147	struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
1148	struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);
1149	struct ssd130x_plane_state *ssd130x_state = to_ssd130x_plane_state(plane_state);
1150	struct drm_shadow_plane_state *shadow_plane_state = &ssd130x_state->base;
1151	struct drm_crtc *crtc = plane_state->crtc;
1152	struct drm_crtc_state *crtc_state = NULL;
1153	const struct drm_format_info *fi;
1154	unsigned int pitch;
1155	int ret;
1156
1157	if (crtc)
1158		crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
1159
1160	ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,
1161						  DRM_PLANE_NO_SCALING,
1162						  DRM_PLANE_NO_SCALING,
1163						  false, false);
1164	if (ret)
1165		return ret;
1166	else if (!plane_state->visible)
1167		return 0;
1168
1169	fi = drm_format_info(DRM_FORMAT_R8);
1170	if (!fi)
1171		return -EINVAL;
1172
1173	pitch = drm_format_info_min_pitch(fi, 0, ssd130x->width);
1174
1175	if (plane_state->fb->format != fi) {
1176		void *buf;
1177
1178		/* format conversion necessary; reserve buffer */
1179		buf = drm_format_conv_state_reserve(&shadow_plane_state->fmtcnv_state,
1180						    pitch, GFP_KERNEL);
1181		if (!buf)
1182			return -ENOMEM;
1183	}
1184
1185	ssd130x_state->buffer = kcalloc(pitch, ssd130x->height, GFP_KERNEL);
1186	if (!ssd130x_state->buffer)
1187		return -ENOMEM;
1188
1189	return 0;
1190}
1191
1192static int ssd133x_primary_plane_atomic_check(struct drm_plane *plane,
1193					      struct drm_atomic_state *state)
1194{
1195	struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);
1196	struct drm_crtc *crtc = plane_state->crtc;
1197	struct drm_crtc_state *crtc_state = NULL;
1198	int ret;
1199
1200	if (crtc)
1201		crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
1202
1203	ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,
1204						  DRM_PLANE_NO_SCALING,
1205						  DRM_PLANE_NO_SCALING,
1206						  false, false);
1207	if (ret)
1208		return ret;
1209	else if (!plane_state->visible)
1210		return 0;
1211
1212	return 0;
1213}
1214
1215static void ssd130x_primary_plane_atomic_update(struct drm_plane *plane,
1216						struct drm_atomic_state *state)
1217{
1218	struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);
1219	struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane);
1220	struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);
1221	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);
1222	struct ssd130x_crtc_state *ssd130x_crtc_state =  to_ssd130x_crtc_state(crtc_state);
1223	struct ssd130x_plane_state *ssd130x_plane_state = to_ssd130x_plane_state(plane_state);
1224	struct drm_framebuffer *fb = plane_state->fb;
1225	struct drm_atomic_helper_damage_iter iter;
1226	struct drm_device *drm = plane->dev;
1227	struct drm_rect dst_clip;
1228	struct drm_rect damage;
1229	int idx;
1230
1231	if (!drm_dev_enter(drm, &idx))
1232		return;
1233
1234	drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);
1235	drm_atomic_for_each_plane_damage(&iter, &damage) {
1236		dst_clip = plane_state->dst;
1237
1238		if (!drm_rect_intersect(&dst_clip, &damage))
1239			continue;
1240
1241		ssd130x_fb_blit_rect(fb, &shadow_plane_state->data[0], &dst_clip,
1242				     ssd130x_plane_state->buffer,
1243				     ssd130x_crtc_state->data_array,
1244				     &shadow_plane_state->fmtcnv_state);
1245	}
1246
1247	drm_dev_exit(idx);
1248}
1249
1250static void ssd132x_primary_plane_atomic_update(struct drm_plane *plane,
1251						struct drm_atomic_state *state)
1252{
1253	struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);
1254	struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane);
1255	struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);
1256	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);
1257	struct ssd130x_crtc_state *ssd130x_crtc_state =  to_ssd130x_crtc_state(crtc_state);
1258	struct ssd130x_plane_state *ssd130x_plane_state = to_ssd130x_plane_state(plane_state);
1259	struct drm_framebuffer *fb = plane_state->fb;
1260	struct drm_atomic_helper_damage_iter iter;
1261	struct drm_device *drm = plane->dev;
1262	struct drm_rect dst_clip;
1263	struct drm_rect damage;
1264	int idx;
1265
1266	if (!drm_dev_enter(drm, &idx))
1267		return;
1268
1269	drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);
1270	drm_atomic_for_each_plane_damage(&iter, &damage) {
1271		dst_clip = plane_state->dst;
1272
1273		if (!drm_rect_intersect(&dst_clip, &damage))
1274			continue;
1275
1276		ssd132x_fb_blit_rect(fb, &shadow_plane_state->data[0], &dst_clip,
1277				     ssd130x_plane_state->buffer,
1278				     ssd130x_crtc_state->data_array,
1279				     &shadow_plane_state->fmtcnv_state);
1280	}
1281
1282	drm_dev_exit(idx);
1283}
1284
1285static void ssd133x_primary_plane_atomic_update(struct drm_plane *plane,
1286						struct drm_atomic_state *state)
1287{
1288	struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);
1289	struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane);
1290	struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);
1291	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);
1292	struct ssd130x_crtc_state *ssd130x_crtc_state =  to_ssd130x_crtc_state(crtc_state);
1293	struct drm_framebuffer *fb = plane_state->fb;
1294	struct drm_atomic_helper_damage_iter iter;
1295	struct drm_device *drm = plane->dev;
1296	struct drm_rect dst_clip;
1297	struct drm_rect damage;
1298	int idx;
1299
1300	if (!drm_dev_enter(drm, &idx))
1301		return;
1302
1303	drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);
1304	drm_atomic_for_each_plane_damage(&iter, &damage) {
1305		dst_clip = plane_state->dst;
1306
1307		if (!drm_rect_intersect(&dst_clip, &damage))
1308			continue;
1309
1310		ssd133x_fb_blit_rect(fb, &shadow_plane_state->data[0], &dst_clip,
1311				     ssd130x_crtc_state->data_array,
1312				     &shadow_plane_state->fmtcnv_state);
1313	}
1314
1315	drm_dev_exit(idx);
1316}
1317
1318static void ssd130x_primary_plane_atomic_disable(struct drm_plane *plane,
1319						 struct drm_atomic_state *state)
1320{
1321	struct drm_device *drm = plane->dev;
1322	struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
1323	struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);
1324	struct drm_crtc_state *crtc_state;
1325	struct ssd130x_crtc_state *ssd130x_crtc_state;
1326	int idx;
1327
1328	if (!plane_state->crtc)
1329		return;
1330
1331	crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);
1332	ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state);
1333
1334	if (!drm_dev_enter(drm, &idx))
1335		return;
1336
1337	ssd130x_clear_screen(ssd130x, ssd130x_crtc_state->data_array);
1338
1339	drm_dev_exit(idx);
1340}
1341
1342static void ssd132x_primary_plane_atomic_disable(struct drm_plane *plane,
1343						 struct drm_atomic_state *state)
1344{
1345	struct drm_device *drm = plane->dev;
1346	struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
1347	struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);
1348	struct drm_crtc_state *crtc_state;
1349	struct ssd130x_crtc_state *ssd130x_crtc_state;
1350	int idx;
1351
1352	if (!plane_state->crtc)
1353		return;
1354
1355	crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);
1356	ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state);
1357
1358	if (!drm_dev_enter(drm, &idx))
1359		return;
1360
1361	ssd132x_clear_screen(ssd130x, ssd130x_crtc_state->data_array);
1362
1363	drm_dev_exit(idx);
1364}
1365
1366static void ssd133x_primary_plane_atomic_disable(struct drm_plane *plane,
1367						 struct drm_atomic_state *state)
1368{
1369	struct drm_device *drm = plane->dev;
1370	struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
1371	struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);
1372	struct drm_crtc_state *crtc_state;
1373	struct ssd130x_crtc_state *ssd130x_crtc_state;
1374	int idx;
1375
1376	if (!plane_state->crtc)
1377		return;
1378
1379	crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);
1380	ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state);
1381
1382	if (!drm_dev_enter(drm, &idx))
1383		return;
1384
1385	ssd133x_clear_screen(ssd130x, ssd130x_crtc_state->data_array);
1386
1387	drm_dev_exit(idx);
1388}
1389
1390/* Called during init to allocate the plane's atomic state. */
1391static void ssd130x_primary_plane_reset(struct drm_plane *plane)
1392{
1393	struct ssd130x_plane_state *ssd130x_state;
1394
1395	WARN_ON(plane->state);
1396
1397	ssd130x_state = kzalloc(sizeof(*ssd130x_state), GFP_KERNEL);
1398	if (!ssd130x_state)
1399		return;
1400
1401	__drm_gem_reset_shadow_plane(plane, &ssd130x_state->base);
1402}
1403
1404static struct drm_plane_state *ssd130x_primary_plane_duplicate_state(struct drm_plane *plane)
1405{
1406	struct drm_shadow_plane_state *new_shadow_plane_state;
1407	struct ssd130x_plane_state *old_ssd130x_state;
1408	struct ssd130x_plane_state *ssd130x_state;
1409
1410	if (WARN_ON(!plane->state))
1411		return NULL;
1412
1413	old_ssd130x_state = to_ssd130x_plane_state(plane->state);
1414	ssd130x_state = kmemdup(old_ssd130x_state, sizeof(*ssd130x_state), GFP_KERNEL);
1415	if (!ssd130x_state)
1416		return NULL;
1417
1418	/* The buffer is not duplicated and is allocated in .atomic_check */
1419	ssd130x_state->buffer = NULL;
1420
1421	new_shadow_plane_state = &ssd130x_state->base;
1422
1423	__drm_gem_duplicate_shadow_plane_state(plane, new_shadow_plane_state);
1424
1425	return &new_shadow_plane_state->base;
1426}
1427
1428static void ssd130x_primary_plane_destroy_state(struct drm_plane *plane,
1429						struct drm_plane_state *state)
1430{
1431	struct ssd130x_plane_state *ssd130x_state = to_ssd130x_plane_state(state);
1432
1433	kfree(ssd130x_state->buffer);
1434
1435	__drm_gem_destroy_shadow_plane_state(&ssd130x_state->base);
1436
1437	kfree(ssd130x_state);
1438}
1439
1440static const struct drm_plane_helper_funcs ssd130x_primary_plane_helper_funcs[] = {
1441	[SSD130X_FAMILY] = {
1442		DRM_GEM_SHADOW_PLANE_HELPER_FUNCS,
1443		.atomic_check = ssd130x_primary_plane_atomic_check,
1444		.atomic_update = ssd130x_primary_plane_atomic_update,
1445		.atomic_disable = ssd130x_primary_plane_atomic_disable,
1446	},
1447	[SSD132X_FAMILY] = {
1448		DRM_GEM_SHADOW_PLANE_HELPER_FUNCS,
1449		.atomic_check = ssd132x_primary_plane_atomic_check,
1450		.atomic_update = ssd132x_primary_plane_atomic_update,
1451		.atomic_disable = ssd132x_primary_plane_atomic_disable,
1452	},
1453	[SSD133X_FAMILY] = {
1454		DRM_GEM_SHADOW_PLANE_HELPER_FUNCS,
1455		.atomic_check = ssd133x_primary_plane_atomic_check,
1456		.atomic_update = ssd133x_primary_plane_atomic_update,
1457		.atomic_disable = ssd133x_primary_plane_atomic_disable,
1458	}
1459};
1460
1461static const struct drm_plane_funcs ssd130x_primary_plane_funcs = {
1462	.update_plane = drm_atomic_helper_update_plane,
1463	.disable_plane = drm_atomic_helper_disable_plane,
1464	.reset = ssd130x_primary_plane_reset,
1465	.atomic_duplicate_state = ssd130x_primary_plane_duplicate_state,
1466	.atomic_destroy_state = ssd130x_primary_plane_destroy_state,
1467	.destroy = drm_plane_cleanup,
1468};
1469
1470static enum drm_mode_status ssd130x_crtc_mode_valid(struct drm_crtc *crtc,
1471						    const struct drm_display_mode *mode)
1472{
1473	struct ssd130x_device *ssd130x = drm_to_ssd130x(crtc->dev);
1474
1475	if (mode->hdisplay != ssd130x->mode.hdisplay &&
1476	    mode->vdisplay != ssd130x->mode.vdisplay)
1477		return MODE_ONE_SIZE;
1478	else if (mode->hdisplay != ssd130x->mode.hdisplay)
1479		return MODE_ONE_WIDTH;
1480	else if (mode->vdisplay != ssd130x->mode.vdisplay)
1481		return MODE_ONE_HEIGHT;
1482
1483	return MODE_OK;
1484}
1485
1486static int ssd130x_crtc_atomic_check(struct drm_crtc *crtc,
1487				     struct drm_atomic_state *state)
1488{
1489	struct drm_device *drm = crtc->dev;
1490	struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
1491	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
1492	struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(crtc_state);
1493	unsigned int pages = DIV_ROUND_UP(ssd130x->height, SSD130X_PAGE_HEIGHT);
1494	int ret;
1495
1496	ret = drm_crtc_helper_atomic_check(crtc, state);
1497	if (ret)
1498		return ret;
1499
1500	ssd130x_state->data_array = kmalloc(ssd130x->width * pages, GFP_KERNEL);
1501	if (!ssd130x_state->data_array)
1502		return -ENOMEM;
1503
1504	return 0;
1505}
1506
1507static int ssd132x_crtc_atomic_check(struct drm_crtc *crtc,
1508				     struct drm_atomic_state *state)
1509{
1510	struct drm_device *drm = crtc->dev;
1511	struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
1512	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
1513	struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(crtc_state);
1514	unsigned int columns = DIV_ROUND_UP(ssd130x->width, SSD132X_SEGMENT_WIDTH);
1515	int ret;
1516
1517	ret = drm_crtc_helper_atomic_check(crtc, state);
1518	if (ret)
1519		return ret;
1520
1521	ssd130x_state->data_array = kmalloc(columns * ssd130x->height, GFP_KERNEL);
1522	if (!ssd130x_state->data_array)
1523		return -ENOMEM;
1524
1525	return 0;
1526}
1527
1528static int ssd133x_crtc_atomic_check(struct drm_crtc *crtc,
1529				     struct drm_atomic_state *state)
1530{
1531	struct drm_device *drm = crtc->dev;
1532	struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
1533	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
1534	struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(crtc_state);
1535	const struct drm_format_info *fi = drm_format_info(DRM_FORMAT_RGB332);
1536	unsigned int pitch;
1537	int ret;
1538
1539	if (!fi)
1540		return -EINVAL;
1541
1542	ret = drm_crtc_helper_atomic_check(crtc, state);
1543	if (ret)
1544		return ret;
1545
1546	pitch = drm_format_info_min_pitch(fi, 0, ssd130x->width);
1547
1548	ssd130x_state->data_array = kmalloc(pitch * ssd130x->height, GFP_KERNEL);
1549	if (!ssd130x_state->data_array)
1550		return -ENOMEM;
1551
1552	return 0;
1553}
1554
1555/* Called during init to allocate the CRTC's atomic state. */
1556static void ssd130x_crtc_reset(struct drm_crtc *crtc)
1557{
1558	struct ssd130x_crtc_state *ssd130x_state;
1559
1560	WARN_ON(crtc->state);
1561
1562	ssd130x_state = kzalloc(sizeof(*ssd130x_state), GFP_KERNEL);
1563	if (!ssd130x_state)
1564		return;
1565
1566	__drm_atomic_helper_crtc_reset(crtc, &ssd130x_state->base);
1567}
1568
1569static struct drm_crtc_state *ssd130x_crtc_duplicate_state(struct drm_crtc *crtc)
1570{
1571	struct ssd130x_crtc_state *old_ssd130x_state;
1572	struct ssd130x_crtc_state *ssd130x_state;
1573
1574	if (WARN_ON(!crtc->state))
1575		return NULL;
1576
1577	old_ssd130x_state = to_ssd130x_crtc_state(crtc->state);
1578	ssd130x_state = kmemdup(old_ssd130x_state, sizeof(*ssd130x_state), GFP_KERNEL);
1579	if (!ssd130x_state)
1580		return NULL;
1581
1582	/* The buffer is not duplicated and is allocated in .atomic_check */
1583	ssd130x_state->data_array = NULL;
1584
1585	__drm_atomic_helper_crtc_duplicate_state(crtc, &ssd130x_state->base);
1586
1587	return &ssd130x_state->base;
1588}
1589
1590static void ssd130x_crtc_destroy_state(struct drm_crtc *crtc,
1591				       struct drm_crtc_state *state)
1592{
1593	struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(state);
1594
1595	kfree(ssd130x_state->data_array);
1596
1597	__drm_atomic_helper_crtc_destroy_state(state);
1598
1599	kfree(ssd130x_state);
1600}
1601
1602/*
1603 * The CRTC is always enabled. Screen updates are performed by
1604 * the primary plane's atomic_update function. Disabling clears
1605 * the screen in the primary plane's atomic_disable function.
1606 */
1607static const struct drm_crtc_helper_funcs ssd130x_crtc_helper_funcs[] = {
1608	[SSD130X_FAMILY] = {
1609		.mode_valid = ssd130x_crtc_mode_valid,
1610		.atomic_check = ssd130x_crtc_atomic_check,
1611	},
1612	[SSD132X_FAMILY] = {
1613		.mode_valid = ssd130x_crtc_mode_valid,
1614		.atomic_check = ssd132x_crtc_atomic_check,
1615	},
1616	[SSD133X_FAMILY] = {
1617		.mode_valid = ssd130x_crtc_mode_valid,
1618		.atomic_check = ssd133x_crtc_atomic_check,
1619	},
1620};
1621
1622static const struct drm_crtc_funcs ssd130x_crtc_funcs = {
1623	.reset = ssd130x_crtc_reset,
1624	.destroy = drm_crtc_cleanup,
1625	.set_config = drm_atomic_helper_set_config,
1626	.page_flip = drm_atomic_helper_page_flip,
1627	.atomic_duplicate_state = ssd130x_crtc_duplicate_state,
1628	.atomic_destroy_state = ssd130x_crtc_destroy_state,
1629};
1630
1631static void ssd130x_encoder_atomic_enable(struct drm_encoder *encoder,
1632					  struct drm_atomic_state *state)
1633{
1634	struct drm_device *drm = encoder->dev;
1635	struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
1636	int ret;
1637
1638	ret = ssd130x_power_on(ssd130x);
1639	if (ret)
1640		return;
1641
1642	ret = ssd130x_init(ssd130x);
1643	if (ret)
1644		goto power_off;
1645
1646	ssd130x_write_cmd(ssd130x, 1, SSD13XX_DISPLAY_ON);
1647
1648	backlight_enable(ssd130x->bl_dev);
1649
1650	return;
1651
1652power_off:
1653	ssd130x_power_off(ssd130x);
1654	return;
1655}
1656
1657static void ssd132x_encoder_atomic_enable(struct drm_encoder *encoder,
1658					  struct drm_atomic_state *state)
1659{
1660	struct drm_device *drm = encoder->dev;
1661	struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
1662	int ret;
1663
1664	ret = ssd130x_power_on(ssd130x);
1665	if (ret)
1666		return;
1667
1668	ret = ssd132x_init(ssd130x);
1669	if (ret)
1670		goto power_off;
1671
1672	ssd130x_write_cmd(ssd130x, 1, SSD13XX_DISPLAY_ON);
1673
1674	backlight_enable(ssd130x->bl_dev);
1675
1676	return;
1677
1678power_off:
1679	ssd130x_power_off(ssd130x);
1680}
1681
1682static void ssd133x_encoder_atomic_enable(struct drm_encoder *encoder,
1683					  struct drm_atomic_state *state)
1684{
1685	struct drm_device *drm = encoder->dev;
1686	struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
1687	int ret;
1688
1689	ret = ssd130x_power_on(ssd130x);
1690	if (ret)
1691		return;
1692
1693	ret = ssd133x_init(ssd130x);
1694	if (ret)
1695		goto power_off;
1696
1697	ssd130x_write_cmd(ssd130x, 1, SSD13XX_DISPLAY_ON);
1698
1699	backlight_enable(ssd130x->bl_dev);
1700
1701	return;
1702
1703power_off:
1704	ssd130x_power_off(ssd130x);
1705}
1706
1707static void ssd130x_encoder_atomic_disable(struct drm_encoder *encoder,
1708					   struct drm_atomic_state *state)
1709{
1710	struct drm_device *drm = encoder->dev;
1711	struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
1712
1713	backlight_disable(ssd130x->bl_dev);
1714
1715	ssd130x_write_cmd(ssd130x, 1, SSD13XX_DISPLAY_OFF);
1716
1717	ssd130x_power_off(ssd130x);
1718}
1719
1720static const struct drm_encoder_helper_funcs ssd130x_encoder_helper_funcs[] = {
1721	[SSD130X_FAMILY] = {
1722		.atomic_enable = ssd130x_encoder_atomic_enable,
1723		.atomic_disable = ssd130x_encoder_atomic_disable,
1724	},
1725	[SSD132X_FAMILY] = {
1726		.atomic_enable = ssd132x_encoder_atomic_enable,
1727		.atomic_disable = ssd130x_encoder_atomic_disable,
1728	},
1729	[SSD133X_FAMILY] = {
1730		.atomic_enable = ssd133x_encoder_atomic_enable,
1731		.atomic_disable = ssd130x_encoder_atomic_disable,
1732	}
1733};
1734
1735static const struct drm_encoder_funcs ssd130x_encoder_funcs = {
1736	.destroy = drm_encoder_cleanup,
1737};
1738
1739static int ssd130x_connector_get_modes(struct drm_connector *connector)
1740{
1741	struct ssd130x_device *ssd130x = drm_to_ssd130x(connector->dev);
1742	struct drm_display_mode *mode;
1743	struct device *dev = ssd130x->dev;
1744
1745	mode = drm_mode_duplicate(connector->dev, &ssd130x->mode);
1746	if (!mode) {
1747		dev_err(dev, "Failed to duplicated mode\n");
1748		return 0;
1749	}
1750
1751	drm_mode_probed_add(connector, mode);
1752	drm_set_preferred_mode(connector, mode->hdisplay, mode->vdisplay);
1753
1754	/* There is only a single mode */
1755	return 1;
1756}
1757
1758static const struct drm_connector_helper_funcs ssd130x_connector_helper_funcs = {
1759	.get_modes = ssd130x_connector_get_modes,
1760};
1761
1762static const struct drm_connector_funcs ssd130x_connector_funcs = {
1763	.reset = drm_atomic_helper_connector_reset,
1764	.fill_modes = drm_helper_probe_single_connector_modes,
1765	.destroy = drm_connector_cleanup,
1766	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1767	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1768};
1769
1770static const struct drm_mode_config_funcs ssd130x_mode_config_funcs = {
1771	.fb_create = drm_gem_fb_create_with_dirty,
1772	.atomic_check = drm_atomic_helper_check,
1773	.atomic_commit = drm_atomic_helper_commit,
1774};
1775
1776static const uint32_t ssd130x_formats[] = {
1777	DRM_FORMAT_XRGB8888,
1778};
1779
1780DEFINE_DRM_GEM_FOPS(ssd130x_fops);
1781
1782static const struct drm_driver ssd130x_drm_driver = {
1783	DRM_GEM_SHMEM_DRIVER_OPS,
1784	DRM_FBDEV_SHMEM_DRIVER_OPS,
1785	.name			= DRIVER_NAME,
1786	.desc			= DRIVER_DESC,
1787	.date			= DRIVER_DATE,
1788	.major			= DRIVER_MAJOR,
1789	.minor			= DRIVER_MINOR,
1790	.driver_features	= DRIVER_ATOMIC | DRIVER_GEM | DRIVER_MODESET,
1791	.fops			= &ssd130x_fops,
1792};
1793
1794static int ssd130x_update_bl(struct backlight_device *bdev)
1795{
1796	struct ssd130x_device *ssd130x = bl_get_data(bdev);
1797	int brightness = backlight_get_brightness(bdev);
1798	int ret;
1799
1800	ssd130x->contrast = brightness;
1801
1802	ret = ssd130x_write_cmd(ssd130x, 1, SSD13XX_CONTRAST);
1803	if (ret < 0)
1804		return ret;
1805
1806	ret = ssd130x_write_cmd(ssd130x, 1, ssd130x->contrast);
1807	if (ret < 0)
1808		return ret;
1809
1810	return 0;
1811}
1812
1813static const struct backlight_ops ssd130xfb_bl_ops = {
1814	.update_status	= ssd130x_update_bl,
1815};
1816
1817static void ssd130x_parse_properties(struct ssd130x_device *ssd130x)
1818{
1819	struct device *dev = ssd130x->dev;
1820
1821	if (device_property_read_u32(dev, "solomon,width", &ssd130x->width))
1822		ssd130x->width = ssd130x->device_info->default_width;
1823
1824	if (device_property_read_u32(dev, "solomon,height", &ssd130x->height))
1825		ssd130x->height = ssd130x->device_info->default_height;
1826
1827	if (device_property_read_u32(dev, "solomon,page-offset", &ssd130x->page_offset))
1828		ssd130x->page_offset = 1;
1829
1830	if (device_property_read_u32(dev, "solomon,col-offset", &ssd130x->col_offset))
1831		ssd130x->col_offset = 0;
1832
1833	if (device_property_read_u32(dev, "solomon,com-offset", &ssd130x->com_offset))
1834		ssd130x->com_offset = 0;
1835
1836	if (device_property_read_u32(dev, "solomon,prechargep1", &ssd130x->prechargep1))
1837		ssd130x->prechargep1 = 2;
1838
1839	if (device_property_read_u32(dev, "solomon,prechargep2", &ssd130x->prechargep2))
1840		ssd130x->prechargep2 = 2;
1841
1842	if (!device_property_read_u8_array(dev, "solomon,lookup-table",
1843					   ssd130x->lookup_table,
1844					   ARRAY_SIZE(ssd130x->lookup_table)))
1845		ssd130x->lookup_table_set = 1;
1846
1847	ssd130x->seg_remap = !device_property_read_bool(dev, "solomon,segment-no-remap");
1848	ssd130x->com_seq = device_property_read_bool(dev, "solomon,com-seq");
1849	ssd130x->com_lrremap = device_property_read_bool(dev, "solomon,com-lrremap");
1850	ssd130x->com_invdir = device_property_read_bool(dev, "solomon,com-invdir");
1851	ssd130x->area_color_enable =
1852		device_property_read_bool(dev, "solomon,area-color-enable");
1853	ssd130x->low_power = device_property_read_bool(dev, "solomon,low-power");
1854
1855	ssd130x->contrast = 127;
1856	ssd130x->vcomh = ssd130x->device_info->default_vcomh;
1857
1858	/* Setup display timing */
1859	if (device_property_read_u32(dev, "solomon,dclk-div", &ssd130x->dclk_div))
1860		ssd130x->dclk_div = ssd130x->device_info->default_dclk_div;
1861	if (device_property_read_u32(dev, "solomon,dclk-frq", &ssd130x->dclk_frq))
1862		ssd130x->dclk_frq = ssd130x->device_info->default_dclk_frq;
1863}
1864
1865static int ssd130x_init_modeset(struct ssd130x_device *ssd130x)
1866{
1867	enum ssd130x_family_ids family_id = ssd130x->device_info->family_id;
1868	struct drm_display_mode *mode = &ssd130x->mode;
1869	struct device *dev = ssd130x->dev;
1870	struct drm_device *drm = &ssd130x->drm;
1871	unsigned long max_width, max_height;
1872	struct drm_plane *primary_plane;
1873	struct drm_crtc *crtc;
1874	struct drm_encoder *encoder;
1875	struct drm_connector *connector;
1876	int ret;
1877
1878	/*
1879	 * Modesetting
1880	 */
1881
1882	ret = drmm_mode_config_init(drm);
1883	if (ret) {
1884		dev_err(dev, "DRM mode config init failed: %d\n", ret);
1885		return ret;
1886	}
1887
1888	mode->type = DRM_MODE_TYPE_DRIVER;
1889	mode->clock = 1;
1890	mode->hdisplay = mode->htotal = ssd130x->width;
1891	mode->hsync_start = mode->hsync_end = ssd130x->width;
1892	mode->vdisplay = mode->vtotal = ssd130x->height;
1893	mode->vsync_start = mode->vsync_end = ssd130x->height;
1894	mode->width_mm = 27;
1895	mode->height_mm = 27;
1896
1897	max_width = max_t(unsigned long, mode->hdisplay, DRM_SHADOW_PLANE_MAX_WIDTH);
1898	max_height = max_t(unsigned long, mode->vdisplay, DRM_SHADOW_PLANE_MAX_HEIGHT);
1899
1900	drm->mode_config.min_width = mode->hdisplay;
1901	drm->mode_config.max_width = max_width;
1902	drm->mode_config.min_height = mode->vdisplay;
1903	drm->mode_config.max_height = max_height;
1904	drm->mode_config.preferred_depth = 24;
1905	drm->mode_config.funcs = &ssd130x_mode_config_funcs;
1906
1907	/* Primary plane */
1908
1909	primary_plane = &ssd130x->primary_plane;
1910	ret = drm_universal_plane_init(drm, primary_plane, 0, &ssd130x_primary_plane_funcs,
1911				       ssd130x_formats, ARRAY_SIZE(ssd130x_formats),
1912				       NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
1913	if (ret) {
1914		dev_err(dev, "DRM primary plane init failed: %d\n", ret);
1915		return ret;
1916	}
1917
1918	drm_plane_helper_add(primary_plane, &ssd130x_primary_plane_helper_funcs[family_id]);
1919
1920	drm_plane_enable_fb_damage_clips(primary_plane);
1921
1922	/* CRTC */
1923
1924	crtc = &ssd130x->crtc;
1925	ret = drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1926					&ssd130x_crtc_funcs, NULL);
1927	if (ret) {
1928		dev_err(dev, "DRM crtc init failed: %d\n", ret);
1929		return ret;
1930	}
1931
1932	drm_crtc_helper_add(crtc, &ssd130x_crtc_helper_funcs[family_id]);
1933
1934	/* Encoder */
1935
1936	encoder = &ssd130x->encoder;
1937	ret = drm_encoder_init(drm, encoder, &ssd130x_encoder_funcs,
1938			       DRM_MODE_ENCODER_NONE, NULL);
1939	if (ret) {
1940		dev_err(dev, "DRM encoder init failed: %d\n", ret);
1941		return ret;
1942	}
1943
1944	drm_encoder_helper_add(encoder, &ssd130x_encoder_helper_funcs[family_id]);
1945
1946	encoder->possible_crtcs = drm_crtc_mask(crtc);
1947
1948	/* Connector */
1949
1950	connector = &ssd130x->connector;
1951	ret = drm_connector_init(drm, connector, &ssd130x_connector_funcs,
1952				 DRM_MODE_CONNECTOR_Unknown);
1953	if (ret) {
1954		dev_err(dev, "DRM connector init failed: %d\n", ret);
1955		return ret;
1956	}
1957
1958	drm_connector_helper_add(connector, &ssd130x_connector_helper_funcs);
1959
1960	ret = drm_connector_attach_encoder(connector, encoder);
1961	if (ret) {
1962		dev_err(dev, "DRM attach connector to encoder failed: %d\n", ret);
1963		return ret;
1964	}
1965
1966	drm_mode_config_reset(drm);
1967
1968	return 0;
1969}
1970
1971static int ssd130x_get_resources(struct ssd130x_device *ssd130x)
1972{
1973	struct device *dev = ssd130x->dev;
1974
1975	ssd130x->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1976	if (IS_ERR(ssd130x->reset))
1977		return dev_err_probe(dev, PTR_ERR(ssd130x->reset),
1978				     "Failed to get reset gpio\n");
1979
1980	ssd130x->vcc_reg = devm_regulator_get(dev, "vcc");
1981	if (IS_ERR(ssd130x->vcc_reg))
1982		return dev_err_probe(dev, PTR_ERR(ssd130x->vcc_reg),
1983				     "Failed to get VCC regulator\n");
1984
1985	return 0;
1986}
1987
1988struct ssd130x_device *ssd130x_probe(struct device *dev, struct regmap *regmap)
1989{
1990	struct ssd130x_device *ssd130x;
1991	struct backlight_device *bl;
1992	struct drm_device *drm;
1993	int ret;
1994
1995	ssd130x = devm_drm_dev_alloc(dev, &ssd130x_drm_driver,
1996				     struct ssd130x_device, drm);
1997	if (IS_ERR(ssd130x))
1998		return ERR_PTR(dev_err_probe(dev, PTR_ERR(ssd130x),
1999					     "Failed to allocate DRM device\n"));
2000
2001	drm = &ssd130x->drm;
2002
2003	ssd130x->dev = dev;
2004	ssd130x->regmap = regmap;
2005	ssd130x->device_info = device_get_match_data(dev);
2006
2007	if (ssd130x->device_info->page_mode_only)
2008		ssd130x->page_address_mode = 1;
2009
2010	ssd130x_parse_properties(ssd130x);
2011
2012	ret = ssd130x_get_resources(ssd130x);
2013	if (ret)
2014		return ERR_PTR(ret);
2015
2016	bl = devm_backlight_device_register(dev, dev_name(dev), dev, ssd130x,
2017					    &ssd130xfb_bl_ops, NULL);
2018	if (IS_ERR(bl))
2019		return ERR_PTR(dev_err_probe(dev, PTR_ERR(bl),
2020					     "Unable to register backlight device\n"));
2021
2022	bl->props.brightness = ssd130x->contrast;
2023	bl->props.max_brightness = MAX_CONTRAST;
2024	ssd130x->bl_dev = bl;
2025
2026	ret = ssd130x_init_modeset(ssd130x);
2027	if (ret)
2028		return ERR_PTR(ret);
2029
2030	ret = drm_dev_register(drm, 0);
2031	if (ret)
2032		return ERR_PTR(dev_err_probe(dev, ret, "DRM device register failed\n"));
2033
2034	drm_client_setup(drm, NULL);
2035
2036	return ssd130x;
2037}
2038EXPORT_SYMBOL_GPL(ssd130x_probe);
2039
2040void ssd130x_remove(struct ssd130x_device *ssd130x)
2041{
2042	drm_dev_unplug(&ssd130x->drm);
2043	drm_atomic_helper_shutdown(&ssd130x->drm);
2044}
2045EXPORT_SYMBOL_GPL(ssd130x_remove);
2046
2047void ssd130x_shutdown(struct ssd130x_device *ssd130x)
2048{
2049	drm_atomic_helper_shutdown(&ssd130x->drm);
2050}
2051EXPORT_SYMBOL_GPL(ssd130x_shutdown);
2052
2053MODULE_DESCRIPTION(DRIVER_DESC);
2054MODULE_AUTHOR("Javier Martinez Canillas <javierm@redhat.com>");
2055MODULE_LICENSE("GPL v2");