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1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Author: Damien Lespiau <damien.lespiau@intel.com>
24 *
25 */
26
27#include <linux/ctype.h>
28#include <linux/debugfs.h>
29#include <linux/seq_file.h>
30
31#include "i915_irq.h"
32#include "i915_reg.h"
33#include "intel_atomic.h"
34#include "intel_de.h"
35#include "intel_display_irq.h"
36#include "intel_display_types.h"
37#include "intel_pipe_crc.h"
38#include "intel_pipe_crc_regs.h"
39
40static const char * const pipe_crc_sources[] = {
41 [INTEL_PIPE_CRC_SOURCE_NONE] = "none",
42 [INTEL_PIPE_CRC_SOURCE_PLANE1] = "plane1",
43 [INTEL_PIPE_CRC_SOURCE_PLANE2] = "plane2",
44 [INTEL_PIPE_CRC_SOURCE_PLANE3] = "plane3",
45 [INTEL_PIPE_CRC_SOURCE_PLANE4] = "plane4",
46 [INTEL_PIPE_CRC_SOURCE_PLANE5] = "plane5",
47 [INTEL_PIPE_CRC_SOURCE_PLANE6] = "plane6",
48 [INTEL_PIPE_CRC_SOURCE_PLANE7] = "plane7",
49 [INTEL_PIPE_CRC_SOURCE_PIPE] = "pipe",
50 [INTEL_PIPE_CRC_SOURCE_TV] = "TV",
51 [INTEL_PIPE_CRC_SOURCE_DP_B] = "DP-B",
52 [INTEL_PIPE_CRC_SOURCE_DP_C] = "DP-C",
53 [INTEL_PIPE_CRC_SOURCE_DP_D] = "DP-D",
54 [INTEL_PIPE_CRC_SOURCE_AUTO] = "auto",
55};
56
57static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
58 u32 *val)
59{
60 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
61 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
62
63 switch (*source) {
64 case INTEL_PIPE_CRC_SOURCE_PIPE:
65 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
66 break;
67 case INTEL_PIPE_CRC_SOURCE_NONE:
68 *val = 0;
69 break;
70 default:
71 return -EINVAL;
72 }
73
74 return 0;
75}
76
77static void i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
78 enum pipe pipe,
79 enum intel_pipe_crc_source *source)
80{
81 struct intel_encoder *encoder;
82 struct intel_crtc *crtc;
83 struct intel_digital_port *dig_port;
84
85 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
86
87 drm_modeset_lock_all(&dev_priv->drm);
88 for_each_intel_encoder(&dev_priv->drm, encoder) {
89 if (!encoder->base.crtc)
90 continue;
91
92 crtc = to_intel_crtc(encoder->base.crtc);
93
94 if (crtc->pipe != pipe)
95 continue;
96
97 switch (encoder->type) {
98 case INTEL_OUTPUT_TVOUT:
99 *source = INTEL_PIPE_CRC_SOURCE_TV;
100 break;
101 case INTEL_OUTPUT_DP:
102 case INTEL_OUTPUT_EDP:
103 dig_port = enc_to_dig_port(encoder);
104 switch (dig_port->base.port) {
105 case PORT_B:
106 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
107 break;
108 case PORT_C:
109 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
110 break;
111 case PORT_D:
112 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
113 break;
114 default:
115 drm_WARN(&dev_priv->drm, 1, "nonexisting DP port %c\n",
116 port_name(dig_port->base.port));
117 break;
118 }
119 break;
120 default:
121 break;
122 }
123 }
124 drm_modeset_unlock_all(&dev_priv->drm);
125}
126
127static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
128 enum pipe pipe,
129 enum intel_pipe_crc_source *source,
130 u32 *val)
131{
132 bool need_stable_symbols = false;
133
134 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
135 i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
136
137 switch (*source) {
138 case INTEL_PIPE_CRC_SOURCE_PIPE:
139 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
140 break;
141 case INTEL_PIPE_CRC_SOURCE_DP_B:
142 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
143 need_stable_symbols = true;
144 break;
145 case INTEL_PIPE_CRC_SOURCE_DP_C:
146 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
147 need_stable_symbols = true;
148 break;
149 case INTEL_PIPE_CRC_SOURCE_DP_D:
150 if (!IS_CHERRYVIEW(dev_priv))
151 return -EINVAL;
152 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
153 need_stable_symbols = true;
154 break;
155 case INTEL_PIPE_CRC_SOURCE_NONE:
156 *val = 0;
157 break;
158 default:
159 return -EINVAL;
160 }
161
162 /*
163 * When the pipe CRC tap point is after the transcoders we need
164 * to tweak symbol-level features to produce a deterministic series of
165 * symbols for a given frame. We need to reset those features only once
166 * a frame (instead of every nth symbol):
167 * - DC-balance: used to ensure a better clock recovery from the data
168 * link (SDVO)
169 * - DisplayPort scrambling: used for EMI reduction
170 */
171 if (need_stable_symbols) {
172 u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X(dev_priv));
173
174 tmp |= DC_BALANCE_RESET_VLV;
175 switch (pipe) {
176 case PIPE_A:
177 tmp |= PIPE_A_SCRAMBLE_RESET;
178 break;
179 case PIPE_B:
180 tmp |= PIPE_B_SCRAMBLE_RESET;
181 break;
182 case PIPE_C:
183 tmp |= PIPE_C_SCRAMBLE_RESET;
184 break;
185 default:
186 return -EINVAL;
187 }
188 intel_de_write(dev_priv, PORT_DFT2_G4X(dev_priv), tmp);
189 }
190
191 return 0;
192}
193
194static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
195 enum pipe pipe,
196 enum intel_pipe_crc_source *source,
197 u32 *val)
198{
199 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
200 i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
201
202 switch (*source) {
203 case INTEL_PIPE_CRC_SOURCE_PIPE:
204 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
205 break;
206 case INTEL_PIPE_CRC_SOURCE_TV:
207 if (!SUPPORTS_TV(dev_priv))
208 return -EINVAL;
209 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
210 break;
211 case INTEL_PIPE_CRC_SOURCE_NONE:
212 *val = 0;
213 break;
214 default:
215 /*
216 * The DP CRC source doesn't work on g4x.
217 * It can be made to work to some degree by selecting
218 * the correct CRC source before the port is enabled,
219 * and not touching the CRC source bits again until
220 * the port is disabled. But even then the bits
221 * eventually get stuck and a reboot is needed to get
222 * working CRCs on the pipe again. Let's simply
223 * refuse to use DP CRCs on g4x.
224 */
225 return -EINVAL;
226 }
227
228 return 0;
229}
230
231static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
232 enum pipe pipe)
233{
234 u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X(dev_priv));
235
236 switch (pipe) {
237 case PIPE_A:
238 tmp &= ~PIPE_A_SCRAMBLE_RESET;
239 break;
240 case PIPE_B:
241 tmp &= ~PIPE_B_SCRAMBLE_RESET;
242 break;
243 case PIPE_C:
244 tmp &= ~PIPE_C_SCRAMBLE_RESET;
245 break;
246 default:
247 return;
248 }
249 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
250 tmp &= ~DC_BALANCE_RESET_VLV;
251 intel_de_write(dev_priv, PORT_DFT2_G4X(dev_priv), tmp);
252}
253
254static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
255 u32 *val)
256{
257 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
258 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
259
260 switch (*source) {
261 case INTEL_PIPE_CRC_SOURCE_PLANE1:
262 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
263 break;
264 case INTEL_PIPE_CRC_SOURCE_PLANE2:
265 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
266 break;
267 case INTEL_PIPE_CRC_SOURCE_PIPE:
268 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
269 break;
270 case INTEL_PIPE_CRC_SOURCE_NONE:
271 *val = 0;
272 break;
273 default:
274 return -EINVAL;
275 }
276
277 return 0;
278}
279
280static void
281intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
282{
283 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
284 struct intel_crtc_state *pipe_config;
285 struct drm_atomic_state *state;
286 struct drm_modeset_acquire_ctx ctx;
287 int ret;
288
289 if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
290 i915gm_irq_cstate_wa(dev_priv, enable);
291
292 drm_modeset_acquire_init(&ctx, 0);
293
294 state = drm_atomic_state_alloc(&dev_priv->drm);
295 if (!state) {
296 ret = -ENOMEM;
297 goto unlock;
298 }
299
300 state->acquire_ctx = &ctx;
301 to_intel_atomic_state(state)->internal = true;
302
303retry:
304 pipe_config = intel_atomic_get_crtc_state(state, crtc);
305 if (IS_ERR(pipe_config)) {
306 ret = PTR_ERR(pipe_config);
307 goto put_state;
308 }
309
310 pipe_config->uapi.mode_changed = pipe_config->has_psr;
311 pipe_config->crc_enabled = enable;
312
313 if (IS_HASWELL(dev_priv) &&
314 pipe_config->hw.active && crtc->pipe == PIPE_A &&
315 pipe_config->cpu_transcoder == TRANSCODER_EDP)
316 pipe_config->uapi.mode_changed = true;
317
318 ret = drm_atomic_commit(state);
319
320put_state:
321 if (ret == -EDEADLK) {
322 drm_atomic_state_clear(state);
323 drm_modeset_backoff(&ctx);
324 goto retry;
325 }
326
327 drm_atomic_state_put(state);
328unlock:
329 drm_WARN(&dev_priv->drm, ret,
330 "Toggling workaround to %i returns %i\n", enable, ret);
331 drm_modeset_drop_locks(&ctx);
332 drm_modeset_acquire_fini(&ctx);
333}
334
335static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
336 enum pipe pipe,
337 enum intel_pipe_crc_source *source,
338 u32 *val)
339{
340 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
341 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
342
343 switch (*source) {
344 case INTEL_PIPE_CRC_SOURCE_PLANE1:
345 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
346 break;
347 case INTEL_PIPE_CRC_SOURCE_PLANE2:
348 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
349 break;
350 case INTEL_PIPE_CRC_SOURCE_PIPE:
351 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
352 break;
353 case INTEL_PIPE_CRC_SOURCE_NONE:
354 *val = 0;
355 break;
356 default:
357 return -EINVAL;
358 }
359
360 return 0;
361}
362
363static int skl_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
364 enum pipe pipe,
365 enum intel_pipe_crc_source *source,
366 u32 *val)
367{
368 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
369 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
370
371 switch (*source) {
372 case INTEL_PIPE_CRC_SOURCE_PLANE1:
373 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_1_SKL;
374 break;
375 case INTEL_PIPE_CRC_SOURCE_PLANE2:
376 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_2_SKL;
377 break;
378 case INTEL_PIPE_CRC_SOURCE_PLANE3:
379 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_3_SKL;
380 break;
381 case INTEL_PIPE_CRC_SOURCE_PLANE4:
382 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_4_SKL;
383 break;
384 case INTEL_PIPE_CRC_SOURCE_PLANE5:
385 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_5_SKL;
386 break;
387 case INTEL_PIPE_CRC_SOURCE_PLANE6:
388 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_6_SKL;
389 break;
390 case INTEL_PIPE_CRC_SOURCE_PLANE7:
391 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_7_SKL;
392 break;
393 case INTEL_PIPE_CRC_SOURCE_PIPE:
394 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DMUX_SKL;
395 break;
396 case INTEL_PIPE_CRC_SOURCE_NONE:
397 *val = 0;
398 break;
399 default:
400 return -EINVAL;
401 }
402
403 return 0;
404}
405
406static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
407 enum pipe pipe,
408 enum intel_pipe_crc_source *source, u32 *val)
409{
410 if (DISPLAY_VER(dev_priv) == 2)
411 return i8xx_pipe_crc_ctl_reg(source, val);
412 else if (DISPLAY_VER(dev_priv) < 5)
413 return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
414 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
415 return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
416 else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv))
417 return ilk_pipe_crc_ctl_reg(source, val);
418 else if (DISPLAY_VER(dev_priv) < 9)
419 return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
420 else
421 return skl_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
422}
423
424static int
425display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
426{
427 int i;
428
429 if (!buf) {
430 *s = INTEL_PIPE_CRC_SOURCE_NONE;
431 return 0;
432 }
433
434 i = match_string(pipe_crc_sources, ARRAY_SIZE(pipe_crc_sources), buf);
435 if (i < 0)
436 return i;
437
438 *s = i;
439 return 0;
440}
441
442void intel_crtc_crc_init(struct intel_crtc *crtc)
443{
444 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
445
446 spin_lock_init(&pipe_crc->lock);
447}
448
449static int i8xx_crc_source_valid(struct drm_i915_private *dev_priv,
450 const enum intel_pipe_crc_source source)
451{
452 switch (source) {
453 case INTEL_PIPE_CRC_SOURCE_PIPE:
454 case INTEL_PIPE_CRC_SOURCE_NONE:
455 return 0;
456 default:
457 return -EINVAL;
458 }
459}
460
461static int i9xx_crc_source_valid(struct drm_i915_private *dev_priv,
462 const enum intel_pipe_crc_source source)
463{
464 switch (source) {
465 case INTEL_PIPE_CRC_SOURCE_PIPE:
466 case INTEL_PIPE_CRC_SOURCE_TV:
467 case INTEL_PIPE_CRC_SOURCE_NONE:
468 return 0;
469 default:
470 return -EINVAL;
471 }
472}
473
474static int vlv_crc_source_valid(struct drm_i915_private *dev_priv,
475 const enum intel_pipe_crc_source source)
476{
477 switch (source) {
478 case INTEL_PIPE_CRC_SOURCE_PIPE:
479 case INTEL_PIPE_CRC_SOURCE_DP_B:
480 case INTEL_PIPE_CRC_SOURCE_DP_C:
481 case INTEL_PIPE_CRC_SOURCE_DP_D:
482 case INTEL_PIPE_CRC_SOURCE_NONE:
483 return 0;
484 default:
485 return -EINVAL;
486 }
487}
488
489static int ilk_crc_source_valid(struct drm_i915_private *dev_priv,
490 const enum intel_pipe_crc_source source)
491{
492 switch (source) {
493 case INTEL_PIPE_CRC_SOURCE_PIPE:
494 case INTEL_PIPE_CRC_SOURCE_PLANE1:
495 case INTEL_PIPE_CRC_SOURCE_PLANE2:
496 case INTEL_PIPE_CRC_SOURCE_NONE:
497 return 0;
498 default:
499 return -EINVAL;
500 }
501}
502
503static int ivb_crc_source_valid(struct drm_i915_private *dev_priv,
504 const enum intel_pipe_crc_source source)
505{
506 switch (source) {
507 case INTEL_PIPE_CRC_SOURCE_PIPE:
508 case INTEL_PIPE_CRC_SOURCE_PLANE1:
509 case INTEL_PIPE_CRC_SOURCE_PLANE2:
510 case INTEL_PIPE_CRC_SOURCE_NONE:
511 return 0;
512 default:
513 return -EINVAL;
514 }
515}
516
517static int skl_crc_source_valid(struct drm_i915_private *dev_priv,
518 const enum intel_pipe_crc_source source)
519{
520 switch (source) {
521 case INTEL_PIPE_CRC_SOURCE_PIPE:
522 case INTEL_PIPE_CRC_SOURCE_PLANE1:
523 case INTEL_PIPE_CRC_SOURCE_PLANE2:
524 case INTEL_PIPE_CRC_SOURCE_PLANE3:
525 case INTEL_PIPE_CRC_SOURCE_PLANE4:
526 case INTEL_PIPE_CRC_SOURCE_PLANE5:
527 case INTEL_PIPE_CRC_SOURCE_PLANE6:
528 case INTEL_PIPE_CRC_SOURCE_PLANE7:
529 case INTEL_PIPE_CRC_SOURCE_NONE:
530 return 0;
531 default:
532 return -EINVAL;
533 }
534}
535
536static int
537intel_is_valid_crc_source(struct drm_i915_private *dev_priv,
538 const enum intel_pipe_crc_source source)
539{
540 if (DISPLAY_VER(dev_priv) == 2)
541 return i8xx_crc_source_valid(dev_priv, source);
542 else if (DISPLAY_VER(dev_priv) < 5)
543 return i9xx_crc_source_valid(dev_priv, source);
544 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
545 return vlv_crc_source_valid(dev_priv, source);
546 else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv))
547 return ilk_crc_source_valid(dev_priv, source);
548 else if (DISPLAY_VER(dev_priv) < 9)
549 return ivb_crc_source_valid(dev_priv, source);
550 else
551 return skl_crc_source_valid(dev_priv, source);
552}
553
554const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
555 size_t *count)
556{
557 *count = ARRAY_SIZE(pipe_crc_sources);
558 return pipe_crc_sources;
559}
560
561int intel_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
562 size_t *values_cnt)
563{
564 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
565 enum intel_pipe_crc_source source;
566
567 if (display_crc_ctl_parse_source(source_name, &source) < 0) {
568 drm_dbg(&dev_priv->drm, "unknown source %s\n", source_name);
569 return -EINVAL;
570 }
571
572 if (source == INTEL_PIPE_CRC_SOURCE_AUTO ||
573 intel_is_valid_crc_source(dev_priv, source) == 0) {
574 *values_cnt = 5;
575 return 0;
576 }
577
578 return -EINVAL;
579}
580
581int intel_crtc_set_crc_source(struct drm_crtc *_crtc, const char *source_name)
582{
583 struct intel_crtc *crtc = to_intel_crtc(_crtc);
584 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
585 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
586 enum intel_display_power_domain power_domain;
587 enum intel_pipe_crc_source source;
588 enum pipe pipe = crtc->pipe;
589 intel_wakeref_t wakeref;
590 u32 val = 0; /* shut up gcc */
591 int ret = 0;
592 bool enable;
593
594 if (display_crc_ctl_parse_source(source_name, &source) < 0) {
595 drm_dbg(&dev_priv->drm, "unknown source %s\n", source_name);
596 return -EINVAL;
597 }
598
599 power_domain = POWER_DOMAIN_PIPE(pipe);
600 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
601 if (!wakeref) {
602 drm_dbg_kms(&dev_priv->drm,
603 "Trying to capture CRC while pipe is off\n");
604 return -EIO;
605 }
606
607 enable = source != INTEL_PIPE_CRC_SOURCE_NONE;
608 if (enable)
609 intel_crtc_crc_setup_workarounds(crtc, true);
610
611 ret = get_new_crc_ctl_reg(dev_priv, pipe, &source, &val);
612 if (ret != 0)
613 goto out;
614
615 pipe_crc->source = source;
616 intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), val);
617 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe));
618
619 if (!source) {
620 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
621 vlv_undo_pipe_scramble_reset(dev_priv, pipe);
622 }
623
624 pipe_crc->skipped = 0;
625
626out:
627 if (!enable)
628 intel_crtc_crc_setup_workarounds(crtc, false);
629
630 intel_display_power_put(dev_priv, power_domain, wakeref);
631
632 return ret;
633}
634
635void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
636{
637 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
638 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
639 enum pipe pipe = crtc->pipe;
640 u32 val = 0;
641
642 if (!crtc->base.crc.opened)
643 return;
644
645 if (get_new_crc_ctl_reg(dev_priv, pipe, &pipe_crc->source, &val) < 0)
646 return;
647
648 /* Don't need pipe_crc->lock here, IRQs are not generated. */
649 pipe_crc->skipped = 0;
650
651 intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), val);
652 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe));
653}
654
655void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
656{
657 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
658 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
659 enum pipe pipe = crtc->pipe;
660
661 /* Swallow crc's until we stop generating them. */
662 spin_lock_irq(&pipe_crc->lock);
663 pipe_crc->skipped = INT_MIN;
664 spin_unlock_irq(&pipe_crc->lock);
665
666 intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), 0);
667 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe));
668 intel_synchronize_irq(dev_priv);
669}
1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Author: Damien Lespiau <damien.lespiau@intel.com>
24 *
25 */
26
27#include <linux/ctype.h>
28#include <linux/debugfs.h>
29#include <linux/seq_file.h>
30
31#include "i915_irq.h"
32#include "i915_reg.h"
33#include "intel_atomic.h"
34#include "intel_de.h"
35#include "intel_display_types.h"
36#include "intel_pipe_crc.h"
37
38static const char * const pipe_crc_sources[] = {
39 [INTEL_PIPE_CRC_SOURCE_NONE] = "none",
40 [INTEL_PIPE_CRC_SOURCE_PLANE1] = "plane1",
41 [INTEL_PIPE_CRC_SOURCE_PLANE2] = "plane2",
42 [INTEL_PIPE_CRC_SOURCE_PLANE3] = "plane3",
43 [INTEL_PIPE_CRC_SOURCE_PLANE4] = "plane4",
44 [INTEL_PIPE_CRC_SOURCE_PLANE5] = "plane5",
45 [INTEL_PIPE_CRC_SOURCE_PLANE6] = "plane6",
46 [INTEL_PIPE_CRC_SOURCE_PLANE7] = "plane7",
47 [INTEL_PIPE_CRC_SOURCE_PIPE] = "pipe",
48 [INTEL_PIPE_CRC_SOURCE_TV] = "TV",
49 [INTEL_PIPE_CRC_SOURCE_DP_B] = "DP-B",
50 [INTEL_PIPE_CRC_SOURCE_DP_C] = "DP-C",
51 [INTEL_PIPE_CRC_SOURCE_DP_D] = "DP-D",
52 [INTEL_PIPE_CRC_SOURCE_AUTO] = "auto",
53};
54
55static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
56 u32 *val)
57{
58 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
59 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
60
61 switch (*source) {
62 case INTEL_PIPE_CRC_SOURCE_PIPE:
63 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
64 break;
65 case INTEL_PIPE_CRC_SOURCE_NONE:
66 *val = 0;
67 break;
68 default:
69 return -EINVAL;
70 }
71
72 return 0;
73}
74
75static void i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
76 enum pipe pipe,
77 enum intel_pipe_crc_source *source)
78{
79 struct intel_encoder *encoder;
80 struct intel_crtc *crtc;
81 struct intel_digital_port *dig_port;
82
83 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
84
85 drm_modeset_lock_all(&dev_priv->drm);
86 for_each_intel_encoder(&dev_priv->drm, encoder) {
87 if (!encoder->base.crtc)
88 continue;
89
90 crtc = to_intel_crtc(encoder->base.crtc);
91
92 if (crtc->pipe != pipe)
93 continue;
94
95 switch (encoder->type) {
96 case INTEL_OUTPUT_TVOUT:
97 *source = INTEL_PIPE_CRC_SOURCE_TV;
98 break;
99 case INTEL_OUTPUT_DP:
100 case INTEL_OUTPUT_EDP:
101 dig_port = enc_to_dig_port(encoder);
102 switch (dig_port->base.port) {
103 case PORT_B:
104 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
105 break;
106 case PORT_C:
107 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
108 break;
109 case PORT_D:
110 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
111 break;
112 default:
113 drm_WARN(&dev_priv->drm, 1, "nonexisting DP port %c\n",
114 port_name(dig_port->base.port));
115 break;
116 }
117 break;
118 default:
119 break;
120 }
121 }
122 drm_modeset_unlock_all(&dev_priv->drm);
123}
124
125static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
126 enum pipe pipe,
127 enum intel_pipe_crc_source *source,
128 u32 *val)
129{
130 bool need_stable_symbols = false;
131
132 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
133 i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
134
135 switch (*source) {
136 case INTEL_PIPE_CRC_SOURCE_PIPE:
137 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
138 break;
139 case INTEL_PIPE_CRC_SOURCE_DP_B:
140 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
141 need_stable_symbols = true;
142 break;
143 case INTEL_PIPE_CRC_SOURCE_DP_C:
144 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
145 need_stable_symbols = true;
146 break;
147 case INTEL_PIPE_CRC_SOURCE_DP_D:
148 if (!IS_CHERRYVIEW(dev_priv))
149 return -EINVAL;
150 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
151 need_stable_symbols = true;
152 break;
153 case INTEL_PIPE_CRC_SOURCE_NONE:
154 *val = 0;
155 break;
156 default:
157 return -EINVAL;
158 }
159
160 /*
161 * When the pipe CRC tap point is after the transcoders we need
162 * to tweak symbol-level features to produce a deterministic series of
163 * symbols for a given frame. We need to reset those features only once
164 * a frame (instead of every nth symbol):
165 * - DC-balance: used to ensure a better clock recovery from the data
166 * link (SDVO)
167 * - DisplayPort scrambling: used for EMI reduction
168 */
169 if (need_stable_symbols) {
170 u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X);
171
172 tmp |= DC_BALANCE_RESET_VLV;
173 switch (pipe) {
174 case PIPE_A:
175 tmp |= PIPE_A_SCRAMBLE_RESET;
176 break;
177 case PIPE_B:
178 tmp |= PIPE_B_SCRAMBLE_RESET;
179 break;
180 case PIPE_C:
181 tmp |= PIPE_C_SCRAMBLE_RESET;
182 break;
183 default:
184 return -EINVAL;
185 }
186 intel_de_write(dev_priv, PORT_DFT2_G4X, tmp);
187 }
188
189 return 0;
190}
191
192static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
193 enum pipe pipe,
194 enum intel_pipe_crc_source *source,
195 u32 *val)
196{
197 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
198 i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
199
200 switch (*source) {
201 case INTEL_PIPE_CRC_SOURCE_PIPE:
202 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
203 break;
204 case INTEL_PIPE_CRC_SOURCE_TV:
205 if (!SUPPORTS_TV(dev_priv))
206 return -EINVAL;
207 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
208 break;
209 case INTEL_PIPE_CRC_SOURCE_NONE:
210 *val = 0;
211 break;
212 default:
213 /*
214 * The DP CRC source doesn't work on g4x.
215 * It can be made to work to some degree by selecting
216 * the correct CRC source before the port is enabled,
217 * and not touching the CRC source bits again until
218 * the port is disabled. But even then the bits
219 * eventually get stuck and a reboot is needed to get
220 * working CRCs on the pipe again. Let's simply
221 * refuse to use DP CRCs on g4x.
222 */
223 return -EINVAL;
224 }
225
226 return 0;
227}
228
229static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
230 enum pipe pipe)
231{
232 u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X);
233
234 switch (pipe) {
235 case PIPE_A:
236 tmp &= ~PIPE_A_SCRAMBLE_RESET;
237 break;
238 case PIPE_B:
239 tmp &= ~PIPE_B_SCRAMBLE_RESET;
240 break;
241 case PIPE_C:
242 tmp &= ~PIPE_C_SCRAMBLE_RESET;
243 break;
244 default:
245 return;
246 }
247 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
248 tmp &= ~DC_BALANCE_RESET_VLV;
249 intel_de_write(dev_priv, PORT_DFT2_G4X, tmp);
250}
251
252static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
253 u32 *val)
254{
255 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
256 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
257
258 switch (*source) {
259 case INTEL_PIPE_CRC_SOURCE_PLANE1:
260 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
261 break;
262 case INTEL_PIPE_CRC_SOURCE_PLANE2:
263 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
264 break;
265 case INTEL_PIPE_CRC_SOURCE_PIPE:
266 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
267 break;
268 case INTEL_PIPE_CRC_SOURCE_NONE:
269 *val = 0;
270 break;
271 default:
272 return -EINVAL;
273 }
274
275 return 0;
276}
277
278static void
279intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
280{
281 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
282 struct intel_crtc_state *pipe_config;
283 struct drm_atomic_state *state;
284 struct drm_modeset_acquire_ctx ctx;
285 int ret;
286
287 drm_modeset_acquire_init(&ctx, 0);
288
289 state = drm_atomic_state_alloc(&dev_priv->drm);
290 if (!state) {
291 ret = -ENOMEM;
292 goto unlock;
293 }
294
295 state->acquire_ctx = &ctx;
296 to_intel_atomic_state(state)->internal = true;
297
298retry:
299 pipe_config = intel_atomic_get_crtc_state(state, crtc);
300 if (IS_ERR(pipe_config)) {
301 ret = PTR_ERR(pipe_config);
302 goto put_state;
303 }
304
305 pipe_config->uapi.mode_changed = pipe_config->has_psr;
306 pipe_config->crc_enabled = enable;
307
308 if (IS_HASWELL(dev_priv) &&
309 pipe_config->hw.active && crtc->pipe == PIPE_A &&
310 pipe_config->cpu_transcoder == TRANSCODER_EDP)
311 pipe_config->uapi.mode_changed = true;
312
313 ret = drm_atomic_commit(state);
314
315put_state:
316 if (ret == -EDEADLK) {
317 drm_atomic_state_clear(state);
318 drm_modeset_backoff(&ctx);
319 goto retry;
320 }
321
322 drm_atomic_state_put(state);
323unlock:
324 drm_WARN(&dev_priv->drm, ret,
325 "Toggling workaround to %i returns %i\n", enable, ret);
326 drm_modeset_drop_locks(&ctx);
327 drm_modeset_acquire_fini(&ctx);
328}
329
330static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
331 enum pipe pipe,
332 enum intel_pipe_crc_source *source,
333 u32 *val)
334{
335 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
336 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
337
338 switch (*source) {
339 case INTEL_PIPE_CRC_SOURCE_PLANE1:
340 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
341 break;
342 case INTEL_PIPE_CRC_SOURCE_PLANE2:
343 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
344 break;
345 case INTEL_PIPE_CRC_SOURCE_PIPE:
346 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
347 break;
348 case INTEL_PIPE_CRC_SOURCE_NONE:
349 *val = 0;
350 break;
351 default:
352 return -EINVAL;
353 }
354
355 return 0;
356}
357
358static int skl_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
359 enum pipe pipe,
360 enum intel_pipe_crc_source *source,
361 u32 *val)
362{
363 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
364 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
365
366 switch (*source) {
367 case INTEL_PIPE_CRC_SOURCE_PLANE1:
368 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_1_SKL;
369 break;
370 case INTEL_PIPE_CRC_SOURCE_PLANE2:
371 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_2_SKL;
372 break;
373 case INTEL_PIPE_CRC_SOURCE_PLANE3:
374 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_3_SKL;
375 break;
376 case INTEL_PIPE_CRC_SOURCE_PLANE4:
377 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_4_SKL;
378 break;
379 case INTEL_PIPE_CRC_SOURCE_PLANE5:
380 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_5_SKL;
381 break;
382 case INTEL_PIPE_CRC_SOURCE_PLANE6:
383 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_6_SKL;
384 break;
385 case INTEL_PIPE_CRC_SOURCE_PLANE7:
386 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_7_SKL;
387 break;
388 case INTEL_PIPE_CRC_SOURCE_PIPE:
389 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DMUX_SKL;
390 break;
391 case INTEL_PIPE_CRC_SOURCE_NONE:
392 *val = 0;
393 break;
394 default:
395 return -EINVAL;
396 }
397
398 return 0;
399}
400
401static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
402 enum pipe pipe,
403 enum intel_pipe_crc_source *source, u32 *val)
404{
405 if (DISPLAY_VER(dev_priv) == 2)
406 return i8xx_pipe_crc_ctl_reg(source, val);
407 else if (DISPLAY_VER(dev_priv) < 5)
408 return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
409 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
410 return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
411 else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv))
412 return ilk_pipe_crc_ctl_reg(source, val);
413 else if (DISPLAY_VER(dev_priv) < 9)
414 return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
415 else
416 return skl_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
417}
418
419static int
420display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
421{
422 int i;
423
424 if (!buf) {
425 *s = INTEL_PIPE_CRC_SOURCE_NONE;
426 return 0;
427 }
428
429 i = match_string(pipe_crc_sources, ARRAY_SIZE(pipe_crc_sources), buf);
430 if (i < 0)
431 return i;
432
433 *s = i;
434 return 0;
435}
436
437void intel_crtc_crc_init(struct intel_crtc *crtc)
438{
439 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
440
441 spin_lock_init(&pipe_crc->lock);
442}
443
444static int i8xx_crc_source_valid(struct drm_i915_private *dev_priv,
445 const enum intel_pipe_crc_source source)
446{
447 switch (source) {
448 case INTEL_PIPE_CRC_SOURCE_PIPE:
449 case INTEL_PIPE_CRC_SOURCE_NONE:
450 return 0;
451 default:
452 return -EINVAL;
453 }
454}
455
456static int i9xx_crc_source_valid(struct drm_i915_private *dev_priv,
457 const enum intel_pipe_crc_source source)
458{
459 switch (source) {
460 case INTEL_PIPE_CRC_SOURCE_PIPE:
461 case INTEL_PIPE_CRC_SOURCE_TV:
462 case INTEL_PIPE_CRC_SOURCE_NONE:
463 return 0;
464 default:
465 return -EINVAL;
466 }
467}
468
469static int vlv_crc_source_valid(struct drm_i915_private *dev_priv,
470 const enum intel_pipe_crc_source source)
471{
472 switch (source) {
473 case INTEL_PIPE_CRC_SOURCE_PIPE:
474 case INTEL_PIPE_CRC_SOURCE_DP_B:
475 case INTEL_PIPE_CRC_SOURCE_DP_C:
476 case INTEL_PIPE_CRC_SOURCE_DP_D:
477 case INTEL_PIPE_CRC_SOURCE_NONE:
478 return 0;
479 default:
480 return -EINVAL;
481 }
482}
483
484static int ilk_crc_source_valid(struct drm_i915_private *dev_priv,
485 const enum intel_pipe_crc_source source)
486{
487 switch (source) {
488 case INTEL_PIPE_CRC_SOURCE_PIPE:
489 case INTEL_PIPE_CRC_SOURCE_PLANE1:
490 case INTEL_PIPE_CRC_SOURCE_PLANE2:
491 case INTEL_PIPE_CRC_SOURCE_NONE:
492 return 0;
493 default:
494 return -EINVAL;
495 }
496}
497
498static int ivb_crc_source_valid(struct drm_i915_private *dev_priv,
499 const enum intel_pipe_crc_source source)
500{
501 switch (source) {
502 case INTEL_PIPE_CRC_SOURCE_PIPE:
503 case INTEL_PIPE_CRC_SOURCE_PLANE1:
504 case INTEL_PIPE_CRC_SOURCE_PLANE2:
505 case INTEL_PIPE_CRC_SOURCE_NONE:
506 return 0;
507 default:
508 return -EINVAL;
509 }
510}
511
512static int skl_crc_source_valid(struct drm_i915_private *dev_priv,
513 const enum intel_pipe_crc_source source)
514{
515 switch (source) {
516 case INTEL_PIPE_CRC_SOURCE_PIPE:
517 case INTEL_PIPE_CRC_SOURCE_PLANE1:
518 case INTEL_PIPE_CRC_SOURCE_PLANE2:
519 case INTEL_PIPE_CRC_SOURCE_PLANE3:
520 case INTEL_PIPE_CRC_SOURCE_PLANE4:
521 case INTEL_PIPE_CRC_SOURCE_PLANE5:
522 case INTEL_PIPE_CRC_SOURCE_PLANE6:
523 case INTEL_PIPE_CRC_SOURCE_PLANE7:
524 case INTEL_PIPE_CRC_SOURCE_NONE:
525 return 0;
526 default:
527 return -EINVAL;
528 }
529}
530
531static int
532intel_is_valid_crc_source(struct drm_i915_private *dev_priv,
533 const enum intel_pipe_crc_source source)
534{
535 if (DISPLAY_VER(dev_priv) == 2)
536 return i8xx_crc_source_valid(dev_priv, source);
537 else if (DISPLAY_VER(dev_priv) < 5)
538 return i9xx_crc_source_valid(dev_priv, source);
539 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
540 return vlv_crc_source_valid(dev_priv, source);
541 else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv))
542 return ilk_crc_source_valid(dev_priv, source);
543 else if (DISPLAY_VER(dev_priv) < 9)
544 return ivb_crc_source_valid(dev_priv, source);
545 else
546 return skl_crc_source_valid(dev_priv, source);
547}
548
549const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
550 size_t *count)
551{
552 *count = ARRAY_SIZE(pipe_crc_sources);
553 return pipe_crc_sources;
554}
555
556int intel_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
557 size_t *values_cnt)
558{
559 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
560 enum intel_pipe_crc_source source;
561
562 if (display_crc_ctl_parse_source(source_name, &source) < 0) {
563 drm_dbg(&dev_priv->drm, "unknown source %s\n", source_name);
564 return -EINVAL;
565 }
566
567 if (source == INTEL_PIPE_CRC_SOURCE_AUTO ||
568 intel_is_valid_crc_source(dev_priv, source) == 0) {
569 *values_cnt = 5;
570 return 0;
571 }
572
573 return -EINVAL;
574}
575
576int intel_crtc_set_crc_source(struct drm_crtc *_crtc, const char *source_name)
577{
578 struct intel_crtc *crtc = to_intel_crtc(_crtc);
579 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
580 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
581 enum intel_display_power_domain power_domain;
582 enum intel_pipe_crc_source source;
583 enum pipe pipe = crtc->pipe;
584 intel_wakeref_t wakeref;
585 u32 val = 0; /* shut up gcc */
586 int ret = 0;
587 bool enable;
588
589 if (display_crc_ctl_parse_source(source_name, &source) < 0) {
590 drm_dbg(&dev_priv->drm, "unknown source %s\n", source_name);
591 return -EINVAL;
592 }
593
594 power_domain = POWER_DOMAIN_PIPE(pipe);
595 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
596 if (!wakeref) {
597 drm_dbg_kms(&dev_priv->drm,
598 "Trying to capture CRC while pipe is off\n");
599 return -EIO;
600 }
601
602 enable = source != INTEL_PIPE_CRC_SOURCE_NONE;
603 if (enable)
604 intel_crtc_crc_setup_workarounds(crtc, true);
605
606 ret = get_new_crc_ctl_reg(dev_priv, pipe, &source, &val);
607 if (ret != 0)
608 goto out;
609
610 pipe_crc->source = source;
611 intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), val);
612 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
613
614 if (!source) {
615 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
616 vlv_undo_pipe_scramble_reset(dev_priv, pipe);
617 }
618
619 pipe_crc->skipped = 0;
620
621out:
622 if (!enable)
623 intel_crtc_crc_setup_workarounds(crtc, false);
624
625 intel_display_power_put(dev_priv, power_domain, wakeref);
626
627 return ret;
628}
629
630void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
631{
632 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
633 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
634 enum pipe pipe = crtc->pipe;
635 u32 val = 0;
636
637 if (!crtc->base.crc.opened)
638 return;
639
640 if (get_new_crc_ctl_reg(dev_priv, pipe, &pipe_crc->source, &val) < 0)
641 return;
642
643 /* Don't need pipe_crc->lock here, IRQs are not generated. */
644 pipe_crc->skipped = 0;
645
646 intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), val);
647 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
648}
649
650void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
651{
652 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
653 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
654 enum pipe pipe = crtc->pipe;
655
656 /* Swallow crc's until we stop generating them. */
657 spin_lock_irq(&pipe_crc->lock);
658 pipe_crc->skipped = INT_MIN;
659 spin_unlock_irq(&pipe_crc->lock);
660
661 intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), 0);
662 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
663 intel_synchronize_irq(dev_priv);
664}