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1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/export.h>
29#include <linux/i2c.h>
30#include <linux/notifier.h>
31#include <linux/slab.h>
32#include <linux/sort.h>
33#include <linux/string_helpers.h>
34#include <linux/timekeeping.h>
35#include <linux/types.h>
36
37#include <asm/byteorder.h>
38
39#include <drm/display/drm_dp_helper.h>
40#include <drm/display/drm_dp_tunnel.h>
41#include <drm/display/drm_dsc_helper.h>
42#include <drm/display/drm_hdmi_helper.h>
43#include <drm/drm_atomic_helper.h>
44#include <drm/drm_crtc.h>
45#include <drm/drm_edid.h>
46#include <drm/drm_fixed.h>
47#include <drm/drm_probe_helper.h>
48
49#include "g4x_dp.h"
50#include "i915_drv.h"
51#include "i915_irq.h"
52#include "i915_reg.h"
53#include "intel_alpm.h"
54#include "intel_atomic.h"
55#include "intel_audio.h"
56#include "intel_backlight.h"
57#include "intel_combo_phy_regs.h"
58#include "intel_connector.h"
59#include "intel_crtc.h"
60#include "intel_cx0_phy.h"
61#include "intel_ddi.h"
62#include "intel_de.h"
63#include "intel_display_driver.h"
64#include "intel_display_types.h"
65#include "intel_dp.h"
66#include "intel_dp_aux.h"
67#include "intel_dp_hdcp.h"
68#include "intel_dp_link_training.h"
69#include "intel_dp_mst.h"
70#include "intel_dp_test.h"
71#include "intel_dp_tunnel.h"
72#include "intel_dpio_phy.h"
73#include "intel_dpll.h"
74#include "intel_drrs.h"
75#include "intel_encoder.h"
76#include "intel_fifo_underrun.h"
77#include "intel_hdcp.h"
78#include "intel_hdmi.h"
79#include "intel_hotplug.h"
80#include "intel_hotplug_irq.h"
81#include "intel_lspcon.h"
82#include "intel_lvds.h"
83#include "intel_modeset_lock.h"
84#include "intel_panel.h"
85#include "intel_pch_display.h"
86#include "intel_pfit.h"
87#include "intel_pps.h"
88#include "intel_psr.h"
89#include "intel_runtime_pm.h"
90#include "intel_quirks.h"
91#include "intel_tc.h"
92#include "intel_vdsc.h"
93#include "intel_vrr.h"
94#include "intel_crtc_state_dump.h"
95
96#define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev)
97
98/* DP DSC throughput values used for slice count calculations KPixels/s */
99#define DP_DSC_PEAK_PIXEL_RATE 2720000
100#define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
101#define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
102
103/* Max DSC line buffer depth supported by HW. */
104#define INTEL_DP_DSC_MAX_LINE_BUF_DEPTH 13
105
106/* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */
107#define DP_DSC_FEC_OVERHEAD_FACTOR 1028530
108
109/* Constants for DP DSC configurations */
110static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
111
112/* With Single pipe configuration, HW is capable of supporting maximum
113 * of 4 slices per line.
114 */
115static const u8 valid_dsc_slicecount[] = {1, 2, 4};
116
117/**
118 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
119 * @intel_dp: DP struct
120 *
121 * If a CPU or PCH DP output is attached to an eDP panel, this function
122 * will return true, and false otherwise.
123 *
124 * This function is not safe to use prior to encoder type being set.
125 */
126bool intel_dp_is_edp(struct intel_dp *intel_dp)
127{
128 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
129
130 return dig_port->base.type == INTEL_OUTPUT_EDP;
131}
132
133static void intel_dp_unset_edid(struct intel_dp *intel_dp);
134
135/* Is link rate UHBR and thus 128b/132b? */
136bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
137{
138 return drm_dp_is_uhbr_rate(crtc_state->port_clock);
139}
140
141/**
142 * intel_dp_link_symbol_size - get the link symbol size for a given link rate
143 * @rate: link rate in 10kbit/s units
144 *
145 * Returns the link symbol size in bits/symbol units depending on the link
146 * rate -> channel coding.
147 */
148int intel_dp_link_symbol_size(int rate)
149{
150 return drm_dp_is_uhbr_rate(rate) ? 32 : 10;
151}
152
153/**
154 * intel_dp_link_symbol_clock - convert link rate to link symbol clock
155 * @rate: link rate in 10kbit/s units
156 *
157 * Returns the link symbol clock frequency in kHz units depending on the
158 * link rate and channel coding.
159 */
160int intel_dp_link_symbol_clock(int rate)
161{
162 return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate));
163}
164
165static int max_dprx_rate(struct intel_dp *intel_dp)
166{
167 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
168 return drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);
169
170 return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
171}
172
173static int max_dprx_lane_count(struct intel_dp *intel_dp)
174{
175 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
176 return drm_dp_tunnel_max_dprx_lane_count(intel_dp->tunnel);
177
178 return drm_dp_max_lane_count(intel_dp->dpcd);
179}
180
181static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
182{
183 intel_dp->sink_rates[0] = 162000;
184 intel_dp->num_sink_rates = 1;
185}
186
187/* update sink rates from dpcd */
188static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
189{
190 static const int dp_rates[] = {
191 162000, 270000, 540000, 810000
192 };
193 int i, max_rate;
194 int max_lttpr_rate;
195
196 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
197 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
198 static const int quirk_rates[] = { 162000, 270000, 324000 };
199
200 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
201 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
202
203 return;
204 }
205
206 /*
207 * Sink rates for 8b/10b.
208 */
209 max_rate = max_dprx_rate(intel_dp);
210 max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
211 if (max_lttpr_rate)
212 max_rate = min(max_rate, max_lttpr_rate);
213
214 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
215 if (dp_rates[i] > max_rate)
216 break;
217 intel_dp->sink_rates[i] = dp_rates[i];
218 }
219
220 /*
221 * Sink rates for 128b/132b. If set, sink should support all 8b/10b
222 * rates and 10 Gbps.
223 */
224 if (drm_dp_128b132b_supported(intel_dp->dpcd)) {
225 u8 uhbr_rates = 0;
226
227 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
228
229 drm_dp_dpcd_readb(&intel_dp->aux,
230 DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
231
232 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
233 /* We have a repeater */
234 if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
235 intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
236 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
237 DP_PHY_REPEATER_128B132B_SUPPORTED) {
238 /* Repeater supports 128b/132b, valid UHBR rates */
239 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
240 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
241 } else {
242 /* Does not support 128b/132b */
243 uhbr_rates = 0;
244 }
245 }
246
247 if (uhbr_rates & DP_UHBR10)
248 intel_dp->sink_rates[i++] = 1000000;
249 if (uhbr_rates & DP_UHBR13_5)
250 intel_dp->sink_rates[i++] = 1350000;
251 if (uhbr_rates & DP_UHBR20)
252 intel_dp->sink_rates[i++] = 2000000;
253 }
254
255 intel_dp->num_sink_rates = i;
256}
257
258static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
259{
260 struct intel_connector *connector = intel_dp->attached_connector;
261 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
262 struct intel_encoder *encoder = &intel_dig_port->base;
263
264 intel_dp_set_dpcd_sink_rates(intel_dp);
265
266 if (intel_dp->num_sink_rates)
267 return;
268
269 drm_err(&dp_to_i915(intel_dp)->drm,
270 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
271 connector->base.base.id, connector->base.name,
272 encoder->base.base.id, encoder->base.name);
273
274 intel_dp_set_default_sink_rates(intel_dp);
275}
276
277static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
278{
279 intel_dp->max_sink_lane_count = 1;
280}
281
282static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
283{
284 struct intel_connector *connector = intel_dp->attached_connector;
285 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
286 struct intel_encoder *encoder = &intel_dig_port->base;
287
288 intel_dp->max_sink_lane_count = max_dprx_lane_count(intel_dp);
289
290 switch (intel_dp->max_sink_lane_count) {
291 case 1:
292 case 2:
293 case 4:
294 return;
295 }
296
297 drm_err(&dp_to_i915(intel_dp)->drm,
298 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
299 connector->base.base.id, connector->base.name,
300 encoder->base.base.id, encoder->base.name,
301 intel_dp->max_sink_lane_count);
302
303 intel_dp_set_default_max_sink_lane_count(intel_dp);
304}
305
306/* Get length of rates array potentially limited by max_rate. */
307static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
308{
309 int i;
310
311 /* Limit results by potentially reduced max rate */
312 for (i = 0; i < len; i++) {
313 if (rates[len - i - 1] <= max_rate)
314 return len - i;
315 }
316
317 return 0;
318}
319
320/* Get length of common rates array potentially limited by max_rate. */
321static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
322 int max_rate)
323{
324 return intel_dp_rate_limit_len(intel_dp->common_rates,
325 intel_dp->num_common_rates, max_rate);
326}
327
328int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
329{
330 if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
331 index < 0 || index >= intel_dp->num_common_rates))
332 return 162000;
333
334 return intel_dp->common_rates[index];
335}
336
337/* Theoretical max between source and sink */
338int intel_dp_max_common_rate(struct intel_dp *intel_dp)
339{
340 return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
341}
342
343int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
344{
345 int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata);
346 int max_lanes = dig_port->max_lanes;
347
348 if (vbt_max_lanes)
349 max_lanes = min(max_lanes, vbt_max_lanes);
350
351 return max_lanes;
352}
353
354/* Theoretical max between source and sink */
355int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
356{
357 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
358 int source_max = intel_dp_max_source_lane_count(dig_port);
359 int sink_max = intel_dp->max_sink_lane_count;
360 int lane_max = intel_tc_port_max_lane_count(dig_port);
361 int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
362
363 if (lttpr_max)
364 sink_max = min(sink_max, lttpr_max);
365
366 return min3(source_max, sink_max, lane_max);
367}
368
369static int forced_lane_count(struct intel_dp *intel_dp)
370{
371 return clamp(intel_dp->link.force_lane_count, 1, intel_dp_max_common_lane_count(intel_dp));
372}
373
374int intel_dp_max_lane_count(struct intel_dp *intel_dp)
375{
376 int lane_count;
377
378 if (intel_dp->link.force_lane_count)
379 lane_count = forced_lane_count(intel_dp);
380 else
381 lane_count = intel_dp->link.max_lane_count;
382
383 switch (lane_count) {
384 case 1:
385 case 2:
386 case 4:
387 return lane_count;
388 default:
389 MISSING_CASE(lane_count);
390 return 1;
391 }
392}
393
394static int intel_dp_min_lane_count(struct intel_dp *intel_dp)
395{
396 if (intel_dp->link.force_lane_count)
397 return forced_lane_count(intel_dp);
398
399 return 1;
400}
401
402/*
403 * The required data bandwidth for a mode with given pixel clock and bpp. This
404 * is the required net bandwidth independent of the data bandwidth efficiency.
405 *
406 * TODO: check if callers of this functions should use
407 * intel_dp_effective_data_rate() instead.
408 */
409int
410intel_dp_link_required(int pixel_clock, int bpp)
411{
412 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
413 return DIV_ROUND_UP(pixel_clock * bpp, 8);
414}
415
416/**
417 * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead
418 * @pixel_clock: pixel clock in kHz
419 * @bpp_x16: bits per pixel .4 fixed point format
420 * @bw_overhead: BW allocation overhead in 1ppm units
421 *
422 * Return the effective pixel data rate in kB/sec units taking into account
423 * the provided SSC, FEC, DSC BW allocation overhead.
424 */
425int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,
426 int bw_overhead)
427{
428 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead),
429 1000000 * 16 * 8);
430}
431
432/**
433 * intel_dp_max_link_data_rate: Calculate the maximum rate for the given link params
434 * @intel_dp: Intel DP object
435 * @max_dprx_rate: Maximum data rate of the DPRX
436 * @max_dprx_lanes: Maximum lane count of the DPRX
437 *
438 * Calculate the maximum data rate for the provided link parameters taking into
439 * account any BW limitations by a DP tunnel attached to @intel_dp.
440 *
441 * Returns the maximum data rate in kBps units.
442 */
443int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,
444 int max_dprx_rate, int max_dprx_lanes)
445{
446 int max_rate = drm_dp_max_dprx_data_rate(max_dprx_rate, max_dprx_lanes);
447
448 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
449 max_rate = min(max_rate,
450 drm_dp_tunnel_available_bw(intel_dp->tunnel));
451
452 return max_rate;
453}
454
455bool intel_dp_has_joiner(struct intel_dp *intel_dp)
456{
457 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
458 struct intel_encoder *encoder = &intel_dig_port->base;
459 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
460
461 /* eDP MSO is not compatible with joiner */
462 if (intel_dp->mso_link_count)
463 return false;
464
465 return DISPLAY_VER(dev_priv) >= 12 ||
466 (DISPLAY_VER(dev_priv) == 11 &&
467 encoder->port != PORT_A);
468}
469
470static int dg2_max_source_rate(struct intel_dp *intel_dp)
471{
472 return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
473}
474
475static int icl_max_source_rate(struct intel_dp *intel_dp)
476{
477 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
478
479 if (intel_encoder_is_combo(encoder) && !intel_dp_is_edp(intel_dp))
480 return 540000;
481
482 return 810000;
483}
484
485static int ehl_max_source_rate(struct intel_dp *intel_dp)
486{
487 if (intel_dp_is_edp(intel_dp))
488 return 540000;
489
490 return 810000;
491}
492
493static int mtl_max_source_rate(struct intel_dp *intel_dp)
494{
495 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
496
497 if (intel_encoder_is_c10phy(encoder))
498 return 810000;
499
500 if (DISPLAY_VERx100(to_i915(encoder->base.dev)) == 1401)
501 return 1350000;
502
503 return 2000000;
504}
505
506static int vbt_max_link_rate(struct intel_dp *intel_dp)
507{
508 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
509 int max_rate;
510
511 max_rate = intel_bios_dp_max_link_rate(encoder->devdata);
512
513 if (intel_dp_is_edp(intel_dp)) {
514 struct intel_connector *connector = intel_dp->attached_connector;
515 int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
516
517 if (max_rate && edp_max_rate)
518 max_rate = min(max_rate, edp_max_rate);
519 else if (edp_max_rate)
520 max_rate = edp_max_rate;
521 }
522
523 return max_rate;
524}
525
526static void
527intel_dp_set_source_rates(struct intel_dp *intel_dp)
528{
529 /* The values must be in increasing order */
530 static const int bmg_rates[] = {
531 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
532 810000, 1000000, 1350000,
533 };
534 static const int mtl_rates[] = {
535 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
536 810000, 1000000, 2000000,
537 };
538 static const int icl_rates[] = {
539 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
540 1000000, 1350000,
541 };
542 static const int bxt_rates[] = {
543 162000, 216000, 243000, 270000, 324000, 432000, 540000
544 };
545 static const int skl_rates[] = {
546 162000, 216000, 270000, 324000, 432000, 540000
547 };
548 static const int hsw_rates[] = {
549 162000, 270000, 540000
550 };
551 static const int g4x_rates[] = {
552 162000, 270000
553 };
554 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
555 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
556 const int *source_rates;
557 int size, max_rate = 0, vbt_max_rate;
558
559 /* This should only be done once */
560 drm_WARN_ON(&dev_priv->drm,
561 intel_dp->source_rates || intel_dp->num_source_rates);
562
563 if (DISPLAY_VER(dev_priv) >= 14) {
564 if (IS_BATTLEMAGE(dev_priv)) {
565 source_rates = bmg_rates;
566 size = ARRAY_SIZE(bmg_rates);
567 } else {
568 source_rates = mtl_rates;
569 size = ARRAY_SIZE(mtl_rates);
570 }
571 max_rate = mtl_max_source_rate(intel_dp);
572 } else if (DISPLAY_VER(dev_priv) >= 11) {
573 source_rates = icl_rates;
574 size = ARRAY_SIZE(icl_rates);
575 if (IS_DG2(dev_priv))
576 max_rate = dg2_max_source_rate(intel_dp);
577 else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
578 IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
579 max_rate = 810000;
580 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
581 max_rate = ehl_max_source_rate(intel_dp);
582 else
583 max_rate = icl_max_source_rate(intel_dp);
584 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
585 source_rates = bxt_rates;
586 size = ARRAY_SIZE(bxt_rates);
587 } else if (DISPLAY_VER(dev_priv) == 9) {
588 source_rates = skl_rates;
589 size = ARRAY_SIZE(skl_rates);
590 } else if ((IS_HASWELL(dev_priv) && !IS_HASWELL_ULX(dev_priv)) ||
591 IS_BROADWELL(dev_priv)) {
592 source_rates = hsw_rates;
593 size = ARRAY_SIZE(hsw_rates);
594 } else {
595 source_rates = g4x_rates;
596 size = ARRAY_SIZE(g4x_rates);
597 }
598
599 vbt_max_rate = vbt_max_link_rate(intel_dp);
600 if (max_rate && vbt_max_rate)
601 max_rate = min(max_rate, vbt_max_rate);
602 else if (vbt_max_rate)
603 max_rate = vbt_max_rate;
604
605 if (max_rate)
606 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
607
608 intel_dp->source_rates = source_rates;
609 intel_dp->num_source_rates = size;
610}
611
612static int intersect_rates(const int *source_rates, int source_len,
613 const int *sink_rates, int sink_len,
614 int *common_rates)
615{
616 int i = 0, j = 0, k = 0;
617
618 while (i < source_len && j < sink_len) {
619 if (source_rates[i] == sink_rates[j]) {
620 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
621 return k;
622 common_rates[k] = source_rates[i];
623 ++k;
624 ++i;
625 ++j;
626 } else if (source_rates[i] < sink_rates[j]) {
627 ++i;
628 } else {
629 ++j;
630 }
631 }
632 return k;
633}
634
635/* return index of rate in rates array, or -1 if not found */
636int intel_dp_rate_index(const int *rates, int len, int rate)
637{
638 int i;
639
640 for (i = 0; i < len; i++)
641 if (rate == rates[i])
642 return i;
643
644 return -1;
645}
646
647static int intel_dp_link_config_rate(struct intel_dp *intel_dp,
648 const struct intel_dp_link_config *lc)
649{
650 return intel_dp_common_rate(intel_dp, lc->link_rate_idx);
651}
652
653static int intel_dp_link_config_lane_count(const struct intel_dp_link_config *lc)
654{
655 return 1 << lc->lane_count_exp;
656}
657
658static int intel_dp_link_config_bw(struct intel_dp *intel_dp,
659 const struct intel_dp_link_config *lc)
660{
661 return drm_dp_max_dprx_data_rate(intel_dp_link_config_rate(intel_dp, lc),
662 intel_dp_link_config_lane_count(lc));
663}
664
665static int link_config_cmp_by_bw(const void *a, const void *b, const void *p)
666{
667 struct intel_dp *intel_dp = (struct intel_dp *)p; /* remove const */
668 const struct intel_dp_link_config *lc_a = a;
669 const struct intel_dp_link_config *lc_b = b;
670 int bw_a = intel_dp_link_config_bw(intel_dp, lc_a);
671 int bw_b = intel_dp_link_config_bw(intel_dp, lc_b);
672
673 if (bw_a != bw_b)
674 return bw_a - bw_b;
675
676 return intel_dp_link_config_rate(intel_dp, lc_a) -
677 intel_dp_link_config_rate(intel_dp, lc_b);
678}
679
680static void intel_dp_link_config_init(struct intel_dp *intel_dp)
681{
682 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
683 struct intel_dp_link_config *lc;
684 int num_common_lane_configs;
685 int i;
686 int j;
687
688 if (drm_WARN_ON(&i915->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp))))
689 return;
690
691 num_common_lane_configs = ilog2(intel_dp_max_common_lane_count(intel_dp)) + 1;
692
693 if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates * num_common_lane_configs >
694 ARRAY_SIZE(intel_dp->link.configs)))
695 return;
696
697 intel_dp->link.num_configs = intel_dp->num_common_rates * num_common_lane_configs;
698
699 lc = &intel_dp->link.configs[0];
700 for (i = 0; i < intel_dp->num_common_rates; i++) {
701 for (j = 0; j < num_common_lane_configs; j++) {
702 lc->lane_count_exp = j;
703 lc->link_rate_idx = i;
704
705 lc++;
706 }
707 }
708
709 sort_r(intel_dp->link.configs, intel_dp->link.num_configs,
710 sizeof(intel_dp->link.configs[0]),
711 link_config_cmp_by_bw, NULL,
712 intel_dp);
713}
714
715void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count)
716{
717 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
718 const struct intel_dp_link_config *lc;
719
720 if (drm_WARN_ON(&i915->drm, idx < 0 || idx >= intel_dp->link.num_configs))
721 idx = 0;
722
723 lc = &intel_dp->link.configs[idx];
724
725 *link_rate = intel_dp_link_config_rate(intel_dp, lc);
726 *lane_count = intel_dp_link_config_lane_count(lc);
727}
728
729int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count)
730{
731 int link_rate_idx = intel_dp_rate_index(intel_dp->common_rates, intel_dp->num_common_rates,
732 link_rate);
733 int lane_count_exp = ilog2(lane_count);
734 int i;
735
736 for (i = 0; i < intel_dp->link.num_configs; i++) {
737 const struct intel_dp_link_config *lc = &intel_dp->link.configs[i];
738
739 if (lc->lane_count_exp == lane_count_exp &&
740 lc->link_rate_idx == link_rate_idx)
741 return i;
742 }
743
744 return -1;
745}
746
747static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
748{
749 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
750
751 drm_WARN_ON(&i915->drm,
752 !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
753
754 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
755 intel_dp->num_source_rates,
756 intel_dp->sink_rates,
757 intel_dp->num_sink_rates,
758 intel_dp->common_rates);
759
760 /* Paranoia, there should always be something in common. */
761 if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
762 intel_dp->common_rates[0] = 162000;
763 intel_dp->num_common_rates = 1;
764 }
765
766 intel_dp_link_config_init(intel_dp);
767}
768
769bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
770 u8 lane_count)
771{
772 /*
773 * FIXME: we need to synchronize the current link parameters with
774 * hardware readout. Currently fast link training doesn't work on
775 * boot-up.
776 */
777 if (link_rate == 0 ||
778 link_rate > intel_dp->link.max_rate)
779 return false;
780
781 if (lane_count == 0 ||
782 lane_count > intel_dp_max_lane_count(intel_dp))
783 return false;
784
785 return true;
786}
787
788u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
789{
790 return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR),
791 1000000U);
792}
793
794int intel_dp_bw_fec_overhead(bool fec_enabled)
795{
796 /*
797 * TODO: Calculate the actual overhead for a given mode.
798 * The hard-coded 1/0.972261=2.853% overhead factor
799 * corresponds (for instance) to the 8b/10b DP FEC 2.4% +
800 * 0.453% DSC overhead. This is enough for a 3840 width mode,
801 * which has a DSC overhead of up to ~0.2%, but may not be
802 * enough for a 1024 width mode where this is ~0.8% (on a 4
803 * lane DP link, with 2 DSC slices and 8 bpp color depth).
804 */
805 return fec_enabled ? DP_DSC_FEC_OVERHEAD_FACTOR : 1000000;
806}
807
808static int
809small_joiner_ram_size_bits(struct drm_i915_private *i915)
810{
811 if (DISPLAY_VER(i915) >= 13)
812 return 17280 * 8;
813 else if (DISPLAY_VER(i915) >= 11)
814 return 7680 * 8;
815 else
816 return 6144 * 8;
817}
818
819u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp)
820{
821 u32 bits_per_pixel = bpp;
822 int i;
823
824 /* Error out if the max bpp is less than smallest allowed valid bpp */
825 if (bits_per_pixel < valid_dsc_bpp[0]) {
826 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
827 bits_per_pixel, valid_dsc_bpp[0]);
828 return 0;
829 }
830
831 /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
832 if (DISPLAY_VER(i915) >= 13) {
833 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
834
835 /*
836 * According to BSpec, 27 is the max DSC output bpp,
837 * 8 is the min DSC output bpp.
838 * While we can still clamp higher bpp values to 27, saving bandwidth,
839 * if it is required to oompress up to bpp < 8, means we can't do
840 * that and probably means we can't fit the required mode, even with
841 * DSC enabled.
842 */
843 if (bits_per_pixel < 8) {
844 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min 8\n",
845 bits_per_pixel);
846 return 0;
847 }
848 bits_per_pixel = min_t(u32, bits_per_pixel, 27);
849 } else {
850 /* Find the nearest match in the array of known BPPs from VESA */
851 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
852 if (bits_per_pixel < valid_dsc_bpp[i + 1])
853 break;
854 }
855 drm_dbg_kms(&i915->drm, "Set dsc bpp from %d to VESA %d\n",
856 bits_per_pixel, valid_dsc_bpp[i]);
857
858 bits_per_pixel = valid_dsc_bpp[i];
859 }
860
861 return bits_per_pixel;
862}
863
864static int bigjoiner_interface_bits(struct intel_display *display)
865{
866 return DISPLAY_VER(display) >= 14 ? 36 : 24;
867}
868
869static u32 bigjoiner_bw_max_bpp(struct intel_display *display, u32 mode_clock,
870 int num_joined_pipes)
871{
872 u32 max_bpp;
873 /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */
874 int ppc = 2;
875 int num_big_joiners = num_joined_pipes / 2;
876
877 max_bpp = display->cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits(display) /
878 intel_dp_mode_to_fec_clock(mode_clock);
879
880 max_bpp *= num_big_joiners;
881
882 return max_bpp;
883
884}
885
886static u32 small_joiner_ram_max_bpp(struct intel_display *display,
887 u32 mode_hdisplay,
888 int num_joined_pipes)
889{
890 struct drm_i915_private *i915 = to_i915(display->drm);
891 u32 max_bpp;
892
893 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
894 max_bpp = small_joiner_ram_size_bits(i915) / mode_hdisplay;
895
896 max_bpp *= num_joined_pipes;
897
898 return max_bpp;
899}
900
901static int ultrajoiner_ram_bits(void)
902{
903 return 4 * 72 * 512;
904}
905
906static u32 ultrajoiner_ram_max_bpp(u32 mode_hdisplay)
907{
908 return ultrajoiner_ram_bits() / mode_hdisplay;
909}
910
911static
912u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915,
913 u32 mode_clock, u32 mode_hdisplay,
914 int num_joined_pipes)
915{
916 struct intel_display *display = to_intel_display(&i915->drm);
917 u32 max_bpp = small_joiner_ram_max_bpp(display, mode_hdisplay, num_joined_pipes);
918
919 if (num_joined_pipes > 1)
920 max_bpp = min(max_bpp, bigjoiner_bw_max_bpp(display, mode_clock,
921 num_joined_pipes));
922 if (num_joined_pipes == 4)
923 max_bpp = min(max_bpp, ultrajoiner_ram_max_bpp(mode_hdisplay));
924
925 return max_bpp;
926}
927
928u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
929 u32 link_clock, u32 lane_count,
930 u32 mode_clock, u32 mode_hdisplay,
931 int num_joined_pipes,
932 enum intel_output_format output_format,
933 u32 pipe_bpp,
934 u32 timeslots)
935{
936 u32 bits_per_pixel, joiner_max_bpp;
937
938 /*
939 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
940 * (LinkSymbolClock)* 8 * (TimeSlots / 64)
941 * for SST -> TimeSlots is 64(i.e all TimeSlots that are available)
942 * for MST -> TimeSlots has to be calculated, based on mode requirements
943 *
944 * Due to FEC overhead, the available bw is reduced to 97.2261%.
945 * To support the given mode:
946 * Bandwidth required should be <= Available link Bandwidth * FEC Overhead
947 * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead
948 * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock
949 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) /
950 * (ModeClock / FEC Overhead)
951 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) /
952 * (ModeClock / FEC Overhead * 8)
953 */
954 bits_per_pixel = ((link_clock * lane_count) * timeslots) /
955 (intel_dp_mode_to_fec_clock(mode_clock) * 8);
956
957 /* Bandwidth required for 420 is half, that of 444 format */
958 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
959 bits_per_pixel *= 2;
960
961 /*
962 * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
963 * supported PPS value can be 63.9375 and with the further
964 * mention that for 420, 422 formats, bpp should be programmed double
965 * the target bpp restricting our target bpp to be 31.9375 at max.
966 */
967 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
968 bits_per_pixel = min_t(u32, bits_per_pixel, 31);
969
970 drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
971 "total bw %u pixel clock %u\n",
972 bits_per_pixel, timeslots,
973 (link_clock * lane_count * 8),
974 intel_dp_mode_to_fec_clock(mode_clock));
975
976 joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock,
977 mode_hdisplay, num_joined_pipes);
978 bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
979
980 bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
981
982 return bits_per_pixel;
983}
984
985u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
986 int mode_clock, int mode_hdisplay,
987 int num_joined_pipes)
988{
989 struct drm_i915_private *i915 = to_i915(connector->base.dev);
990 u8 min_slice_count, i;
991 int max_slice_width;
992
993 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
994 min_slice_count = DIV_ROUND_UP(mode_clock,
995 DP_DSC_MAX_ENC_THROUGHPUT_0);
996 else
997 min_slice_count = DIV_ROUND_UP(mode_clock,
998 DP_DSC_MAX_ENC_THROUGHPUT_1);
999
1000 /*
1001 * Due to some DSC engine BW limitations, we need to enable second
1002 * slice and VDSC engine, whenever we approach close enough to max CDCLK
1003 */
1004 if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100))
1005 min_slice_count = max_t(u8, min_slice_count, 2);
1006
1007 max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd);
1008 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
1009 drm_dbg_kms(&i915->drm,
1010 "Unsupported slice width %d by DP DSC Sink device\n",
1011 max_slice_width);
1012 return 0;
1013 }
1014 /* Also take into account max slice width */
1015 min_slice_count = max_t(u8, min_slice_count,
1016 DIV_ROUND_UP(mode_hdisplay,
1017 max_slice_width));
1018
1019 /* Find the closest match to the valid slice count values */
1020 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
1021 u8 test_slice_count = valid_dsc_slicecount[i] * num_joined_pipes;
1022
1023 if (test_slice_count >
1024 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false))
1025 break;
1026
1027 /*
1028 * Bigjoiner needs small joiner to be enabled.
1029 * So there should be at least 2 dsc slices per pipe,
1030 * whenever bigjoiner is enabled.
1031 */
1032 if (num_joined_pipes > 1 && valid_dsc_slicecount[i] < 2)
1033 continue;
1034
1035 if (min_slice_count <= test_slice_count)
1036 return test_slice_count;
1037 }
1038
1039 drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
1040 min_slice_count);
1041 return 0;
1042}
1043
1044static bool source_can_output(struct intel_dp *intel_dp,
1045 enum intel_output_format format)
1046{
1047 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1048
1049 switch (format) {
1050 case INTEL_OUTPUT_FORMAT_RGB:
1051 return true;
1052
1053 case INTEL_OUTPUT_FORMAT_YCBCR444:
1054 /*
1055 * No YCbCr output support on gmch platforms.
1056 * Also, ILK doesn't seem capable of DP YCbCr output.
1057 * The displayed image is severly corrupted. SNB+ is fine.
1058 */
1059 return !HAS_GMCH(i915) && !IS_IRONLAKE(i915);
1060
1061 case INTEL_OUTPUT_FORMAT_YCBCR420:
1062 /* Platform < Gen 11 cannot output YCbCr420 format */
1063 return DISPLAY_VER(i915) >= 11;
1064
1065 default:
1066 MISSING_CASE(format);
1067 return false;
1068 }
1069}
1070
1071static bool
1072dfp_can_convert_from_rgb(struct intel_dp *intel_dp,
1073 enum intel_output_format sink_format)
1074{
1075 if (!drm_dp_is_branch(intel_dp->dpcd))
1076 return false;
1077
1078 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1079 return intel_dp->dfp.rgb_to_ycbcr;
1080
1081 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1082 return intel_dp->dfp.rgb_to_ycbcr &&
1083 intel_dp->dfp.ycbcr_444_to_420;
1084
1085 return false;
1086}
1087
1088static bool
1089dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
1090 enum intel_output_format sink_format)
1091{
1092 if (!drm_dp_is_branch(intel_dp->dpcd))
1093 return false;
1094
1095 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1096 return intel_dp->dfp.ycbcr_444_to_420;
1097
1098 return false;
1099}
1100
1101static bool
1102dfp_can_convert(struct intel_dp *intel_dp,
1103 enum intel_output_format output_format,
1104 enum intel_output_format sink_format)
1105{
1106 switch (output_format) {
1107 case INTEL_OUTPUT_FORMAT_RGB:
1108 return dfp_can_convert_from_rgb(intel_dp, sink_format);
1109 case INTEL_OUTPUT_FORMAT_YCBCR444:
1110 return dfp_can_convert_from_ycbcr444(intel_dp, sink_format);
1111 default:
1112 MISSING_CASE(output_format);
1113 return false;
1114 }
1115
1116 return false;
1117}
1118
1119static enum intel_output_format
1120intel_dp_output_format(struct intel_connector *connector,
1121 enum intel_output_format sink_format)
1122{
1123 struct intel_dp *intel_dp = intel_attached_dp(connector);
1124 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1125 enum intel_output_format force_dsc_output_format =
1126 intel_dp->force_dsc_output_format;
1127 enum intel_output_format output_format;
1128 if (force_dsc_output_format) {
1129 if (source_can_output(intel_dp, force_dsc_output_format) &&
1130 (!drm_dp_is_branch(intel_dp->dpcd) ||
1131 sink_format != force_dsc_output_format ||
1132 dfp_can_convert(intel_dp, force_dsc_output_format, sink_format)))
1133 return force_dsc_output_format;
1134
1135 drm_dbg_kms(&i915->drm, "Cannot force DSC output format\n");
1136 }
1137
1138 if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||
1139 dfp_can_convert_from_rgb(intel_dp, sink_format))
1140 output_format = INTEL_OUTPUT_FORMAT_RGB;
1141
1142 else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
1143 dfp_can_convert_from_ycbcr444(intel_dp, sink_format))
1144 output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
1145
1146 else
1147 output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1148
1149 drm_WARN_ON(&i915->drm, !source_can_output(intel_dp, output_format));
1150
1151 return output_format;
1152}
1153
1154int intel_dp_min_bpp(enum intel_output_format output_format)
1155{
1156 if (output_format == INTEL_OUTPUT_FORMAT_RGB)
1157 return 6 * 3;
1158 else
1159 return 8 * 3;
1160}
1161
1162int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
1163{
1164 /*
1165 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
1166 * format of the number of bytes per pixel will be half the number
1167 * of bytes of RGB pixel.
1168 */
1169 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1170 bpp /= 2;
1171
1172 return bpp;
1173}
1174
1175static enum intel_output_format
1176intel_dp_sink_format(struct intel_connector *connector,
1177 const struct drm_display_mode *mode)
1178{
1179 const struct drm_display_info *info = &connector->base.display_info;
1180
1181 if (drm_mode_is_420_only(info, mode))
1182 return INTEL_OUTPUT_FORMAT_YCBCR420;
1183
1184 return INTEL_OUTPUT_FORMAT_RGB;
1185}
1186
1187static int
1188intel_dp_mode_min_output_bpp(struct intel_connector *connector,
1189 const struct drm_display_mode *mode)
1190{
1191 enum intel_output_format output_format, sink_format;
1192
1193 sink_format = intel_dp_sink_format(connector, mode);
1194
1195 output_format = intel_dp_output_format(connector, sink_format);
1196
1197 return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
1198}
1199
1200static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
1201 int hdisplay)
1202{
1203 /*
1204 * Older platforms don't like hdisplay==4096 with DP.
1205 *
1206 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
1207 * and frame counter increment), but we don't get vblank interrupts,
1208 * and the pipe underruns immediately. The link also doesn't seem
1209 * to get trained properly.
1210 *
1211 * On CHV the vblank interrupts don't seem to disappear but
1212 * otherwise the symptoms are similar.
1213 *
1214 * TODO: confirm the behaviour on HSW+
1215 */
1216 return hdisplay == 4096 && !HAS_DDI(dev_priv);
1217}
1218
1219static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
1220{
1221 struct intel_connector *connector = intel_dp->attached_connector;
1222 const struct drm_display_info *info = &connector->base.display_info;
1223 int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
1224
1225 /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
1226 if (max_tmds_clock && info->max_tmds_clock)
1227 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1228
1229 return max_tmds_clock;
1230}
1231
1232static enum drm_mode_status
1233intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
1234 int clock, int bpc,
1235 enum intel_output_format sink_format,
1236 bool respect_downstream_limits)
1237{
1238 int tmds_clock, min_tmds_clock, max_tmds_clock;
1239
1240 if (!respect_downstream_limits)
1241 return MODE_OK;
1242
1243 tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
1244
1245 min_tmds_clock = intel_dp->dfp.min_tmds_clock;
1246 max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
1247
1248 if (min_tmds_clock && tmds_clock < min_tmds_clock)
1249 return MODE_CLOCK_LOW;
1250
1251 if (max_tmds_clock && tmds_clock > max_tmds_clock)
1252 return MODE_CLOCK_HIGH;
1253
1254 return MODE_OK;
1255}
1256
1257static enum drm_mode_status
1258intel_dp_mode_valid_downstream(struct intel_connector *connector,
1259 const struct drm_display_mode *mode,
1260 int target_clock)
1261{
1262 struct intel_dp *intel_dp = intel_attached_dp(connector);
1263 const struct drm_display_info *info = &connector->base.display_info;
1264 enum drm_mode_status status;
1265 enum intel_output_format sink_format;
1266
1267 /* If PCON supports FRL MODE, check FRL bandwidth constraints */
1268 if (intel_dp->dfp.pcon_max_frl_bw) {
1269 int target_bw;
1270 int max_frl_bw;
1271 int bpp = intel_dp_mode_min_output_bpp(connector, mode);
1272
1273 target_bw = bpp * target_clock;
1274
1275 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
1276
1277 /* converting bw from Gbps to Kbps*/
1278 max_frl_bw = max_frl_bw * 1000000;
1279
1280 if (target_bw > max_frl_bw)
1281 return MODE_CLOCK_HIGH;
1282
1283 return MODE_OK;
1284 }
1285
1286 if (intel_dp->dfp.max_dotclock &&
1287 target_clock > intel_dp->dfp.max_dotclock)
1288 return MODE_CLOCK_HIGH;
1289
1290 sink_format = intel_dp_sink_format(connector, mode);
1291
1292 /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
1293 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1294 8, sink_format, true);
1295
1296 if (status != MODE_OK) {
1297 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1298 !connector->base.ycbcr_420_allowed ||
1299 !drm_mode_is_420_also(info, mode))
1300 return status;
1301 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1302 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1303 8, sink_format, true);
1304 if (status != MODE_OK)
1305 return status;
1306 }
1307
1308 return MODE_OK;
1309}
1310
1311static
1312bool intel_dp_needs_joiner(struct intel_dp *intel_dp,
1313 struct intel_connector *connector,
1314 int hdisplay, int clock,
1315 int num_joined_pipes)
1316{
1317 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1318 int hdisplay_limit;
1319
1320 if (!intel_dp_has_joiner(intel_dp))
1321 return false;
1322
1323 num_joined_pipes /= 2;
1324
1325 hdisplay_limit = DISPLAY_VER(i915) >= 30 ? 6144 : 5120;
1326
1327 return clock > num_joined_pipes * i915->display.cdclk.max_dotclk_freq ||
1328 hdisplay > num_joined_pipes * hdisplay_limit;
1329}
1330
1331int intel_dp_num_joined_pipes(struct intel_dp *intel_dp,
1332 struct intel_connector *connector,
1333 int hdisplay, int clock)
1334{
1335 struct intel_display *display = to_intel_display(intel_dp);
1336 struct drm_i915_private *i915 = to_i915(display->drm);
1337
1338 if (connector->force_joined_pipes)
1339 return connector->force_joined_pipes;
1340
1341 if (HAS_ULTRAJOINER(i915) &&
1342 intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 4))
1343 return 4;
1344
1345 if ((HAS_BIGJOINER(i915) || HAS_UNCOMPRESSED_JOINER(i915)) &&
1346 intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 2))
1347 return 2;
1348
1349 return 1;
1350}
1351
1352bool intel_dp_has_dsc(const struct intel_connector *connector)
1353{
1354 struct drm_i915_private *i915 = to_i915(connector->base.dev);
1355
1356 if (!HAS_DSC(i915))
1357 return false;
1358
1359 if (connector->mst_port && !HAS_DSC_MST(i915))
1360 return false;
1361
1362 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&
1363 connector->panel.vbt.edp.dsc_disable)
1364 return false;
1365
1366 if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd))
1367 return false;
1368
1369 return true;
1370}
1371
1372static enum drm_mode_status
1373intel_dp_mode_valid(struct drm_connector *_connector,
1374 struct drm_display_mode *mode)
1375{
1376 struct intel_connector *connector = to_intel_connector(_connector);
1377 struct intel_dp *intel_dp = intel_attached_dp(connector);
1378 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1379 const struct drm_display_mode *fixed_mode;
1380 int target_clock = mode->clock;
1381 int max_rate, mode_rate, max_lanes, max_link_clock;
1382 int max_dotclk = dev_priv->display.cdclk.max_dotclk_freq;
1383 u16 dsc_max_compressed_bpp = 0;
1384 u8 dsc_slice_count = 0;
1385 enum drm_mode_status status;
1386 bool dsc = false;
1387 int num_joined_pipes;
1388
1389 status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
1390 if (status != MODE_OK)
1391 return status;
1392
1393 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1394 return MODE_H_ILLEGAL;
1395
1396 if (mode->clock < 10000)
1397 return MODE_CLOCK_LOW;
1398
1399 fixed_mode = intel_panel_fixed_mode(connector, mode);
1400 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
1401 status = intel_panel_mode_valid(connector, mode);
1402 if (status != MODE_OK)
1403 return status;
1404
1405 target_clock = fixed_mode->clock;
1406 }
1407
1408 num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
1409 mode->hdisplay, target_clock);
1410 max_dotclk *= num_joined_pipes;
1411
1412 if (target_clock > max_dotclk)
1413 return MODE_CLOCK_HIGH;
1414
1415 if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
1416 return MODE_H_ILLEGAL;
1417
1418 max_link_clock = intel_dp_max_link_rate(intel_dp);
1419 max_lanes = intel_dp_max_lane_count(intel_dp);
1420
1421 max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes);
1422
1423 mode_rate = intel_dp_link_required(target_clock,
1424 intel_dp_mode_min_output_bpp(connector, mode));
1425
1426 if (intel_dp_has_dsc(connector)) {
1427 enum intel_output_format sink_format, output_format;
1428 int pipe_bpp;
1429
1430 sink_format = intel_dp_sink_format(connector, mode);
1431 output_format = intel_dp_output_format(connector, sink_format);
1432 /*
1433 * TBD pass the connector BPC,
1434 * for now U8_MAX so that max BPC on that platform would be picked
1435 */
1436 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
1437
1438 /*
1439 * Output bpp is stored in 6.4 format so right shift by 4 to get the
1440 * integer value since we support only integer values of bpp.
1441 */
1442 if (intel_dp_is_edp(intel_dp)) {
1443 dsc_max_compressed_bpp =
1444 drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
1445 dsc_slice_count =
1446 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
1447 true);
1448 } else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
1449 dsc_max_compressed_bpp =
1450 intel_dp_dsc_get_max_compressed_bpp(dev_priv,
1451 max_link_clock,
1452 max_lanes,
1453 target_clock,
1454 mode->hdisplay,
1455 num_joined_pipes,
1456 output_format,
1457 pipe_bpp, 64);
1458 dsc_slice_count =
1459 intel_dp_dsc_get_slice_count(connector,
1460 target_clock,
1461 mode->hdisplay,
1462 num_joined_pipes);
1463 }
1464
1465 dsc = dsc_max_compressed_bpp && dsc_slice_count;
1466 }
1467
1468 if (intel_dp_joiner_needs_dsc(dev_priv, num_joined_pipes) && !dsc)
1469 return MODE_CLOCK_HIGH;
1470
1471 if (mode_rate > max_rate && !dsc)
1472 return MODE_CLOCK_HIGH;
1473
1474 status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1475 if (status != MODE_OK)
1476 return status;
1477
1478 return intel_mode_valid_max_plane_size(dev_priv, mode, num_joined_pipes);
1479}
1480
1481bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
1482{
1483 return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
1484}
1485
1486bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
1487{
1488 return DISPLAY_VER(i915) >= 10;
1489}
1490
1491static void snprintf_int_array(char *str, size_t len,
1492 const int *array, int nelem)
1493{
1494 int i;
1495
1496 str[0] = '\0';
1497
1498 for (i = 0; i < nelem; i++) {
1499 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1500 if (r >= len)
1501 return;
1502 str += r;
1503 len -= r;
1504 }
1505}
1506
1507static void intel_dp_print_rates(struct intel_dp *intel_dp)
1508{
1509 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1510 char str[128]; /* FIXME: too big for stack? */
1511
1512 if (!drm_debug_enabled(DRM_UT_KMS))
1513 return;
1514
1515 snprintf_int_array(str, sizeof(str),
1516 intel_dp->source_rates, intel_dp->num_source_rates);
1517 drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1518
1519 snprintf_int_array(str, sizeof(str),
1520 intel_dp->sink_rates, intel_dp->num_sink_rates);
1521 drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1522
1523 snprintf_int_array(str, sizeof(str),
1524 intel_dp->common_rates, intel_dp->num_common_rates);
1525 drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1526}
1527
1528static int forced_link_rate(struct intel_dp *intel_dp)
1529{
1530 int len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.force_rate);
1531
1532 if (len == 0)
1533 return intel_dp_common_rate(intel_dp, 0);
1534
1535 return intel_dp_common_rate(intel_dp, len - 1);
1536}
1537
1538int
1539intel_dp_max_link_rate(struct intel_dp *intel_dp)
1540{
1541 int len;
1542
1543 if (intel_dp->link.force_rate)
1544 return forced_link_rate(intel_dp);
1545
1546 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.max_rate);
1547
1548 return intel_dp_common_rate(intel_dp, len - 1);
1549}
1550
1551static int
1552intel_dp_min_link_rate(struct intel_dp *intel_dp)
1553{
1554 if (intel_dp->link.force_rate)
1555 return forced_link_rate(intel_dp);
1556
1557 return intel_dp_common_rate(intel_dp, 0);
1558}
1559
1560int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1561{
1562 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1563 int i = intel_dp_rate_index(intel_dp->sink_rates,
1564 intel_dp->num_sink_rates, rate);
1565
1566 if (drm_WARN_ON(&i915->drm, i < 0))
1567 i = 0;
1568
1569 return i;
1570}
1571
1572void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1573 u8 *link_bw, u8 *rate_select)
1574{
1575 /* eDP 1.4 rate select method. */
1576 if (intel_dp->use_rate_select) {
1577 *link_bw = 0;
1578 *rate_select =
1579 intel_dp_rate_select(intel_dp, port_clock);
1580 } else {
1581 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1582 *rate_select = 0;
1583 }
1584}
1585
1586bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp)
1587{
1588 struct intel_connector *connector = intel_dp->attached_connector;
1589
1590 return connector->base.display_info.is_hdmi;
1591}
1592
1593static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1594 const struct intel_crtc_state *pipe_config)
1595{
1596 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1597 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1598
1599 if (DISPLAY_VER(dev_priv) >= 12)
1600 return true;
1601
1602 if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A &&
1603 !intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
1604 return true;
1605
1606 return false;
1607}
1608
1609bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1610 const struct intel_connector *connector,
1611 const struct intel_crtc_state *pipe_config)
1612{
1613 return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1614 drm_dp_sink_supports_fec(connector->dp.fec_capability);
1615}
1616
1617bool intel_dp_supports_dsc(const struct intel_connector *connector,
1618 const struct intel_crtc_state *crtc_state)
1619{
1620 if (!intel_dp_has_dsc(connector))
1621 return false;
1622
1623 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
1624 return false;
1625
1626 return intel_dsc_source_support(crtc_state);
1627}
1628
1629static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
1630 const struct intel_crtc_state *crtc_state,
1631 int bpc, bool respect_downstream_limits)
1632{
1633 int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1634
1635 /*
1636 * Current bpc could already be below 8bpc due to
1637 * FDI bandwidth constraints or other limits.
1638 * HDMI minimum is 8bpc however.
1639 */
1640 bpc = max(bpc, 8);
1641
1642 /*
1643 * We will never exceed downstream TMDS clock limits while
1644 * attempting deep color. If the user insists on forcing an
1645 * out of spec mode they will have to be satisfied with 8bpc.
1646 */
1647 if (!respect_downstream_limits)
1648 bpc = 8;
1649
1650 for (; bpc >= 8; bpc -= 2) {
1651 if (intel_hdmi_bpc_possible(crtc_state, bpc,
1652 intel_dp_has_hdmi_sink(intel_dp)) &&
1653 intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,
1654 respect_downstream_limits) == MODE_OK)
1655 return bpc;
1656 }
1657
1658 return -EINVAL;
1659}
1660
1661static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1662 const struct intel_crtc_state *crtc_state,
1663 bool respect_downstream_limits)
1664{
1665 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1666 struct intel_connector *intel_connector = intel_dp->attached_connector;
1667 int bpp, bpc;
1668
1669 bpc = crtc_state->pipe_bpp / 3;
1670
1671 if (intel_dp->dfp.max_bpc)
1672 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1673
1674 if (intel_dp->dfp.min_tmds_clock) {
1675 int max_hdmi_bpc;
1676
1677 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
1678 respect_downstream_limits);
1679 if (max_hdmi_bpc < 0)
1680 return 0;
1681
1682 bpc = min(bpc, max_hdmi_bpc);
1683 }
1684
1685 bpp = bpc * 3;
1686 if (intel_dp_is_edp(intel_dp)) {
1687 /* Get bpp from vbt only for panels that dont have bpp in edid */
1688 if (intel_connector->base.display_info.bpc == 0 &&
1689 intel_connector->panel.vbt.edp.bpp &&
1690 intel_connector->panel.vbt.edp.bpp < bpp) {
1691 drm_dbg_kms(&dev_priv->drm,
1692 "clamping bpp for eDP panel to BIOS-provided %i\n",
1693 intel_connector->panel.vbt.edp.bpp);
1694 bpp = intel_connector->panel.vbt.edp.bpp;
1695 }
1696 }
1697
1698 return bpp;
1699}
1700
1701static bool has_seamless_m_n(struct intel_connector *connector)
1702{
1703 struct drm_i915_private *i915 = to_i915(connector->base.dev);
1704
1705 /*
1706 * Seamless M/N reprogramming only implemented
1707 * for BDW+ double buffered M/N registers so far.
1708 */
1709 return HAS_DOUBLE_BUFFERED_M_N(i915) &&
1710 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1711}
1712
1713static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
1714 const struct drm_connector_state *conn_state)
1715{
1716 struct intel_connector *connector = to_intel_connector(conn_state->connector);
1717 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1718
1719 /* FIXME a bit of a mess wrt clock vs. crtc_clock */
1720 if (has_seamless_m_n(connector))
1721 return intel_panel_highest_mode(connector, adjusted_mode)->clock;
1722 else
1723 return adjusted_mode->crtc_clock;
1724}
1725
1726/* Optimize link config in order: max bpp, min clock, min lanes */
1727static int
1728intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1729 struct intel_crtc_state *pipe_config,
1730 const struct drm_connector_state *conn_state,
1731 const struct link_config_limits *limits)
1732{
1733 int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
1734 int mode_rate, link_rate, link_avail;
1735
1736 for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16);
1737 bpp >= fxp_q4_to_int(limits->link.min_bpp_x16);
1738 bpp -= 2 * 3) {
1739 int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1740
1741 mode_rate = intel_dp_link_required(clock, link_bpp);
1742
1743 for (i = 0; i < intel_dp->num_common_rates; i++) {
1744 link_rate = intel_dp_common_rate(intel_dp, i);
1745 if (link_rate < limits->min_rate ||
1746 link_rate > limits->max_rate)
1747 continue;
1748
1749 for (lane_count = limits->min_lane_count;
1750 lane_count <= limits->max_lane_count;
1751 lane_count <<= 1) {
1752 link_avail = intel_dp_max_link_data_rate(intel_dp,
1753 link_rate,
1754 lane_count);
1755
1756
1757 if (mode_rate <= link_avail) {
1758 pipe_config->lane_count = lane_count;
1759 pipe_config->pipe_bpp = bpp;
1760 pipe_config->port_clock = link_rate;
1761
1762 return 0;
1763 }
1764 }
1765 }
1766 }
1767
1768 return -EINVAL;
1769}
1770
1771static
1772u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
1773{
1774 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1775 if (DISPLAY_VER(i915) >= 12)
1776 return 12;
1777 if (DISPLAY_VER(i915) == 11)
1778 return 10;
1779
1780 return 0;
1781}
1782
1783int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
1784 u8 max_req_bpc)
1785{
1786 struct drm_i915_private *i915 = to_i915(connector->base.dev);
1787 int i, num_bpc;
1788 u8 dsc_bpc[3] = {};
1789 u8 dsc_max_bpc;
1790
1791 dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
1792
1793 if (!dsc_max_bpc)
1794 return dsc_max_bpc;
1795
1796 dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
1797
1798 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,
1799 dsc_bpc);
1800 for (i = 0; i < num_bpc; i++) {
1801 if (dsc_max_bpc >= dsc_bpc[i])
1802 return dsc_bpc[i] * 3;
1803 }
1804
1805 return 0;
1806}
1807
1808static int intel_dp_source_dsc_version_minor(struct drm_i915_private *i915)
1809{
1810 return DISPLAY_VER(i915) >= 14 ? 2 : 1;
1811}
1812
1813static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1814{
1815 return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>
1816 DP_DSC_MINOR_SHIFT;
1817}
1818
1819static int intel_dp_get_slice_height(int vactive)
1820{
1821 int slice_height;
1822
1823 /*
1824 * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108
1825 * lines is an optimal slice height, but any size can be used as long as
1826 * vertical active integer multiple and maximum vertical slice count
1827 * requirements are met.
1828 */
1829 for (slice_height = 108; slice_height <= vactive; slice_height += 2)
1830 if (vactive % slice_height == 0)
1831 return slice_height;
1832
1833 /*
1834 * Highly unlikely we reach here as most of the resolutions will end up
1835 * finding appropriate slice_height in above loop but returning
1836 * slice_height as 2 here as it should work with all resolutions.
1837 */
1838 return 2;
1839}
1840
1841static int intel_dp_dsc_compute_params(const struct intel_connector *connector,
1842 struct intel_crtc_state *crtc_state)
1843{
1844 struct drm_i915_private *i915 = to_i915(connector->base.dev);
1845 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1846 int ret;
1847
1848 /*
1849 * RC_MODEL_SIZE is currently a constant across all configurations.
1850 *
1851 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1852 * DP_DSC_RC_BUF_SIZE for this.
1853 */
1854 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1855 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1856
1857 vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height);
1858
1859 ret = intel_dsc_compute_params(crtc_state);
1860 if (ret)
1861 return ret;
1862
1863 vdsc_cfg->dsc_version_major =
1864 (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1865 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1866 vdsc_cfg->dsc_version_minor =
1867 min(intel_dp_source_dsc_version_minor(i915),
1868 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd));
1869 if (vdsc_cfg->convert_rgb)
1870 vdsc_cfg->convert_rgb =
1871 connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1872 DP_DSC_RGB;
1873
1874 vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH,
1875 drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd));
1876 if (!vdsc_cfg->line_buf_depth) {
1877 drm_dbg_kms(&i915->drm,
1878 "DSC Sink Line Buffer Depth invalid\n");
1879 return -EINVAL;
1880 }
1881
1882 vdsc_cfg->block_pred_enable =
1883 connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1884 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1885
1886 return drm_dsc_compute_rc_parameters(vdsc_cfg);
1887}
1888
1889static bool intel_dp_dsc_supports_format(const struct intel_connector *connector,
1890 enum intel_output_format output_format)
1891{
1892 struct drm_i915_private *i915 = to_i915(connector->base.dev);
1893 u8 sink_dsc_format;
1894
1895 switch (output_format) {
1896 case INTEL_OUTPUT_FORMAT_RGB:
1897 sink_dsc_format = DP_DSC_RGB;
1898 break;
1899 case INTEL_OUTPUT_FORMAT_YCBCR444:
1900 sink_dsc_format = DP_DSC_YCbCr444;
1901 break;
1902 case INTEL_OUTPUT_FORMAT_YCBCR420:
1903 if (min(intel_dp_source_dsc_version_minor(i915),
1904 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2)
1905 return false;
1906 sink_dsc_format = DP_DSC_YCbCr420_Native;
1907 break;
1908 default:
1909 return false;
1910 }
1911
1912 return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format);
1913}
1914
1915static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_clock,
1916 u32 lane_count, u32 mode_clock,
1917 enum intel_output_format output_format,
1918 int timeslots)
1919{
1920 u32 available_bw, required_bw;
1921
1922 available_bw = (link_clock * lane_count * timeslots * 16) / 8;
1923 required_bw = compressed_bppx16 * (intel_dp_mode_to_fec_clock(mode_clock));
1924
1925 return available_bw > required_bw;
1926}
1927
1928static int dsc_compute_link_config(struct intel_dp *intel_dp,
1929 struct intel_crtc_state *pipe_config,
1930 struct link_config_limits *limits,
1931 u16 compressed_bppx16,
1932 int timeslots)
1933{
1934 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1935 int link_rate, lane_count;
1936 int i;
1937
1938 for (i = 0; i < intel_dp->num_common_rates; i++) {
1939 link_rate = intel_dp_common_rate(intel_dp, i);
1940 if (link_rate < limits->min_rate || link_rate > limits->max_rate)
1941 continue;
1942
1943 for (lane_count = limits->min_lane_count;
1944 lane_count <= limits->max_lane_count;
1945 lane_count <<= 1) {
1946 if (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate,
1947 lane_count, adjusted_mode->clock,
1948 pipe_config->output_format,
1949 timeslots))
1950 continue;
1951
1952 pipe_config->lane_count = lane_count;
1953 pipe_config->port_clock = link_rate;
1954
1955 return 0;
1956 }
1957 }
1958
1959 return -EINVAL;
1960}
1961
1962static
1963u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector,
1964 struct intel_crtc_state *pipe_config,
1965 int bpc)
1966{
1967 u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd);
1968
1969 if (max_bppx16)
1970 return max_bppx16;
1971 /*
1972 * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate
1973 * values as given in spec Table 2-157 DP v2.0
1974 */
1975 switch (pipe_config->output_format) {
1976 case INTEL_OUTPUT_FORMAT_RGB:
1977 case INTEL_OUTPUT_FORMAT_YCBCR444:
1978 return (3 * bpc) << 4;
1979 case INTEL_OUTPUT_FORMAT_YCBCR420:
1980 return (3 * (bpc / 2)) << 4;
1981 default:
1982 MISSING_CASE(pipe_config->output_format);
1983 break;
1984 }
1985
1986 return 0;
1987}
1988
1989int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
1990{
1991 /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
1992 switch (pipe_config->output_format) {
1993 case INTEL_OUTPUT_FORMAT_RGB:
1994 case INTEL_OUTPUT_FORMAT_YCBCR444:
1995 return 8;
1996 case INTEL_OUTPUT_FORMAT_YCBCR420:
1997 return 6;
1998 default:
1999 MISSING_CASE(pipe_config->output_format);
2000 break;
2001 }
2002
2003 return 0;
2004}
2005
2006int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
2007 struct intel_crtc_state *pipe_config,
2008 int bpc)
2009{
2010 return intel_dp_dsc_max_sink_compressed_bppx16(connector,
2011 pipe_config, bpc) >> 4;
2012}
2013
2014static int dsc_src_min_compressed_bpp(void)
2015{
2016 /* Min Compressed bpp supported by source is 8 */
2017 return 8;
2018}
2019
2020static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)
2021{
2022 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2023
2024 /*
2025 * Max Compressed bpp for Gen 13+ is 27bpp.
2026 * For earlier platform is 23bpp. (Bspec:49259).
2027 */
2028 if (DISPLAY_VER(i915) < 13)
2029 return 23;
2030 else
2031 return 27;
2032}
2033
2034/*
2035 * From a list of valid compressed bpps try different compressed bpp and find a
2036 * suitable link configuration that can support it.
2037 */
2038static int
2039icl_dsc_compute_link_config(struct intel_dp *intel_dp,
2040 struct intel_crtc_state *pipe_config,
2041 struct link_config_limits *limits,
2042 int dsc_max_bpp,
2043 int dsc_min_bpp,
2044 int pipe_bpp,
2045 int timeslots)
2046{
2047 int i, ret;
2048
2049 /* Compressed BPP should be less than the Input DSC bpp */
2050 dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
2051
2052 for (i = ARRAY_SIZE(valid_dsc_bpp) - 1; i >= 0; i--) {
2053 if (valid_dsc_bpp[i] < dsc_min_bpp ||
2054 valid_dsc_bpp[i] > dsc_max_bpp)
2055 continue;
2056
2057 ret = dsc_compute_link_config(intel_dp,
2058 pipe_config,
2059 limits,
2060 valid_dsc_bpp[i] << 4,
2061 timeslots);
2062 if (ret == 0) {
2063 pipe_config->dsc.compressed_bpp_x16 =
2064 fxp_q4_from_int(valid_dsc_bpp[i]);
2065 return 0;
2066 }
2067 }
2068
2069 return -EINVAL;
2070}
2071
2072/*
2073 * From XE_LPD onwards we supports compression bpps in steps of 1 up to
2074 * uncompressed bpp-1. So we start from max compressed bpp and see if any
2075 * link configuration is able to support that compressed bpp, if not we
2076 * step down and check for lower compressed bpp.
2077 */
2078static int
2079xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
2080 const struct intel_connector *connector,
2081 struct intel_crtc_state *pipe_config,
2082 struct link_config_limits *limits,
2083 int dsc_max_bpp,
2084 int dsc_min_bpp,
2085 int pipe_bpp,
2086 int timeslots)
2087{
2088 u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd);
2089 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2090 u16 compressed_bppx16;
2091 u8 bppx16_step;
2092 int ret;
2093
2094 if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1)
2095 bppx16_step = 16;
2096 else
2097 bppx16_step = 16 / bppx16_incr;
2098
2099 /* Compressed BPP should be less than the Input DSC bpp */
2100 dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step);
2101 dsc_min_bpp = dsc_min_bpp << 4;
2102
2103 for (compressed_bppx16 = dsc_max_bpp;
2104 compressed_bppx16 >= dsc_min_bpp;
2105 compressed_bppx16 -= bppx16_step) {
2106 if (intel_dp->force_dsc_fractional_bpp_en &&
2107 !fxp_q4_to_frac(compressed_bppx16))
2108 continue;
2109 ret = dsc_compute_link_config(intel_dp,
2110 pipe_config,
2111 limits,
2112 compressed_bppx16,
2113 timeslots);
2114 if (ret == 0) {
2115 pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;
2116 if (intel_dp->force_dsc_fractional_bpp_en &&
2117 fxp_q4_to_frac(compressed_bppx16))
2118 drm_dbg_kms(&i915->drm, "Forcing DSC fractional bpp\n");
2119
2120 return 0;
2121 }
2122 }
2123 return -EINVAL;
2124}
2125
2126static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
2127 const struct intel_connector *connector,
2128 struct intel_crtc_state *pipe_config,
2129 struct link_config_limits *limits,
2130 int pipe_bpp,
2131 int timeslots)
2132{
2133 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2134 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2135 int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2136 int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2137 int dsc_joiner_max_bpp;
2138 int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config);
2139
2140 dsc_src_min_bpp = dsc_src_min_compressed_bpp();
2141 dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
2142 dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2143 dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits->link.min_bpp_x16));
2144
2145 dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2146 dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2147 pipe_config,
2148 pipe_bpp / 3);
2149 dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2150
2151 dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
2152 adjusted_mode->hdisplay,
2153 num_joined_pipes);
2154 dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp);
2155 dsc_max_bpp = min(dsc_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16));
2156
2157 if (DISPLAY_VER(i915) >= 13)
2158 return xelpd_dsc_compute_link_config(intel_dp, connector, pipe_config, limits,
2159 dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
2160 return icl_dsc_compute_link_config(intel_dp, pipe_config, limits,
2161 dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
2162}
2163
2164static
2165u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
2166{
2167 /* Min DSC Input BPC for ICL+ is 8 */
2168 return HAS_DSC(i915) ? 8 : 0;
2169}
2170
2171static
2172bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
2173 struct drm_connector_state *conn_state,
2174 struct link_config_limits *limits,
2175 int pipe_bpp)
2176{
2177 u8 dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
2178
2179 dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc);
2180 dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2181
2182 dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
2183 dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
2184
2185 return pipe_bpp >= dsc_min_pipe_bpp &&
2186 pipe_bpp <= dsc_max_pipe_bpp;
2187}
2188
2189static
2190int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
2191 struct drm_connector_state *conn_state,
2192 struct link_config_limits *limits)
2193{
2194 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2195 int forced_bpp;
2196
2197 if (!intel_dp->force_dsc_bpc)
2198 return 0;
2199
2200 forced_bpp = intel_dp->force_dsc_bpc * 3;
2201
2202 if (is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, forced_bpp)) {
2203 drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);
2204 return forced_bpp;
2205 }
2206
2207 drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
2208 intel_dp->force_dsc_bpc);
2209
2210 return 0;
2211}
2212
2213static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2214 struct intel_crtc_state *pipe_config,
2215 struct drm_connector_state *conn_state,
2216 struct link_config_limits *limits,
2217 int timeslots)
2218{
2219 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2220 const struct intel_connector *connector =
2221 to_intel_connector(conn_state->connector);
2222 u8 max_req_bpc = conn_state->max_requested_bpc;
2223 u8 dsc_max_bpc, dsc_max_bpp;
2224 u8 dsc_min_bpc, dsc_min_bpp;
2225 u8 dsc_bpc[3] = {};
2226 int forced_bpp, pipe_bpp;
2227 int num_bpc, i, ret;
2228
2229 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
2230
2231 if (forced_bpp) {
2232 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,
2233 limits, forced_bpp, timeslots);
2234 if (ret == 0) {
2235 pipe_config->pipe_bpp = forced_bpp;
2236 return 0;
2237 }
2238 }
2239
2240 dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
2241 if (!dsc_max_bpc)
2242 return -EINVAL;
2243
2244 dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
2245 dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
2246
2247 dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2248 dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
2249
2250 /*
2251 * Get the maximum DSC bpc that will be supported by any valid
2252 * link configuration and compressed bpp.
2253 */
2254 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc);
2255 for (i = 0; i < num_bpc; i++) {
2256 pipe_bpp = dsc_bpc[i] * 3;
2257 if (pipe_bpp < dsc_min_bpp)
2258 break;
2259 if (pipe_bpp > dsc_max_bpp)
2260 continue;
2261 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,
2262 limits, pipe_bpp, timeslots);
2263 if (ret == 0) {
2264 pipe_config->pipe_bpp = pipe_bpp;
2265 return 0;
2266 }
2267 }
2268
2269 return -EINVAL;
2270}
2271
2272static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2273 struct intel_crtc_state *pipe_config,
2274 struct drm_connector_state *conn_state,
2275 struct link_config_limits *limits)
2276{
2277 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2278 struct intel_connector *connector =
2279 to_intel_connector(conn_state->connector);
2280 int pipe_bpp, forced_bpp;
2281 int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2282 int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2283
2284 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
2285
2286 if (forced_bpp) {
2287 pipe_bpp = forced_bpp;
2288 } else {
2289 int max_bpc = min(limits->pipe.max_bpp / 3, (int)conn_state->max_requested_bpc);
2290
2291 /* For eDP use max bpp that can be supported with DSC. */
2292 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc);
2293 if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
2294 drm_dbg_kms(&i915->drm,
2295 "Computed BPC is not in DSC BPC limits\n");
2296 return -EINVAL;
2297 }
2298 }
2299 pipe_config->port_clock = limits->max_rate;
2300 pipe_config->lane_count = limits->max_lane_count;
2301
2302 dsc_src_min_bpp = dsc_src_min_compressed_bpp();
2303 dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
2304 dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2305 dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits->link.min_bpp_x16));
2306
2307 dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2308 dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2309 pipe_config,
2310 pipe_bpp / 3);
2311 dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2312 dsc_max_bpp = min(dsc_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16));
2313
2314 /* Compressed BPP should be less than the Input DSC bpp */
2315 dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
2316
2317 pipe_config->dsc.compressed_bpp_x16 =
2318 fxp_q4_from_int(max(dsc_min_bpp, dsc_max_bpp));
2319
2320 pipe_config->pipe_bpp = pipe_bpp;
2321
2322 return 0;
2323}
2324
2325int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2326 struct intel_crtc_state *pipe_config,
2327 struct drm_connector_state *conn_state,
2328 struct link_config_limits *limits,
2329 int timeslots,
2330 bool compute_pipe_bpp)
2331{
2332 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2333 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2334 const struct intel_connector *connector =
2335 to_intel_connector(conn_state->connector);
2336 const struct drm_display_mode *adjusted_mode =
2337 &pipe_config->hw.adjusted_mode;
2338 int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config);
2339 int ret;
2340
2341 /*
2342 * Though eDP v1.5 supports FEC with DSC, unlike DP, it is optional.
2343 * Since, FEC is a bandwidth overhead, continue to not enable it for
2344 * eDP. Until, there is a good reason to do so.
2345 */
2346 pipe_config->fec_enable = pipe_config->fec_enable ||
2347 (!intel_dp_is_edp(intel_dp) &&
2348 intel_dp_supports_fec(intel_dp, connector, pipe_config) &&
2349 !intel_dp_is_uhbr(pipe_config));
2350
2351 if (!intel_dp_supports_dsc(connector, pipe_config))
2352 return -EINVAL;
2353
2354 if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format))
2355 return -EINVAL;
2356
2357 /*
2358 * compute pipe bpp is set to false for DP MST DSC case
2359 * and compressed_bpp is calculated same time once
2360 * vpci timeslots are allocated, because overall bpp
2361 * calculation procedure is bit different for MST case.
2362 */
2363 if (compute_pipe_bpp) {
2364 if (intel_dp_is_edp(intel_dp))
2365 ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2366 conn_state, limits);
2367 else
2368 ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2369 conn_state, limits, timeslots);
2370 if (ret) {
2371 drm_dbg_kms(&dev_priv->drm,
2372 "No Valid pipe bpp for given mode ret = %d\n", ret);
2373 return ret;
2374 }
2375 }
2376
2377 /* Calculate Slice count */
2378 if (intel_dp_is_edp(intel_dp)) {
2379 pipe_config->dsc.slice_count =
2380 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
2381 true);
2382 if (!pipe_config->dsc.slice_count) {
2383 drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n",
2384 pipe_config->dsc.slice_count);
2385 return -EINVAL;
2386 }
2387 } else {
2388 u8 dsc_dp_slice_count;
2389
2390 dsc_dp_slice_count =
2391 intel_dp_dsc_get_slice_count(connector,
2392 adjusted_mode->crtc_clock,
2393 adjusted_mode->crtc_hdisplay,
2394 num_joined_pipes);
2395 if (!dsc_dp_slice_count) {
2396 drm_dbg_kms(&dev_priv->drm,
2397 "Compressed Slice Count not supported\n");
2398 return -EINVAL;
2399 }
2400
2401 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2402 }
2403 /*
2404 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2405 * is greater than the maximum Cdclock and if slice count is even
2406 * then we need to use 2 VDSC instances.
2407 */
2408 if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1)
2409 pipe_config->dsc.dsc_split = true;
2410
2411 ret = intel_dp_dsc_compute_params(connector, pipe_config);
2412 if (ret < 0) {
2413 drm_dbg_kms(&dev_priv->drm,
2414 "Cannot compute valid DSC parameters for Input Bpp = %d"
2415 "Compressed BPP = " FXP_Q4_FMT "\n",
2416 pipe_config->pipe_bpp,
2417 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16));
2418 return ret;
2419 }
2420
2421 pipe_config->dsc.compression_enable = true;
2422 drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2423 "Compressed Bpp = " FXP_Q4_FMT " Slice Count = %d\n",
2424 pipe_config->pipe_bpp,
2425 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),
2426 pipe_config->dsc.slice_count);
2427
2428 return 0;
2429}
2430
2431/**
2432 * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits
2433 * @intel_dp: intel DP
2434 * @crtc_state: crtc state
2435 * @dsc: DSC compression mode
2436 * @limits: link configuration limits
2437 *
2438 * Calculates the output link min, max bpp values in @limits based on the
2439 * pipe bpp range, @crtc_state and @dsc mode.
2440 *
2441 * Returns %true in case of success.
2442 */
2443bool
2444intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
2445 const struct intel_crtc_state *crtc_state,
2446 bool dsc,
2447 struct link_config_limits *limits)
2448{
2449 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2450 const struct drm_display_mode *adjusted_mode =
2451 &crtc_state->hw.adjusted_mode;
2452 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2453 const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2454 int max_link_bpp_x16;
2455
2456 max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
2457 fxp_q4_from_int(limits->pipe.max_bpp));
2458
2459 if (!dsc) {
2460 max_link_bpp_x16 = rounddown(max_link_bpp_x16, fxp_q4_from_int(2 * 3));
2461
2462 if (max_link_bpp_x16 < fxp_q4_from_int(limits->pipe.min_bpp))
2463 return false;
2464
2465 limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp);
2466 } else {
2467 /*
2468 * TODO: set the DSC link limits already here, atm these are
2469 * initialized only later in intel_edp_dsc_compute_pipe_bpp() /
2470 * intel_dp_dsc_compute_pipe_bpp()
2471 */
2472 limits->link.min_bpp_x16 = 0;
2473 }
2474
2475 limits->link.max_bpp_x16 = max_link_bpp_x16;
2476
2477 drm_dbg_kms(&i915->drm,
2478 "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n",
2479 encoder->base.base.id, encoder->base.name,
2480 crtc->base.base.id, crtc->base.name,
2481 adjusted_mode->crtc_clock,
2482 str_on_off(dsc),
2483 limits->max_lane_count,
2484 limits->max_rate,
2485 limits->pipe.max_bpp,
2486 FXP_Q4_ARGS(limits->link.max_bpp_x16));
2487
2488 return true;
2489}
2490
2491static bool
2492intel_dp_compute_config_limits(struct intel_dp *intel_dp,
2493 struct intel_crtc_state *crtc_state,
2494 bool respect_downstream_limits,
2495 bool dsc,
2496 struct link_config_limits *limits)
2497{
2498 limits->min_rate = intel_dp_min_link_rate(intel_dp);
2499 limits->max_rate = intel_dp_max_link_rate(intel_dp);
2500
2501 /* FIXME 128b/132b SST support missing */
2502 limits->max_rate = min(limits->max_rate, 810000);
2503 limits->min_rate = min(limits->min_rate, limits->max_rate);
2504
2505 limits->min_lane_count = intel_dp_min_lane_count(intel_dp);
2506 limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
2507
2508 limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
2509 limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
2510 respect_downstream_limits);
2511
2512 if (intel_dp->use_max_params) {
2513 /*
2514 * Use the maximum clock and number of lanes the eDP panel
2515 * advertizes being capable of in case the initial fast
2516 * optimal params failed us. The panels are generally
2517 * designed to support only a single clock and lane
2518 * configuration, and typically on older panels these
2519 * values correspond to the native resolution of the panel.
2520 */
2521 limits->min_lane_count = limits->max_lane_count;
2522 limits->min_rate = limits->max_rate;
2523 }
2524
2525 intel_dp_test_compute_config(intel_dp, crtc_state, limits);
2526
2527 return intel_dp_compute_config_link_bpp_limits(intel_dp,
2528 crtc_state,
2529 dsc,
2530 limits);
2531}
2532
2533int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state)
2534{
2535 const struct drm_display_mode *adjusted_mode =
2536 &crtc_state->hw.adjusted_mode;
2537 int bpp = crtc_state->dsc.compression_enable ?
2538 fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) :
2539 crtc_state->pipe_bpp;
2540
2541 return intel_dp_link_required(adjusted_mode->crtc_clock, bpp);
2542}
2543
2544bool intel_dp_joiner_needs_dsc(struct drm_i915_private *i915,
2545 int num_joined_pipes)
2546{
2547 /*
2548 * Pipe joiner needs compression up to display 12 due to bandwidth
2549 * limitation. DG2 onwards pipe joiner can be enabled without
2550 * compression.
2551 * Ultrajoiner always needs compression.
2552 */
2553 return (!HAS_UNCOMPRESSED_JOINER(i915) && num_joined_pipes == 2) ||
2554 num_joined_pipes == 4;
2555}
2556
2557static int
2558intel_dp_compute_link_config(struct intel_encoder *encoder,
2559 struct intel_crtc_state *pipe_config,
2560 struct drm_connector_state *conn_state,
2561 bool respect_downstream_limits)
2562{
2563 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2564 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2565 struct intel_connector *connector =
2566 to_intel_connector(conn_state->connector);
2567 const struct drm_display_mode *adjusted_mode =
2568 &pipe_config->hw.adjusted_mode;
2569 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2570 struct link_config_limits limits;
2571 bool dsc_needed, joiner_needs_dsc;
2572 int num_joined_pipes;
2573 int ret = 0;
2574
2575 if (pipe_config->fec_enable &&
2576 !intel_dp_supports_fec(intel_dp, connector, pipe_config))
2577 return -EINVAL;
2578
2579 num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
2580 adjusted_mode->crtc_hdisplay,
2581 adjusted_mode->crtc_clock);
2582 if (num_joined_pipes > 1)
2583 pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);
2584
2585 joiner_needs_dsc = intel_dp_joiner_needs_dsc(i915, num_joined_pipes);
2586
2587 dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
2588 !intel_dp_compute_config_limits(intel_dp, pipe_config,
2589 respect_downstream_limits,
2590 false,
2591 &limits);
2592
2593 if (!dsc_needed) {
2594 /*
2595 * Optimize for slow and wide for everything, because there are some
2596 * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
2597 */
2598 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2599 conn_state, &limits);
2600 if (ret)
2601 dsc_needed = true;
2602 }
2603
2604 if (dsc_needed) {
2605 drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
2606 str_yes_no(ret), str_yes_no(joiner_needs_dsc),
2607 str_yes_no(intel_dp->force_dsc_en));
2608
2609 if (!intel_dp_compute_config_limits(intel_dp, pipe_config,
2610 respect_downstream_limits,
2611 true,
2612 &limits))
2613 return -EINVAL;
2614
2615 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2616 conn_state, &limits, 64, true);
2617 if (ret < 0)
2618 return ret;
2619 }
2620
2621 drm_dbg_kms(&i915->drm,
2622 "DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available %d\n",
2623 pipe_config->lane_count, pipe_config->port_clock,
2624 pipe_config->pipe_bpp,
2625 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),
2626 intel_dp_config_required_rate(pipe_config),
2627 intel_dp_max_link_data_rate(intel_dp,
2628 pipe_config->port_clock,
2629 pipe_config->lane_count));
2630
2631 return 0;
2632}
2633
2634bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2635 const struct drm_connector_state *conn_state)
2636{
2637 const struct intel_digital_connector_state *intel_conn_state =
2638 to_intel_digital_connector_state(conn_state);
2639 const struct drm_display_mode *adjusted_mode =
2640 &crtc_state->hw.adjusted_mode;
2641
2642 /*
2643 * Our YCbCr output is always limited range.
2644 * crtc_state->limited_color_range only applies to RGB,
2645 * and it must never be set for YCbCr or we risk setting
2646 * some conflicting bits in TRANSCONF which will mess up
2647 * the colors on the monitor.
2648 */
2649 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2650 return false;
2651
2652 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2653 /*
2654 * See:
2655 * CEA-861-E - 5.1 Default Encoding Parameters
2656 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2657 */
2658 return crtc_state->pipe_bpp != 18 &&
2659 drm_default_rgb_quant_range(adjusted_mode) ==
2660 HDMI_QUANTIZATION_RANGE_LIMITED;
2661 } else {
2662 return intel_conn_state->broadcast_rgb ==
2663 INTEL_BROADCAST_RGB_LIMITED;
2664 }
2665}
2666
2667static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2668 enum port port)
2669{
2670 if (IS_G4X(dev_priv))
2671 return false;
2672 if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
2673 return false;
2674
2675 return true;
2676}
2677
2678static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2679 const struct drm_connector_state *conn_state,
2680 struct drm_dp_vsc_sdp *vsc)
2681{
2682 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2683 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2684
2685 if (crtc_state->has_panel_replay) {
2686 /*
2687 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2688 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
2689 * Encoding/Colorimetry Format indication.
2690 */
2691 vsc->revision = 0x7;
2692 } else {
2693 /*
2694 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2695 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2696 * Colorimetry Format indication.
2697 */
2698 vsc->revision = 0x5;
2699 }
2700
2701 vsc->length = 0x13;
2702
2703 /* DP 1.4a spec, Table 2-120 */
2704 switch (crtc_state->output_format) {
2705 case INTEL_OUTPUT_FORMAT_YCBCR444:
2706 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2707 break;
2708 case INTEL_OUTPUT_FORMAT_YCBCR420:
2709 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2710 break;
2711 case INTEL_OUTPUT_FORMAT_RGB:
2712 default:
2713 vsc->pixelformat = DP_PIXELFORMAT_RGB;
2714 }
2715
2716 switch (conn_state->colorspace) {
2717 case DRM_MODE_COLORIMETRY_BT709_YCC:
2718 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2719 break;
2720 case DRM_MODE_COLORIMETRY_XVYCC_601:
2721 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2722 break;
2723 case DRM_MODE_COLORIMETRY_XVYCC_709:
2724 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2725 break;
2726 case DRM_MODE_COLORIMETRY_SYCC_601:
2727 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2728 break;
2729 case DRM_MODE_COLORIMETRY_OPYCC_601:
2730 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2731 break;
2732 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2733 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2734 break;
2735 case DRM_MODE_COLORIMETRY_BT2020_RGB:
2736 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2737 break;
2738 case DRM_MODE_COLORIMETRY_BT2020_YCC:
2739 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2740 break;
2741 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2742 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2743 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2744 break;
2745 default:
2746 /*
2747 * RGB->YCBCR color conversion uses the BT.709
2748 * color space.
2749 */
2750 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2751 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2752 else
2753 vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2754 break;
2755 }
2756
2757 vsc->bpc = crtc_state->pipe_bpp / 3;
2758
2759 /* only RGB pixelformat supports 6 bpc */
2760 drm_WARN_ON(&dev_priv->drm,
2761 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2762
2763 /* all YCbCr are always limited range */
2764 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2765 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2766}
2767
2768static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
2769 struct intel_crtc_state *crtc_state)
2770{
2771 struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
2772 const struct drm_display_mode *adjusted_mode =
2773 &crtc_state->hw.adjusted_mode;
2774
2775 if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
2776 return;
2777
2778 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
2779
2780 as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
2781 as_sdp->length = 0x9;
2782 as_sdp->duration_incr_ms = 0;
2783
2784 if (crtc_state->cmrr.enable) {
2785 as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
2786 as_sdp->vtotal = adjusted_mode->vtotal;
2787 as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
2788 as_sdp->target_rr_divider = true;
2789 } else {
2790 as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
2791 as_sdp->vtotal = adjusted_mode->vtotal;
2792 as_sdp->target_rr = 0;
2793 }
2794}
2795
2796static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2797 struct intel_crtc_state *crtc_state,
2798 const struct drm_connector_state *conn_state)
2799{
2800 struct drm_dp_vsc_sdp *vsc;
2801
2802 if ((!intel_dp->colorimetry_support ||
2803 !intel_dp_needs_vsc_sdp(crtc_state, conn_state)) &&
2804 !crtc_state->has_psr)
2805 return;
2806
2807 vsc = &crtc_state->infoframes.vsc;
2808
2809 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2810 vsc->sdp_type = DP_SDP_VSC;
2811
2812 /* Needs colorimetry */
2813 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2814 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2815 vsc);
2816 } else if (crtc_state->has_panel_replay) {
2817 /*
2818 * [Panel Replay without colorimetry info]
2819 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2820 * VSC SDP supporting 3D stereo + Panel Replay.
2821 */
2822 vsc->revision = 0x6;
2823 vsc->length = 0x10;
2824 } else if (crtc_state->has_sel_update) {
2825 /*
2826 * [PSR2 without colorimetry]
2827 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2828 * 3D stereo + PSR/PSR2 + Y-coordinate.
2829 */
2830 vsc->revision = 0x4;
2831 vsc->length = 0xe;
2832 } else {
2833 /*
2834 * [PSR1]
2835 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2836 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2837 * higher).
2838 */
2839 vsc->revision = 0x2;
2840 vsc->length = 0x8;
2841 }
2842}
2843
2844static void
2845intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2846 struct intel_crtc_state *crtc_state,
2847 const struct drm_connector_state *conn_state)
2848{
2849 int ret;
2850 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2851 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2852
2853 if (!conn_state->hdr_output_metadata)
2854 return;
2855
2856 ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2857
2858 if (ret) {
2859 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2860 return;
2861 }
2862
2863 crtc_state->infoframes.enable |=
2864 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2865}
2866
2867static bool can_enable_drrs(struct intel_connector *connector,
2868 const struct intel_crtc_state *pipe_config,
2869 const struct drm_display_mode *downclock_mode)
2870{
2871 struct drm_i915_private *i915 = to_i915(connector->base.dev);
2872
2873 if (pipe_config->vrr.enable)
2874 return false;
2875
2876 /*
2877 * DRRS and PSR can't be enable together, so giving preference to PSR
2878 * as it allows more power-savings by complete shutting down display,
2879 * so to guarantee this, intel_drrs_compute_config() must be called
2880 * after intel_psr_compute_config().
2881 */
2882 if (pipe_config->has_psr)
2883 return false;
2884
2885 /* FIXME missing FDI M2/N2 etc. */
2886 if (pipe_config->has_pch_encoder)
2887 return false;
2888
2889 if (!intel_cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))
2890 return false;
2891
2892 return downclock_mode &&
2893 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
2894}
2895
2896static void
2897intel_dp_drrs_compute_config(struct intel_connector *connector,
2898 struct intel_crtc_state *pipe_config,
2899 int link_bpp_x16)
2900{
2901 struct drm_i915_private *i915 = to_i915(connector->base.dev);
2902 const struct drm_display_mode *downclock_mode =
2903 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
2904 int pixel_clock;
2905
2906 /*
2907 * FIXME all joined pipes share the same transcoder.
2908 * Need to account for that when updating M/N live.
2909 */
2910 if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes)
2911 pipe_config->update_m_n = true;
2912
2913 if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
2914 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
2915 intel_zero_m_n(&pipe_config->dp_m2_n2);
2916 return;
2917 }
2918
2919 if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
2920 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
2921
2922 pipe_config->has_drrs = true;
2923
2924 pixel_clock = downclock_mode->clock;
2925 if (pipe_config->splitter.enable)
2926 pixel_clock /= pipe_config->splitter.link_count;
2927
2928 intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock,
2929 pipe_config->port_clock,
2930 intel_dp_bw_fec_overhead(pipe_config->fec_enable),
2931 &pipe_config->dp_m2_n2);
2932
2933 /* FIXME: abstract this better */
2934 if (pipe_config->splitter.enable)
2935 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
2936}
2937
2938static bool intel_dp_has_audio(struct intel_encoder *encoder,
2939 const struct drm_connector_state *conn_state)
2940{
2941 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2942 const struct intel_digital_connector_state *intel_conn_state =
2943 to_intel_digital_connector_state(conn_state);
2944 struct intel_connector *connector =
2945 to_intel_connector(conn_state->connector);
2946
2947 if (!intel_dp_port_has_audio(i915, encoder->port))
2948 return false;
2949
2950 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2951 return connector->base.display_info.has_audio;
2952 else
2953 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2954}
2955
2956static int
2957intel_dp_compute_output_format(struct intel_encoder *encoder,
2958 struct intel_crtc_state *crtc_state,
2959 struct drm_connector_state *conn_state,
2960 bool respect_downstream_limits)
2961{
2962 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2963 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2964 struct intel_connector *connector = intel_dp->attached_connector;
2965 const struct drm_display_info *info = &connector->base.display_info;
2966 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2967 bool ycbcr_420_only;
2968 int ret;
2969
2970 ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2971
2972 if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
2973 drm_dbg_kms(&i915->drm,
2974 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2975 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
2976 } else {
2977 crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode);
2978 }
2979
2980 crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);
2981
2982 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2983 respect_downstream_limits);
2984 if (ret) {
2985 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2986 !connector->base.ycbcr_420_allowed ||
2987 !drm_mode_is_420_also(info, adjusted_mode))
2988 return ret;
2989
2990 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2991 crtc_state->output_format = intel_dp_output_format(connector,
2992 crtc_state->sink_format);
2993 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2994 respect_downstream_limits);
2995 }
2996
2997 return ret;
2998}
2999
3000void
3001intel_dp_audio_compute_config(struct intel_encoder *encoder,
3002 struct intel_crtc_state *pipe_config,
3003 struct drm_connector_state *conn_state)
3004{
3005 pipe_config->has_audio =
3006 intel_dp_has_audio(encoder, conn_state) &&
3007 intel_audio_compute_config(encoder, pipe_config, conn_state);
3008
3009 pipe_config->sdp_split_enable = pipe_config->has_audio &&
3010 intel_dp_is_uhbr(pipe_config);
3011}
3012
3013static void intel_dp_queue_modeset_retry_work(struct intel_connector *connector)
3014{
3015 struct drm_i915_private *i915 = to_i915(connector->base.dev);
3016
3017 drm_connector_get(&connector->base);
3018 if (!queue_work(i915->unordered_wq, &connector->modeset_retry_work))
3019 drm_connector_put(&connector->base);
3020}
3021
3022void
3023intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state,
3024 struct intel_encoder *encoder,
3025 const struct intel_crtc_state *crtc_state)
3026{
3027 struct intel_connector *connector;
3028 struct intel_digital_connector_state *conn_state;
3029 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3030 int i;
3031
3032 if (intel_dp->needs_modeset_retry)
3033 return;
3034
3035 intel_dp->needs_modeset_retry = true;
3036
3037 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3038 intel_dp_queue_modeset_retry_work(intel_dp->attached_connector);
3039
3040 return;
3041 }
3042
3043 for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
3044 if (!conn_state->base.crtc)
3045 continue;
3046
3047 if (connector->mst_port == intel_dp)
3048 intel_dp_queue_modeset_retry_work(connector);
3049 }
3050}
3051
3052int
3053intel_dp_compute_config(struct intel_encoder *encoder,
3054 struct intel_crtc_state *pipe_config,
3055 struct drm_connector_state *conn_state)
3056{
3057 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3058 struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
3059 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
3060 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3061 const struct drm_display_mode *fixed_mode;
3062 struct intel_connector *connector = intel_dp->attached_connector;
3063 int ret = 0, link_bpp_x16;
3064
3065 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
3066 pipe_config->has_pch_encoder = true;
3067
3068 fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
3069 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
3070 ret = intel_panel_compute_config(connector, adjusted_mode);
3071 if (ret)
3072 return ret;
3073 }
3074
3075 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
3076 return -EINVAL;
3077
3078 if (!connector->base.interlace_allowed &&
3079 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
3080 return -EINVAL;
3081
3082 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
3083 return -EINVAL;
3084
3085 if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
3086 return -EINVAL;
3087
3088 /*
3089 * Try to respect downstream TMDS clock limits first, if
3090 * that fails assume the user might know something we don't.
3091 */
3092 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
3093 if (ret)
3094 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
3095 if (ret)
3096 return ret;
3097
3098 if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
3099 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3100 ret = intel_panel_fitting(pipe_config, conn_state);
3101 if (ret)
3102 return ret;
3103 }
3104
3105 pipe_config->limited_color_range =
3106 intel_dp_limited_color_range(pipe_config, conn_state);
3107
3108 pipe_config->enhanced_framing =
3109 drm_dp_enhanced_frame_cap(intel_dp->dpcd);
3110
3111 if (pipe_config->dsc.compression_enable)
3112 link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
3113 else
3114 link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(pipe_config->output_format,
3115 pipe_config->pipe_bpp));
3116
3117 if (intel_dp->mso_link_count) {
3118 int n = intel_dp->mso_link_count;
3119 int overlap = intel_dp->mso_pixel_overlap;
3120
3121 pipe_config->splitter.enable = true;
3122 pipe_config->splitter.link_count = n;
3123 pipe_config->splitter.pixel_overlap = overlap;
3124
3125 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
3126 n, overlap);
3127
3128 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
3129 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
3130 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
3131 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
3132 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
3133 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
3134 adjusted_mode->crtc_clock /= n;
3135 }
3136
3137 intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
3138
3139 intel_link_compute_m_n(link_bpp_x16,
3140 pipe_config->lane_count,
3141 adjusted_mode->crtc_clock,
3142 pipe_config->port_clock,
3143 intel_dp_bw_fec_overhead(pipe_config->fec_enable),
3144 &pipe_config->dp_m_n);
3145
3146 /* FIXME: abstract this better */
3147 if (pipe_config->splitter.enable)
3148 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
3149
3150 if (!HAS_DDI(dev_priv))
3151 g4x_dp_set_clock(encoder, pipe_config);
3152
3153 intel_vrr_compute_config(pipe_config, conn_state);
3154 intel_dp_compute_as_sdp(intel_dp, pipe_config);
3155 intel_psr_compute_config(intel_dp, pipe_config, conn_state);
3156 intel_alpm_lobf_compute_config(intel_dp, pipe_config, conn_state);
3157 intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
3158 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
3159 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
3160
3161 return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,
3162 pipe_config);
3163}
3164
3165void intel_dp_set_link_params(struct intel_dp *intel_dp,
3166 int link_rate, int lane_count)
3167{
3168 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3169 intel_dp->link_trained = false;
3170 intel_dp->needs_modeset_retry = false;
3171 intel_dp->link_rate = link_rate;
3172 intel_dp->lane_count = lane_count;
3173}
3174
3175void intel_dp_reset_link_params(struct intel_dp *intel_dp)
3176{
3177 intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp);
3178 intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
3179 intel_dp->link.mst_probed_lane_count = 0;
3180 intel_dp->link.mst_probed_rate = 0;
3181 intel_dp->link.retrain_disabled = false;
3182 intel_dp->link.seq_train_failures = 0;
3183}
3184
3185/* Enable backlight PWM and backlight PP control. */
3186void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
3187 const struct drm_connector_state *conn_state)
3188{
3189 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
3190 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3191
3192 if (!intel_dp_is_edp(intel_dp))
3193 return;
3194
3195 drm_dbg_kms(&i915->drm, "\n");
3196
3197 intel_backlight_enable(crtc_state, conn_state);
3198 intel_pps_backlight_on(intel_dp);
3199}
3200
3201/* Disable backlight PP control and backlight PWM. */
3202void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3203{
3204 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3205 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3206
3207 if (!intel_dp_is_edp(intel_dp))
3208 return;
3209
3210 drm_dbg_kms(&i915->drm, "\n");
3211
3212 intel_pps_backlight_off(intel_dp);
3213 intel_backlight_disable(old_conn_state);
3214}
3215
3216static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3217{
3218 /*
3219 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3220 * be capable of signalling downstream hpd with a long pulse.
3221 * Whether or not that means D3 is safe to use is not clear,
3222 * but let's assume so until proven otherwise.
3223 *
3224 * FIXME should really check all downstream ports...
3225 */
3226 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3227 drm_dp_is_branch(intel_dp->dpcd) &&
3228 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3229}
3230
3231static int
3232write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set)
3233{
3234 int err;
3235 u8 val;
3236
3237 err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val);
3238 if (err < 0)
3239 return err;
3240
3241 if (set)
3242 val |= flag;
3243 else
3244 val &= ~flag;
3245
3246 return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val);
3247}
3248
3249static void
3250intel_dp_sink_set_dsc_decompression(struct intel_connector *connector,
3251 bool enable)
3252{
3253 struct drm_i915_private *i915 = to_i915(connector->base.dev);
3254
3255 if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux,
3256 DP_DECOMPRESSION_EN, enable) < 0)
3257 drm_dbg_kms(&i915->drm,
3258 "Failed to %s sink decompression state\n",
3259 str_enable_disable(enable));
3260}
3261
3262static void
3263intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,
3264 bool enable)
3265{
3266 struct drm_i915_private *i915 = to_i915(connector->base.dev);
3267 struct drm_dp_aux *aux = connector->port ?
3268 connector->port->passthrough_aux : NULL;
3269
3270 if (!aux)
3271 return;
3272
3273 if (write_dsc_decompression_flag(aux,
3274 DP_DSC_PASSTHROUGH_EN, enable) < 0)
3275 drm_dbg_kms(&i915->drm,
3276 "Failed to %s sink compression passthrough state\n",
3277 str_enable_disable(enable));
3278}
3279
3280static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state,
3281 const struct intel_connector *connector,
3282 bool for_get_ref)
3283{
3284 struct drm_i915_private *i915 = to_i915(state->base.dev);
3285 struct drm_connector *_connector_iter;
3286 struct drm_connector_state *old_conn_state;
3287 struct drm_connector_state *new_conn_state;
3288 int ref_count = 0;
3289 int i;
3290
3291 /*
3292 * On SST the decompression AUX device won't be shared, each connector
3293 * uses for this its own AUX targeting the sink device.
3294 */
3295 if (!connector->mst_port)
3296 return connector->dp.dsc_decompression_enabled ? 1 : 0;
3297
3298 for_each_oldnew_connector_in_state(&state->base, _connector_iter,
3299 old_conn_state, new_conn_state, i) {
3300 const struct intel_connector *
3301 connector_iter = to_intel_connector(_connector_iter);
3302
3303 if (connector_iter->mst_port != connector->mst_port)
3304 continue;
3305
3306 if (!connector_iter->dp.dsc_decompression_enabled)
3307 continue;
3308
3309 drm_WARN_ON(&i915->drm,
3310 (for_get_ref && !new_conn_state->crtc) ||
3311 (!for_get_ref && !old_conn_state->crtc));
3312
3313 if (connector_iter->dp.dsc_decompression_aux ==
3314 connector->dp.dsc_decompression_aux)
3315 ref_count++;
3316 }
3317
3318 return ref_count;
3319}
3320
3321static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state,
3322 struct intel_connector *connector)
3323{
3324 bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0;
3325
3326 connector->dp.dsc_decompression_enabled = true;
3327
3328 return ret;
3329}
3330
3331static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state,
3332 struct intel_connector *connector)
3333{
3334 connector->dp.dsc_decompression_enabled = false;
3335
3336 return intel_dp_dsc_aux_ref_count(state, connector, false) == 0;
3337}
3338
3339/**
3340 * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device
3341 * @state: atomic state
3342 * @connector: connector to enable the decompression for
3343 * @new_crtc_state: new state for the CRTC driving @connector
3344 *
3345 * Enable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3346 * register of the appropriate sink/branch device. On SST this is always the
3347 * sink device, whereas on MST based on each device's DSC capabilities it's
3348 * either the last branch device (enabling decompression in it) or both the
3349 * last branch device (enabling passthrough in it) and the sink device
3350 * (enabling decompression in it).
3351 */
3352void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
3353 struct intel_connector *connector,
3354 const struct intel_crtc_state *new_crtc_state)
3355{
3356 struct drm_i915_private *i915 = to_i915(state->base.dev);
3357
3358 if (!new_crtc_state->dsc.compression_enable)
3359 return;
3360
3361 if (drm_WARN_ON(&i915->drm,
3362 !connector->dp.dsc_decompression_aux ||
3363 connector->dp.dsc_decompression_enabled))
3364 return;
3365
3366 if (!intel_dp_dsc_aux_get_ref(state, connector))
3367 return;
3368
3369 intel_dp_sink_set_dsc_passthrough(connector, true);
3370 intel_dp_sink_set_dsc_decompression(connector, true);
3371}
3372
3373/**
3374 * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device
3375 * @state: atomic state
3376 * @connector: connector to disable the decompression for
3377 * @old_crtc_state: old state for the CRTC driving @connector
3378 *
3379 * Disable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3380 * register of the appropriate sink/branch device, corresponding to the
3381 * sequence in intel_dp_sink_enable_decompression().
3382 */
3383void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
3384 struct intel_connector *connector,
3385 const struct intel_crtc_state *old_crtc_state)
3386{
3387 struct drm_i915_private *i915 = to_i915(state->base.dev);
3388
3389 if (!old_crtc_state->dsc.compression_enable)
3390 return;
3391
3392 if (drm_WARN_ON(&i915->drm,
3393 !connector->dp.dsc_decompression_aux ||
3394 !connector->dp.dsc_decompression_enabled))
3395 return;
3396
3397 if (!intel_dp_dsc_aux_put_ref(state, connector))
3398 return;
3399
3400 intel_dp_sink_set_dsc_decompression(connector, false);
3401 intel_dp_sink_set_dsc_passthrough(connector, false);
3402}
3403
3404static void
3405intel_dp_init_source_oui(struct intel_dp *intel_dp)
3406{
3407 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3408 u8 oui[] = { 0x00, 0xaa, 0x01 };
3409 u8 buf[3] = {};
3410
3411 if (READ_ONCE(intel_dp->oui_valid))
3412 return;
3413
3414 WRITE_ONCE(intel_dp->oui_valid, true);
3415
3416 /*
3417 * During driver init, we want to be careful and avoid changing the source OUI if it's
3418 * already set to what we want, so as to avoid clearing any state by accident
3419 */
3420 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
3421 drm_err(&i915->drm, "Failed to read source OUI\n");
3422
3423 if (memcmp(oui, buf, sizeof(oui)) == 0) {
3424 /* Assume the OUI was written now. */
3425 intel_dp->last_oui_write = jiffies;
3426 return;
3427 }
3428
3429 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) {
3430 drm_info(&i915->drm, "Failed to write source OUI\n");
3431 WRITE_ONCE(intel_dp->oui_valid, false);
3432 }
3433
3434 intel_dp->last_oui_write = jiffies;
3435}
3436
3437void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp)
3438{
3439 WRITE_ONCE(intel_dp->oui_valid, false);
3440}
3441
3442void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
3443{
3444 struct intel_connector *connector = intel_dp->attached_connector;
3445 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3446
3447 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",
3448 connector->base.base.id, connector->base.name,
3449 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3450
3451 wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,
3452 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3453}
3454
3455/* If the device supports it, try to set the power state appropriately */
3456void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
3457{
3458 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3459 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3460 int ret, i;
3461
3462 /* Should have a valid DPCD by this point */
3463 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3464 return;
3465
3466 if (mode != DP_SET_POWER_D0) {
3467 if (downstream_hpd_needs_d0(intel_dp))
3468 return;
3469
3470 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3471 } else {
3472 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3473
3474 lspcon_resume(dp_to_dig_port(intel_dp));
3475
3476 /* Write the source OUI as early as possible */
3477 intel_dp_init_source_oui(intel_dp);
3478
3479 /*
3480 * When turning on, we need to retry for 1ms to give the sink
3481 * time to wake up.
3482 */
3483 for (i = 0; i < 3; i++) {
3484 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3485 if (ret == 1)
3486 break;
3487 msleep(1);
3488 }
3489
3490 if (ret == 1 && lspcon->active)
3491 lspcon_wait_pcon_mode(lspcon);
3492 }
3493
3494 if (ret != 1)
3495 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
3496 encoder->base.base.id, encoder->base.name,
3497 mode == DP_SET_POWER_D0 ? "D0" : "D3");
3498}
3499
3500static bool
3501intel_dp_get_dpcd(struct intel_dp *intel_dp);
3502
3503/**
3504 * intel_dp_sync_state - sync the encoder state during init/resume
3505 * @encoder: intel encoder to sync
3506 * @crtc_state: state for the CRTC connected to the encoder
3507 *
3508 * Sync any state stored in the encoder wrt. HW state during driver init
3509 * and system resume.
3510 */
3511void intel_dp_sync_state(struct intel_encoder *encoder,
3512 const struct intel_crtc_state *crtc_state)
3513{
3514 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3515 bool dpcd_updated = false;
3516
3517 /*
3518 * Don't clobber DPCD if it's been already read out during output
3519 * setup (eDP) or detect.
3520 */
3521 if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) {
3522 intel_dp_get_dpcd(intel_dp);
3523 dpcd_updated = true;
3524 }
3525
3526 intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated);
3527
3528 if (crtc_state) {
3529 intel_dp_reset_link_params(intel_dp);
3530 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count);
3531 intel_dp->link_trained = true;
3532 }
3533}
3534
3535bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
3536 struct intel_crtc_state *crtc_state)
3537{
3538 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3539 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3540 bool fastset = true;
3541
3542 /*
3543 * If BIOS has set an unsupported or non-standard link rate for some
3544 * reason force an encoder recompute and full modeset.
3545 */
3546 if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
3547 crtc_state->port_clock) < 0) {
3548 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",
3549 encoder->base.base.id, encoder->base.name);
3550 crtc_state->uapi.connectors_changed = true;
3551 fastset = false;
3552 }
3553
3554 /*
3555 * FIXME hack to force full modeset when DSC is being used.
3556 *
3557 * As long as we do not have full state readout and config comparison
3558 * of crtc_state->dsc, we have no way to ensure reliable fastset.
3559 * Remove once we have readout for DSC.
3560 */
3561 if (crtc_state->dsc.compression_enable) {
3562 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",
3563 encoder->base.base.id, encoder->base.name);
3564 crtc_state->uapi.mode_changed = true;
3565 fastset = false;
3566 }
3567
3568 if (CAN_PANEL_REPLAY(intel_dp)) {
3569 drm_dbg_kms(&i915->drm,
3570 "[ENCODER:%d:%s] Forcing full modeset to compute panel replay state\n",
3571 encoder->base.base.id, encoder->base.name);
3572 crtc_state->uapi.mode_changed = true;
3573 fastset = false;
3574 }
3575
3576 return fastset;
3577}
3578
3579static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
3580{
3581 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3582
3583 /* Clear the cached register set to avoid using stale values */
3584
3585 memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
3586
3587 if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
3588 intel_dp->pcon_dsc_dpcd,
3589 sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
3590 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
3591 DP_PCON_DSC_ENCODER);
3592
3593 drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
3594 (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
3595}
3596
3597static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
3598{
3599 static const int bw_gbps[] = {9, 18, 24, 32, 40, 48};
3600 int i;
3601
3602 for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
3603 if (frl_bw_mask & (1 << i))
3604 return bw_gbps[i];
3605 }
3606 return 0;
3607}
3608
3609static int intel_dp_pcon_set_frl_mask(int max_frl)
3610{
3611 switch (max_frl) {
3612 case 48:
3613 return DP_PCON_FRL_BW_MASK_48GBPS;
3614 case 40:
3615 return DP_PCON_FRL_BW_MASK_40GBPS;
3616 case 32:
3617 return DP_PCON_FRL_BW_MASK_32GBPS;
3618 case 24:
3619 return DP_PCON_FRL_BW_MASK_24GBPS;
3620 case 18:
3621 return DP_PCON_FRL_BW_MASK_18GBPS;
3622 case 9:
3623 return DP_PCON_FRL_BW_MASK_9GBPS;
3624 }
3625
3626 return 0;
3627}
3628
3629static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
3630{
3631 struct intel_connector *intel_connector = intel_dp->attached_connector;
3632 struct drm_connector *connector = &intel_connector->base;
3633 int max_frl_rate;
3634 int max_lanes, rate_per_lane;
3635 int max_dsc_lanes, dsc_rate_per_lane;
3636
3637 max_lanes = connector->display_info.hdmi.max_lanes;
3638 rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
3639 max_frl_rate = max_lanes * rate_per_lane;
3640
3641 if (connector->display_info.hdmi.dsc_cap.v_1p2) {
3642 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
3643 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
3644 if (max_dsc_lanes && dsc_rate_per_lane)
3645 max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
3646 }
3647
3648 return max_frl_rate;
3649}
3650
3651static bool
3652intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
3653 u8 max_frl_bw_mask, u8 *frl_trained_mask)
3654{
3655 if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&
3656 drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
3657 *frl_trained_mask >= max_frl_bw_mask)
3658 return true;
3659
3660 return false;
3661}
3662
3663static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
3664{
3665#define TIMEOUT_FRL_READY_MS 500
3666#define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
3667
3668 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3669 int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
3670 u8 max_frl_bw_mask = 0, frl_trained_mask;
3671 bool is_active;
3672
3673 max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
3674 drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
3675
3676 max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
3677 drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
3678
3679 max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
3680
3681 if (max_frl_bw <= 0)
3682 return -EINVAL;
3683
3684 max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
3685 drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
3686
3687 if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
3688 goto frl_trained;
3689
3690 ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
3691 if (ret < 0)
3692 return ret;
3693 /* Wait for PCON to be FRL Ready */
3694 wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
3695
3696 if (!is_active)
3697 return -ETIMEDOUT;
3698
3699 ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
3700 DP_PCON_ENABLE_SEQUENTIAL_LINK);
3701 if (ret < 0)
3702 return ret;
3703 ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
3704 DP_PCON_FRL_LINK_TRAIN_NORMAL);
3705 if (ret < 0)
3706 return ret;
3707 ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
3708 if (ret < 0)
3709 return ret;
3710 /*
3711 * Wait for FRL to be completed
3712 * Check if the HDMI Link is up and active.
3713 */
3714 wait_for(is_active =
3715 intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
3716 TIMEOUT_HDMI_LINK_ACTIVE_MS);
3717
3718 if (!is_active)
3719 return -ETIMEDOUT;
3720
3721frl_trained:
3722 drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
3723 intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
3724 intel_dp->frl.is_trained = true;
3725 drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
3726
3727 return 0;
3728}
3729
3730static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
3731{
3732 if (drm_dp_is_branch(intel_dp->dpcd) &&
3733 intel_dp_has_hdmi_sink(intel_dp) &&
3734 intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
3735 return true;
3736
3737 return false;
3738}
3739
3740static
3741int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
3742{
3743 int ret;
3744 u8 buf = 0;
3745
3746 /* Set PCON source control mode */
3747 buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
3748
3749 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3750 if (ret < 0)
3751 return ret;
3752
3753 /* Set HDMI LINK ENABLE */
3754 buf |= DP_PCON_ENABLE_HDMI_LINK;
3755 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3756 if (ret < 0)
3757 return ret;
3758
3759 return 0;
3760}
3761
3762void intel_dp_check_frl_training(struct intel_dp *intel_dp)
3763{
3764 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3765
3766 /*
3767 * Always go for FRL training if:
3768 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
3769 * -sink is HDMI2.1
3770 */
3771 if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
3772 !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
3773 intel_dp->frl.is_trained)
3774 return;
3775
3776 if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
3777 int ret, mode;
3778
3779 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
3780 ret = intel_dp_pcon_set_tmds_mode(intel_dp);
3781 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
3782
3783 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
3784 drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
3785 } else {
3786 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
3787 }
3788}
3789
3790static int
3791intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
3792{
3793 int vactive = crtc_state->hw.adjusted_mode.vdisplay;
3794
3795 return intel_hdmi_dsc_get_slice_height(vactive);
3796}
3797
3798static int
3799intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
3800 const struct intel_crtc_state *crtc_state)
3801{
3802 struct intel_connector *intel_connector = intel_dp->attached_connector;
3803 struct drm_connector *connector = &intel_connector->base;
3804 int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
3805 int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
3806 int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
3807 int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
3808
3809 return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
3810 pcon_max_slice_width,
3811 hdmi_max_slices, hdmi_throughput);
3812}
3813
3814static int
3815intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
3816 const struct intel_crtc_state *crtc_state,
3817 int num_slices, int slice_width)
3818{
3819 struct intel_connector *intel_connector = intel_dp->attached_connector;
3820 struct drm_connector *connector = &intel_connector->base;
3821 int output_format = crtc_state->output_format;
3822 bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
3823 int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
3824 int hdmi_max_chunk_bytes =
3825 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
3826
3827 return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
3828 num_slices, output_format, hdmi_all_bpp,
3829 hdmi_max_chunk_bytes);
3830}
3831
3832void
3833intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
3834 const struct intel_crtc_state *crtc_state)
3835{
3836 u8 pps_param[6];
3837 int slice_height;
3838 int slice_width;
3839 int num_slices;
3840 int bits_per_pixel;
3841 int ret;
3842 struct intel_connector *intel_connector = intel_dp->attached_connector;
3843 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3844 struct drm_connector *connector;
3845 bool hdmi_is_dsc_1_2;
3846
3847 if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
3848 return;
3849
3850 if (!intel_connector)
3851 return;
3852 connector = &intel_connector->base;
3853 hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
3854
3855 if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
3856 !hdmi_is_dsc_1_2)
3857 return;
3858
3859 slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
3860 if (!slice_height)
3861 return;
3862
3863 num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
3864 if (!num_slices)
3865 return;
3866
3867 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
3868 num_slices);
3869
3870 bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
3871 num_slices, slice_width);
3872 if (!bits_per_pixel)
3873 return;
3874
3875 pps_param[0] = slice_height & 0xFF;
3876 pps_param[1] = slice_height >> 8;
3877 pps_param[2] = slice_width & 0xFF;
3878 pps_param[3] = slice_width >> 8;
3879 pps_param[4] = bits_per_pixel & 0xFF;
3880 pps_param[5] = (bits_per_pixel >> 8) & 0x3;
3881
3882 ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
3883 if (ret < 0)
3884 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
3885}
3886
3887void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
3888 const struct intel_crtc_state *crtc_state)
3889{
3890 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3891 bool ycbcr444_to_420 = false;
3892 bool rgb_to_ycbcr = false;
3893 u8 tmp;
3894
3895 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
3896 return;
3897
3898 if (!drm_dp_is_branch(intel_dp->dpcd))
3899 return;
3900
3901 tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0;
3902
3903 if (drm_dp_dpcd_writeb(&intel_dp->aux,
3904 DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
3905 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
3906 str_enable_disable(intel_dp_has_hdmi_sink(intel_dp)));
3907
3908 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3909 switch (crtc_state->output_format) {
3910 case INTEL_OUTPUT_FORMAT_YCBCR420:
3911 break;
3912 case INTEL_OUTPUT_FORMAT_YCBCR444:
3913 ycbcr444_to_420 = true;
3914 break;
3915 case INTEL_OUTPUT_FORMAT_RGB:
3916 rgb_to_ycbcr = true;
3917 ycbcr444_to_420 = true;
3918 break;
3919 default:
3920 MISSING_CASE(crtc_state->output_format);
3921 break;
3922 }
3923 } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
3924 switch (crtc_state->output_format) {
3925 case INTEL_OUTPUT_FORMAT_YCBCR444:
3926 break;
3927 case INTEL_OUTPUT_FORMAT_RGB:
3928 rgb_to_ycbcr = true;
3929 break;
3930 default:
3931 MISSING_CASE(crtc_state->output_format);
3932 break;
3933 }
3934 }
3935
3936 tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
3937
3938 if (drm_dp_dpcd_writeb(&intel_dp->aux,
3939 DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
3940 drm_dbg_kms(&i915->drm,
3941 "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
3942 str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
3943
3944 tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
3945
3946 if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
3947 drm_dbg_kms(&i915->drm,
3948 "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
3949 str_enable_disable(tmp));
3950}
3951
3952static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3953{
3954 u8 dprx = 0;
3955
3956 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
3957 &dprx) != 1)
3958 return false;
3959 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3960}
3961
3962static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux,
3963 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
3964{
3965 if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, dsc_dpcd,
3966 DP_DSC_RECEIVER_CAP_SIZE) < 0) {
3967 drm_err(aux->drm_dev,
3968 "Failed to read DPCD register 0x%x\n",
3969 DP_DSC_SUPPORT);
3970 return;
3971 }
3972
3973 drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n",
3974 DP_DSC_RECEIVER_CAP_SIZE,
3975 dsc_dpcd);
3976}
3977
3978void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector)
3979{
3980 struct drm_i915_private *i915 = to_i915(connector->base.dev);
3981
3982 /*
3983 * Clear the cached register set to avoid using stale values
3984 * for the sinks that do not support DSC.
3985 */
3986 memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
3987
3988 /* Clear fec_capable to avoid using stale values */
3989 connector->dp.fec_capability = 0;
3990
3991 if (dpcd_rev < DP_DPCD_REV_14)
3992 return;
3993
3994 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux,
3995 connector->dp.dsc_dpcd);
3996
3997 if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY,
3998 &connector->dp.fec_capability) < 0) {
3999 drm_err(&i915->drm, "Failed to read FEC DPCD register\n");
4000 return;
4001 }
4002
4003 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
4004 connector->dp.fec_capability);
4005}
4006
4007static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
4008{
4009 if (edp_dpcd_rev < DP_EDP_14)
4010 return;
4011
4012 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd);
4013}
4014
4015static void
4016intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector)
4017{
4018 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4019
4020 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4021 if (!HAS_DSC(i915))
4022 return;
4023
4024 if (intel_dp_is_edp(intel_dp))
4025 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],
4026 connector);
4027 else
4028 intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],
4029 connector);
4030}
4031
4032static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
4033 struct drm_display_mode *mode)
4034{
4035 struct intel_dp *intel_dp = intel_attached_dp(connector);
4036 struct drm_i915_private *i915 = to_i915(connector->base.dev);
4037 int n = intel_dp->mso_link_count;
4038 int overlap = intel_dp->mso_pixel_overlap;
4039
4040 if (!mode || !n)
4041 return;
4042
4043 mode->hdisplay = (mode->hdisplay - overlap) * n;
4044 mode->hsync_start = (mode->hsync_start - overlap) * n;
4045 mode->hsync_end = (mode->hsync_end - overlap) * n;
4046 mode->htotal = (mode->htotal - overlap) * n;
4047 mode->clock *= n;
4048
4049 drm_mode_set_name(mode);
4050
4051 drm_dbg_kms(&i915->drm,
4052 "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
4053 connector->base.base.id, connector->base.name,
4054 DRM_MODE_ARG(mode));
4055}
4056
4057void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
4058{
4059 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4060 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4061 struct intel_connector *connector = intel_dp->attached_connector;
4062
4063 if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {
4064 /*
4065 * This is a big fat ugly hack.
4066 *
4067 * Some machines in UEFI boot mode provide us a VBT that has 18
4068 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
4069 * unknown we fail to light up. Yet the same BIOS boots up with
4070 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
4071 * max, not what it tells us to use.
4072 *
4073 * Note: This will still be broken if the eDP panel is not lit
4074 * up by the BIOS, and thus we can't get the mode at module
4075 * load.
4076 */
4077 drm_dbg_kms(&dev_priv->drm,
4078 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
4079 pipe_bpp, connector->panel.vbt.edp.bpp);
4080 connector->panel.vbt.edp.bpp = pipe_bpp;
4081 }
4082}
4083
4084static void intel_edp_mso_init(struct intel_dp *intel_dp)
4085{
4086 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4087 struct intel_connector *connector = intel_dp->attached_connector;
4088 struct drm_display_info *info = &connector->base.display_info;
4089 u8 mso;
4090
4091 if (intel_dp->edp_dpcd[0] < DP_EDP_14)
4092 return;
4093
4094 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
4095 drm_err(&i915->drm, "Failed to read MSO cap\n");
4096 return;
4097 }
4098
4099 /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
4100 mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
4101 if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
4102 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
4103 mso = 0;
4104 }
4105
4106 if (mso) {
4107 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
4108 mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
4109 info->mso_pixel_overlap);
4110 if (!HAS_MSO(i915)) {
4111 drm_err(&i915->drm, "No source MSO support, disabling\n");
4112 mso = 0;
4113 }
4114 }
4115
4116 intel_dp->mso_link_count = mso;
4117 intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
4118}
4119
4120static void
4121intel_edp_set_sink_rates(struct intel_dp *intel_dp)
4122{
4123 intel_dp->num_sink_rates = 0;
4124
4125 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4126 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4127 int i;
4128
4129 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4130 sink_rates, sizeof(sink_rates));
4131
4132 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4133 int val = le16_to_cpu(sink_rates[i]);
4134
4135 if (val == 0)
4136 break;
4137
4138 /* Value read multiplied by 200kHz gives the per-lane
4139 * link rate in kHz. The source rates are, however,
4140 * stored in terms of LS_Clk kHz. The full conversion
4141 * back to symbols is
4142 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4143 */
4144 intel_dp->sink_rates[i] = (val * 200) / 10;
4145 }
4146 intel_dp->num_sink_rates = i;
4147 }
4148
4149 /*
4150 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4151 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4152 */
4153 if (intel_dp->num_sink_rates)
4154 intel_dp->use_rate_select = true;
4155 else
4156 intel_dp_set_sink_rates(intel_dp);
4157}
4158
4159static bool
4160intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
4161{
4162 struct drm_i915_private *dev_priv =
4163 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4164
4165 /* this function is meant to be called only once */
4166 drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
4167
4168 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
4169 return false;
4170
4171 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4172 drm_dp_is_branch(intel_dp->dpcd));
4173 intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident);
4174
4175 intel_dp->colorimetry_support =
4176 intel_dp_get_colorimetry_status(intel_dp);
4177
4178 /*
4179 * Read the eDP display control registers.
4180 *
4181 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4182 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4183 * set, but require eDP 1.4+ detection (e.g. for supported link rates
4184 * method). The display control registers should read zero if they're
4185 * not supported anyway.
4186 */
4187 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4188 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4189 sizeof(intel_dp->edp_dpcd)) {
4190 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
4191 (int)sizeof(intel_dp->edp_dpcd),
4192 intel_dp->edp_dpcd);
4193
4194 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
4195 }
4196
4197 /*
4198 * If needed, program our source OUI so we can make various Intel-specific AUX services
4199 * available (such as HDR backlight controls)
4200 */
4201 intel_dp_init_source_oui(intel_dp);
4202
4203 /*
4204 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4205 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4206 */
4207 intel_psr_init_dpcd(intel_dp);
4208
4209 intel_edp_set_sink_rates(intel_dp);
4210 intel_dp_set_max_sink_lane_count(intel_dp);
4211
4212 /* Read the eDP DSC DPCD registers */
4213 intel_dp_detect_dsc_caps(intel_dp, connector);
4214
4215 return true;
4216}
4217
4218static bool
4219intel_dp_has_sink_count(struct intel_dp *intel_dp)
4220{
4221 if (!intel_dp->attached_connector)
4222 return false;
4223
4224 return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
4225 intel_dp->dpcd,
4226 &intel_dp->desc);
4227}
4228
4229void intel_dp_update_sink_caps(struct intel_dp *intel_dp)
4230{
4231 intel_dp_set_sink_rates(intel_dp);
4232 intel_dp_set_max_sink_lane_count(intel_dp);
4233 intel_dp_set_common_rates(intel_dp);
4234}
4235
4236static bool
4237intel_dp_get_dpcd(struct intel_dp *intel_dp)
4238{
4239 int ret;
4240
4241 if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
4242 return false;
4243
4244 /*
4245 * Don't clobber cached eDP rates. Also skip re-reading
4246 * the OUI/ID since we know it won't change.
4247 */
4248 if (!intel_dp_is_edp(intel_dp)) {
4249 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4250 drm_dp_is_branch(intel_dp->dpcd));
4251
4252 intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident);
4253
4254 intel_dp->colorimetry_support =
4255 intel_dp_get_colorimetry_status(intel_dp);
4256
4257 intel_dp_update_sink_caps(intel_dp);
4258 }
4259
4260 if (intel_dp_has_sink_count(intel_dp)) {
4261 ret = drm_dp_read_sink_count(&intel_dp->aux);
4262 if (ret < 0)
4263 return false;
4264
4265 /*
4266 * Sink count can change between short pulse hpd hence
4267 * a member variable in intel_dp will track any changes
4268 * between short pulse interrupts.
4269 */
4270 intel_dp->sink_count = ret;
4271
4272 /*
4273 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4274 * a dongle is present but no display. Unless we require to know
4275 * if a dongle is present or not, we don't need to update
4276 * downstream port information. So, an early return here saves
4277 * time from performing other operations which are not required.
4278 */
4279 if (!intel_dp->sink_count)
4280 return false;
4281 }
4282
4283 return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
4284 intel_dp->downstream_ports) == 0;
4285}
4286
4287static const char *intel_dp_mst_mode_str(enum drm_dp_mst_mode mst_mode)
4288{
4289 if (mst_mode == DRM_DP_MST)
4290 return "MST";
4291 else if (mst_mode == DRM_DP_SST_SIDEBAND_MSG)
4292 return "SST w/ sideband messaging";
4293 else
4294 return "SST";
4295}
4296
4297static enum drm_dp_mst_mode
4298intel_dp_mst_mode_choose(struct intel_dp *intel_dp,
4299 enum drm_dp_mst_mode sink_mst_mode)
4300{
4301 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4302
4303 if (!i915->display.params.enable_dp_mst)
4304 return DRM_DP_SST;
4305
4306 if (!intel_dp_mst_source_support(intel_dp))
4307 return DRM_DP_SST;
4308
4309 if (sink_mst_mode == DRM_DP_SST_SIDEBAND_MSG &&
4310 !(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B))
4311 return DRM_DP_SST;
4312
4313 return sink_mst_mode;
4314}
4315
4316static enum drm_dp_mst_mode
4317intel_dp_mst_detect(struct intel_dp *intel_dp)
4318{
4319 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4320 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4321 enum drm_dp_mst_mode sink_mst_mode;
4322 enum drm_dp_mst_mode mst_detect;
4323
4324 sink_mst_mode = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4325
4326 mst_detect = intel_dp_mst_mode_choose(intel_dp, sink_mst_mode);
4327
4328 drm_dbg_kms(&i915->drm,
4329 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s -> enable: %s\n",
4330 encoder->base.base.id, encoder->base.name,
4331 str_yes_no(intel_dp_mst_source_support(intel_dp)),
4332 intel_dp_mst_mode_str(sink_mst_mode),
4333 str_yes_no(i915->display.params.enable_dp_mst),
4334 intel_dp_mst_mode_str(mst_detect));
4335
4336 return mst_detect;
4337}
4338
4339static void
4340intel_dp_mst_configure(struct intel_dp *intel_dp)
4341{
4342 if (!intel_dp_mst_source_support(intel_dp))
4343 return;
4344
4345 intel_dp->is_mst = intel_dp->mst_detect != DRM_DP_SST;
4346
4347 if (intel_dp->is_mst)
4348 intel_dp_mst_prepare_probe(intel_dp);
4349
4350 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4351
4352 /* Avoid stale info on the next detect cycle. */
4353 intel_dp->mst_detect = DRM_DP_SST;
4354}
4355
4356static void
4357intel_dp_mst_disconnect(struct intel_dp *intel_dp)
4358{
4359 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4360
4361 if (!intel_dp->is_mst)
4362 return;
4363
4364 drm_dbg_kms(&i915->drm, "MST device may have disappeared %d vs %d\n",
4365 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4366 intel_dp->is_mst = false;
4367 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4368}
4369
4370static bool
4371intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
4372{
4373 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
4374}
4375
4376static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
4377{
4378 int retry;
4379
4380 for (retry = 0; retry < 3; retry++) {
4381 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
4382 &esi[1], 3) == 3)
4383 return true;
4384 }
4385
4386 return false;
4387}
4388
4389bool
4390intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4391 const struct drm_connector_state *conn_state)
4392{
4393 /*
4394 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4395 * of Color Encoding Format and Content Color Gamut], in order to
4396 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4397 */
4398 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4399 return true;
4400
4401 switch (conn_state->colorspace) {
4402 case DRM_MODE_COLORIMETRY_SYCC_601:
4403 case DRM_MODE_COLORIMETRY_OPYCC_601:
4404 case DRM_MODE_COLORIMETRY_BT2020_YCC:
4405 case DRM_MODE_COLORIMETRY_BT2020_RGB:
4406 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4407 return true;
4408 default:
4409 break;
4410 }
4411
4412 return false;
4413}
4414
4415static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
4416 struct dp_sdp *sdp, size_t size)
4417{
4418 size_t length = sizeof(struct dp_sdp);
4419
4420 if (size < length)
4421 return -ENOSPC;
4422
4423 memset(sdp, 0, size);
4424
4425 /* Prepare AS (Adaptive Sync) SDP Header */
4426 sdp->sdp_header.HB0 = 0;
4427 sdp->sdp_header.HB1 = as_sdp->sdp_type;
4428 sdp->sdp_header.HB2 = 0x02;
4429 sdp->sdp_header.HB3 = as_sdp->length;
4430
4431 /* Fill AS (Adaptive Sync) SDP Payload */
4432 sdp->db[0] = as_sdp->mode;
4433 sdp->db[1] = as_sdp->vtotal & 0xFF;
4434 sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF;
4435 sdp->db[3] = as_sdp->target_rr & 0xFF;
4436 sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3;
4437
4438 if (as_sdp->target_rr_divider)
4439 sdp->db[4] |= 0x20;
4440
4441 return length;
4442}
4443
4444static ssize_t
4445intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
4446 const struct hdmi_drm_infoframe *drm_infoframe,
4447 struct dp_sdp *sdp,
4448 size_t size)
4449{
4450 size_t length = sizeof(struct dp_sdp);
4451 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
4452 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
4453 ssize_t len;
4454
4455 if (size < length)
4456 return -ENOSPC;
4457
4458 memset(sdp, 0, size);
4459
4460 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
4461 if (len < 0) {
4462 drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
4463 return -ENOSPC;
4464 }
4465
4466 if (len != infoframe_size) {
4467 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
4468 return -ENOSPC;
4469 }
4470
4471 /*
4472 * Set up the infoframe sdp packet for HDR static metadata.
4473 * Prepare VSC Header for SU as per DP 1.4a spec,
4474 * Table 2-100 and Table 2-101
4475 */
4476
4477 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
4478 sdp->sdp_header.HB0 = 0;
4479 /*
4480 * Packet Type 80h + Non-audio INFOFRAME Type value
4481 * HDMI_INFOFRAME_TYPE_DRM: 0x87
4482 * - 80h + Non-audio INFOFRAME Type value
4483 * - InfoFrame Type: 0x07
4484 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
4485 */
4486 sdp->sdp_header.HB1 = drm_infoframe->type;
4487 /*
4488 * Least Significant Eight Bits of (Data Byte Count – 1)
4489 * infoframe_size - 1
4490 */
4491 sdp->sdp_header.HB2 = 0x1D;
4492 /* INFOFRAME SDP Version Number */
4493 sdp->sdp_header.HB3 = (0x13 << 2);
4494 /* CTA Header Byte 2 (INFOFRAME Version Number) */
4495 sdp->db[0] = drm_infoframe->version;
4496 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4497 sdp->db[1] = drm_infoframe->length;
4498 /*
4499 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
4500 * HDMI_INFOFRAME_HEADER_SIZE
4501 */
4502 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
4503 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
4504 HDMI_DRM_INFOFRAME_SIZE);
4505
4506 /*
4507 * Size of DP infoframe sdp packet for HDR static metadata consists of
4508 * - DP SDP Header(struct dp_sdp_header): 4 bytes
4509 * - Two Data Blocks: 2 bytes
4510 * CTA Header Byte2 (INFOFRAME Version Number)
4511 * CTA Header Byte3 (Length of INFOFRAME)
4512 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
4513 *
4514 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
4515 * infoframe size. But GEN11+ has larger than that size, write_infoframe
4516 * will pad rest of the size.
4517 */
4518 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
4519}
4520
4521static void intel_write_dp_sdp(struct intel_encoder *encoder,
4522 const struct intel_crtc_state *crtc_state,
4523 unsigned int type)
4524{
4525 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4526 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4527 struct dp_sdp sdp = {};
4528 ssize_t len;
4529
4530 if ((crtc_state->infoframes.enable &
4531 intel_hdmi_infoframe_enable(type)) == 0)
4532 return;
4533
4534 switch (type) {
4535 case DP_SDP_VSC:
4536 len = drm_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp);
4537 break;
4538 case HDMI_PACKET_TYPE_GAMUT_METADATA:
4539 len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
4540 &crtc_state->infoframes.drm.drm,
4541 &sdp, sizeof(sdp));
4542 break;
4543 case DP_SDP_ADAPTIVE_SYNC:
4544 len = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp,
4545 sizeof(sdp));
4546 break;
4547 default:
4548 MISSING_CASE(type);
4549 return;
4550 }
4551
4552 if (drm_WARN_ON(&dev_priv->drm, len < 0))
4553 return;
4554
4555 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
4556}
4557
4558void intel_dp_set_infoframes(struct intel_encoder *encoder,
4559 bool enable,
4560 const struct intel_crtc_state *crtc_state,
4561 const struct drm_connector_state *conn_state)
4562{
4563 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4564 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(dev_priv,
4565 crtc_state->cpu_transcoder);
4566 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
4567 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
4568 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
4569
4570 if (HAS_AS_SDP(dev_priv))
4571 dip_enable |= VIDEO_DIP_ENABLE_AS_ADL;
4572
4573 u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
4574
4575 /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
4576 if (!enable && HAS_DSC(dev_priv))
4577 val &= ~VDIP_ENABLE_PPS;
4578
4579 /*
4580 * This routine disables VSC DIP if the function is called
4581 * to disable SDP or if it does not have PSR
4582 */
4583 if (!enable || !crtc_state->has_psr)
4584 val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
4585
4586 intel_de_write(dev_priv, reg, val);
4587 intel_de_posting_read(dev_priv, reg);
4588
4589 if (!enable)
4590 return;
4591
4592 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
4593 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC);
4594
4595 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
4596}
4597
4598static
4599int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
4600 const void *buffer, size_t size)
4601{
4602 const struct dp_sdp *sdp = buffer;
4603
4604 if (size < sizeof(struct dp_sdp))
4605 return -EINVAL;
4606
4607 memset(as_sdp, 0, sizeof(*as_sdp));
4608
4609 if (sdp->sdp_header.HB0 != 0)
4610 return -EINVAL;
4611
4612 if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)
4613 return -EINVAL;
4614
4615 if (sdp->sdp_header.HB2 != 0x02)
4616 return -EINVAL;
4617
4618 if ((sdp->sdp_header.HB3 & 0x3F) != 9)
4619 return -EINVAL;
4620
4621 as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH;
4622 as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;
4623 as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
4624 as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
4625 as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
4626
4627 return 0;
4628}
4629
4630static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
4631 const void *buffer, size_t size)
4632{
4633 const struct dp_sdp *sdp = buffer;
4634
4635 if (size < sizeof(struct dp_sdp))
4636 return -EINVAL;
4637
4638 memset(vsc, 0, sizeof(*vsc));
4639
4640 if (sdp->sdp_header.HB0 != 0)
4641 return -EINVAL;
4642
4643 if (sdp->sdp_header.HB1 != DP_SDP_VSC)
4644 return -EINVAL;
4645
4646 vsc->sdp_type = sdp->sdp_header.HB1;
4647 vsc->revision = sdp->sdp_header.HB2;
4648 vsc->length = sdp->sdp_header.HB3;
4649
4650 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
4651 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) ||
4652 (sdp->sdp_header.HB2 == 0x6 && sdp->sdp_header.HB3 == 0x10)) {
4653 /*
4654 * - HB2 = 0x2, HB3 = 0x8
4655 * VSC SDP supporting 3D stereo + PSR
4656 * - HB2 = 0x4, HB3 = 0xe
4657 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
4658 * first scan line of the SU region (applies to eDP v1.4b
4659 * and higher).
4660 * - HB2 = 0x6, HB3 = 0x10
4661 * VSC SDP supporting 3D stereo + Panel Replay.
4662 */
4663 return 0;
4664 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
4665 /*
4666 * - HB2 = 0x5, HB3 = 0x13
4667 * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
4668 * Format.
4669 */
4670 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
4671 vsc->colorimetry = sdp->db[16] & 0xf;
4672 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
4673
4674 switch (sdp->db[17] & 0x7) {
4675 case 0x0:
4676 vsc->bpc = 6;
4677 break;
4678 case 0x1:
4679 vsc->bpc = 8;
4680 break;
4681 case 0x2:
4682 vsc->bpc = 10;
4683 break;
4684 case 0x3:
4685 vsc->bpc = 12;
4686 break;
4687 case 0x4:
4688 vsc->bpc = 16;
4689 break;
4690 default:
4691 MISSING_CASE(sdp->db[17] & 0x7);
4692 return -EINVAL;
4693 }
4694
4695 vsc->content_type = sdp->db[18] & 0x7;
4696 } else {
4697 return -EINVAL;
4698 }
4699
4700 return 0;
4701}
4702
4703static void
4704intel_read_dp_as_sdp(struct intel_encoder *encoder,
4705 struct intel_crtc_state *crtc_state,
4706 struct drm_dp_as_sdp *as_sdp)
4707{
4708 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4709 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4710 unsigned int type = DP_SDP_ADAPTIVE_SYNC;
4711 struct dp_sdp sdp = {};
4712 int ret;
4713
4714 if ((crtc_state->infoframes.enable &
4715 intel_hdmi_infoframe_enable(type)) == 0)
4716 return;
4717
4718 dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
4719 sizeof(sdp));
4720
4721 ret = intel_dp_as_sdp_unpack(as_sdp, &sdp, sizeof(sdp));
4722 if (ret)
4723 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP AS SDP\n");
4724}
4725
4726static int
4727intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
4728 const void *buffer, size_t size)
4729{
4730 int ret;
4731
4732 const struct dp_sdp *sdp = buffer;
4733
4734 if (size < sizeof(struct dp_sdp))
4735 return -EINVAL;
4736
4737 if (sdp->sdp_header.HB0 != 0)
4738 return -EINVAL;
4739
4740 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
4741 return -EINVAL;
4742
4743 /*
4744 * Least Significant Eight Bits of (Data Byte Count – 1)
4745 * 1Dh (i.e., Data Byte Count = 30 bytes).
4746 */
4747 if (sdp->sdp_header.HB2 != 0x1D)
4748 return -EINVAL;
4749
4750 /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
4751 if ((sdp->sdp_header.HB3 & 0x3) != 0)
4752 return -EINVAL;
4753
4754 /* INFOFRAME SDP Version Number */
4755 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
4756 return -EINVAL;
4757
4758 /* CTA Header Byte 2 (INFOFRAME Version Number) */
4759 if (sdp->db[0] != 1)
4760 return -EINVAL;
4761
4762 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4763 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
4764 return -EINVAL;
4765
4766 ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
4767 HDMI_DRM_INFOFRAME_SIZE);
4768
4769 return ret;
4770}
4771
4772static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
4773 struct intel_crtc_state *crtc_state,
4774 struct drm_dp_vsc_sdp *vsc)
4775{
4776 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4777 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4778 unsigned int type = DP_SDP_VSC;
4779 struct dp_sdp sdp = {};
4780 int ret;
4781
4782 if ((crtc_state->infoframes.enable &
4783 intel_hdmi_infoframe_enable(type)) == 0)
4784 return;
4785
4786 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
4787
4788 ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
4789
4790 if (ret)
4791 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
4792}
4793
4794static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
4795 struct intel_crtc_state *crtc_state,
4796 struct hdmi_drm_infoframe *drm_infoframe)
4797{
4798 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4799 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4800 unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
4801 struct dp_sdp sdp = {};
4802 int ret;
4803
4804 if ((crtc_state->infoframes.enable &
4805 intel_hdmi_infoframe_enable(type)) == 0)
4806 return;
4807
4808 dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
4809 sizeof(sdp));
4810
4811 ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
4812 sizeof(sdp));
4813
4814 if (ret)
4815 drm_dbg_kms(&dev_priv->drm,
4816 "Failed to unpack DP HDR Metadata Infoframe SDP\n");
4817}
4818
4819void intel_read_dp_sdp(struct intel_encoder *encoder,
4820 struct intel_crtc_state *crtc_state,
4821 unsigned int type)
4822{
4823 switch (type) {
4824 case DP_SDP_VSC:
4825 intel_read_dp_vsc_sdp(encoder, crtc_state,
4826 &crtc_state->infoframes.vsc);
4827 break;
4828 case HDMI_PACKET_TYPE_GAMUT_METADATA:
4829 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
4830 &crtc_state->infoframes.drm.drm);
4831 break;
4832 case DP_SDP_ADAPTIVE_SYNC:
4833 intel_read_dp_as_sdp(encoder, crtc_state,
4834 &crtc_state->infoframes.as_sdp);
4835 break;
4836 default:
4837 MISSING_CASE(type);
4838 break;
4839 }
4840}
4841
4842static bool intel_dp_link_ok(struct intel_dp *intel_dp,
4843 u8 link_status[DP_LINK_STATUS_SIZE])
4844{
4845 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4846 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4847 bool uhbr = intel_dp->link_rate >= 1000000;
4848 bool ok;
4849
4850 if (uhbr)
4851 ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
4852 intel_dp->lane_count);
4853 else
4854 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4855
4856 if (ok)
4857 return true;
4858
4859 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
4860 drm_dbg_kms(&i915->drm,
4861 "[ENCODER:%d:%s] %s link not ok, retraining\n",
4862 encoder->base.base.id, encoder->base.name,
4863 uhbr ? "128b/132b" : "8b/10b");
4864
4865 return false;
4866}
4867
4868static void
4869intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
4870{
4871 bool handled = false;
4872
4873 drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled);
4874
4875 if (esi[1] & DP_CP_IRQ) {
4876 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4877 ack[1] |= DP_CP_IRQ;
4878 }
4879}
4880
4881static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
4882{
4883 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4884 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4885 u8 link_status[DP_LINK_STATUS_SIZE] = {};
4886 const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
4887
4888 if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
4889 esi_link_status_size) != esi_link_status_size) {
4890 drm_err(&i915->drm,
4891 "[ENCODER:%d:%s] Failed to read link status\n",
4892 encoder->base.base.id, encoder->base.name);
4893 return false;
4894 }
4895
4896 return intel_dp_link_ok(intel_dp, link_status);
4897}
4898
4899/**
4900 * intel_dp_check_mst_status - service any pending MST interrupts, check link status
4901 * @intel_dp: Intel DP struct
4902 *
4903 * Read any pending MST interrupts, call MST core to handle these and ack the
4904 * interrupts. Check if the main and AUX link state is ok.
4905 *
4906 * Returns:
4907 * - %true if pending interrupts were serviced (or no interrupts were
4908 * pending) w/o detecting an error condition.
4909 * - %false if an error condition - like AUX failure or a loss of link - is
4910 * detected, or another condition - like a DP tunnel BW state change - needs
4911 * servicing from the hotplug work.
4912 */
4913static bool
4914intel_dp_check_mst_status(struct intel_dp *intel_dp)
4915{
4916 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4917 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4918 struct intel_encoder *encoder = &dig_port->base;
4919 bool link_ok = true;
4920 bool reprobe_needed = false;
4921
4922 drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
4923
4924 for (;;) {
4925 u8 esi[4] = {};
4926 u8 ack[4] = {};
4927
4928 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
4929 drm_dbg_kms(&i915->drm,
4930 "failed to get ESI - device may have failed\n");
4931 link_ok = false;
4932
4933 break;
4934 }
4935
4936 drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
4937
4938 if (intel_dp->active_mst_links > 0 && link_ok &&
4939 esi[3] & LINK_STATUS_CHANGED) {
4940 if (!intel_dp_mst_link_status(intel_dp))
4941 link_ok = false;
4942 ack[3] |= LINK_STATUS_CHANGED;
4943 }
4944
4945 intel_dp_mst_hpd_irq(intel_dp, esi, ack);
4946
4947 if (esi[3] & DP_TUNNELING_IRQ) {
4948 if (drm_dp_tunnel_handle_irq(i915->display.dp_tunnel_mgr,
4949 &intel_dp->aux))
4950 reprobe_needed = true;
4951 ack[3] |= DP_TUNNELING_IRQ;
4952 }
4953
4954 if (mem_is_zero(ack, sizeof(ack)))
4955 break;
4956
4957 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
4958 drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
4959
4960 if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY))
4961 drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr);
4962 }
4963
4964 if (!link_ok || intel_dp->link.force_retrain)
4965 intel_encoder_link_check_queue_work(encoder, 0);
4966
4967 return !reprobe_needed;
4968}
4969
4970static void
4971intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
4972{
4973 bool is_active;
4974 u8 buf = 0;
4975
4976 is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
4977 if (intel_dp->frl.is_trained && !is_active) {
4978 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
4979 return;
4980
4981 buf &= ~DP_PCON_ENABLE_HDMI_LINK;
4982 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
4983 return;
4984
4985 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
4986
4987 intel_dp->frl.is_trained = false;
4988
4989 /* Restart FRL training or fall back to TMDS mode */
4990 intel_dp_check_frl_training(intel_dp);
4991 }
4992}
4993
4994static bool
4995intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4996{
4997 u8 link_status[DP_LINK_STATUS_SIZE];
4998
4999 if (!intel_dp->link_trained)
5000 return false;
5001
5002 /*
5003 * While PSR source HW is enabled, it will control main-link sending
5004 * frames, enabling and disabling it so trying to do a retrain will fail
5005 * as the link would or not be on or it could mix training patterns
5006 * and frame data at the same time causing retrain to fail.
5007 * Also when exiting PSR, HW will retrain the link anyways fixing
5008 * any link status error.
5009 */
5010 if (intel_psr_enabled(intel_dp))
5011 return false;
5012
5013 if (intel_dp->link.force_retrain)
5014 return true;
5015
5016 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
5017 link_status) < 0)
5018 return false;
5019
5020 /*
5021 * Validate the cached values of intel_dp->link_rate and
5022 * intel_dp->lane_count before attempting to retrain.
5023 *
5024 * FIXME would be nice to user the crtc state here, but since
5025 * we need to call this from the short HPD handler that seems
5026 * a bit hard.
5027 */
5028 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
5029 intel_dp->lane_count))
5030 return false;
5031
5032 if (intel_dp->link.retrain_disabled)
5033 return false;
5034
5035 if (intel_dp->link.seq_train_failures)
5036 return true;
5037
5038 /* Retrain if link not ok */
5039 return !intel_dp_link_ok(intel_dp, link_status) &&
5040 !intel_psr_link_ok(intel_dp);
5041}
5042
5043bool intel_dp_has_connector(struct intel_dp *intel_dp,
5044 const struct drm_connector_state *conn_state)
5045{
5046 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5047 struct intel_encoder *encoder;
5048 enum pipe pipe;
5049
5050 if (!conn_state->best_encoder)
5051 return false;
5052
5053 /* SST */
5054 encoder = &dp_to_dig_port(intel_dp)->base;
5055 if (conn_state->best_encoder == &encoder->base)
5056 return true;
5057
5058 /* MST */
5059 for_each_pipe(i915, pipe) {
5060 encoder = &intel_dp->mst_encoders[pipe]->base;
5061 if (conn_state->best_encoder == &encoder->base)
5062 return true;
5063 }
5064
5065 return false;
5066}
5067
5068static void wait_for_connector_hw_done(const struct drm_connector_state *conn_state)
5069{
5070 struct intel_connector *connector = to_intel_connector(conn_state->connector);
5071 struct intel_display *display = to_intel_display(connector);
5072
5073 drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex);
5074
5075 if (!conn_state->commit)
5076 return;
5077
5078 drm_WARN_ON(display->drm,
5079 !wait_for_completion_timeout(&conn_state->commit->hw_done,
5080 msecs_to_jiffies(5000)));
5081}
5082
5083int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
5084 struct drm_modeset_acquire_ctx *ctx,
5085 u8 *pipe_mask)
5086{
5087 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5088 struct drm_connector_list_iter conn_iter;
5089 struct intel_connector *connector;
5090 int ret = 0;
5091
5092 *pipe_mask = 0;
5093
5094 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
5095 for_each_intel_connector_iter(connector, &conn_iter) {
5096 struct drm_connector_state *conn_state =
5097 connector->base.state;
5098 struct intel_crtc_state *crtc_state;
5099 struct intel_crtc *crtc;
5100
5101 if (!intel_dp_has_connector(intel_dp, conn_state))
5102 continue;
5103
5104 crtc = to_intel_crtc(conn_state->crtc);
5105 if (!crtc)
5106 continue;
5107
5108 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5109 if (ret)
5110 break;
5111
5112 crtc_state = to_intel_crtc_state(crtc->base.state);
5113
5114 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
5115
5116 if (!crtc_state->hw.active)
5117 continue;
5118
5119 wait_for_connector_hw_done(conn_state);
5120
5121 *pipe_mask |= BIT(crtc->pipe);
5122 }
5123 drm_connector_list_iter_end(&conn_iter);
5124
5125 return ret;
5126}
5127
5128void intel_dp_flush_connector_commits(struct intel_connector *connector)
5129{
5130 wait_for_connector_hw_done(connector->base.state);
5131}
5132
5133static bool intel_dp_is_connected(struct intel_dp *intel_dp)
5134{
5135 struct intel_connector *connector = intel_dp->attached_connector;
5136
5137 return connector->base.status == connector_status_connected ||
5138 intel_dp->is_mst;
5139}
5140
5141static int intel_dp_retrain_link(struct intel_encoder *encoder,
5142 struct drm_modeset_acquire_ctx *ctx)
5143{
5144 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5145 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5146 u8 pipe_mask;
5147 int ret;
5148
5149 if (!intel_dp_is_connected(intel_dp))
5150 return 0;
5151
5152 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5153 ctx);
5154 if (ret)
5155 return ret;
5156
5157 if (!intel_dp_needs_link_retrain(intel_dp))
5158 return 0;
5159
5160 ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);
5161 if (ret)
5162 return ret;
5163
5164 if (pipe_mask == 0)
5165 return 0;
5166
5167 if (!intel_dp_needs_link_retrain(intel_dp))
5168 return 0;
5169
5170 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link (forced %s)\n",
5171 encoder->base.base.id, encoder->base.name,
5172 str_yes_no(intel_dp->link.force_retrain));
5173
5174 ret = intel_modeset_commit_pipes(dev_priv, pipe_mask, ctx);
5175 if (ret == -EDEADLK)
5176 return ret;
5177
5178 intel_dp->link.force_retrain = false;
5179
5180 if (ret)
5181 drm_dbg_kms(&dev_priv->drm,
5182 "[ENCODER:%d:%s] link retraining failed: %pe\n",
5183 encoder->base.base.id, encoder->base.name,
5184 ERR_PTR(ret));
5185
5186 return ret;
5187}
5188
5189void intel_dp_link_check(struct intel_encoder *encoder)
5190{
5191 struct drm_modeset_acquire_ctx ctx;
5192 int ret;
5193
5194 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret)
5195 ret = intel_dp_retrain_link(encoder, &ctx);
5196}
5197
5198void intel_dp_check_link_state(struct intel_dp *intel_dp)
5199{
5200 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5201 struct intel_encoder *encoder = &dig_port->base;
5202
5203 if (!intel_dp_is_connected(intel_dp))
5204 return;
5205
5206 if (!intel_dp_needs_link_retrain(intel_dp))
5207 return;
5208
5209 intel_encoder_link_check_queue_work(encoder, 0);
5210}
5211
5212static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
5213{
5214 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5215 u8 val;
5216
5217 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5218 return;
5219
5220 if (drm_dp_dpcd_readb(&intel_dp->aux,
5221 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
5222 return;
5223
5224 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
5225
5226 if (val & DP_AUTOMATED_TEST_REQUEST)
5227 intel_dp_test_request(intel_dp);
5228
5229 if (val & DP_CP_IRQ)
5230 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5231
5232 if (val & DP_SINK_SPECIFIC_IRQ)
5233 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
5234}
5235
5236static bool intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
5237{
5238 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5239 bool reprobe_needed = false;
5240 u8 val;
5241
5242 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5243 return false;
5244
5245 if (drm_dp_dpcd_readb(&intel_dp->aux,
5246 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
5247 return false;
5248
5249 if ((val & DP_TUNNELING_IRQ) &&
5250 drm_dp_tunnel_handle_irq(i915->display.dp_tunnel_mgr,
5251 &intel_dp->aux))
5252 reprobe_needed = true;
5253
5254 if (drm_dp_dpcd_writeb(&intel_dp->aux,
5255 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
5256 return reprobe_needed;
5257
5258 if (val & HDMI_LINK_STATUS_CHANGED)
5259 intel_dp_handle_hdmi_link_status_change(intel_dp);
5260
5261 return reprobe_needed;
5262}
5263
5264/*
5265 * According to DP spec
5266 * 5.1.2:
5267 * 1. Read DPCD
5268 * 2. Configure link according to Receiver Capabilities
5269 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
5270 * 4. Check link status on receipt of hot-plug interrupt
5271 *
5272 * intel_dp_short_pulse - handles short pulse interrupts
5273 * when full detection is not required.
5274 * Returns %true if short pulse is handled and full detection
5275 * is NOT required and %false otherwise.
5276 */
5277static bool
5278intel_dp_short_pulse(struct intel_dp *intel_dp)
5279{
5280 u8 old_sink_count = intel_dp->sink_count;
5281 bool reprobe_needed = false;
5282 bool ret;
5283
5284 intel_dp_test_reset(intel_dp);
5285
5286 /*
5287 * Now read the DPCD to see if it's actually running
5288 * If the current value of sink count doesn't match with
5289 * the value that was stored earlier or dpcd read failed
5290 * we need to do full detection
5291 */
5292 ret = intel_dp_get_dpcd(intel_dp);
5293
5294 if ((old_sink_count != intel_dp->sink_count) || !ret) {
5295 /* No need to proceed if we are going to do full detect */
5296 return false;
5297 }
5298
5299 intel_dp_check_device_service_irq(intel_dp);
5300 reprobe_needed = intel_dp_check_link_service_irq(intel_dp);
5301
5302 /* Handle CEC interrupts, if any */
5303 drm_dp_cec_irq(&intel_dp->aux);
5304
5305 intel_dp_check_link_state(intel_dp);
5306
5307 intel_psr_short_pulse(intel_dp);
5308
5309 if (intel_dp_test_short_pulse(intel_dp))
5310 reprobe_needed = true;
5311
5312 return !reprobe_needed;
5313}
5314
5315/* XXX this is probably wrong for multiple downstream ports */
5316static enum drm_connector_status
5317intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5318{
5319 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5320 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5321 u8 *dpcd = intel_dp->dpcd;
5322 u8 type;
5323
5324 if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
5325 return connector_status_connected;
5326
5327 lspcon_resume(dig_port);
5328
5329 if (!intel_dp_get_dpcd(intel_dp))
5330 return connector_status_disconnected;
5331
5332 intel_dp->mst_detect = intel_dp_mst_detect(intel_dp);
5333
5334 /* if there's no downstream port, we're done */
5335 if (!drm_dp_is_branch(dpcd))
5336 return connector_status_connected;
5337
5338 /* If we're HPD-aware, SINK_COUNT changes dynamically */
5339 if (intel_dp_has_sink_count(intel_dp) &&
5340 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5341 return intel_dp->sink_count ?
5342 connector_status_connected : connector_status_disconnected;
5343 }
5344
5345 if (intel_dp->mst_detect == DRM_DP_MST)
5346 return connector_status_connected;
5347
5348 /* If no HPD, poke DDC gently */
5349 if (drm_probe_ddc(&intel_dp->aux.ddc))
5350 return connector_status_connected;
5351
5352 /* Well we tried, say unknown for unreliable port types */
5353 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5354 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5355 if (type == DP_DS_PORT_TYPE_VGA ||
5356 type == DP_DS_PORT_TYPE_NON_EDID)
5357 return connector_status_unknown;
5358 } else {
5359 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5360 DP_DWN_STRM_PORT_TYPE_MASK;
5361 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5362 type == DP_DWN_STRM_PORT_TYPE_OTHER)
5363 return connector_status_unknown;
5364 }
5365
5366 /* Anything else is out of spec, warn and ignore */
5367 drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
5368 return connector_status_disconnected;
5369}
5370
5371static enum drm_connector_status
5372edp_detect(struct intel_dp *intel_dp)
5373{
5374 return connector_status_connected;
5375}
5376
5377void intel_digital_port_lock(struct intel_encoder *encoder)
5378{
5379 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5380
5381 if (dig_port->lock)
5382 dig_port->lock(dig_port);
5383}
5384
5385void intel_digital_port_unlock(struct intel_encoder *encoder)
5386{
5387 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5388
5389 if (dig_port->unlock)
5390 dig_port->unlock(dig_port);
5391}
5392
5393/*
5394 * intel_digital_port_connected_locked - is the specified port connected?
5395 * @encoder: intel_encoder
5396 *
5397 * In cases where there's a connector physically connected but it can't be used
5398 * by our hardware we also return false, since the rest of the driver should
5399 * pretty much treat the port as disconnected. This is relevant for type-C
5400 * (starting on ICL) where there's ownership involved.
5401 *
5402 * The caller must hold the lock acquired by calling intel_digital_port_lock()
5403 * when calling this function.
5404 *
5405 * Return %true if port is connected, %false otherwise.
5406 */
5407bool intel_digital_port_connected_locked(struct intel_encoder *encoder)
5408{
5409 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5410 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5411 bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port);
5412 bool is_connected = false;
5413 intel_wakeref_t wakeref;
5414
5415 with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref) {
5416 unsigned long wait_expires = jiffies + msecs_to_jiffies_timeout(4);
5417
5418 do {
5419 is_connected = dig_port->connected(encoder);
5420 if (is_connected || is_glitch_free)
5421 break;
5422 usleep_range(10, 30);
5423 } while (time_before(jiffies, wait_expires));
5424 }
5425
5426 return is_connected;
5427}
5428
5429bool intel_digital_port_connected(struct intel_encoder *encoder)
5430{
5431 bool ret;
5432
5433 intel_digital_port_lock(encoder);
5434 ret = intel_digital_port_connected_locked(encoder);
5435 intel_digital_port_unlock(encoder);
5436
5437 return ret;
5438}
5439
5440static const struct drm_edid *
5441intel_dp_get_edid(struct intel_dp *intel_dp)
5442{
5443 struct intel_connector *connector = intel_dp->attached_connector;
5444 const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
5445
5446 /* Use panel fixed edid if we have one */
5447 if (fixed_edid) {
5448 /* invalid edid */
5449 if (IS_ERR(fixed_edid))
5450 return NULL;
5451
5452 return drm_edid_dup(fixed_edid);
5453 }
5454
5455 return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc);
5456}
5457
5458static void
5459intel_dp_update_dfp(struct intel_dp *intel_dp,
5460 const struct drm_edid *drm_edid)
5461{
5462 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5463 struct intel_connector *connector = intel_dp->attached_connector;
5464
5465 intel_dp->dfp.max_bpc =
5466 drm_dp_downstream_max_bpc(intel_dp->dpcd,
5467 intel_dp->downstream_ports, drm_edid);
5468
5469 intel_dp->dfp.max_dotclock =
5470 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
5471 intel_dp->downstream_ports);
5472
5473 intel_dp->dfp.min_tmds_clock =
5474 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
5475 intel_dp->downstream_ports,
5476 drm_edid);
5477 intel_dp->dfp.max_tmds_clock =
5478 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
5479 intel_dp->downstream_ports,
5480 drm_edid);
5481
5482 intel_dp->dfp.pcon_max_frl_bw =
5483 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
5484 intel_dp->downstream_ports);
5485
5486 drm_dbg_kms(&i915->drm,
5487 "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
5488 connector->base.base.id, connector->base.name,
5489 intel_dp->dfp.max_bpc,
5490 intel_dp->dfp.max_dotclock,
5491 intel_dp->dfp.min_tmds_clock,
5492 intel_dp->dfp.max_tmds_clock,
5493 intel_dp->dfp.pcon_max_frl_bw);
5494
5495 intel_dp_get_pcon_dsc_cap(intel_dp);
5496}
5497
5498static bool
5499intel_dp_can_ycbcr420(struct intel_dp *intel_dp)
5500{
5501 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) &&
5502 (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))
5503 return true;
5504
5505 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&
5506 dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
5507 return true;
5508
5509 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) &&
5510 dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
5511 return true;
5512
5513 return false;
5514}
5515
5516static void
5517intel_dp_update_420(struct intel_dp *intel_dp)
5518{
5519 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5520 struct intel_connector *connector = intel_dp->attached_connector;
5521
5522 intel_dp->dfp.ycbcr420_passthrough =
5523 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
5524 intel_dp->downstream_ports);
5525 /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
5526 intel_dp->dfp.ycbcr_444_to_420 =
5527 dp_to_dig_port(intel_dp)->lspcon.active ||
5528 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
5529 intel_dp->downstream_ports);
5530 intel_dp->dfp.rgb_to_ycbcr =
5531 drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
5532 intel_dp->downstream_ports,
5533 DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
5534
5535 connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);
5536
5537 drm_dbg_kms(&i915->drm,
5538 "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
5539 connector->base.base.id, connector->base.name,
5540 str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
5541 str_yes_no(connector->base.ycbcr_420_allowed),
5542 str_yes_no(intel_dp->dfp.ycbcr_444_to_420));
5543}
5544
5545static void
5546intel_dp_set_edid(struct intel_dp *intel_dp)
5547{
5548 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5549 struct intel_connector *connector = intel_dp->attached_connector;
5550 const struct drm_edid *drm_edid;
5551 bool vrr_capable;
5552
5553 intel_dp_unset_edid(intel_dp);
5554 drm_edid = intel_dp_get_edid(intel_dp);
5555 connector->detect_edid = drm_edid;
5556
5557 /* Below we depend on display info having been updated */
5558 drm_edid_connector_update(&connector->base, drm_edid);
5559
5560 vrr_capable = intel_vrr_is_capable(connector);
5561 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
5562 connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
5563 drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
5564
5565 intel_dp_update_dfp(intel_dp, drm_edid);
5566 intel_dp_update_420(intel_dp);
5567
5568 drm_dp_cec_attach(&intel_dp->aux,
5569 connector->base.display_info.source_physical_address);
5570}
5571
5572static void
5573intel_dp_unset_edid(struct intel_dp *intel_dp)
5574{
5575 struct intel_connector *connector = intel_dp->attached_connector;
5576
5577 drm_dp_cec_unset_edid(&intel_dp->aux);
5578 drm_edid_free(connector->detect_edid);
5579 connector->detect_edid = NULL;
5580
5581 intel_dp->dfp.max_bpc = 0;
5582 intel_dp->dfp.max_dotclock = 0;
5583 intel_dp->dfp.min_tmds_clock = 0;
5584 intel_dp->dfp.max_tmds_clock = 0;
5585
5586 intel_dp->dfp.pcon_max_frl_bw = 0;
5587
5588 intel_dp->dfp.ycbcr_444_to_420 = false;
5589 connector->base.ycbcr_420_allowed = false;
5590
5591 drm_connector_set_vrr_capable_property(&connector->base,
5592 false);
5593}
5594
5595static void
5596intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
5597{
5598 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5599
5600 intel_dp->as_sdp_supported = HAS_AS_SDP(i915) &&
5601 drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
5602}
5603
5604static int
5605intel_dp_detect(struct drm_connector *connector,
5606 struct drm_modeset_acquire_ctx *ctx,
5607 bool force)
5608{
5609 struct drm_i915_private *dev_priv = to_i915(connector->dev);
5610 struct intel_connector *intel_connector =
5611 to_intel_connector(connector);
5612 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5613 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5614 struct intel_encoder *encoder = &dig_port->base;
5615 enum drm_connector_status status;
5616 int ret;
5617
5618 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5619 connector->base.id, connector->name);
5620 drm_WARN_ON(&dev_priv->drm,
5621 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5622
5623 if (!intel_display_device_enabled(dev_priv))
5624 return connector_status_disconnected;
5625
5626 if (!intel_display_driver_check_access(dev_priv))
5627 return connector->status;
5628
5629 intel_dp_flush_connector_commits(intel_connector);
5630
5631 intel_pps_vdd_on(intel_dp);
5632
5633 /* Can't disconnect eDP */
5634 if (intel_dp_is_edp(intel_dp))
5635 status = edp_detect(intel_dp);
5636 else if (intel_digital_port_connected(encoder))
5637 status = intel_dp_detect_dpcd(intel_dp);
5638 else
5639 status = connector_status_disconnected;
5640
5641 if (status != connector_status_disconnected &&
5642 !intel_dp_mst_verify_dpcd_state(intel_dp))
5643 /*
5644 * This requires retrying detection for instance to re-enable
5645 * the MST mode that got reset via a long HPD pulse. The retry
5646 * will happen either via the hotplug handler's retry logic,
5647 * ensured by setting the connector here to SST/disconnected,
5648 * or via a userspace connector probing in response to the
5649 * hotplug uevent sent when removing the MST connectors.
5650 */
5651 status = connector_status_disconnected;
5652
5653 if (status == connector_status_disconnected) {
5654 intel_dp_test_reset(intel_dp);
5655 memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd));
5656 intel_dp->psr.sink_panel_replay_support = false;
5657 intel_dp->psr.sink_panel_replay_su_support = false;
5658
5659 intel_dp_mst_disconnect(intel_dp);
5660
5661 intel_dp_tunnel_disconnect(intel_dp);
5662
5663 goto out_unset_edid;
5664 }
5665
5666 intel_dp_init_source_oui(intel_dp);
5667
5668 ret = intel_dp_tunnel_detect(intel_dp, ctx);
5669 if (ret == -EDEADLK) {
5670 status = ret;
5671
5672 goto out_vdd_off;
5673 }
5674
5675 if (ret == 1)
5676 intel_connector->base.epoch_counter++;
5677
5678 if (!intel_dp_is_edp(intel_dp))
5679 intel_psr_init_dpcd(intel_dp);
5680
5681 intel_dp_detect_dsc_caps(intel_dp, intel_connector);
5682
5683 intel_dp_detect_sdp_caps(intel_dp);
5684
5685 if (intel_dp->reset_link_params) {
5686 intel_dp_reset_link_params(intel_dp);
5687 intel_dp->reset_link_params = false;
5688 }
5689
5690 intel_dp_mst_configure(intel_dp);
5691
5692 intel_dp_print_rates(intel_dp);
5693
5694 if (intel_dp->is_mst) {
5695 /*
5696 * If we are in MST mode then this connector
5697 * won't appear connected or have anything
5698 * with EDID on it
5699 */
5700 status = connector_status_disconnected;
5701 goto out_unset_edid;
5702 }
5703
5704 /*
5705 * Some external monitors do not signal loss of link synchronization
5706 * with an IRQ_HPD, so force a link status check.
5707 *
5708 * TODO: this probably became redundant, so remove it: the link state
5709 * is rechecked/recovered now after modesets, where the loss of
5710 * synchronization tends to occur.
5711 */
5712 if (!intel_dp_is_edp(intel_dp))
5713 intel_dp_check_link_state(intel_dp);
5714
5715 /*
5716 * Clearing NACK and defer counts to get their exact values
5717 * while reading EDID which are required by Compliance tests
5718 * 4.2.2.4 and 4.2.2.5
5719 */
5720 intel_dp->aux.i2c_nack_count = 0;
5721 intel_dp->aux.i2c_defer_count = 0;
5722
5723 intel_dp_set_edid(intel_dp);
5724 if (intel_dp_is_edp(intel_dp) ||
5725 to_intel_connector(connector)->detect_edid)
5726 status = connector_status_connected;
5727
5728 intel_dp_check_device_service_irq(intel_dp);
5729
5730out_unset_edid:
5731 if (status != connector_status_connected && !intel_dp->is_mst)
5732 intel_dp_unset_edid(intel_dp);
5733
5734 if (!intel_dp_is_edp(intel_dp))
5735 drm_dp_set_subconnector_property(connector,
5736 status,
5737 intel_dp->dpcd,
5738 intel_dp->downstream_ports);
5739out_vdd_off:
5740 intel_pps_vdd_off(intel_dp);
5741
5742 return status;
5743}
5744
5745static void
5746intel_dp_force(struct drm_connector *connector)
5747{
5748 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5749 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5750 struct intel_encoder *intel_encoder = &dig_port->base;
5751 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5752
5753 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5754 connector->base.id, connector->name);
5755
5756 if (!intel_display_driver_check_access(dev_priv))
5757 return;
5758
5759 intel_dp_unset_edid(intel_dp);
5760
5761 if (connector->status != connector_status_connected)
5762 return;
5763
5764 intel_dp_set_edid(intel_dp);
5765}
5766
5767static int intel_dp_get_modes(struct drm_connector *connector)
5768{
5769 struct intel_connector *intel_connector = to_intel_connector(connector);
5770 int num_modes;
5771
5772 /* drm_edid_connector_update() done in ->detect() or ->force() */
5773 num_modes = drm_edid_connector_add_modes(connector);
5774
5775 /* Also add fixed mode, which may or may not be present in EDID */
5776 if (intel_dp_is_edp(intel_attached_dp(intel_connector)))
5777 num_modes += intel_panel_get_modes(intel_connector);
5778
5779 if (num_modes)
5780 return num_modes;
5781
5782 if (!intel_connector->detect_edid) {
5783 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5784 struct drm_display_mode *mode;
5785
5786 mode = drm_dp_downstream_mode(connector->dev,
5787 intel_dp->dpcd,
5788 intel_dp->downstream_ports);
5789 if (mode) {
5790 drm_mode_probed_add(connector, mode);
5791 num_modes++;
5792 }
5793 }
5794
5795 return num_modes;
5796}
5797
5798static int
5799intel_dp_connector_register(struct drm_connector *connector)
5800{
5801 struct drm_i915_private *i915 = to_i915(connector->dev);
5802 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5803 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5804 struct intel_lspcon *lspcon = &dig_port->lspcon;
5805 int ret;
5806
5807 ret = intel_connector_register(connector);
5808 if (ret)
5809 return ret;
5810
5811 drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
5812 intel_dp->aux.name, connector->kdev->kobj.name);
5813
5814 intel_dp->aux.dev = connector->kdev;
5815 ret = drm_dp_aux_register(&intel_dp->aux);
5816 if (!ret)
5817 drm_dp_cec_register_connector(&intel_dp->aux, connector);
5818
5819 if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata))
5820 return ret;
5821
5822 /*
5823 * ToDo: Clean this up to handle lspcon init and resume more
5824 * efficiently and streamlined.
5825 */
5826 if (lspcon_init(dig_port)) {
5827 lspcon_detect_hdr_capability(lspcon);
5828 if (lspcon->hdr_supported)
5829 drm_connector_attach_hdr_output_metadata_property(connector);
5830 }
5831
5832 return ret;
5833}
5834
5835static void
5836intel_dp_connector_unregister(struct drm_connector *connector)
5837{
5838 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5839
5840 drm_dp_cec_unregister_connector(&intel_dp->aux);
5841 drm_dp_aux_unregister(&intel_dp->aux);
5842 intel_connector_unregister(connector);
5843}
5844
5845void intel_dp_connector_sync_state(struct intel_connector *connector,
5846 const struct intel_crtc_state *crtc_state)
5847{
5848 struct drm_i915_private *i915 = to_i915(connector->base.dev);
5849
5850 if (crtc_state && crtc_state->dsc.compression_enable) {
5851 drm_WARN_ON(&i915->drm, !connector->dp.dsc_decompression_aux);
5852 connector->dp.dsc_decompression_enabled = true;
5853 } else {
5854 connector->dp.dsc_decompression_enabled = false;
5855 }
5856}
5857
5858void intel_dp_encoder_flush_work(struct drm_encoder *_encoder)
5859{
5860 struct intel_encoder *encoder = to_intel_encoder(_encoder);
5861 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5862 struct intel_dp *intel_dp = &dig_port->dp;
5863
5864 intel_encoder_link_check_flush_work(encoder);
5865
5866 intel_dp_mst_encoder_cleanup(dig_port);
5867
5868 intel_dp_tunnel_destroy(intel_dp);
5869
5870 intel_pps_vdd_off_sync(intel_dp);
5871
5872 /*
5873 * Ensure power off delay is respected on module remove, so that we can
5874 * reduce delays at driver probe. See pps_init_timestamps().
5875 */
5876 intel_pps_wait_power_cycle(intel_dp);
5877
5878 intel_dp_aux_fini(intel_dp);
5879}
5880
5881void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5882{
5883 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5884
5885 intel_pps_vdd_off_sync(intel_dp);
5886
5887 intel_dp_tunnel_suspend(intel_dp);
5888}
5889
5890void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
5891{
5892 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5893
5894 intel_pps_wait_power_cycle(intel_dp);
5895}
5896
5897static int intel_modeset_tile_group(struct intel_atomic_state *state,
5898 int tile_group_id)
5899{
5900 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5901 struct drm_connector_list_iter conn_iter;
5902 struct drm_connector *connector;
5903 int ret = 0;
5904
5905 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
5906 drm_for_each_connector_iter(connector, &conn_iter) {
5907 struct drm_connector_state *conn_state;
5908 struct intel_crtc_state *crtc_state;
5909 struct intel_crtc *crtc;
5910
5911 if (!connector->has_tile ||
5912 connector->tile_group->id != tile_group_id)
5913 continue;
5914
5915 conn_state = drm_atomic_get_connector_state(&state->base,
5916 connector);
5917 if (IS_ERR(conn_state)) {
5918 ret = PTR_ERR(conn_state);
5919 break;
5920 }
5921
5922 crtc = to_intel_crtc(conn_state->crtc);
5923
5924 if (!crtc)
5925 continue;
5926
5927 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
5928 crtc_state->uapi.mode_changed = true;
5929
5930 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5931 if (ret)
5932 break;
5933 }
5934 drm_connector_list_iter_end(&conn_iter);
5935
5936 return ret;
5937}
5938
5939static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
5940{
5941 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5942 struct intel_crtc *crtc;
5943
5944 if (transcoders == 0)
5945 return 0;
5946
5947 for_each_intel_crtc(&dev_priv->drm, crtc) {
5948 struct intel_crtc_state *crtc_state;
5949 int ret;
5950
5951 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5952 if (IS_ERR(crtc_state))
5953 return PTR_ERR(crtc_state);
5954
5955 if (!crtc_state->hw.enable)
5956 continue;
5957
5958 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
5959 continue;
5960
5961 crtc_state->uapi.mode_changed = true;
5962
5963 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
5964 if (ret)
5965 return ret;
5966
5967 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5968 if (ret)
5969 return ret;
5970
5971 transcoders &= ~BIT(crtc_state->cpu_transcoder);
5972 }
5973
5974 drm_WARN_ON(&dev_priv->drm, transcoders != 0);
5975
5976 return 0;
5977}
5978
5979static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
5980 struct drm_connector *connector)
5981{
5982 const struct drm_connector_state *old_conn_state =
5983 drm_atomic_get_old_connector_state(&state->base, connector);
5984 const struct intel_crtc_state *old_crtc_state;
5985 struct intel_crtc *crtc;
5986 u8 transcoders;
5987
5988 crtc = to_intel_crtc(old_conn_state->crtc);
5989 if (!crtc)
5990 return 0;
5991
5992 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
5993
5994 if (!old_crtc_state->hw.active)
5995 return 0;
5996
5997 transcoders = old_crtc_state->sync_mode_slaves_mask;
5998 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
5999 transcoders |= BIT(old_crtc_state->master_transcoder);
6000
6001 return intel_modeset_affected_transcoders(state,
6002 transcoders);
6003}
6004
6005static int intel_dp_connector_atomic_check(struct drm_connector *conn,
6006 struct drm_atomic_state *_state)
6007{
6008 struct drm_i915_private *dev_priv = to_i915(conn->dev);
6009 struct intel_atomic_state *state = to_intel_atomic_state(_state);
6010 struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn);
6011 struct intel_connector *intel_conn = to_intel_connector(conn);
6012 struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder);
6013 int ret;
6014
6015 ret = intel_digital_connector_atomic_check(conn, &state->base);
6016 if (ret)
6017 return ret;
6018
6019 if (intel_dp_mst_source_support(intel_dp)) {
6020 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr);
6021 if (ret)
6022 return ret;
6023 }
6024
6025 if (!intel_connector_needs_modeset(state, conn))
6026 return 0;
6027
6028 ret = intel_dp_tunnel_atomic_check_state(state,
6029 intel_dp,
6030 intel_conn);
6031 if (ret)
6032 return ret;
6033
6034 /*
6035 * We don't enable port sync on BDW due to missing w/as and
6036 * due to not having adjusted the modeset sequence appropriately.
6037 */
6038 if (DISPLAY_VER(dev_priv) < 9)
6039 return 0;
6040
6041 if (conn->has_tile) {
6042 ret = intel_modeset_tile_group(state, conn->tile_group->id);
6043 if (ret)
6044 return ret;
6045 }
6046
6047 return intel_modeset_synced_crtcs(state, conn);
6048}
6049
6050static void intel_dp_oob_hotplug_event(struct drm_connector *connector,
6051 enum drm_connector_status hpd_state)
6052{
6053 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
6054 struct drm_i915_private *i915 = to_i915(connector->dev);
6055 bool hpd_high = hpd_state == connector_status_connected;
6056 unsigned int hpd_pin = encoder->hpd_pin;
6057 bool need_work = false;
6058
6059 spin_lock_irq(&i915->irq_lock);
6060 if (hpd_high != test_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state)) {
6061 i915->display.hotplug.event_bits |= BIT(hpd_pin);
6062
6063 __assign_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state, hpd_high);
6064 need_work = true;
6065 }
6066 spin_unlock_irq(&i915->irq_lock);
6067
6068 if (need_work)
6069 intel_hpd_schedule_detection(i915);
6070}
6071
6072static const struct drm_connector_funcs intel_dp_connector_funcs = {
6073 .force = intel_dp_force,
6074 .fill_modes = drm_helper_probe_single_connector_modes,
6075 .atomic_get_property = intel_digital_connector_atomic_get_property,
6076 .atomic_set_property = intel_digital_connector_atomic_set_property,
6077 .late_register = intel_dp_connector_register,
6078 .early_unregister = intel_dp_connector_unregister,
6079 .destroy = intel_connector_destroy,
6080 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6081 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
6082 .oob_hotplug_event = intel_dp_oob_hotplug_event,
6083};
6084
6085static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6086 .detect_ctx = intel_dp_detect,
6087 .get_modes = intel_dp_get_modes,
6088 .mode_valid = intel_dp_mode_valid,
6089 .atomic_check = intel_dp_connector_atomic_check,
6090};
6091
6092enum irqreturn
6093intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
6094{
6095 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
6096 struct intel_dp *intel_dp = &dig_port->dp;
6097 u8 dpcd[DP_RECEIVER_CAP_SIZE];
6098
6099 if (dig_port->base.type == INTEL_OUTPUT_EDP &&
6100 (long_hpd ||
6101 intel_runtime_pm_suspended(&i915->runtime_pm) ||
6102 !intel_pps_have_panel_power_or_vdd(intel_dp))) {
6103 /*
6104 * vdd off can generate a long/short pulse on eDP which
6105 * would require vdd on to handle it, and thus we
6106 * would end up in an endless cycle of
6107 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
6108 */
6109 drm_dbg_kms(&i915->drm,
6110 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
6111 long_hpd ? "long" : "short",
6112 dig_port->base.base.base.id,
6113 dig_port->base.base.name);
6114 return IRQ_HANDLED;
6115 }
6116
6117 drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
6118 dig_port->base.base.base.id,
6119 dig_port->base.base.name,
6120 long_hpd ? "long" : "short");
6121
6122 /*
6123 * TBT DP tunnels require the GFX driver to read out the DPRX caps in
6124 * response to long HPD pulses. The DP hotplug handler does that,
6125 * however the hotplug handler may be blocked by another
6126 * connector's/encoder's hotplug handler. Since the TBT CM may not
6127 * complete the DP tunnel BW request for the latter connector/encoder
6128 * waiting for this encoder's DPRX read, perform a dummy read here.
6129 */
6130 if (long_hpd)
6131 intel_dp_read_dprx_caps(intel_dp, dpcd);
6132
6133 if (long_hpd) {
6134 intel_dp->reset_link_params = true;
6135 intel_dp_invalidate_source_oui(intel_dp);
6136
6137 return IRQ_NONE;
6138 }
6139
6140 if (intel_dp->is_mst) {
6141 if (!intel_dp_check_mst_status(intel_dp))
6142 return IRQ_NONE;
6143 } else if (!intel_dp_short_pulse(intel_dp)) {
6144 return IRQ_NONE;
6145 }
6146
6147 return IRQ_HANDLED;
6148}
6149
6150static bool _intel_dp_is_port_edp(struct drm_i915_private *dev_priv,
6151 const struct intel_bios_encoder_data *devdata,
6152 enum port port)
6153{
6154 /*
6155 * eDP not supported on g4x. so bail out early just
6156 * for a bit extra safety in case the VBT is bonkers.
6157 */
6158 if (DISPLAY_VER(dev_priv) < 5)
6159 return false;
6160
6161 if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
6162 return true;
6163
6164 return devdata && intel_bios_encoder_supports_edp(devdata);
6165}
6166
6167bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port)
6168{
6169 struct intel_display *display = &i915->display;
6170 const struct intel_bios_encoder_data *devdata =
6171 intel_bios_encoder_data_lookup(display, port);
6172
6173 return _intel_dp_is_port_edp(i915, devdata, port);
6174}
6175
6176bool
6177intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder)
6178{
6179 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
6180 enum port port = encoder->port;
6181
6182 if (intel_bios_encoder_is_lspcon(encoder->devdata))
6183 return false;
6184
6185 if (DISPLAY_VER(i915) >= 11)
6186 return true;
6187
6188 if (port == PORT_A)
6189 return false;
6190
6191 if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
6192 DISPLAY_VER(i915) >= 9)
6193 return true;
6194
6195 return false;
6196}
6197
6198static void
6199intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6200{
6201 struct drm_i915_private *dev_priv = to_i915(connector->dev);
6202 enum port port = dp_to_dig_port(intel_dp)->base.port;
6203
6204 if (!intel_dp_is_edp(intel_dp))
6205 drm_connector_attach_dp_subconnector_property(connector);
6206
6207 if (!IS_G4X(dev_priv) && port != PORT_A)
6208 intel_attach_force_audio_property(connector);
6209
6210 intel_attach_broadcast_rgb_property(connector);
6211 if (HAS_GMCH(dev_priv))
6212 drm_connector_attach_max_bpc_property(connector, 6, 10);
6213 else if (DISPLAY_VER(dev_priv) >= 5)
6214 drm_connector_attach_max_bpc_property(connector, 6, 12);
6215
6216 /* Register HDMI colorspace for case of lspcon */
6217 if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) {
6218 drm_connector_attach_content_type_property(connector);
6219 intel_attach_hdmi_colorspace_property(connector);
6220 } else {
6221 intel_attach_dp_colorspace_property(connector);
6222 }
6223
6224 if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
6225 drm_connector_attach_hdr_output_metadata_property(connector);
6226
6227 if (HAS_VRR(dev_priv))
6228 drm_connector_attach_vrr_capable_property(connector);
6229}
6230
6231static void
6232intel_edp_add_properties(struct intel_dp *intel_dp)
6233{
6234 struct intel_connector *connector = intel_dp->attached_connector;
6235 struct drm_i915_private *i915 = to_i915(connector->base.dev);
6236 const struct drm_display_mode *fixed_mode =
6237 intel_panel_preferred_fixed_mode(connector);
6238
6239 intel_attach_scaling_mode_property(&connector->base);
6240
6241 drm_connector_set_panel_orientation_with_quirk(&connector->base,
6242 i915->display.vbt.orientation,
6243 fixed_mode->hdisplay,
6244 fixed_mode->vdisplay);
6245}
6246
6247static void intel_edp_backlight_setup(struct intel_dp *intel_dp,
6248 struct intel_connector *connector)
6249{
6250 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6251 enum pipe pipe = INVALID_PIPE;
6252
6253 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
6254 pipe = vlv_pps_backlight_initial_pipe(intel_dp);
6255
6256 intel_backlight_setup(connector, pipe);
6257}
6258
6259static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6260 struct intel_connector *intel_connector)
6261{
6262 struct intel_display *display = to_intel_display(intel_dp);
6263 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6264 struct drm_connector *connector = &intel_connector->base;
6265 struct drm_display_mode *fixed_mode;
6266 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6267 bool has_dpcd;
6268 const struct drm_edid *drm_edid;
6269
6270 if (!intel_dp_is_edp(intel_dp))
6271 return true;
6272
6273 /*
6274 * On IBX/CPT we may get here with LVDS already registered. Since the
6275 * driver uses the only internal power sequencer available for both
6276 * eDP and LVDS bail out early in this case to prevent interfering
6277 * with an already powered-on LVDS power sequencer.
6278 */
6279 if (intel_get_lvds_encoder(dev_priv)) {
6280 drm_WARN_ON(&dev_priv->drm,
6281 !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6282 drm_info(&dev_priv->drm,
6283 "LVDS was detected, not registering eDP\n");
6284
6285 return false;
6286 }
6287
6288 intel_bios_init_panel_early(display, &intel_connector->panel,
6289 encoder->devdata);
6290
6291 if (!intel_pps_init(intel_dp)) {
6292 drm_info(&dev_priv->drm,
6293 "[ENCODER:%d:%s] unusable PPS, disabling eDP\n",
6294 encoder->base.base.id, encoder->base.name);
6295 /*
6296 * The BIOS may have still enabled VDD on the PPS even
6297 * though it's unusable. Make sure we turn it back off
6298 * and to release the power domain references/etc.
6299 */
6300 goto out_vdd_off;
6301 }
6302
6303 /*
6304 * Enable HPD sense for live status check.
6305 * intel_hpd_irq_setup() will turn it off again
6306 * if it's no longer needed later.
6307 *
6308 * The DPCD probe below will make sure VDD is on.
6309 */
6310 intel_hpd_enable_detection(encoder);
6311
6312 intel_alpm_init_dpcd(intel_dp);
6313
6314 /* Cache DPCD and EDID for edp. */
6315 has_dpcd = intel_edp_init_dpcd(intel_dp, intel_connector);
6316
6317 if (!has_dpcd) {
6318 /* if this fails, presume the device is a ghost */
6319 drm_info(&dev_priv->drm,
6320 "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n",
6321 encoder->base.base.id, encoder->base.name);
6322 goto out_vdd_off;
6323 }
6324
6325 /*
6326 * VBT and straps are liars. Also check HPD as that seems
6327 * to be the most reliable piece of information available.
6328 *
6329 * ... expect on devices that forgot to hook HPD up for eDP
6330 * (eg. Acer Chromebook C710), so we'll check it only if multiple
6331 * ports are attempting to use the same AUX CH, according to VBT.
6332 */
6333 if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) {
6334 /*
6335 * If this fails, presume the DPCD answer came
6336 * from some other port using the same AUX CH.
6337 *
6338 * FIXME maybe cleaner to check this before the
6339 * DPCD read? Would need sort out the VDD handling...
6340 */
6341 if (!intel_digital_port_connected(encoder)) {
6342 drm_info(&dev_priv->drm,
6343 "[ENCODER:%d:%s] HPD is down, disabling eDP\n",
6344 encoder->base.base.id, encoder->base.name);
6345 goto out_vdd_off;
6346 }
6347
6348 /*
6349 * Unfortunately even the HPD based detection fails on
6350 * eg. Asus B360M-A (CFL+CNP), so as a last resort fall
6351 * back to checking for a VGA branch device. Only do this
6352 * on known affected platforms to minimize false positives.
6353 */
6354 if (DISPLAY_VER(dev_priv) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&
6355 (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==
6356 DP_DWN_STRM_PORT_TYPE_ANALOG) {
6357 drm_info(&dev_priv->drm,
6358 "[ENCODER:%d:%s] VGA converter detected, disabling eDP\n",
6359 encoder->base.base.id, encoder->base.name);
6360 goto out_vdd_off;
6361 }
6362 }
6363
6364 mutex_lock(&dev_priv->drm.mode_config.mutex);
6365 drm_edid = drm_edid_read_ddc(connector, connector->ddc);
6366 if (!drm_edid) {
6367 /* Fallback to EDID from ACPI OpRegion, if any */
6368 drm_edid = intel_opregion_get_edid(intel_connector);
6369 if (drm_edid)
6370 drm_dbg_kms(&dev_priv->drm,
6371 "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
6372 connector->base.id, connector->name);
6373 }
6374 if (drm_edid) {
6375 if (drm_edid_connector_update(connector, drm_edid) ||
6376 !drm_edid_connector_add_modes(connector)) {
6377 drm_edid_connector_update(connector, NULL);
6378 drm_edid_free(drm_edid);
6379 drm_edid = ERR_PTR(-EINVAL);
6380 }
6381 } else {
6382 drm_edid = ERR_PTR(-ENOENT);
6383 }
6384
6385 intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata,
6386 IS_ERR(drm_edid) ? NULL : drm_edid);
6387
6388 intel_panel_add_edid_fixed_modes(intel_connector, true);
6389
6390 /* MSO requires information from the EDID */
6391 intel_edp_mso_init(intel_dp);
6392
6393 /* multiply the mode clock and horizontal timings for MSO */
6394 list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head)
6395 intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
6396
6397 /* fallback to VBT if available for eDP */
6398 if (!intel_panel_preferred_fixed_mode(intel_connector))
6399 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
6400
6401 mutex_unlock(&dev_priv->drm.mode_config.mutex);
6402
6403 if (!intel_panel_preferred_fixed_mode(intel_connector)) {
6404 drm_info(&dev_priv->drm,
6405 "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n",
6406 encoder->base.base.id, encoder->base.name);
6407 goto out_vdd_off;
6408 }
6409
6410 intel_panel_init(intel_connector, drm_edid);
6411
6412 intel_edp_backlight_setup(intel_dp, intel_connector);
6413
6414 intel_edp_add_properties(intel_dp);
6415
6416 intel_pps_init_late(intel_dp);
6417
6418 return true;
6419
6420out_vdd_off:
6421 intel_pps_vdd_off_sync(intel_dp);
6422 intel_bios_fini_panel(&intel_connector->panel);
6423
6424 return false;
6425}
6426
6427static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6428{
6429 struct intel_connector *intel_connector;
6430 struct drm_connector *connector;
6431
6432 intel_connector = container_of(work, typeof(*intel_connector),
6433 modeset_retry_work);
6434 connector = &intel_connector->base;
6435 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
6436 connector->name);
6437
6438 /* Grab the locks before changing connector property*/
6439 mutex_lock(&connector->dev->mode_config.mutex);
6440 /* Set connector link status to BAD and send a Uevent to notify
6441 * userspace to do a modeset.
6442 */
6443 drm_connector_set_link_status_property(connector,
6444 DRM_MODE_LINK_STATUS_BAD);
6445 mutex_unlock(&connector->dev->mode_config.mutex);
6446 /* Send Hotplug uevent so userspace can reprobe */
6447 drm_kms_helper_connector_hotplug_event(connector);
6448
6449 drm_connector_put(connector);
6450}
6451
6452void intel_dp_init_modeset_retry_work(struct intel_connector *connector)
6453{
6454 INIT_WORK(&connector->modeset_retry_work,
6455 intel_dp_modeset_retry_work_fn);
6456}
6457
6458bool
6459intel_dp_init_connector(struct intel_digital_port *dig_port,
6460 struct intel_connector *intel_connector)
6461{
6462 struct intel_display *display = to_intel_display(dig_port);
6463 struct drm_connector *connector = &intel_connector->base;
6464 struct intel_dp *intel_dp = &dig_port->dp;
6465 struct intel_encoder *intel_encoder = &dig_port->base;
6466 struct drm_device *dev = intel_encoder->base.dev;
6467 struct drm_i915_private *dev_priv = to_i915(dev);
6468 enum port port = intel_encoder->port;
6469 int type;
6470
6471 /* Initialize the work for modeset in case of link train failure */
6472 intel_dp_init_modeset_retry_work(intel_connector);
6473
6474 if (drm_WARN(dev, dig_port->max_lanes < 1,
6475 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
6476 dig_port->max_lanes, intel_encoder->base.base.id,
6477 intel_encoder->base.name))
6478 return false;
6479
6480 intel_dp->reset_link_params = true;
6481
6482 /* Preserve the current hw state. */
6483 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
6484 intel_dp->attached_connector = intel_connector;
6485
6486 if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
6487 /*
6488 * Currently we don't support eDP on TypeC ports for DISPLAY_VER < 30,
6489 * although in theory it could work on TypeC legacy ports.
6490 */
6491 drm_WARN_ON(dev, intel_encoder_is_tc(intel_encoder) &&
6492 DISPLAY_VER(dev_priv) < 30);
6493 type = DRM_MODE_CONNECTOR_eDP;
6494 intel_encoder->type = INTEL_OUTPUT_EDP;
6495
6496 /* eDP only on port B and/or C on vlv/chv */
6497 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
6498 IS_CHERRYVIEW(dev_priv)) &&
6499 port != PORT_B && port != PORT_C))
6500 return false;
6501 } else {
6502 type = DRM_MODE_CONNECTOR_DisplayPort;
6503 }
6504
6505 intel_dp_set_default_sink_rates(intel_dp);
6506 intel_dp_set_default_max_sink_lane_count(intel_dp);
6507
6508 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6509 vlv_pps_pipe_init(intel_dp);
6510
6511 intel_dp_aux_init(intel_dp);
6512 intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
6513
6514 drm_dbg_kms(&dev_priv->drm,
6515 "Adding %s connector on [ENCODER:%d:%s]\n",
6516 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6517 intel_encoder->base.base.id, intel_encoder->base.name);
6518
6519 drm_connector_init_with_ddc(dev, connector, &intel_dp_connector_funcs,
6520 type, &intel_dp->aux.ddc);
6521 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6522
6523 if (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) < 12)
6524 connector->interlace_allowed = true;
6525
6526 if (type != DRM_MODE_CONNECTOR_eDP)
6527 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
6528 intel_connector->base.polled = intel_connector->polled;
6529
6530 intel_connector_attach_encoder(intel_connector, intel_encoder);
6531
6532 if (HAS_DDI(dev_priv))
6533 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6534 else
6535 intel_connector->get_hw_state = intel_connector_get_hw_state;
6536 intel_connector->sync_state = intel_dp_connector_sync_state;
6537
6538 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6539 intel_dp_aux_fini(intel_dp);
6540 goto fail;
6541 }
6542
6543 intel_dp_set_source_rates(intel_dp);
6544 intel_dp_set_common_rates(intel_dp);
6545 intel_dp_reset_link_params(intel_dp);
6546
6547 /* init MST on ports that can support it */
6548 intel_dp_mst_encoder_init(dig_port,
6549 intel_connector->base.base.id);
6550
6551 intel_dp_add_properties(intel_dp, connector);
6552
6553 if (is_hdcp_supported(display, port) && !intel_dp_is_edp(intel_dp)) {
6554 int ret = intel_dp_hdcp_init(dig_port, intel_connector);
6555 if (ret)
6556 drm_dbg_kms(&dev_priv->drm,
6557 "HDCP init failed, skipping.\n");
6558 }
6559
6560 intel_dp->frl.is_trained = false;
6561 intel_dp->frl.trained_rate_gbps = 0;
6562
6563 intel_psr_init(intel_dp);
6564
6565 return true;
6566
6567fail:
6568 intel_display_power_flush_work(dev_priv);
6569 drm_connector_cleanup(connector);
6570
6571 return false;
6572}
6573
6574void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
6575{
6576 struct intel_encoder *encoder;
6577
6578 if (!HAS_DISPLAY(dev_priv))
6579 return;
6580
6581 for_each_intel_encoder(&dev_priv->drm, encoder) {
6582 struct intel_dp *intel_dp;
6583
6584 if (encoder->type != INTEL_OUTPUT_DDI)
6585 continue;
6586
6587 intel_dp = enc_to_intel_dp(encoder);
6588
6589 if (!intel_dp_mst_source_support(intel_dp))
6590 continue;
6591
6592 if (intel_dp->is_mst)
6593 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
6594 }
6595}
6596
6597void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
6598{
6599 struct intel_encoder *encoder;
6600
6601 if (!HAS_DISPLAY(dev_priv))
6602 return;
6603
6604 for_each_intel_encoder(&dev_priv->drm, encoder) {
6605 struct intel_dp *intel_dp;
6606 int ret;
6607
6608 if (encoder->type != INTEL_OUTPUT_DDI)
6609 continue;
6610
6611 intel_dp = enc_to_intel_dp(encoder);
6612
6613 if (!intel_dp_mst_source_support(intel_dp))
6614 continue;
6615
6616 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
6617 true);
6618 if (ret) {
6619 intel_dp->is_mst = false;
6620 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6621 false);
6622 }
6623 }
6624}
1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/export.h>
29#include <linux/i2c.h>
30#include <linux/notifier.h>
31#include <linux/slab.h>
32#include <linux/string_helpers.h>
33#include <linux/timekeeping.h>
34#include <linux/types.h>
35
36#include <asm/byteorder.h>
37
38#include <drm/display/drm_dp_helper.h>
39#include <drm/display/drm_dp_tunnel.h>
40#include <drm/display/drm_dsc_helper.h>
41#include <drm/display/drm_hdmi_helper.h>
42#include <drm/drm_atomic_helper.h>
43#include <drm/drm_crtc.h>
44#include <drm/drm_edid.h>
45#include <drm/drm_probe_helper.h>
46
47#include "g4x_dp.h"
48#include "i915_drv.h"
49#include "i915_irq.h"
50#include "i915_reg.h"
51#include "intel_atomic.h"
52#include "intel_audio.h"
53#include "intel_backlight.h"
54#include "intel_combo_phy_regs.h"
55#include "intel_connector.h"
56#include "intel_crtc.h"
57#include "intel_cx0_phy.h"
58#include "intel_ddi.h"
59#include "intel_de.h"
60#include "intel_display_driver.h"
61#include "intel_display_types.h"
62#include "intel_dp.h"
63#include "intel_dp_aux.h"
64#include "intel_dp_hdcp.h"
65#include "intel_dp_link_training.h"
66#include "intel_dp_mst.h"
67#include "intel_dp_tunnel.h"
68#include "intel_dpio_phy.h"
69#include "intel_dpll.h"
70#include "intel_drrs.h"
71#include "intel_fifo_underrun.h"
72#include "intel_hdcp.h"
73#include "intel_hdmi.h"
74#include "intel_hotplug.h"
75#include "intel_hotplug_irq.h"
76#include "intel_lspcon.h"
77#include "intel_lvds.h"
78#include "intel_panel.h"
79#include "intel_pch_display.h"
80#include "intel_pps.h"
81#include "intel_psr.h"
82#include "intel_tc.h"
83#include "intel_vdsc.h"
84#include "intel_vrr.h"
85#include "intel_crtc_state_dump.h"
86
87/* DP DSC throughput values used for slice count calculations KPixels/s */
88#define DP_DSC_PEAK_PIXEL_RATE 2720000
89#define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
90#define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
91
92/* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */
93#define DP_DSC_FEC_OVERHEAD_FACTOR 1028530
94
95/* Compliance test status bits */
96#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
97#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
98#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
99#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
100
101
102/* Constants for DP DSC configurations */
103static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
104
105/* With Single pipe configuration, HW is capable of supporting maximum
106 * of 4 slices per line.
107 */
108static const u8 valid_dsc_slicecount[] = {1, 2, 4};
109
110/**
111 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
112 * @intel_dp: DP struct
113 *
114 * If a CPU or PCH DP output is attached to an eDP panel, this function
115 * will return true, and false otherwise.
116 *
117 * This function is not safe to use prior to encoder type being set.
118 */
119bool intel_dp_is_edp(struct intel_dp *intel_dp)
120{
121 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
122
123 return dig_port->base.type == INTEL_OUTPUT_EDP;
124}
125
126static void intel_dp_unset_edid(struct intel_dp *intel_dp);
127
128/* Is link rate UHBR and thus 128b/132b? */
129bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
130{
131 return drm_dp_is_uhbr_rate(crtc_state->port_clock);
132}
133
134/**
135 * intel_dp_link_symbol_size - get the link symbol size for a given link rate
136 * @rate: link rate in 10kbit/s units
137 *
138 * Returns the link symbol size in bits/symbol units depending on the link
139 * rate -> channel coding.
140 */
141int intel_dp_link_symbol_size(int rate)
142{
143 return drm_dp_is_uhbr_rate(rate) ? 32 : 10;
144}
145
146/**
147 * intel_dp_link_symbol_clock - convert link rate to link symbol clock
148 * @rate: link rate in 10kbit/s units
149 *
150 * Returns the link symbol clock frequency in kHz units depending on the
151 * link rate and channel coding.
152 */
153int intel_dp_link_symbol_clock(int rate)
154{
155 return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate));
156}
157
158static int max_dprx_rate(struct intel_dp *intel_dp)
159{
160 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
161 return drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);
162
163 return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
164}
165
166static int max_dprx_lane_count(struct intel_dp *intel_dp)
167{
168 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
169 return drm_dp_tunnel_max_dprx_lane_count(intel_dp->tunnel);
170
171 return drm_dp_max_lane_count(intel_dp->dpcd);
172}
173
174static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
175{
176 intel_dp->sink_rates[0] = 162000;
177 intel_dp->num_sink_rates = 1;
178}
179
180/* update sink rates from dpcd */
181static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
182{
183 static const int dp_rates[] = {
184 162000, 270000, 540000, 810000
185 };
186 int i, max_rate;
187 int max_lttpr_rate;
188
189 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
190 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
191 static const int quirk_rates[] = { 162000, 270000, 324000 };
192
193 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
194 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
195
196 return;
197 }
198
199 /*
200 * Sink rates for 8b/10b.
201 */
202 max_rate = max_dprx_rate(intel_dp);
203 max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
204 if (max_lttpr_rate)
205 max_rate = min(max_rate, max_lttpr_rate);
206
207 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
208 if (dp_rates[i] > max_rate)
209 break;
210 intel_dp->sink_rates[i] = dp_rates[i];
211 }
212
213 /*
214 * Sink rates for 128b/132b. If set, sink should support all 8b/10b
215 * rates and 10 Gbps.
216 */
217 if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) {
218 u8 uhbr_rates = 0;
219
220 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
221
222 drm_dp_dpcd_readb(&intel_dp->aux,
223 DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
224
225 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
226 /* We have a repeater */
227 if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
228 intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
229 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
230 DP_PHY_REPEATER_128B132B_SUPPORTED) {
231 /* Repeater supports 128b/132b, valid UHBR rates */
232 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
233 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
234 } else {
235 /* Does not support 128b/132b */
236 uhbr_rates = 0;
237 }
238 }
239
240 if (uhbr_rates & DP_UHBR10)
241 intel_dp->sink_rates[i++] = 1000000;
242 if (uhbr_rates & DP_UHBR13_5)
243 intel_dp->sink_rates[i++] = 1350000;
244 if (uhbr_rates & DP_UHBR20)
245 intel_dp->sink_rates[i++] = 2000000;
246 }
247
248 intel_dp->num_sink_rates = i;
249}
250
251static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
252{
253 struct intel_connector *connector = intel_dp->attached_connector;
254 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
255 struct intel_encoder *encoder = &intel_dig_port->base;
256
257 intel_dp_set_dpcd_sink_rates(intel_dp);
258
259 if (intel_dp->num_sink_rates)
260 return;
261
262 drm_err(&dp_to_i915(intel_dp)->drm,
263 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
264 connector->base.base.id, connector->base.name,
265 encoder->base.base.id, encoder->base.name);
266
267 intel_dp_set_default_sink_rates(intel_dp);
268}
269
270static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
271{
272 intel_dp->max_sink_lane_count = 1;
273}
274
275static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
276{
277 struct intel_connector *connector = intel_dp->attached_connector;
278 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
279 struct intel_encoder *encoder = &intel_dig_port->base;
280
281 intel_dp->max_sink_lane_count = max_dprx_lane_count(intel_dp);
282
283 switch (intel_dp->max_sink_lane_count) {
284 case 1:
285 case 2:
286 case 4:
287 return;
288 }
289
290 drm_err(&dp_to_i915(intel_dp)->drm,
291 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
292 connector->base.base.id, connector->base.name,
293 encoder->base.base.id, encoder->base.name,
294 intel_dp->max_sink_lane_count);
295
296 intel_dp_set_default_max_sink_lane_count(intel_dp);
297}
298
299/* Get length of rates array potentially limited by max_rate. */
300static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
301{
302 int i;
303
304 /* Limit results by potentially reduced max rate */
305 for (i = 0; i < len; i++) {
306 if (rates[len - i - 1] <= max_rate)
307 return len - i;
308 }
309
310 return 0;
311}
312
313/* Get length of common rates array potentially limited by max_rate. */
314static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
315 int max_rate)
316{
317 return intel_dp_rate_limit_len(intel_dp->common_rates,
318 intel_dp->num_common_rates, max_rate);
319}
320
321static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
322{
323 if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
324 index < 0 || index >= intel_dp->num_common_rates))
325 return 162000;
326
327 return intel_dp->common_rates[index];
328}
329
330/* Theoretical max between source and sink */
331int intel_dp_max_common_rate(struct intel_dp *intel_dp)
332{
333 return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
334}
335
336static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
337{
338 int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata);
339 int max_lanes = dig_port->max_lanes;
340
341 if (vbt_max_lanes)
342 max_lanes = min(max_lanes, vbt_max_lanes);
343
344 return max_lanes;
345}
346
347/* Theoretical max between source and sink */
348int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
349{
350 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
351 int source_max = intel_dp_max_source_lane_count(dig_port);
352 int sink_max = intel_dp->max_sink_lane_count;
353 int lane_max = intel_tc_port_max_lane_count(dig_port);
354 int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
355
356 if (lttpr_max)
357 sink_max = min(sink_max, lttpr_max);
358
359 return min3(source_max, sink_max, lane_max);
360}
361
362int intel_dp_max_lane_count(struct intel_dp *intel_dp)
363{
364 switch (intel_dp->max_link_lane_count) {
365 case 1:
366 case 2:
367 case 4:
368 return intel_dp->max_link_lane_count;
369 default:
370 MISSING_CASE(intel_dp->max_link_lane_count);
371 return 1;
372 }
373}
374
375/*
376 * The required data bandwidth for a mode with given pixel clock and bpp. This
377 * is the required net bandwidth independent of the data bandwidth efficiency.
378 *
379 * TODO: check if callers of this functions should use
380 * intel_dp_effective_data_rate() instead.
381 */
382int
383intel_dp_link_required(int pixel_clock, int bpp)
384{
385 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
386 return DIV_ROUND_UP(pixel_clock * bpp, 8);
387}
388
389/**
390 * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead
391 * @pixel_clock: pixel clock in kHz
392 * @bpp_x16: bits per pixel .4 fixed point format
393 * @bw_overhead: BW allocation overhead in 1ppm units
394 *
395 * Return the effective pixel data rate in kB/sec units taking into account
396 * the provided SSC, FEC, DSC BW allocation overhead.
397 */
398int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,
399 int bw_overhead)
400{
401 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead),
402 1000000 * 16 * 8);
403}
404
405/**
406 * intel_dp_max_link_data_rate: Calculate the maximum rate for the given link params
407 * @intel_dp: Intel DP object
408 * @max_dprx_rate: Maximum data rate of the DPRX
409 * @max_dprx_lanes: Maximum lane count of the DPRX
410 *
411 * Calculate the maximum data rate for the provided link parameters taking into
412 * account any BW limitations by a DP tunnel attached to @intel_dp.
413 *
414 * Returns the maximum data rate in kBps units.
415 */
416int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,
417 int max_dprx_rate, int max_dprx_lanes)
418{
419 int max_rate = drm_dp_max_dprx_data_rate(max_dprx_rate, max_dprx_lanes);
420
421 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
422 max_rate = min(max_rate,
423 drm_dp_tunnel_available_bw(intel_dp->tunnel));
424
425 return max_rate;
426}
427
428bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
429{
430 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
431 struct intel_encoder *encoder = &intel_dig_port->base;
432 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
433
434 return DISPLAY_VER(dev_priv) >= 12 ||
435 (DISPLAY_VER(dev_priv) == 11 &&
436 encoder->port != PORT_A);
437}
438
439static int dg2_max_source_rate(struct intel_dp *intel_dp)
440{
441 return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
442}
443
444static int icl_max_source_rate(struct intel_dp *intel_dp)
445{
446 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
447 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
448 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
449
450 if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp))
451 return 540000;
452
453 return 810000;
454}
455
456static int ehl_max_source_rate(struct intel_dp *intel_dp)
457{
458 if (intel_dp_is_edp(intel_dp))
459 return 540000;
460
461 return 810000;
462}
463
464static int mtl_max_source_rate(struct intel_dp *intel_dp)
465{
466 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
467 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
468 enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
469
470 if (intel_is_c10phy(i915, phy))
471 return 810000;
472
473 return 2000000;
474}
475
476static int vbt_max_link_rate(struct intel_dp *intel_dp)
477{
478 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
479 int max_rate;
480
481 max_rate = intel_bios_dp_max_link_rate(encoder->devdata);
482
483 if (intel_dp_is_edp(intel_dp)) {
484 struct intel_connector *connector = intel_dp->attached_connector;
485 int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
486
487 if (max_rate && edp_max_rate)
488 max_rate = min(max_rate, edp_max_rate);
489 else if (edp_max_rate)
490 max_rate = edp_max_rate;
491 }
492
493 return max_rate;
494}
495
496static void
497intel_dp_set_source_rates(struct intel_dp *intel_dp)
498{
499 /* The values must be in increasing order */
500 static const int mtl_rates[] = {
501 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
502 810000, 1000000, 2000000,
503 };
504 static const int icl_rates[] = {
505 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
506 1000000, 1350000,
507 };
508 static const int bxt_rates[] = {
509 162000, 216000, 243000, 270000, 324000, 432000, 540000
510 };
511 static const int skl_rates[] = {
512 162000, 216000, 270000, 324000, 432000, 540000
513 };
514 static const int hsw_rates[] = {
515 162000, 270000, 540000
516 };
517 static const int g4x_rates[] = {
518 162000, 270000
519 };
520 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
521 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
522 const int *source_rates;
523 int size, max_rate = 0, vbt_max_rate;
524
525 /* This should only be done once */
526 drm_WARN_ON(&dev_priv->drm,
527 intel_dp->source_rates || intel_dp->num_source_rates);
528
529 if (DISPLAY_VER(dev_priv) >= 14) {
530 source_rates = mtl_rates;
531 size = ARRAY_SIZE(mtl_rates);
532 max_rate = mtl_max_source_rate(intel_dp);
533 } else if (DISPLAY_VER(dev_priv) >= 11) {
534 source_rates = icl_rates;
535 size = ARRAY_SIZE(icl_rates);
536 if (IS_DG2(dev_priv))
537 max_rate = dg2_max_source_rate(intel_dp);
538 else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
539 IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
540 max_rate = 810000;
541 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
542 max_rate = ehl_max_source_rate(intel_dp);
543 else
544 max_rate = icl_max_source_rate(intel_dp);
545 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
546 source_rates = bxt_rates;
547 size = ARRAY_SIZE(bxt_rates);
548 } else if (DISPLAY_VER(dev_priv) == 9) {
549 source_rates = skl_rates;
550 size = ARRAY_SIZE(skl_rates);
551 } else if ((IS_HASWELL(dev_priv) && !IS_HASWELL_ULX(dev_priv)) ||
552 IS_BROADWELL(dev_priv)) {
553 source_rates = hsw_rates;
554 size = ARRAY_SIZE(hsw_rates);
555 } else {
556 source_rates = g4x_rates;
557 size = ARRAY_SIZE(g4x_rates);
558 }
559
560 vbt_max_rate = vbt_max_link_rate(intel_dp);
561 if (max_rate && vbt_max_rate)
562 max_rate = min(max_rate, vbt_max_rate);
563 else if (vbt_max_rate)
564 max_rate = vbt_max_rate;
565
566 if (max_rate)
567 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
568
569 intel_dp->source_rates = source_rates;
570 intel_dp->num_source_rates = size;
571}
572
573static int intersect_rates(const int *source_rates, int source_len,
574 const int *sink_rates, int sink_len,
575 int *common_rates)
576{
577 int i = 0, j = 0, k = 0;
578
579 while (i < source_len && j < sink_len) {
580 if (source_rates[i] == sink_rates[j]) {
581 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
582 return k;
583 common_rates[k] = source_rates[i];
584 ++k;
585 ++i;
586 ++j;
587 } else if (source_rates[i] < sink_rates[j]) {
588 ++i;
589 } else {
590 ++j;
591 }
592 }
593 return k;
594}
595
596/* return index of rate in rates array, or -1 if not found */
597static int intel_dp_rate_index(const int *rates, int len, int rate)
598{
599 int i;
600
601 for (i = 0; i < len; i++)
602 if (rate == rates[i])
603 return i;
604
605 return -1;
606}
607
608static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
609{
610 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
611
612 drm_WARN_ON(&i915->drm,
613 !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
614
615 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
616 intel_dp->num_source_rates,
617 intel_dp->sink_rates,
618 intel_dp->num_sink_rates,
619 intel_dp->common_rates);
620
621 /* Paranoia, there should always be something in common. */
622 if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
623 intel_dp->common_rates[0] = 162000;
624 intel_dp->num_common_rates = 1;
625 }
626}
627
628static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
629 u8 lane_count)
630{
631 /*
632 * FIXME: we need to synchronize the current link parameters with
633 * hardware readout. Currently fast link training doesn't work on
634 * boot-up.
635 */
636 if (link_rate == 0 ||
637 link_rate > intel_dp->max_link_rate)
638 return false;
639
640 if (lane_count == 0 ||
641 lane_count > intel_dp_max_lane_count(intel_dp))
642 return false;
643
644 return true;
645}
646
647static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
648 int link_rate,
649 u8 lane_count)
650{
651 /* FIXME figure out what we actually want here */
652 const struct drm_display_mode *fixed_mode =
653 intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
654 int mode_rate, max_rate;
655
656 mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
657 max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count);
658 if (mode_rate > max_rate)
659 return false;
660
661 return true;
662}
663
664int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
665 int link_rate, u8 lane_count)
666{
667 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
668 int index;
669
670 /*
671 * TODO: Enable fallback on MST links once MST link compute can handle
672 * the fallback params.
673 */
674 if (intel_dp->is_mst) {
675 drm_err(&i915->drm, "Link Training Unsuccessful\n");
676 return -1;
677 }
678
679 if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
680 drm_dbg_kms(&i915->drm,
681 "Retrying Link training for eDP with max parameters\n");
682 intel_dp->use_max_params = true;
683 return 0;
684 }
685
686 index = intel_dp_rate_index(intel_dp->common_rates,
687 intel_dp->num_common_rates,
688 link_rate);
689 if (index > 0) {
690 if (intel_dp_is_edp(intel_dp) &&
691 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
692 intel_dp_common_rate(intel_dp, index - 1),
693 lane_count)) {
694 drm_dbg_kms(&i915->drm,
695 "Retrying Link training for eDP with same parameters\n");
696 return 0;
697 }
698 intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1);
699 intel_dp->max_link_lane_count = lane_count;
700 } else if (lane_count > 1) {
701 if (intel_dp_is_edp(intel_dp) &&
702 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
703 intel_dp_max_common_rate(intel_dp),
704 lane_count >> 1)) {
705 drm_dbg_kms(&i915->drm,
706 "Retrying Link training for eDP with same parameters\n");
707 return 0;
708 }
709 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
710 intel_dp->max_link_lane_count = lane_count >> 1;
711 } else {
712 drm_err(&i915->drm, "Link Training Unsuccessful\n");
713 return -1;
714 }
715
716 return 0;
717}
718
719u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
720{
721 return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR),
722 1000000U);
723}
724
725int intel_dp_bw_fec_overhead(bool fec_enabled)
726{
727 /*
728 * TODO: Calculate the actual overhead for a given mode.
729 * The hard-coded 1/0.972261=2.853% overhead factor
730 * corresponds (for instance) to the 8b/10b DP FEC 2.4% +
731 * 0.453% DSC overhead. This is enough for a 3840 width mode,
732 * which has a DSC overhead of up to ~0.2%, but may not be
733 * enough for a 1024 width mode where this is ~0.8% (on a 4
734 * lane DP link, with 2 DSC slices and 8 bpp color depth).
735 */
736 return fec_enabled ? DP_DSC_FEC_OVERHEAD_FACTOR : 1000000;
737}
738
739static int
740small_joiner_ram_size_bits(struct drm_i915_private *i915)
741{
742 if (DISPLAY_VER(i915) >= 13)
743 return 17280 * 8;
744 else if (DISPLAY_VER(i915) >= 11)
745 return 7680 * 8;
746 else
747 return 6144 * 8;
748}
749
750u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp)
751{
752 u32 bits_per_pixel = bpp;
753 int i;
754
755 /* Error out if the max bpp is less than smallest allowed valid bpp */
756 if (bits_per_pixel < valid_dsc_bpp[0]) {
757 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
758 bits_per_pixel, valid_dsc_bpp[0]);
759 return 0;
760 }
761
762 /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
763 if (DISPLAY_VER(i915) >= 13) {
764 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
765
766 /*
767 * According to BSpec, 27 is the max DSC output bpp,
768 * 8 is the min DSC output bpp.
769 * While we can still clamp higher bpp values to 27, saving bandwidth,
770 * if it is required to oompress up to bpp < 8, means we can't do
771 * that and probably means we can't fit the required mode, even with
772 * DSC enabled.
773 */
774 if (bits_per_pixel < 8) {
775 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min 8\n",
776 bits_per_pixel);
777 return 0;
778 }
779 bits_per_pixel = min_t(u32, bits_per_pixel, 27);
780 } else {
781 /* Find the nearest match in the array of known BPPs from VESA */
782 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
783 if (bits_per_pixel < valid_dsc_bpp[i + 1])
784 break;
785 }
786 drm_dbg_kms(&i915->drm, "Set dsc bpp from %d to VESA %d\n",
787 bits_per_pixel, valid_dsc_bpp[i]);
788
789 bits_per_pixel = valid_dsc_bpp[i];
790 }
791
792 return bits_per_pixel;
793}
794
795static
796u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915,
797 u32 mode_clock, u32 mode_hdisplay,
798 bool bigjoiner)
799{
800 u32 max_bpp_small_joiner_ram;
801
802 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
803 max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay;
804
805 if (bigjoiner) {
806 int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
807 /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */
808 int ppc = 2;
809 u32 max_bpp_bigjoiner =
810 i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits /
811 intel_dp_mode_to_fec_clock(mode_clock);
812
813 max_bpp_small_joiner_ram *= 2;
814
815 return min(max_bpp_small_joiner_ram, max_bpp_bigjoiner);
816 }
817
818 return max_bpp_small_joiner_ram;
819}
820
821u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
822 u32 link_clock, u32 lane_count,
823 u32 mode_clock, u32 mode_hdisplay,
824 bool bigjoiner,
825 enum intel_output_format output_format,
826 u32 pipe_bpp,
827 u32 timeslots)
828{
829 u32 bits_per_pixel, joiner_max_bpp;
830
831 /*
832 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
833 * (LinkSymbolClock)* 8 * (TimeSlots / 64)
834 * for SST -> TimeSlots is 64(i.e all TimeSlots that are available)
835 * for MST -> TimeSlots has to be calculated, based on mode requirements
836 *
837 * Due to FEC overhead, the available bw is reduced to 97.2261%.
838 * To support the given mode:
839 * Bandwidth required should be <= Available link Bandwidth * FEC Overhead
840 * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead
841 * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock
842 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) /
843 * (ModeClock / FEC Overhead)
844 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) /
845 * (ModeClock / FEC Overhead * 8)
846 */
847 bits_per_pixel = ((link_clock * lane_count) * timeslots) /
848 (intel_dp_mode_to_fec_clock(mode_clock) * 8);
849
850 /* Bandwidth required for 420 is half, that of 444 format */
851 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
852 bits_per_pixel *= 2;
853
854 /*
855 * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
856 * supported PPS value can be 63.9375 and with the further
857 * mention that for 420, 422 formats, bpp should be programmed double
858 * the target bpp restricting our target bpp to be 31.9375 at max.
859 */
860 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
861 bits_per_pixel = min_t(u32, bits_per_pixel, 31);
862
863 drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
864 "total bw %u pixel clock %u\n",
865 bits_per_pixel, timeslots,
866 (link_clock * lane_count * 8),
867 intel_dp_mode_to_fec_clock(mode_clock));
868
869 joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock,
870 mode_hdisplay, bigjoiner);
871 bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
872
873 bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
874
875 return bits_per_pixel;
876}
877
878u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
879 int mode_clock, int mode_hdisplay,
880 bool bigjoiner)
881{
882 struct drm_i915_private *i915 = to_i915(connector->base.dev);
883 u8 min_slice_count, i;
884 int max_slice_width;
885
886 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
887 min_slice_count = DIV_ROUND_UP(mode_clock,
888 DP_DSC_MAX_ENC_THROUGHPUT_0);
889 else
890 min_slice_count = DIV_ROUND_UP(mode_clock,
891 DP_DSC_MAX_ENC_THROUGHPUT_1);
892
893 /*
894 * Due to some DSC engine BW limitations, we need to enable second
895 * slice and VDSC engine, whenever we approach close enough to max CDCLK
896 */
897 if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100))
898 min_slice_count = max_t(u8, min_slice_count, 2);
899
900 max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd);
901 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
902 drm_dbg_kms(&i915->drm,
903 "Unsupported slice width %d by DP DSC Sink device\n",
904 max_slice_width);
905 return 0;
906 }
907 /* Also take into account max slice width */
908 min_slice_count = max_t(u8, min_slice_count,
909 DIV_ROUND_UP(mode_hdisplay,
910 max_slice_width));
911
912 /* Find the closest match to the valid slice count values */
913 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
914 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
915
916 if (test_slice_count >
917 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false))
918 break;
919
920 /* big joiner needs small joiner to be enabled */
921 if (bigjoiner && test_slice_count < 4)
922 continue;
923
924 if (min_slice_count <= test_slice_count)
925 return test_slice_count;
926 }
927
928 drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
929 min_slice_count);
930 return 0;
931}
932
933static bool source_can_output(struct intel_dp *intel_dp,
934 enum intel_output_format format)
935{
936 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
937
938 switch (format) {
939 case INTEL_OUTPUT_FORMAT_RGB:
940 return true;
941
942 case INTEL_OUTPUT_FORMAT_YCBCR444:
943 /*
944 * No YCbCr output support on gmch platforms.
945 * Also, ILK doesn't seem capable of DP YCbCr output.
946 * The displayed image is severly corrupted. SNB+ is fine.
947 */
948 return !HAS_GMCH(i915) && !IS_IRONLAKE(i915);
949
950 case INTEL_OUTPUT_FORMAT_YCBCR420:
951 /* Platform < Gen 11 cannot output YCbCr420 format */
952 return DISPLAY_VER(i915) >= 11;
953
954 default:
955 MISSING_CASE(format);
956 return false;
957 }
958}
959
960static bool
961dfp_can_convert_from_rgb(struct intel_dp *intel_dp,
962 enum intel_output_format sink_format)
963{
964 if (!drm_dp_is_branch(intel_dp->dpcd))
965 return false;
966
967 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444)
968 return intel_dp->dfp.rgb_to_ycbcr;
969
970 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
971 return intel_dp->dfp.rgb_to_ycbcr &&
972 intel_dp->dfp.ycbcr_444_to_420;
973
974 return false;
975}
976
977static bool
978dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
979 enum intel_output_format sink_format)
980{
981 if (!drm_dp_is_branch(intel_dp->dpcd))
982 return false;
983
984 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
985 return intel_dp->dfp.ycbcr_444_to_420;
986
987 return false;
988}
989
990static bool
991dfp_can_convert(struct intel_dp *intel_dp,
992 enum intel_output_format output_format,
993 enum intel_output_format sink_format)
994{
995 switch (output_format) {
996 case INTEL_OUTPUT_FORMAT_RGB:
997 return dfp_can_convert_from_rgb(intel_dp, sink_format);
998 case INTEL_OUTPUT_FORMAT_YCBCR444:
999 return dfp_can_convert_from_ycbcr444(intel_dp, sink_format);
1000 default:
1001 MISSING_CASE(output_format);
1002 return false;
1003 }
1004
1005 return false;
1006}
1007
1008static enum intel_output_format
1009intel_dp_output_format(struct intel_connector *connector,
1010 enum intel_output_format sink_format)
1011{
1012 struct intel_dp *intel_dp = intel_attached_dp(connector);
1013 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1014 enum intel_output_format force_dsc_output_format =
1015 intel_dp->force_dsc_output_format;
1016 enum intel_output_format output_format;
1017 if (force_dsc_output_format) {
1018 if (source_can_output(intel_dp, force_dsc_output_format) &&
1019 (!drm_dp_is_branch(intel_dp->dpcd) ||
1020 sink_format != force_dsc_output_format ||
1021 dfp_can_convert(intel_dp, force_dsc_output_format, sink_format)))
1022 return force_dsc_output_format;
1023
1024 drm_dbg_kms(&i915->drm, "Cannot force DSC output format\n");
1025 }
1026
1027 if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||
1028 dfp_can_convert_from_rgb(intel_dp, sink_format))
1029 output_format = INTEL_OUTPUT_FORMAT_RGB;
1030
1031 else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
1032 dfp_can_convert_from_ycbcr444(intel_dp, sink_format))
1033 output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
1034
1035 else
1036 output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1037
1038 drm_WARN_ON(&i915->drm, !source_can_output(intel_dp, output_format));
1039
1040 return output_format;
1041}
1042
1043int intel_dp_min_bpp(enum intel_output_format output_format)
1044{
1045 if (output_format == INTEL_OUTPUT_FORMAT_RGB)
1046 return 6 * 3;
1047 else
1048 return 8 * 3;
1049}
1050
1051int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
1052{
1053 /*
1054 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
1055 * format of the number of bytes per pixel will be half the number
1056 * of bytes of RGB pixel.
1057 */
1058 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1059 bpp /= 2;
1060
1061 return bpp;
1062}
1063
1064static enum intel_output_format
1065intel_dp_sink_format(struct intel_connector *connector,
1066 const struct drm_display_mode *mode)
1067{
1068 const struct drm_display_info *info = &connector->base.display_info;
1069
1070 if (drm_mode_is_420_only(info, mode))
1071 return INTEL_OUTPUT_FORMAT_YCBCR420;
1072
1073 return INTEL_OUTPUT_FORMAT_RGB;
1074}
1075
1076static int
1077intel_dp_mode_min_output_bpp(struct intel_connector *connector,
1078 const struct drm_display_mode *mode)
1079{
1080 enum intel_output_format output_format, sink_format;
1081
1082 sink_format = intel_dp_sink_format(connector, mode);
1083
1084 output_format = intel_dp_output_format(connector, sink_format);
1085
1086 return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
1087}
1088
1089static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
1090 int hdisplay)
1091{
1092 /*
1093 * Older platforms don't like hdisplay==4096 with DP.
1094 *
1095 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
1096 * and frame counter increment), but we don't get vblank interrupts,
1097 * and the pipe underruns immediately. The link also doesn't seem
1098 * to get trained properly.
1099 *
1100 * On CHV the vblank interrupts don't seem to disappear but
1101 * otherwise the symptoms are similar.
1102 *
1103 * TODO: confirm the behaviour on HSW+
1104 */
1105 return hdisplay == 4096 && !HAS_DDI(dev_priv);
1106}
1107
1108static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
1109{
1110 struct intel_connector *connector = intel_dp->attached_connector;
1111 const struct drm_display_info *info = &connector->base.display_info;
1112 int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
1113
1114 /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
1115 if (max_tmds_clock && info->max_tmds_clock)
1116 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1117
1118 return max_tmds_clock;
1119}
1120
1121static enum drm_mode_status
1122intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
1123 int clock, int bpc,
1124 enum intel_output_format sink_format,
1125 bool respect_downstream_limits)
1126{
1127 int tmds_clock, min_tmds_clock, max_tmds_clock;
1128
1129 if (!respect_downstream_limits)
1130 return MODE_OK;
1131
1132 tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
1133
1134 min_tmds_clock = intel_dp->dfp.min_tmds_clock;
1135 max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
1136
1137 if (min_tmds_clock && tmds_clock < min_tmds_clock)
1138 return MODE_CLOCK_LOW;
1139
1140 if (max_tmds_clock && tmds_clock > max_tmds_clock)
1141 return MODE_CLOCK_HIGH;
1142
1143 return MODE_OK;
1144}
1145
1146static enum drm_mode_status
1147intel_dp_mode_valid_downstream(struct intel_connector *connector,
1148 const struct drm_display_mode *mode,
1149 int target_clock)
1150{
1151 struct intel_dp *intel_dp = intel_attached_dp(connector);
1152 const struct drm_display_info *info = &connector->base.display_info;
1153 enum drm_mode_status status;
1154 enum intel_output_format sink_format;
1155
1156 /* If PCON supports FRL MODE, check FRL bandwidth constraints */
1157 if (intel_dp->dfp.pcon_max_frl_bw) {
1158 int target_bw;
1159 int max_frl_bw;
1160 int bpp = intel_dp_mode_min_output_bpp(connector, mode);
1161
1162 target_bw = bpp * target_clock;
1163
1164 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
1165
1166 /* converting bw from Gbps to Kbps*/
1167 max_frl_bw = max_frl_bw * 1000000;
1168
1169 if (target_bw > max_frl_bw)
1170 return MODE_CLOCK_HIGH;
1171
1172 return MODE_OK;
1173 }
1174
1175 if (intel_dp->dfp.max_dotclock &&
1176 target_clock > intel_dp->dfp.max_dotclock)
1177 return MODE_CLOCK_HIGH;
1178
1179 sink_format = intel_dp_sink_format(connector, mode);
1180
1181 /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
1182 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1183 8, sink_format, true);
1184
1185 if (status != MODE_OK) {
1186 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1187 !connector->base.ycbcr_420_allowed ||
1188 !drm_mode_is_420_also(info, mode))
1189 return status;
1190 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1191 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1192 8, sink_format, true);
1193 if (status != MODE_OK)
1194 return status;
1195 }
1196
1197 return MODE_OK;
1198}
1199
1200bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
1201 int hdisplay, int clock)
1202{
1203 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1204 struct intel_connector *connector = intel_dp->attached_connector;
1205
1206 if (!intel_dp_can_bigjoiner(intel_dp))
1207 return false;
1208
1209 return clock > i915->max_dotclk_freq || hdisplay > 5120 ||
1210 connector->force_bigjoiner_enable;
1211}
1212
1213static enum drm_mode_status
1214intel_dp_mode_valid(struct drm_connector *_connector,
1215 struct drm_display_mode *mode)
1216{
1217 struct intel_connector *connector = to_intel_connector(_connector);
1218 struct intel_dp *intel_dp = intel_attached_dp(connector);
1219 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1220 const struct drm_display_mode *fixed_mode;
1221 int target_clock = mode->clock;
1222 int max_rate, mode_rate, max_lanes, max_link_clock;
1223 int max_dotclk = dev_priv->max_dotclk_freq;
1224 u16 dsc_max_compressed_bpp = 0;
1225 u8 dsc_slice_count = 0;
1226 enum drm_mode_status status;
1227 bool dsc = false, bigjoiner = false;
1228
1229 status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
1230 if (status != MODE_OK)
1231 return status;
1232
1233 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1234 return MODE_H_ILLEGAL;
1235
1236 fixed_mode = intel_panel_fixed_mode(connector, mode);
1237 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
1238 status = intel_panel_mode_valid(connector, mode);
1239 if (status != MODE_OK)
1240 return status;
1241
1242 target_clock = fixed_mode->clock;
1243 }
1244
1245 if (mode->clock < 10000)
1246 return MODE_CLOCK_LOW;
1247
1248 if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
1249 bigjoiner = true;
1250 max_dotclk *= 2;
1251 }
1252 if (target_clock > max_dotclk)
1253 return MODE_CLOCK_HIGH;
1254
1255 if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
1256 return MODE_H_ILLEGAL;
1257
1258 max_link_clock = intel_dp_max_link_rate(intel_dp);
1259 max_lanes = intel_dp_max_lane_count(intel_dp);
1260
1261 max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes);
1262
1263 mode_rate = intel_dp_link_required(target_clock,
1264 intel_dp_mode_min_output_bpp(connector, mode));
1265
1266 if (HAS_DSC(dev_priv) &&
1267 drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) {
1268 enum intel_output_format sink_format, output_format;
1269 int pipe_bpp;
1270
1271 sink_format = intel_dp_sink_format(connector, mode);
1272 output_format = intel_dp_output_format(connector, sink_format);
1273 /*
1274 * TBD pass the connector BPC,
1275 * for now U8_MAX so that max BPC on that platform would be picked
1276 */
1277 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
1278
1279 /*
1280 * Output bpp is stored in 6.4 format so right shift by 4 to get the
1281 * integer value since we support only integer values of bpp.
1282 */
1283 if (intel_dp_is_edp(intel_dp)) {
1284 dsc_max_compressed_bpp =
1285 drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
1286 dsc_slice_count =
1287 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
1288 true);
1289 } else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
1290 dsc_max_compressed_bpp =
1291 intel_dp_dsc_get_max_compressed_bpp(dev_priv,
1292 max_link_clock,
1293 max_lanes,
1294 target_clock,
1295 mode->hdisplay,
1296 bigjoiner,
1297 output_format,
1298 pipe_bpp, 64);
1299 dsc_slice_count =
1300 intel_dp_dsc_get_slice_count(connector,
1301 target_clock,
1302 mode->hdisplay,
1303 bigjoiner);
1304 }
1305
1306 dsc = dsc_max_compressed_bpp && dsc_slice_count;
1307 }
1308
1309 /*
1310 * Big joiner configuration needs DSC for TGL which is not true for
1311 * XE_LPD where uncompressed joiner is supported.
1312 */
1313 if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
1314 return MODE_CLOCK_HIGH;
1315
1316 if (mode_rate > max_rate && !dsc)
1317 return MODE_CLOCK_HIGH;
1318
1319 status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1320 if (status != MODE_OK)
1321 return status;
1322
1323 return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
1324}
1325
1326bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
1327{
1328 return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
1329}
1330
1331bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
1332{
1333 return DISPLAY_VER(i915) >= 10;
1334}
1335
1336static void snprintf_int_array(char *str, size_t len,
1337 const int *array, int nelem)
1338{
1339 int i;
1340
1341 str[0] = '\0';
1342
1343 for (i = 0; i < nelem; i++) {
1344 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1345 if (r >= len)
1346 return;
1347 str += r;
1348 len -= r;
1349 }
1350}
1351
1352static void intel_dp_print_rates(struct intel_dp *intel_dp)
1353{
1354 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1355 char str[128]; /* FIXME: too big for stack? */
1356
1357 if (!drm_debug_enabled(DRM_UT_KMS))
1358 return;
1359
1360 snprintf_int_array(str, sizeof(str),
1361 intel_dp->source_rates, intel_dp->num_source_rates);
1362 drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1363
1364 snprintf_int_array(str, sizeof(str),
1365 intel_dp->sink_rates, intel_dp->num_sink_rates);
1366 drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1367
1368 snprintf_int_array(str, sizeof(str),
1369 intel_dp->common_rates, intel_dp->num_common_rates);
1370 drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1371}
1372
1373int
1374intel_dp_max_link_rate(struct intel_dp *intel_dp)
1375{
1376 int len;
1377
1378 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1379
1380 return intel_dp_common_rate(intel_dp, len - 1);
1381}
1382
1383int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1384{
1385 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1386 int i = intel_dp_rate_index(intel_dp->sink_rates,
1387 intel_dp->num_sink_rates, rate);
1388
1389 if (drm_WARN_ON(&i915->drm, i < 0))
1390 i = 0;
1391
1392 return i;
1393}
1394
1395void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1396 u8 *link_bw, u8 *rate_select)
1397{
1398 /* eDP 1.4 rate select method. */
1399 if (intel_dp->use_rate_select) {
1400 *link_bw = 0;
1401 *rate_select =
1402 intel_dp_rate_select(intel_dp, port_clock);
1403 } else {
1404 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1405 *rate_select = 0;
1406 }
1407}
1408
1409bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp)
1410{
1411 struct intel_connector *connector = intel_dp->attached_connector;
1412
1413 return connector->base.display_info.is_hdmi;
1414}
1415
1416static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1417 const struct intel_crtc_state *pipe_config)
1418{
1419 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1420 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1421
1422 if (DISPLAY_VER(dev_priv) >= 12)
1423 return true;
1424
1425 if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A &&
1426 !intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
1427 return true;
1428
1429 return false;
1430}
1431
1432bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1433 const struct intel_connector *connector,
1434 const struct intel_crtc_state *pipe_config)
1435{
1436 return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1437 drm_dp_sink_supports_fec(connector->dp.fec_capability);
1438}
1439
1440static bool intel_dp_supports_dsc(const struct intel_connector *connector,
1441 const struct intel_crtc_state *crtc_state)
1442{
1443 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
1444 return false;
1445
1446 return intel_dsc_source_support(crtc_state) &&
1447 connector->dp.dsc_decompression_aux &&
1448 drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd);
1449}
1450
1451static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
1452 const struct intel_crtc_state *crtc_state,
1453 int bpc, bool respect_downstream_limits)
1454{
1455 int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1456
1457 /*
1458 * Current bpc could already be below 8bpc due to
1459 * FDI bandwidth constraints or other limits.
1460 * HDMI minimum is 8bpc however.
1461 */
1462 bpc = max(bpc, 8);
1463
1464 /*
1465 * We will never exceed downstream TMDS clock limits while
1466 * attempting deep color. If the user insists on forcing an
1467 * out of spec mode they will have to be satisfied with 8bpc.
1468 */
1469 if (!respect_downstream_limits)
1470 bpc = 8;
1471
1472 for (; bpc >= 8; bpc -= 2) {
1473 if (intel_hdmi_bpc_possible(crtc_state, bpc,
1474 intel_dp_has_hdmi_sink(intel_dp)) &&
1475 intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,
1476 respect_downstream_limits) == MODE_OK)
1477 return bpc;
1478 }
1479
1480 return -EINVAL;
1481}
1482
1483static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1484 const struct intel_crtc_state *crtc_state,
1485 bool respect_downstream_limits)
1486{
1487 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1488 struct intel_connector *intel_connector = intel_dp->attached_connector;
1489 int bpp, bpc;
1490
1491 bpc = crtc_state->pipe_bpp / 3;
1492
1493 if (intel_dp->dfp.max_bpc)
1494 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1495
1496 if (intel_dp->dfp.min_tmds_clock) {
1497 int max_hdmi_bpc;
1498
1499 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
1500 respect_downstream_limits);
1501 if (max_hdmi_bpc < 0)
1502 return 0;
1503
1504 bpc = min(bpc, max_hdmi_bpc);
1505 }
1506
1507 bpp = bpc * 3;
1508 if (intel_dp_is_edp(intel_dp)) {
1509 /* Get bpp from vbt only for panels that dont have bpp in edid */
1510 if (intel_connector->base.display_info.bpc == 0 &&
1511 intel_connector->panel.vbt.edp.bpp &&
1512 intel_connector->panel.vbt.edp.bpp < bpp) {
1513 drm_dbg_kms(&dev_priv->drm,
1514 "clamping bpp for eDP panel to BIOS-provided %i\n",
1515 intel_connector->panel.vbt.edp.bpp);
1516 bpp = intel_connector->panel.vbt.edp.bpp;
1517 }
1518 }
1519
1520 return bpp;
1521}
1522
1523/* Adjust link config limits based on compliance test requests. */
1524void
1525intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1526 struct intel_crtc_state *pipe_config,
1527 struct link_config_limits *limits)
1528{
1529 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1530
1531 /* For DP Compliance we override the computed bpp for the pipe */
1532 if (intel_dp->compliance.test_data.bpc != 0) {
1533 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1534
1535 limits->pipe.min_bpp = limits->pipe.max_bpp = bpp;
1536 pipe_config->dither_force_disable = bpp == 6 * 3;
1537
1538 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1539 }
1540
1541 /* Use values requested by Compliance Test Request */
1542 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1543 int index;
1544
1545 /* Validate the compliance test data since max values
1546 * might have changed due to link train fallback.
1547 */
1548 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1549 intel_dp->compliance.test_lane_count)) {
1550 index = intel_dp_rate_index(intel_dp->common_rates,
1551 intel_dp->num_common_rates,
1552 intel_dp->compliance.test_link_rate);
1553 if (index >= 0)
1554 limits->min_rate = limits->max_rate =
1555 intel_dp->compliance.test_link_rate;
1556 limits->min_lane_count = limits->max_lane_count =
1557 intel_dp->compliance.test_lane_count;
1558 }
1559 }
1560}
1561
1562static bool has_seamless_m_n(struct intel_connector *connector)
1563{
1564 struct drm_i915_private *i915 = to_i915(connector->base.dev);
1565
1566 /*
1567 * Seamless M/N reprogramming only implemented
1568 * for BDW+ double buffered M/N registers so far.
1569 */
1570 return HAS_DOUBLE_BUFFERED_M_N(i915) &&
1571 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1572}
1573
1574static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
1575 const struct drm_connector_state *conn_state)
1576{
1577 struct intel_connector *connector = to_intel_connector(conn_state->connector);
1578 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1579
1580 /* FIXME a bit of a mess wrt clock vs. crtc_clock */
1581 if (has_seamless_m_n(connector))
1582 return intel_panel_highest_mode(connector, adjusted_mode)->clock;
1583 else
1584 return adjusted_mode->crtc_clock;
1585}
1586
1587/* Optimize link config in order: max bpp, min clock, min lanes */
1588static int
1589intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1590 struct intel_crtc_state *pipe_config,
1591 const struct drm_connector_state *conn_state,
1592 const struct link_config_limits *limits)
1593{
1594 int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
1595 int mode_rate, link_rate, link_avail;
1596
1597 for (bpp = to_bpp_int(limits->link.max_bpp_x16);
1598 bpp >= to_bpp_int(limits->link.min_bpp_x16);
1599 bpp -= 2 * 3) {
1600 int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1601
1602 mode_rate = intel_dp_link_required(clock, link_bpp);
1603
1604 for (i = 0; i < intel_dp->num_common_rates; i++) {
1605 link_rate = intel_dp_common_rate(intel_dp, i);
1606 if (link_rate < limits->min_rate ||
1607 link_rate > limits->max_rate)
1608 continue;
1609
1610 for (lane_count = limits->min_lane_count;
1611 lane_count <= limits->max_lane_count;
1612 lane_count <<= 1) {
1613 link_avail = intel_dp_max_link_data_rate(intel_dp,
1614 link_rate,
1615 lane_count);
1616
1617
1618 if (mode_rate <= link_avail) {
1619 pipe_config->lane_count = lane_count;
1620 pipe_config->pipe_bpp = bpp;
1621 pipe_config->port_clock = link_rate;
1622
1623 return 0;
1624 }
1625 }
1626 }
1627 }
1628
1629 return -EINVAL;
1630}
1631
1632static
1633u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
1634{
1635 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1636 if (DISPLAY_VER(i915) >= 12)
1637 return 12;
1638 if (DISPLAY_VER(i915) == 11)
1639 return 10;
1640
1641 return 0;
1642}
1643
1644int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
1645 u8 max_req_bpc)
1646{
1647 struct drm_i915_private *i915 = to_i915(connector->base.dev);
1648 int i, num_bpc;
1649 u8 dsc_bpc[3] = {};
1650 u8 dsc_max_bpc;
1651
1652 dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
1653
1654 if (!dsc_max_bpc)
1655 return dsc_max_bpc;
1656
1657 dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
1658
1659 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,
1660 dsc_bpc);
1661 for (i = 0; i < num_bpc; i++) {
1662 if (dsc_max_bpc >= dsc_bpc[i])
1663 return dsc_bpc[i] * 3;
1664 }
1665
1666 return 0;
1667}
1668
1669static int intel_dp_source_dsc_version_minor(struct drm_i915_private *i915)
1670{
1671 return DISPLAY_VER(i915) >= 14 ? 2 : 1;
1672}
1673
1674static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1675{
1676 return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>
1677 DP_DSC_MINOR_SHIFT;
1678}
1679
1680static int intel_dp_get_slice_height(int vactive)
1681{
1682 int slice_height;
1683
1684 /*
1685 * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108
1686 * lines is an optimal slice height, but any size can be used as long as
1687 * vertical active integer multiple and maximum vertical slice count
1688 * requirements are met.
1689 */
1690 for (slice_height = 108; slice_height <= vactive; slice_height += 2)
1691 if (vactive % slice_height == 0)
1692 return slice_height;
1693
1694 /*
1695 * Highly unlikely we reach here as most of the resolutions will end up
1696 * finding appropriate slice_height in above loop but returning
1697 * slice_height as 2 here as it should work with all resolutions.
1698 */
1699 return 2;
1700}
1701
1702static int intel_dp_dsc_compute_params(const struct intel_connector *connector,
1703 struct intel_crtc_state *crtc_state)
1704{
1705 struct drm_i915_private *i915 = to_i915(connector->base.dev);
1706 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1707 u8 line_buf_depth;
1708 int ret;
1709
1710 /*
1711 * RC_MODEL_SIZE is currently a constant across all configurations.
1712 *
1713 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1714 * DP_DSC_RC_BUF_SIZE for this.
1715 */
1716 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1717 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1718
1719 vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height);
1720
1721 ret = intel_dsc_compute_params(crtc_state);
1722 if (ret)
1723 return ret;
1724
1725 vdsc_cfg->dsc_version_major =
1726 (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1727 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1728 vdsc_cfg->dsc_version_minor =
1729 min(intel_dp_source_dsc_version_minor(i915),
1730 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd));
1731 if (vdsc_cfg->convert_rgb)
1732 vdsc_cfg->convert_rgb =
1733 connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1734 DP_DSC_RGB;
1735
1736 line_buf_depth = drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd);
1737 if (!line_buf_depth) {
1738 drm_dbg_kms(&i915->drm,
1739 "DSC Sink Line Buffer Depth invalid\n");
1740 return -EINVAL;
1741 }
1742
1743 if (vdsc_cfg->dsc_version_minor == 2)
1744 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1745 DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1746 else
1747 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1748 DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1749
1750 vdsc_cfg->block_pred_enable =
1751 connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1752 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1753
1754 return drm_dsc_compute_rc_parameters(vdsc_cfg);
1755}
1756
1757static bool intel_dp_dsc_supports_format(const struct intel_connector *connector,
1758 enum intel_output_format output_format)
1759{
1760 struct drm_i915_private *i915 = to_i915(connector->base.dev);
1761 u8 sink_dsc_format;
1762
1763 switch (output_format) {
1764 case INTEL_OUTPUT_FORMAT_RGB:
1765 sink_dsc_format = DP_DSC_RGB;
1766 break;
1767 case INTEL_OUTPUT_FORMAT_YCBCR444:
1768 sink_dsc_format = DP_DSC_YCbCr444;
1769 break;
1770 case INTEL_OUTPUT_FORMAT_YCBCR420:
1771 if (min(intel_dp_source_dsc_version_minor(i915),
1772 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2)
1773 return false;
1774 sink_dsc_format = DP_DSC_YCbCr420_Native;
1775 break;
1776 default:
1777 return false;
1778 }
1779
1780 return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format);
1781}
1782
1783static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_clock,
1784 u32 lane_count, u32 mode_clock,
1785 enum intel_output_format output_format,
1786 int timeslots)
1787{
1788 u32 available_bw, required_bw;
1789
1790 available_bw = (link_clock * lane_count * timeslots * 16) / 8;
1791 required_bw = compressed_bppx16 * (intel_dp_mode_to_fec_clock(mode_clock));
1792
1793 return available_bw > required_bw;
1794}
1795
1796static int dsc_compute_link_config(struct intel_dp *intel_dp,
1797 struct intel_crtc_state *pipe_config,
1798 struct link_config_limits *limits,
1799 u16 compressed_bppx16,
1800 int timeslots)
1801{
1802 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1803 int link_rate, lane_count;
1804 int i;
1805
1806 for (i = 0; i < intel_dp->num_common_rates; i++) {
1807 link_rate = intel_dp_common_rate(intel_dp, i);
1808 if (link_rate < limits->min_rate || link_rate > limits->max_rate)
1809 continue;
1810
1811 for (lane_count = limits->min_lane_count;
1812 lane_count <= limits->max_lane_count;
1813 lane_count <<= 1) {
1814 if (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate,
1815 lane_count, adjusted_mode->clock,
1816 pipe_config->output_format,
1817 timeslots))
1818 continue;
1819
1820 pipe_config->lane_count = lane_count;
1821 pipe_config->port_clock = link_rate;
1822
1823 return 0;
1824 }
1825 }
1826
1827 return -EINVAL;
1828}
1829
1830static
1831u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector,
1832 struct intel_crtc_state *pipe_config,
1833 int bpc)
1834{
1835 u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd);
1836
1837 if (max_bppx16)
1838 return max_bppx16;
1839 /*
1840 * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate
1841 * values as given in spec Table 2-157 DP v2.0
1842 */
1843 switch (pipe_config->output_format) {
1844 case INTEL_OUTPUT_FORMAT_RGB:
1845 case INTEL_OUTPUT_FORMAT_YCBCR444:
1846 return (3 * bpc) << 4;
1847 case INTEL_OUTPUT_FORMAT_YCBCR420:
1848 return (3 * (bpc / 2)) << 4;
1849 default:
1850 MISSING_CASE(pipe_config->output_format);
1851 break;
1852 }
1853
1854 return 0;
1855}
1856
1857int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
1858{
1859 /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
1860 switch (pipe_config->output_format) {
1861 case INTEL_OUTPUT_FORMAT_RGB:
1862 case INTEL_OUTPUT_FORMAT_YCBCR444:
1863 return 8;
1864 case INTEL_OUTPUT_FORMAT_YCBCR420:
1865 return 6;
1866 default:
1867 MISSING_CASE(pipe_config->output_format);
1868 break;
1869 }
1870
1871 return 0;
1872}
1873
1874int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
1875 struct intel_crtc_state *pipe_config,
1876 int bpc)
1877{
1878 return intel_dp_dsc_max_sink_compressed_bppx16(connector,
1879 pipe_config, bpc) >> 4;
1880}
1881
1882static int dsc_src_min_compressed_bpp(void)
1883{
1884 /* Min Compressed bpp supported by source is 8 */
1885 return 8;
1886}
1887
1888static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)
1889{
1890 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1891
1892 /*
1893 * Max Compressed bpp for Gen 13+ is 27bpp.
1894 * For earlier platform is 23bpp. (Bspec:49259).
1895 */
1896 if (DISPLAY_VER(i915) < 13)
1897 return 23;
1898 else
1899 return 27;
1900}
1901
1902/*
1903 * From a list of valid compressed bpps try different compressed bpp and find a
1904 * suitable link configuration that can support it.
1905 */
1906static int
1907icl_dsc_compute_link_config(struct intel_dp *intel_dp,
1908 struct intel_crtc_state *pipe_config,
1909 struct link_config_limits *limits,
1910 int dsc_max_bpp,
1911 int dsc_min_bpp,
1912 int pipe_bpp,
1913 int timeslots)
1914{
1915 int i, ret;
1916
1917 /* Compressed BPP should be less than the Input DSC bpp */
1918 dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
1919
1920 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) {
1921 if (valid_dsc_bpp[i] < dsc_min_bpp)
1922 continue;
1923 if (valid_dsc_bpp[i] > dsc_max_bpp)
1924 break;
1925
1926 ret = dsc_compute_link_config(intel_dp,
1927 pipe_config,
1928 limits,
1929 valid_dsc_bpp[i] << 4,
1930 timeslots);
1931 if (ret == 0) {
1932 pipe_config->dsc.compressed_bpp_x16 =
1933 to_bpp_x16(valid_dsc_bpp[i]);
1934 return 0;
1935 }
1936 }
1937
1938 return -EINVAL;
1939}
1940
1941/*
1942 * From XE_LPD onwards we supports compression bpps in steps of 1 up to
1943 * uncompressed bpp-1. So we start from max compressed bpp and see if any
1944 * link configuration is able to support that compressed bpp, if not we
1945 * step down and check for lower compressed bpp.
1946 */
1947static int
1948xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
1949 const struct intel_connector *connector,
1950 struct intel_crtc_state *pipe_config,
1951 struct link_config_limits *limits,
1952 int dsc_max_bpp,
1953 int dsc_min_bpp,
1954 int pipe_bpp,
1955 int timeslots)
1956{
1957 u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd);
1958 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1959 u16 compressed_bppx16;
1960 u8 bppx16_step;
1961 int ret;
1962
1963 if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1)
1964 bppx16_step = 16;
1965 else
1966 bppx16_step = 16 / bppx16_incr;
1967
1968 /* Compressed BPP should be less than the Input DSC bpp */
1969 dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step);
1970 dsc_min_bpp = dsc_min_bpp << 4;
1971
1972 for (compressed_bppx16 = dsc_max_bpp;
1973 compressed_bppx16 >= dsc_min_bpp;
1974 compressed_bppx16 -= bppx16_step) {
1975 if (intel_dp->force_dsc_fractional_bpp_en &&
1976 !to_bpp_frac(compressed_bppx16))
1977 continue;
1978 ret = dsc_compute_link_config(intel_dp,
1979 pipe_config,
1980 limits,
1981 compressed_bppx16,
1982 timeslots);
1983 if (ret == 0) {
1984 pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;
1985 if (intel_dp->force_dsc_fractional_bpp_en &&
1986 to_bpp_frac(compressed_bppx16))
1987 drm_dbg_kms(&i915->drm, "Forcing DSC fractional bpp\n");
1988
1989 return 0;
1990 }
1991 }
1992 return -EINVAL;
1993}
1994
1995static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
1996 const struct intel_connector *connector,
1997 struct intel_crtc_state *pipe_config,
1998 struct link_config_limits *limits,
1999 int pipe_bpp,
2000 int timeslots)
2001{
2002 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2003 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2004 int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2005 int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2006 int dsc_joiner_max_bpp;
2007
2008 dsc_src_min_bpp = dsc_src_min_compressed_bpp();
2009 dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
2010 dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2011 dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
2012
2013 dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2014 dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2015 pipe_config,
2016 pipe_bpp / 3);
2017 dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2018
2019 dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
2020 adjusted_mode->hdisplay,
2021 pipe_config->bigjoiner_pipes);
2022 dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp);
2023 dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
2024
2025 if (DISPLAY_VER(i915) >= 13)
2026 return xelpd_dsc_compute_link_config(intel_dp, connector, pipe_config, limits,
2027 dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
2028 return icl_dsc_compute_link_config(intel_dp, pipe_config, limits,
2029 dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
2030}
2031
2032static
2033u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
2034{
2035 /* Min DSC Input BPC for ICL+ is 8 */
2036 return HAS_DSC(i915) ? 8 : 0;
2037}
2038
2039static
2040bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
2041 struct drm_connector_state *conn_state,
2042 struct link_config_limits *limits,
2043 int pipe_bpp)
2044{
2045 u8 dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
2046
2047 dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc);
2048 dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2049
2050 dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
2051 dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
2052
2053 return pipe_bpp >= dsc_min_pipe_bpp &&
2054 pipe_bpp <= dsc_max_pipe_bpp;
2055}
2056
2057static
2058int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
2059 struct drm_connector_state *conn_state,
2060 struct link_config_limits *limits)
2061{
2062 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2063 int forced_bpp;
2064
2065 if (!intel_dp->force_dsc_bpc)
2066 return 0;
2067
2068 forced_bpp = intel_dp->force_dsc_bpc * 3;
2069
2070 if (is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, forced_bpp)) {
2071 drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);
2072 return forced_bpp;
2073 }
2074
2075 drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
2076 intel_dp->force_dsc_bpc);
2077
2078 return 0;
2079}
2080
2081static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2082 struct intel_crtc_state *pipe_config,
2083 struct drm_connector_state *conn_state,
2084 struct link_config_limits *limits,
2085 int timeslots)
2086{
2087 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2088 const struct intel_connector *connector =
2089 to_intel_connector(conn_state->connector);
2090 u8 max_req_bpc = conn_state->max_requested_bpc;
2091 u8 dsc_max_bpc, dsc_max_bpp;
2092 u8 dsc_min_bpc, dsc_min_bpp;
2093 u8 dsc_bpc[3] = {};
2094 int forced_bpp, pipe_bpp;
2095 int num_bpc, i, ret;
2096
2097 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
2098
2099 if (forced_bpp) {
2100 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,
2101 limits, forced_bpp, timeslots);
2102 if (ret == 0) {
2103 pipe_config->pipe_bpp = forced_bpp;
2104 return 0;
2105 }
2106 }
2107
2108 dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
2109 if (!dsc_max_bpc)
2110 return -EINVAL;
2111
2112 dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
2113 dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
2114
2115 dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2116 dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
2117
2118 /*
2119 * Get the maximum DSC bpc that will be supported by any valid
2120 * link configuration and compressed bpp.
2121 */
2122 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc);
2123 for (i = 0; i < num_bpc; i++) {
2124 pipe_bpp = dsc_bpc[i] * 3;
2125 if (pipe_bpp < dsc_min_bpp)
2126 break;
2127 if (pipe_bpp > dsc_max_bpp)
2128 continue;
2129 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,
2130 limits, pipe_bpp, timeslots);
2131 if (ret == 0) {
2132 pipe_config->pipe_bpp = pipe_bpp;
2133 return 0;
2134 }
2135 }
2136
2137 return -EINVAL;
2138}
2139
2140static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2141 struct intel_crtc_state *pipe_config,
2142 struct drm_connector_state *conn_state,
2143 struct link_config_limits *limits)
2144{
2145 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2146 struct intel_connector *connector =
2147 to_intel_connector(conn_state->connector);
2148 int pipe_bpp, forced_bpp;
2149 int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2150 int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2151
2152 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
2153
2154 if (forced_bpp) {
2155 pipe_bpp = forced_bpp;
2156 } else {
2157 int max_bpc = min(limits->pipe.max_bpp / 3, (int)conn_state->max_requested_bpc);
2158
2159 /* For eDP use max bpp that can be supported with DSC. */
2160 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc);
2161 if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
2162 drm_dbg_kms(&i915->drm,
2163 "Computed BPC is not in DSC BPC limits\n");
2164 return -EINVAL;
2165 }
2166 }
2167 pipe_config->port_clock = limits->max_rate;
2168 pipe_config->lane_count = limits->max_lane_count;
2169
2170 dsc_src_min_bpp = dsc_src_min_compressed_bpp();
2171 dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
2172 dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2173 dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
2174
2175 dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2176 dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2177 pipe_config,
2178 pipe_bpp / 3);
2179 dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2180 dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
2181
2182 /* Compressed BPP should be less than the Input DSC bpp */
2183 dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
2184
2185 pipe_config->dsc.compressed_bpp_x16 =
2186 to_bpp_x16(max(dsc_min_bpp, dsc_max_bpp));
2187
2188 pipe_config->pipe_bpp = pipe_bpp;
2189
2190 return 0;
2191}
2192
2193int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2194 struct intel_crtc_state *pipe_config,
2195 struct drm_connector_state *conn_state,
2196 struct link_config_limits *limits,
2197 int timeslots,
2198 bool compute_pipe_bpp)
2199{
2200 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2201 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2202 const struct intel_connector *connector =
2203 to_intel_connector(conn_state->connector);
2204 const struct drm_display_mode *adjusted_mode =
2205 &pipe_config->hw.adjusted_mode;
2206 int ret;
2207
2208 pipe_config->fec_enable = pipe_config->fec_enable ||
2209 (!intel_dp_is_edp(intel_dp) &&
2210 intel_dp_supports_fec(intel_dp, connector, pipe_config));
2211
2212 if (!intel_dp_supports_dsc(connector, pipe_config))
2213 return -EINVAL;
2214
2215 if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format))
2216 return -EINVAL;
2217
2218 /*
2219 * compute pipe bpp is set to false for DP MST DSC case
2220 * and compressed_bpp is calculated same time once
2221 * vpci timeslots are allocated, because overall bpp
2222 * calculation procedure is bit different for MST case.
2223 */
2224 if (compute_pipe_bpp) {
2225 if (intel_dp_is_edp(intel_dp))
2226 ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2227 conn_state, limits);
2228 else
2229 ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2230 conn_state, limits, timeslots);
2231 if (ret) {
2232 drm_dbg_kms(&dev_priv->drm,
2233 "No Valid pipe bpp for given mode ret = %d\n", ret);
2234 return ret;
2235 }
2236 }
2237
2238 /* Calculate Slice count */
2239 if (intel_dp_is_edp(intel_dp)) {
2240 pipe_config->dsc.slice_count =
2241 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
2242 true);
2243 if (!pipe_config->dsc.slice_count) {
2244 drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n",
2245 pipe_config->dsc.slice_count);
2246 return -EINVAL;
2247 }
2248 } else {
2249 u8 dsc_dp_slice_count;
2250
2251 dsc_dp_slice_count =
2252 intel_dp_dsc_get_slice_count(connector,
2253 adjusted_mode->crtc_clock,
2254 adjusted_mode->crtc_hdisplay,
2255 pipe_config->bigjoiner_pipes);
2256 if (!dsc_dp_slice_count) {
2257 drm_dbg_kms(&dev_priv->drm,
2258 "Compressed Slice Count not supported\n");
2259 return -EINVAL;
2260 }
2261
2262 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2263 }
2264 /*
2265 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2266 * is greater than the maximum Cdclock and if slice count is even
2267 * then we need to use 2 VDSC instances.
2268 */
2269 if (pipe_config->bigjoiner_pipes || pipe_config->dsc.slice_count > 1)
2270 pipe_config->dsc.dsc_split = true;
2271
2272 ret = intel_dp_dsc_compute_params(connector, pipe_config);
2273 if (ret < 0) {
2274 drm_dbg_kms(&dev_priv->drm,
2275 "Cannot compute valid DSC parameters for Input Bpp = %d"
2276 "Compressed BPP = " BPP_X16_FMT "\n",
2277 pipe_config->pipe_bpp,
2278 BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16));
2279 return ret;
2280 }
2281
2282 pipe_config->dsc.compression_enable = true;
2283 drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2284 "Compressed Bpp = " BPP_X16_FMT " Slice Count = %d\n",
2285 pipe_config->pipe_bpp,
2286 BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16),
2287 pipe_config->dsc.slice_count);
2288
2289 return 0;
2290}
2291
2292/**
2293 * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits
2294 * @intel_dp: intel DP
2295 * @crtc_state: crtc state
2296 * @dsc: DSC compression mode
2297 * @limits: link configuration limits
2298 *
2299 * Calculates the output link min, max bpp values in @limits based on the
2300 * pipe bpp range, @crtc_state and @dsc mode.
2301 *
2302 * Returns %true in case of success.
2303 */
2304bool
2305intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
2306 const struct intel_crtc_state *crtc_state,
2307 bool dsc,
2308 struct link_config_limits *limits)
2309{
2310 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2311 const struct drm_display_mode *adjusted_mode =
2312 &crtc_state->hw.adjusted_mode;
2313 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2314 const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2315 int max_link_bpp_x16;
2316
2317 max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
2318 to_bpp_x16(limits->pipe.max_bpp));
2319
2320 if (!dsc) {
2321 max_link_bpp_x16 = rounddown(max_link_bpp_x16, to_bpp_x16(2 * 3));
2322
2323 if (max_link_bpp_x16 < to_bpp_x16(limits->pipe.min_bpp))
2324 return false;
2325
2326 limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
2327 } else {
2328 /*
2329 * TODO: set the DSC link limits already here, atm these are
2330 * initialized only later in intel_edp_dsc_compute_pipe_bpp() /
2331 * intel_dp_dsc_compute_pipe_bpp()
2332 */
2333 limits->link.min_bpp_x16 = 0;
2334 }
2335
2336 limits->link.max_bpp_x16 = max_link_bpp_x16;
2337
2338 drm_dbg_kms(&i915->drm,
2339 "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " BPP_X16_FMT "\n",
2340 encoder->base.base.id, encoder->base.name,
2341 crtc->base.base.id, crtc->base.name,
2342 adjusted_mode->crtc_clock,
2343 dsc ? "on" : "off",
2344 limits->max_lane_count,
2345 limits->max_rate,
2346 limits->pipe.max_bpp,
2347 BPP_X16_ARGS(limits->link.max_bpp_x16));
2348
2349 return true;
2350}
2351
2352static bool
2353intel_dp_compute_config_limits(struct intel_dp *intel_dp,
2354 struct intel_crtc_state *crtc_state,
2355 bool respect_downstream_limits,
2356 bool dsc,
2357 struct link_config_limits *limits)
2358{
2359 limits->min_rate = intel_dp_common_rate(intel_dp, 0);
2360 limits->max_rate = intel_dp_max_link_rate(intel_dp);
2361
2362 /* FIXME 128b/132b SST support missing */
2363 limits->max_rate = min(limits->max_rate, 810000);
2364
2365 limits->min_lane_count = 1;
2366 limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
2367
2368 limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
2369 limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
2370 respect_downstream_limits);
2371
2372 if (intel_dp->use_max_params) {
2373 /*
2374 * Use the maximum clock and number of lanes the eDP panel
2375 * advertizes being capable of in case the initial fast
2376 * optimal params failed us. The panels are generally
2377 * designed to support only a single clock and lane
2378 * configuration, and typically on older panels these
2379 * values correspond to the native resolution of the panel.
2380 */
2381 limits->min_lane_count = limits->max_lane_count;
2382 limits->min_rate = limits->max_rate;
2383 }
2384
2385 intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
2386
2387 return intel_dp_compute_config_link_bpp_limits(intel_dp,
2388 crtc_state,
2389 dsc,
2390 limits);
2391}
2392
2393int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state)
2394{
2395 const struct drm_display_mode *adjusted_mode =
2396 &crtc_state->hw.adjusted_mode;
2397 int bpp = crtc_state->dsc.compression_enable ?
2398 to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) :
2399 crtc_state->pipe_bpp;
2400
2401 return intel_dp_link_required(adjusted_mode->crtc_clock, bpp);
2402}
2403
2404static int
2405intel_dp_compute_link_config(struct intel_encoder *encoder,
2406 struct intel_crtc_state *pipe_config,
2407 struct drm_connector_state *conn_state,
2408 bool respect_downstream_limits)
2409{
2410 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2411 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2412 const struct intel_connector *connector =
2413 to_intel_connector(conn_state->connector);
2414 const struct drm_display_mode *adjusted_mode =
2415 &pipe_config->hw.adjusted_mode;
2416 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2417 struct link_config_limits limits;
2418 bool joiner_needs_dsc = false;
2419 bool dsc_needed;
2420 int ret = 0;
2421
2422 if (pipe_config->fec_enable &&
2423 !intel_dp_supports_fec(intel_dp, connector, pipe_config))
2424 return -EINVAL;
2425
2426 if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
2427 adjusted_mode->crtc_clock))
2428 pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
2429
2430 /*
2431 * Pipe joiner needs compression up to display 12 due to bandwidth
2432 * limitation. DG2 onwards pipe joiner can be enabled without
2433 * compression.
2434 */
2435 joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
2436
2437 dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
2438 !intel_dp_compute_config_limits(intel_dp, pipe_config,
2439 respect_downstream_limits,
2440 false,
2441 &limits);
2442
2443 if (!dsc_needed) {
2444 /*
2445 * Optimize for slow and wide for everything, because there are some
2446 * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
2447 */
2448 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2449 conn_state, &limits);
2450 if (ret)
2451 dsc_needed = true;
2452 }
2453
2454 if (dsc_needed) {
2455 drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
2456 str_yes_no(ret), str_yes_no(joiner_needs_dsc),
2457 str_yes_no(intel_dp->force_dsc_en));
2458
2459 if (!intel_dp_compute_config_limits(intel_dp, pipe_config,
2460 respect_downstream_limits,
2461 true,
2462 &limits))
2463 return -EINVAL;
2464
2465 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2466 conn_state, &limits, 64, true);
2467 if (ret < 0)
2468 return ret;
2469 }
2470
2471 drm_dbg_kms(&i915->drm,
2472 "DP lane count %d clock %d bpp input %d compressed " BPP_X16_FMT " link rate required %d available %d\n",
2473 pipe_config->lane_count, pipe_config->port_clock,
2474 pipe_config->pipe_bpp,
2475 BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16),
2476 intel_dp_config_required_rate(pipe_config),
2477 intel_dp_max_link_data_rate(intel_dp,
2478 pipe_config->port_clock,
2479 pipe_config->lane_count));
2480
2481 return 0;
2482}
2483
2484bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2485 const struct drm_connector_state *conn_state)
2486{
2487 const struct intel_digital_connector_state *intel_conn_state =
2488 to_intel_digital_connector_state(conn_state);
2489 const struct drm_display_mode *adjusted_mode =
2490 &crtc_state->hw.adjusted_mode;
2491
2492 /*
2493 * Our YCbCr output is always limited range.
2494 * crtc_state->limited_color_range only applies to RGB,
2495 * and it must never be set for YCbCr or we risk setting
2496 * some conflicting bits in TRANSCONF which will mess up
2497 * the colors on the monitor.
2498 */
2499 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2500 return false;
2501
2502 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2503 /*
2504 * See:
2505 * CEA-861-E - 5.1 Default Encoding Parameters
2506 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2507 */
2508 return crtc_state->pipe_bpp != 18 &&
2509 drm_default_rgb_quant_range(adjusted_mode) ==
2510 HDMI_QUANTIZATION_RANGE_LIMITED;
2511 } else {
2512 return intel_conn_state->broadcast_rgb ==
2513 INTEL_BROADCAST_RGB_LIMITED;
2514 }
2515}
2516
2517static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2518 enum port port)
2519{
2520 if (IS_G4X(dev_priv))
2521 return false;
2522 if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
2523 return false;
2524
2525 return true;
2526}
2527
2528static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2529 const struct drm_connector_state *conn_state,
2530 struct drm_dp_vsc_sdp *vsc)
2531{
2532 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2533 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2534
2535 if (crtc_state->has_panel_replay) {
2536 /*
2537 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2538 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
2539 * Encoding/Colorimetry Format indication.
2540 */
2541 vsc->revision = 0x7;
2542 } else {
2543 /*
2544 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2545 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2546 * Colorimetry Format indication.
2547 */
2548 vsc->revision = 0x5;
2549 }
2550
2551 vsc->length = 0x13;
2552
2553 /* DP 1.4a spec, Table 2-120 */
2554 switch (crtc_state->output_format) {
2555 case INTEL_OUTPUT_FORMAT_YCBCR444:
2556 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2557 break;
2558 case INTEL_OUTPUT_FORMAT_YCBCR420:
2559 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2560 break;
2561 case INTEL_OUTPUT_FORMAT_RGB:
2562 default:
2563 vsc->pixelformat = DP_PIXELFORMAT_RGB;
2564 }
2565
2566 switch (conn_state->colorspace) {
2567 case DRM_MODE_COLORIMETRY_BT709_YCC:
2568 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2569 break;
2570 case DRM_MODE_COLORIMETRY_XVYCC_601:
2571 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2572 break;
2573 case DRM_MODE_COLORIMETRY_XVYCC_709:
2574 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2575 break;
2576 case DRM_MODE_COLORIMETRY_SYCC_601:
2577 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2578 break;
2579 case DRM_MODE_COLORIMETRY_OPYCC_601:
2580 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2581 break;
2582 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2583 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2584 break;
2585 case DRM_MODE_COLORIMETRY_BT2020_RGB:
2586 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2587 break;
2588 case DRM_MODE_COLORIMETRY_BT2020_YCC:
2589 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2590 break;
2591 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2592 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2593 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2594 break;
2595 default:
2596 /*
2597 * RGB->YCBCR color conversion uses the BT.709
2598 * color space.
2599 */
2600 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2601 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2602 else
2603 vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2604 break;
2605 }
2606
2607 vsc->bpc = crtc_state->pipe_bpp / 3;
2608
2609 /* only RGB pixelformat supports 6 bpc */
2610 drm_WARN_ON(&dev_priv->drm,
2611 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2612
2613 /* all YCbCr are always limited range */
2614 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2615 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2616}
2617
2618static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2619 struct intel_crtc_state *crtc_state,
2620 const struct drm_connector_state *conn_state)
2621{
2622 struct drm_dp_vsc_sdp *vsc;
2623
2624 if ((!intel_dp->colorimetry_support ||
2625 !intel_dp_needs_vsc_sdp(crtc_state, conn_state)) &&
2626 !crtc_state->has_psr)
2627 return;
2628
2629 vsc = &crtc_state->infoframes.vsc;
2630
2631 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2632 vsc->sdp_type = DP_SDP_VSC;
2633
2634 /* Needs colorimetry */
2635 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2636 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2637 vsc);
2638 } else if (crtc_state->has_psr2) {
2639 /*
2640 * [PSR2 without colorimetry]
2641 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2642 * 3D stereo + PSR/PSR2 + Y-coordinate.
2643 */
2644 vsc->revision = 0x4;
2645 vsc->length = 0xe;
2646 } else if (crtc_state->has_panel_replay) {
2647 /*
2648 * [Panel Replay without colorimetry info]
2649 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2650 * VSC SDP supporting 3D stereo + Panel Replay.
2651 */
2652 vsc->revision = 0x6;
2653 vsc->length = 0x10;
2654 } else {
2655 /*
2656 * [PSR1]
2657 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2658 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2659 * higher).
2660 */
2661 vsc->revision = 0x2;
2662 vsc->length = 0x8;
2663 }
2664}
2665
2666static void
2667intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2668 struct intel_crtc_state *crtc_state,
2669 const struct drm_connector_state *conn_state)
2670{
2671 int ret;
2672 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2673 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2674
2675 if (!conn_state->hdr_output_metadata)
2676 return;
2677
2678 ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2679
2680 if (ret) {
2681 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2682 return;
2683 }
2684
2685 crtc_state->infoframes.enable |=
2686 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2687}
2688
2689static bool can_enable_drrs(struct intel_connector *connector,
2690 const struct intel_crtc_state *pipe_config,
2691 const struct drm_display_mode *downclock_mode)
2692{
2693 struct drm_i915_private *i915 = to_i915(connector->base.dev);
2694
2695 if (pipe_config->vrr.enable)
2696 return false;
2697
2698 /*
2699 * DRRS and PSR can't be enable together, so giving preference to PSR
2700 * as it allows more power-savings by complete shutting down display,
2701 * so to guarantee this, intel_drrs_compute_config() must be called
2702 * after intel_psr_compute_config().
2703 */
2704 if (pipe_config->has_psr)
2705 return false;
2706
2707 /* FIXME missing FDI M2/N2 etc. */
2708 if (pipe_config->has_pch_encoder)
2709 return false;
2710
2711 if (!intel_cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))
2712 return false;
2713
2714 return downclock_mode &&
2715 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
2716}
2717
2718static void
2719intel_dp_drrs_compute_config(struct intel_connector *connector,
2720 struct intel_crtc_state *pipe_config,
2721 int link_bpp_x16)
2722{
2723 struct drm_i915_private *i915 = to_i915(connector->base.dev);
2724 const struct drm_display_mode *downclock_mode =
2725 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
2726 int pixel_clock;
2727
2728 /*
2729 * FIXME all joined pipes share the same transcoder.
2730 * Need to account for that when updating M/N live.
2731 */
2732 if (has_seamless_m_n(connector) && !pipe_config->bigjoiner_pipes)
2733 pipe_config->update_m_n = true;
2734
2735 if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
2736 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
2737 intel_zero_m_n(&pipe_config->dp_m2_n2);
2738 return;
2739 }
2740
2741 if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
2742 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
2743
2744 pipe_config->has_drrs = true;
2745
2746 pixel_clock = downclock_mode->clock;
2747 if (pipe_config->splitter.enable)
2748 pixel_clock /= pipe_config->splitter.link_count;
2749
2750 intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock,
2751 pipe_config->port_clock,
2752 intel_dp_bw_fec_overhead(pipe_config->fec_enable),
2753 &pipe_config->dp_m2_n2);
2754
2755 /* FIXME: abstract this better */
2756 if (pipe_config->splitter.enable)
2757 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
2758}
2759
2760static bool intel_dp_has_audio(struct intel_encoder *encoder,
2761 struct intel_crtc_state *crtc_state,
2762 const struct drm_connector_state *conn_state)
2763{
2764 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2765 const struct intel_digital_connector_state *intel_conn_state =
2766 to_intel_digital_connector_state(conn_state);
2767 struct intel_connector *connector =
2768 to_intel_connector(conn_state->connector);
2769
2770 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
2771 !intel_dp_port_has_audio(i915, encoder->port))
2772 return false;
2773
2774 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2775 return connector->base.display_info.has_audio;
2776 else
2777 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2778}
2779
2780static int
2781intel_dp_compute_output_format(struct intel_encoder *encoder,
2782 struct intel_crtc_state *crtc_state,
2783 struct drm_connector_state *conn_state,
2784 bool respect_downstream_limits)
2785{
2786 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2787 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2788 struct intel_connector *connector = intel_dp->attached_connector;
2789 const struct drm_display_info *info = &connector->base.display_info;
2790 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2791 bool ycbcr_420_only;
2792 int ret;
2793
2794 ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2795
2796 if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
2797 drm_dbg_kms(&i915->drm,
2798 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2799 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
2800 } else {
2801 crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode);
2802 }
2803
2804 crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);
2805
2806 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2807 respect_downstream_limits);
2808 if (ret) {
2809 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2810 !connector->base.ycbcr_420_allowed ||
2811 !drm_mode_is_420_also(info, adjusted_mode))
2812 return ret;
2813
2814 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2815 crtc_state->output_format = intel_dp_output_format(connector,
2816 crtc_state->sink_format);
2817 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2818 respect_downstream_limits);
2819 }
2820
2821 return ret;
2822}
2823
2824void
2825intel_dp_audio_compute_config(struct intel_encoder *encoder,
2826 struct intel_crtc_state *pipe_config,
2827 struct drm_connector_state *conn_state)
2828{
2829 pipe_config->has_audio =
2830 intel_dp_has_audio(encoder, pipe_config, conn_state) &&
2831 intel_audio_compute_config(encoder, pipe_config, conn_state);
2832
2833 pipe_config->sdp_split_enable = pipe_config->has_audio &&
2834 intel_dp_is_uhbr(pipe_config);
2835}
2836
2837void intel_dp_queue_modeset_retry_work(struct intel_connector *connector)
2838{
2839 struct drm_i915_private *i915 = to_i915(connector->base.dev);
2840
2841 drm_connector_get(&connector->base);
2842 if (!queue_work(i915->unordered_wq, &connector->modeset_retry_work))
2843 drm_connector_put(&connector->base);
2844}
2845
2846void
2847intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state,
2848 struct intel_encoder *encoder,
2849 const struct intel_crtc_state *crtc_state)
2850{
2851 struct intel_connector *connector;
2852 struct intel_digital_connector_state *conn_state;
2853 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2854 int i;
2855
2856 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
2857 intel_dp_queue_modeset_retry_work(intel_dp->attached_connector);
2858
2859 return;
2860 }
2861
2862 for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
2863 if (!conn_state->base.crtc)
2864 continue;
2865
2866 if (connector->mst_port == intel_dp)
2867 intel_dp_queue_modeset_retry_work(connector);
2868 }
2869}
2870
2871int
2872intel_dp_compute_config(struct intel_encoder *encoder,
2873 struct intel_crtc_state *pipe_config,
2874 struct drm_connector_state *conn_state)
2875{
2876 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2877 struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
2878 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2879 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2880 const struct drm_display_mode *fixed_mode;
2881 struct intel_connector *connector = intel_dp->attached_connector;
2882 int ret = 0, link_bpp_x16;
2883
2884 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
2885 pipe_config->has_pch_encoder = true;
2886
2887 fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
2888 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
2889 ret = intel_panel_compute_config(connector, adjusted_mode);
2890 if (ret)
2891 return ret;
2892 }
2893
2894 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2895 return -EINVAL;
2896
2897 if (!connector->base.interlace_allowed &&
2898 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2899 return -EINVAL;
2900
2901 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2902 return -EINVAL;
2903
2904 if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2905 return -EINVAL;
2906
2907 /*
2908 * Try to respect downstream TMDS clock limits first, if
2909 * that fails assume the user might know something we don't.
2910 */
2911 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
2912 if (ret)
2913 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
2914 if (ret)
2915 return ret;
2916
2917 if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
2918 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2919 ret = intel_panel_fitting(pipe_config, conn_state);
2920 if (ret)
2921 return ret;
2922 }
2923
2924 pipe_config->limited_color_range =
2925 intel_dp_limited_color_range(pipe_config, conn_state);
2926
2927 pipe_config->enhanced_framing =
2928 drm_dp_enhanced_frame_cap(intel_dp->dpcd);
2929
2930 if (pipe_config->dsc.compression_enable)
2931 link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
2932 else
2933 link_bpp_x16 = to_bpp_x16(intel_dp_output_bpp(pipe_config->output_format,
2934 pipe_config->pipe_bpp));
2935
2936 if (intel_dp->mso_link_count) {
2937 int n = intel_dp->mso_link_count;
2938 int overlap = intel_dp->mso_pixel_overlap;
2939
2940 pipe_config->splitter.enable = true;
2941 pipe_config->splitter.link_count = n;
2942 pipe_config->splitter.pixel_overlap = overlap;
2943
2944 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
2945 n, overlap);
2946
2947 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
2948 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
2949 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
2950 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
2951 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
2952 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
2953 adjusted_mode->crtc_clock /= n;
2954 }
2955
2956 intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
2957
2958 intel_link_compute_m_n(link_bpp_x16,
2959 pipe_config->lane_count,
2960 adjusted_mode->crtc_clock,
2961 pipe_config->port_clock,
2962 intel_dp_bw_fec_overhead(pipe_config->fec_enable),
2963 &pipe_config->dp_m_n);
2964
2965 /* FIXME: abstract this better */
2966 if (pipe_config->splitter.enable)
2967 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
2968
2969 if (!HAS_DDI(dev_priv))
2970 g4x_dp_set_clock(encoder, pipe_config);
2971
2972 intel_vrr_compute_config(pipe_config, conn_state);
2973 intel_psr_compute_config(intel_dp, pipe_config, conn_state);
2974 intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
2975 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2976 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2977
2978 return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,
2979 pipe_config);
2980}
2981
2982void intel_dp_set_link_params(struct intel_dp *intel_dp,
2983 int link_rate, int lane_count)
2984{
2985 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2986 intel_dp->link_trained = false;
2987 intel_dp->link_rate = link_rate;
2988 intel_dp->lane_count = lane_count;
2989}
2990
2991static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp)
2992{
2993 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
2994 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
2995}
2996
2997/* Enable backlight PWM and backlight PP control. */
2998void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2999 const struct drm_connector_state *conn_state)
3000{
3001 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
3002 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3003
3004 if (!intel_dp_is_edp(intel_dp))
3005 return;
3006
3007 drm_dbg_kms(&i915->drm, "\n");
3008
3009 intel_backlight_enable(crtc_state, conn_state);
3010 intel_pps_backlight_on(intel_dp);
3011}
3012
3013/* Disable backlight PP control and backlight PWM. */
3014void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3015{
3016 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3017 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3018
3019 if (!intel_dp_is_edp(intel_dp))
3020 return;
3021
3022 drm_dbg_kms(&i915->drm, "\n");
3023
3024 intel_pps_backlight_off(intel_dp);
3025 intel_backlight_disable(old_conn_state);
3026}
3027
3028static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3029{
3030 /*
3031 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3032 * be capable of signalling downstream hpd with a long pulse.
3033 * Whether or not that means D3 is safe to use is not clear,
3034 * but let's assume so until proven otherwise.
3035 *
3036 * FIXME should really check all downstream ports...
3037 */
3038 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3039 drm_dp_is_branch(intel_dp->dpcd) &&
3040 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3041}
3042
3043static int
3044write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set)
3045{
3046 int err;
3047 u8 val;
3048
3049 err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val);
3050 if (err < 0)
3051 return err;
3052
3053 if (set)
3054 val |= flag;
3055 else
3056 val &= ~flag;
3057
3058 return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val);
3059}
3060
3061static void
3062intel_dp_sink_set_dsc_decompression(struct intel_connector *connector,
3063 bool enable)
3064{
3065 struct drm_i915_private *i915 = to_i915(connector->base.dev);
3066
3067 if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux,
3068 DP_DECOMPRESSION_EN, enable) < 0)
3069 drm_dbg_kms(&i915->drm,
3070 "Failed to %s sink decompression state\n",
3071 str_enable_disable(enable));
3072}
3073
3074static void
3075intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,
3076 bool enable)
3077{
3078 struct drm_i915_private *i915 = to_i915(connector->base.dev);
3079 struct drm_dp_aux *aux = connector->port ?
3080 connector->port->passthrough_aux : NULL;
3081
3082 if (!aux)
3083 return;
3084
3085 if (write_dsc_decompression_flag(aux,
3086 DP_DSC_PASSTHROUGH_EN, enable) < 0)
3087 drm_dbg_kms(&i915->drm,
3088 "Failed to %s sink compression passthrough state\n",
3089 str_enable_disable(enable));
3090}
3091
3092static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state,
3093 const struct intel_connector *connector,
3094 bool for_get_ref)
3095{
3096 struct drm_i915_private *i915 = to_i915(state->base.dev);
3097 struct drm_connector *_connector_iter;
3098 struct drm_connector_state *old_conn_state;
3099 struct drm_connector_state *new_conn_state;
3100 int ref_count = 0;
3101 int i;
3102
3103 /*
3104 * On SST the decompression AUX device won't be shared, each connector
3105 * uses for this its own AUX targeting the sink device.
3106 */
3107 if (!connector->mst_port)
3108 return connector->dp.dsc_decompression_enabled ? 1 : 0;
3109
3110 for_each_oldnew_connector_in_state(&state->base, _connector_iter,
3111 old_conn_state, new_conn_state, i) {
3112 const struct intel_connector *
3113 connector_iter = to_intel_connector(_connector_iter);
3114
3115 if (connector_iter->mst_port != connector->mst_port)
3116 continue;
3117
3118 if (!connector_iter->dp.dsc_decompression_enabled)
3119 continue;
3120
3121 drm_WARN_ON(&i915->drm,
3122 (for_get_ref && !new_conn_state->crtc) ||
3123 (!for_get_ref && !old_conn_state->crtc));
3124
3125 if (connector_iter->dp.dsc_decompression_aux ==
3126 connector->dp.dsc_decompression_aux)
3127 ref_count++;
3128 }
3129
3130 return ref_count;
3131}
3132
3133static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state,
3134 struct intel_connector *connector)
3135{
3136 bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0;
3137
3138 connector->dp.dsc_decompression_enabled = true;
3139
3140 return ret;
3141}
3142
3143static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state,
3144 struct intel_connector *connector)
3145{
3146 connector->dp.dsc_decompression_enabled = false;
3147
3148 return intel_dp_dsc_aux_ref_count(state, connector, false) == 0;
3149}
3150
3151/**
3152 * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device
3153 * @state: atomic state
3154 * @connector: connector to enable the decompression for
3155 * @new_crtc_state: new state for the CRTC driving @connector
3156 *
3157 * Enable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3158 * register of the appropriate sink/branch device. On SST this is always the
3159 * sink device, whereas on MST based on each device's DSC capabilities it's
3160 * either the last branch device (enabling decompression in it) or both the
3161 * last branch device (enabling passthrough in it) and the sink device
3162 * (enabling decompression in it).
3163 */
3164void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
3165 struct intel_connector *connector,
3166 const struct intel_crtc_state *new_crtc_state)
3167{
3168 struct drm_i915_private *i915 = to_i915(state->base.dev);
3169
3170 if (!new_crtc_state->dsc.compression_enable)
3171 return;
3172
3173 if (drm_WARN_ON(&i915->drm,
3174 !connector->dp.dsc_decompression_aux ||
3175 connector->dp.dsc_decompression_enabled))
3176 return;
3177
3178 if (!intel_dp_dsc_aux_get_ref(state, connector))
3179 return;
3180
3181 intel_dp_sink_set_dsc_passthrough(connector, true);
3182 intel_dp_sink_set_dsc_decompression(connector, true);
3183}
3184
3185/**
3186 * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device
3187 * @state: atomic state
3188 * @connector: connector to disable the decompression for
3189 * @old_crtc_state: old state for the CRTC driving @connector
3190 *
3191 * Disable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3192 * register of the appropriate sink/branch device, corresponding to the
3193 * sequence in intel_dp_sink_enable_decompression().
3194 */
3195void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
3196 struct intel_connector *connector,
3197 const struct intel_crtc_state *old_crtc_state)
3198{
3199 struct drm_i915_private *i915 = to_i915(state->base.dev);
3200
3201 if (!old_crtc_state->dsc.compression_enable)
3202 return;
3203
3204 if (drm_WARN_ON(&i915->drm,
3205 !connector->dp.dsc_decompression_aux ||
3206 !connector->dp.dsc_decompression_enabled))
3207 return;
3208
3209 if (!intel_dp_dsc_aux_put_ref(state, connector))
3210 return;
3211
3212 intel_dp_sink_set_dsc_decompression(connector, false);
3213 intel_dp_sink_set_dsc_passthrough(connector, false);
3214}
3215
3216static void
3217intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
3218{
3219 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3220 u8 oui[] = { 0x00, 0xaa, 0x01 };
3221 u8 buf[3] = {};
3222
3223 /*
3224 * During driver init, we want to be careful and avoid changing the source OUI if it's
3225 * already set to what we want, so as to avoid clearing any state by accident
3226 */
3227 if (careful) {
3228 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
3229 drm_err(&i915->drm, "Failed to read source OUI\n");
3230
3231 if (memcmp(oui, buf, sizeof(oui)) == 0)
3232 return;
3233 }
3234
3235 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
3236 drm_err(&i915->drm, "Failed to write source OUI\n");
3237
3238 intel_dp->last_oui_write = jiffies;
3239}
3240
3241void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
3242{
3243 struct intel_connector *connector = intel_dp->attached_connector;
3244 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3245
3246 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",
3247 connector->base.base.id, connector->base.name,
3248 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3249
3250 wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,
3251 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3252}
3253
3254/* If the device supports it, try to set the power state appropriately */
3255void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
3256{
3257 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3258 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3259 int ret, i;
3260
3261 /* Should have a valid DPCD by this point */
3262 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3263 return;
3264
3265 if (mode != DP_SET_POWER_D0) {
3266 if (downstream_hpd_needs_d0(intel_dp))
3267 return;
3268
3269 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3270 } else {
3271 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3272
3273 lspcon_resume(dp_to_dig_port(intel_dp));
3274
3275 /* Write the source OUI as early as possible */
3276 if (intel_dp_is_edp(intel_dp))
3277 intel_edp_init_source_oui(intel_dp, false);
3278
3279 /*
3280 * When turning on, we need to retry for 1ms to give the sink
3281 * time to wake up.
3282 */
3283 for (i = 0; i < 3; i++) {
3284 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3285 if (ret == 1)
3286 break;
3287 msleep(1);
3288 }
3289
3290 if (ret == 1 && lspcon->active)
3291 lspcon_wait_pcon_mode(lspcon);
3292 }
3293
3294 if (ret != 1)
3295 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
3296 encoder->base.base.id, encoder->base.name,
3297 mode == DP_SET_POWER_D0 ? "D0" : "D3");
3298}
3299
3300static bool
3301intel_dp_get_dpcd(struct intel_dp *intel_dp);
3302
3303/**
3304 * intel_dp_sync_state - sync the encoder state during init/resume
3305 * @encoder: intel encoder to sync
3306 * @crtc_state: state for the CRTC connected to the encoder
3307 *
3308 * Sync any state stored in the encoder wrt. HW state during driver init
3309 * and system resume.
3310 */
3311void intel_dp_sync_state(struct intel_encoder *encoder,
3312 const struct intel_crtc_state *crtc_state)
3313{
3314 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3315 bool dpcd_updated = false;
3316
3317 /*
3318 * Don't clobber DPCD if it's been already read out during output
3319 * setup (eDP) or detect.
3320 */
3321 if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) {
3322 intel_dp_get_dpcd(intel_dp);
3323 dpcd_updated = true;
3324 }
3325
3326 intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated);
3327
3328 if (crtc_state)
3329 intel_dp_reset_max_link_params(intel_dp);
3330}
3331
3332bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
3333 struct intel_crtc_state *crtc_state)
3334{
3335 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3336 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3337 bool fastset = true;
3338
3339 /*
3340 * If BIOS has set an unsupported or non-standard link rate for some
3341 * reason force an encoder recompute and full modeset.
3342 */
3343 if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
3344 crtc_state->port_clock) < 0) {
3345 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",
3346 encoder->base.base.id, encoder->base.name);
3347 crtc_state->uapi.connectors_changed = true;
3348 fastset = false;
3349 }
3350
3351 /*
3352 * FIXME hack to force full modeset when DSC is being used.
3353 *
3354 * As long as we do not have full state readout and config comparison
3355 * of crtc_state->dsc, we have no way to ensure reliable fastset.
3356 * Remove once we have readout for DSC.
3357 */
3358 if (crtc_state->dsc.compression_enable) {
3359 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",
3360 encoder->base.base.id, encoder->base.name);
3361 crtc_state->uapi.mode_changed = true;
3362 fastset = false;
3363 }
3364
3365 return fastset;
3366}
3367
3368static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
3369{
3370 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3371
3372 /* Clear the cached register set to avoid using stale values */
3373
3374 memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
3375
3376 if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
3377 intel_dp->pcon_dsc_dpcd,
3378 sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
3379 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
3380 DP_PCON_DSC_ENCODER);
3381
3382 drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
3383 (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
3384}
3385
3386static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
3387{
3388 int bw_gbps[] = {9, 18, 24, 32, 40, 48};
3389 int i;
3390
3391 for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
3392 if (frl_bw_mask & (1 << i))
3393 return bw_gbps[i];
3394 }
3395 return 0;
3396}
3397
3398static int intel_dp_pcon_set_frl_mask(int max_frl)
3399{
3400 switch (max_frl) {
3401 case 48:
3402 return DP_PCON_FRL_BW_MASK_48GBPS;
3403 case 40:
3404 return DP_PCON_FRL_BW_MASK_40GBPS;
3405 case 32:
3406 return DP_PCON_FRL_BW_MASK_32GBPS;
3407 case 24:
3408 return DP_PCON_FRL_BW_MASK_24GBPS;
3409 case 18:
3410 return DP_PCON_FRL_BW_MASK_18GBPS;
3411 case 9:
3412 return DP_PCON_FRL_BW_MASK_9GBPS;
3413 }
3414
3415 return 0;
3416}
3417
3418static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
3419{
3420 struct intel_connector *intel_connector = intel_dp->attached_connector;
3421 struct drm_connector *connector = &intel_connector->base;
3422 int max_frl_rate;
3423 int max_lanes, rate_per_lane;
3424 int max_dsc_lanes, dsc_rate_per_lane;
3425
3426 max_lanes = connector->display_info.hdmi.max_lanes;
3427 rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
3428 max_frl_rate = max_lanes * rate_per_lane;
3429
3430 if (connector->display_info.hdmi.dsc_cap.v_1p2) {
3431 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
3432 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
3433 if (max_dsc_lanes && dsc_rate_per_lane)
3434 max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
3435 }
3436
3437 return max_frl_rate;
3438}
3439
3440static bool
3441intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
3442 u8 max_frl_bw_mask, u8 *frl_trained_mask)
3443{
3444 if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&
3445 drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
3446 *frl_trained_mask >= max_frl_bw_mask)
3447 return true;
3448
3449 return false;
3450}
3451
3452static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
3453{
3454#define TIMEOUT_FRL_READY_MS 500
3455#define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
3456
3457 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3458 int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
3459 u8 max_frl_bw_mask = 0, frl_trained_mask;
3460 bool is_active;
3461
3462 max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
3463 drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
3464
3465 max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
3466 drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
3467
3468 max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
3469
3470 if (max_frl_bw <= 0)
3471 return -EINVAL;
3472
3473 max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
3474 drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
3475
3476 if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
3477 goto frl_trained;
3478
3479 ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
3480 if (ret < 0)
3481 return ret;
3482 /* Wait for PCON to be FRL Ready */
3483 wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
3484
3485 if (!is_active)
3486 return -ETIMEDOUT;
3487
3488 ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
3489 DP_PCON_ENABLE_SEQUENTIAL_LINK);
3490 if (ret < 0)
3491 return ret;
3492 ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
3493 DP_PCON_FRL_LINK_TRAIN_NORMAL);
3494 if (ret < 0)
3495 return ret;
3496 ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
3497 if (ret < 0)
3498 return ret;
3499 /*
3500 * Wait for FRL to be completed
3501 * Check if the HDMI Link is up and active.
3502 */
3503 wait_for(is_active =
3504 intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
3505 TIMEOUT_HDMI_LINK_ACTIVE_MS);
3506
3507 if (!is_active)
3508 return -ETIMEDOUT;
3509
3510frl_trained:
3511 drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
3512 intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
3513 intel_dp->frl.is_trained = true;
3514 drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
3515
3516 return 0;
3517}
3518
3519static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
3520{
3521 if (drm_dp_is_branch(intel_dp->dpcd) &&
3522 intel_dp_has_hdmi_sink(intel_dp) &&
3523 intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
3524 return true;
3525
3526 return false;
3527}
3528
3529static
3530int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
3531{
3532 int ret;
3533 u8 buf = 0;
3534
3535 /* Set PCON source control mode */
3536 buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
3537
3538 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3539 if (ret < 0)
3540 return ret;
3541
3542 /* Set HDMI LINK ENABLE */
3543 buf |= DP_PCON_ENABLE_HDMI_LINK;
3544 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3545 if (ret < 0)
3546 return ret;
3547
3548 return 0;
3549}
3550
3551void intel_dp_check_frl_training(struct intel_dp *intel_dp)
3552{
3553 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3554
3555 /*
3556 * Always go for FRL training if:
3557 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
3558 * -sink is HDMI2.1
3559 */
3560 if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
3561 !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
3562 intel_dp->frl.is_trained)
3563 return;
3564
3565 if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
3566 int ret, mode;
3567
3568 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
3569 ret = intel_dp_pcon_set_tmds_mode(intel_dp);
3570 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
3571
3572 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
3573 drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
3574 } else {
3575 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
3576 }
3577}
3578
3579static int
3580intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
3581{
3582 int vactive = crtc_state->hw.adjusted_mode.vdisplay;
3583
3584 return intel_hdmi_dsc_get_slice_height(vactive);
3585}
3586
3587static int
3588intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
3589 const struct intel_crtc_state *crtc_state)
3590{
3591 struct intel_connector *intel_connector = intel_dp->attached_connector;
3592 struct drm_connector *connector = &intel_connector->base;
3593 int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
3594 int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
3595 int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
3596 int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
3597
3598 return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
3599 pcon_max_slice_width,
3600 hdmi_max_slices, hdmi_throughput);
3601}
3602
3603static int
3604intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
3605 const struct intel_crtc_state *crtc_state,
3606 int num_slices, int slice_width)
3607{
3608 struct intel_connector *intel_connector = intel_dp->attached_connector;
3609 struct drm_connector *connector = &intel_connector->base;
3610 int output_format = crtc_state->output_format;
3611 bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
3612 int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
3613 int hdmi_max_chunk_bytes =
3614 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
3615
3616 return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
3617 num_slices, output_format, hdmi_all_bpp,
3618 hdmi_max_chunk_bytes);
3619}
3620
3621void
3622intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
3623 const struct intel_crtc_state *crtc_state)
3624{
3625 u8 pps_param[6];
3626 int slice_height;
3627 int slice_width;
3628 int num_slices;
3629 int bits_per_pixel;
3630 int ret;
3631 struct intel_connector *intel_connector = intel_dp->attached_connector;
3632 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3633 struct drm_connector *connector;
3634 bool hdmi_is_dsc_1_2;
3635
3636 if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
3637 return;
3638
3639 if (!intel_connector)
3640 return;
3641 connector = &intel_connector->base;
3642 hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
3643
3644 if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
3645 !hdmi_is_dsc_1_2)
3646 return;
3647
3648 slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
3649 if (!slice_height)
3650 return;
3651
3652 num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
3653 if (!num_slices)
3654 return;
3655
3656 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
3657 num_slices);
3658
3659 bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
3660 num_slices, slice_width);
3661 if (!bits_per_pixel)
3662 return;
3663
3664 pps_param[0] = slice_height & 0xFF;
3665 pps_param[1] = slice_height >> 8;
3666 pps_param[2] = slice_width & 0xFF;
3667 pps_param[3] = slice_width >> 8;
3668 pps_param[4] = bits_per_pixel & 0xFF;
3669 pps_param[5] = (bits_per_pixel >> 8) & 0x3;
3670
3671 ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
3672 if (ret < 0)
3673 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
3674}
3675
3676void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
3677 const struct intel_crtc_state *crtc_state)
3678{
3679 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3680 bool ycbcr444_to_420 = false;
3681 bool rgb_to_ycbcr = false;
3682 u8 tmp;
3683
3684 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
3685 return;
3686
3687 if (!drm_dp_is_branch(intel_dp->dpcd))
3688 return;
3689
3690 tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0;
3691
3692 if (drm_dp_dpcd_writeb(&intel_dp->aux,
3693 DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
3694 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
3695 str_enable_disable(intel_dp_has_hdmi_sink(intel_dp)));
3696
3697 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3698 switch (crtc_state->output_format) {
3699 case INTEL_OUTPUT_FORMAT_YCBCR420:
3700 break;
3701 case INTEL_OUTPUT_FORMAT_YCBCR444:
3702 ycbcr444_to_420 = true;
3703 break;
3704 case INTEL_OUTPUT_FORMAT_RGB:
3705 rgb_to_ycbcr = true;
3706 ycbcr444_to_420 = true;
3707 break;
3708 default:
3709 MISSING_CASE(crtc_state->output_format);
3710 break;
3711 }
3712 } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
3713 switch (crtc_state->output_format) {
3714 case INTEL_OUTPUT_FORMAT_YCBCR444:
3715 break;
3716 case INTEL_OUTPUT_FORMAT_RGB:
3717 rgb_to_ycbcr = true;
3718 break;
3719 default:
3720 MISSING_CASE(crtc_state->output_format);
3721 break;
3722 }
3723 }
3724
3725 tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
3726
3727 if (drm_dp_dpcd_writeb(&intel_dp->aux,
3728 DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
3729 drm_dbg_kms(&i915->drm,
3730 "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
3731 str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
3732
3733 tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
3734
3735 if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
3736 drm_dbg_kms(&i915->drm,
3737 "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
3738 str_enable_disable(tmp));
3739}
3740
3741bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3742{
3743 u8 dprx = 0;
3744
3745 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
3746 &dprx) != 1)
3747 return false;
3748 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3749}
3750
3751static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux,
3752 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
3753{
3754 if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, dsc_dpcd,
3755 DP_DSC_RECEIVER_CAP_SIZE) < 0) {
3756 drm_err(aux->drm_dev,
3757 "Failed to read DPCD register 0x%x\n",
3758 DP_DSC_SUPPORT);
3759 return;
3760 }
3761
3762 drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n",
3763 DP_DSC_RECEIVER_CAP_SIZE,
3764 dsc_dpcd);
3765}
3766
3767void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector)
3768{
3769 struct drm_i915_private *i915 = to_i915(connector->base.dev);
3770
3771 /*
3772 * Clear the cached register set to avoid using stale values
3773 * for the sinks that do not support DSC.
3774 */
3775 memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
3776
3777 /* Clear fec_capable to avoid using stale values */
3778 connector->dp.fec_capability = 0;
3779
3780 if (dpcd_rev < DP_DPCD_REV_14)
3781 return;
3782
3783 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux,
3784 connector->dp.dsc_dpcd);
3785
3786 if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY,
3787 &connector->dp.fec_capability) < 0) {
3788 drm_err(&i915->drm, "Failed to read FEC DPCD register\n");
3789 return;
3790 }
3791
3792 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
3793 connector->dp.fec_capability);
3794}
3795
3796static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
3797{
3798 if (edp_dpcd_rev < DP_EDP_14)
3799 return;
3800
3801 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd);
3802}
3803
3804static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
3805 struct drm_display_mode *mode)
3806{
3807 struct intel_dp *intel_dp = intel_attached_dp(connector);
3808 struct drm_i915_private *i915 = to_i915(connector->base.dev);
3809 int n = intel_dp->mso_link_count;
3810 int overlap = intel_dp->mso_pixel_overlap;
3811
3812 if (!mode || !n)
3813 return;
3814
3815 mode->hdisplay = (mode->hdisplay - overlap) * n;
3816 mode->hsync_start = (mode->hsync_start - overlap) * n;
3817 mode->hsync_end = (mode->hsync_end - overlap) * n;
3818 mode->htotal = (mode->htotal - overlap) * n;
3819 mode->clock *= n;
3820
3821 drm_mode_set_name(mode);
3822
3823 drm_dbg_kms(&i915->drm,
3824 "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
3825 connector->base.base.id, connector->base.name,
3826 DRM_MODE_ARG(mode));
3827}
3828
3829void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
3830{
3831 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3832 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3833 struct intel_connector *connector = intel_dp->attached_connector;
3834
3835 if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {
3836 /*
3837 * This is a big fat ugly hack.
3838 *
3839 * Some machines in UEFI boot mode provide us a VBT that has 18
3840 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3841 * unknown we fail to light up. Yet the same BIOS boots up with
3842 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3843 * max, not what it tells us to use.
3844 *
3845 * Note: This will still be broken if the eDP panel is not lit
3846 * up by the BIOS, and thus we can't get the mode at module
3847 * load.
3848 */
3849 drm_dbg_kms(&dev_priv->drm,
3850 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3851 pipe_bpp, connector->panel.vbt.edp.bpp);
3852 connector->panel.vbt.edp.bpp = pipe_bpp;
3853 }
3854}
3855
3856static void intel_edp_mso_init(struct intel_dp *intel_dp)
3857{
3858 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3859 struct intel_connector *connector = intel_dp->attached_connector;
3860 struct drm_display_info *info = &connector->base.display_info;
3861 u8 mso;
3862
3863 if (intel_dp->edp_dpcd[0] < DP_EDP_14)
3864 return;
3865
3866 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
3867 drm_err(&i915->drm, "Failed to read MSO cap\n");
3868 return;
3869 }
3870
3871 /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
3872 mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
3873 if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
3874 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
3875 mso = 0;
3876 }
3877
3878 if (mso) {
3879 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
3880 mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
3881 info->mso_pixel_overlap);
3882 if (!HAS_MSO(i915)) {
3883 drm_err(&i915->drm, "No source MSO support, disabling\n");
3884 mso = 0;
3885 }
3886 }
3887
3888 intel_dp->mso_link_count = mso;
3889 intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
3890}
3891
3892static bool
3893intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
3894{
3895 struct drm_i915_private *dev_priv =
3896 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3897
3898 /* this function is meant to be called only once */
3899 drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
3900
3901 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
3902 return false;
3903
3904 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3905 drm_dp_is_branch(intel_dp->dpcd));
3906
3907 /*
3908 * Read the eDP display control registers.
3909 *
3910 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3911 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3912 * set, but require eDP 1.4+ detection (e.g. for supported link rates
3913 * method). The display control registers should read zero if they're
3914 * not supported anyway.
3915 */
3916 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3917 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3918 sizeof(intel_dp->edp_dpcd)) {
3919 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
3920 (int)sizeof(intel_dp->edp_dpcd),
3921 intel_dp->edp_dpcd);
3922
3923 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
3924 }
3925
3926 /*
3927 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
3928 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
3929 */
3930 intel_psr_init_dpcd(intel_dp);
3931
3932 /* Clear the default sink rates */
3933 intel_dp->num_sink_rates = 0;
3934
3935 /* Read the eDP 1.4+ supported link rates. */
3936 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3937 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3938 int i;
3939
3940 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3941 sink_rates, sizeof(sink_rates));
3942
3943 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3944 int val = le16_to_cpu(sink_rates[i]);
3945
3946 if (val == 0)
3947 break;
3948
3949 /* Value read multiplied by 200kHz gives the per-lane
3950 * link rate in kHz. The source rates are, however,
3951 * stored in terms of LS_Clk kHz. The full conversion
3952 * back to symbols is
3953 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3954 */
3955 intel_dp->sink_rates[i] = (val * 200) / 10;
3956 }
3957 intel_dp->num_sink_rates = i;
3958 }
3959
3960 /*
3961 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3962 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3963 */
3964 if (intel_dp->num_sink_rates)
3965 intel_dp->use_rate_select = true;
3966 else
3967 intel_dp_set_sink_rates(intel_dp);
3968 intel_dp_set_max_sink_lane_count(intel_dp);
3969
3970 /* Read the eDP DSC DPCD registers */
3971 if (HAS_DSC(dev_priv))
3972 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],
3973 connector);
3974
3975 /*
3976 * If needed, program our source OUI so we can make various Intel-specific AUX services
3977 * available (such as HDR backlight controls)
3978 */
3979 intel_edp_init_source_oui(intel_dp, true);
3980
3981 return true;
3982}
3983
3984static bool
3985intel_dp_has_sink_count(struct intel_dp *intel_dp)
3986{
3987 if (!intel_dp->attached_connector)
3988 return false;
3989
3990 return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
3991 intel_dp->dpcd,
3992 &intel_dp->desc);
3993}
3994
3995void intel_dp_update_sink_caps(struct intel_dp *intel_dp)
3996{
3997 intel_dp_set_sink_rates(intel_dp);
3998 intel_dp_set_max_sink_lane_count(intel_dp);
3999 intel_dp_set_common_rates(intel_dp);
4000}
4001
4002static bool
4003intel_dp_get_dpcd(struct intel_dp *intel_dp)
4004{
4005 int ret;
4006
4007 if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
4008 return false;
4009
4010 /*
4011 * Don't clobber cached eDP rates. Also skip re-reading
4012 * the OUI/ID since we know it won't change.
4013 */
4014 if (!intel_dp_is_edp(intel_dp)) {
4015 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4016 drm_dp_is_branch(intel_dp->dpcd));
4017
4018 intel_dp_update_sink_caps(intel_dp);
4019 }
4020
4021 if (intel_dp_has_sink_count(intel_dp)) {
4022 ret = drm_dp_read_sink_count(&intel_dp->aux);
4023 if (ret < 0)
4024 return false;
4025
4026 /*
4027 * Sink count can change between short pulse hpd hence
4028 * a member variable in intel_dp will track any changes
4029 * between short pulse interrupts.
4030 */
4031 intel_dp->sink_count = ret;
4032
4033 /*
4034 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4035 * a dongle is present but no display. Unless we require to know
4036 * if a dongle is present or not, we don't need to update
4037 * downstream port information. So, an early return here saves
4038 * time from performing other operations which are not required.
4039 */
4040 if (!intel_dp->sink_count)
4041 return false;
4042 }
4043
4044 return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
4045 intel_dp->downstream_ports) == 0;
4046}
4047
4048static bool
4049intel_dp_can_mst(struct intel_dp *intel_dp)
4050{
4051 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4052
4053 return i915->display.params.enable_dp_mst &&
4054 intel_dp_mst_source_support(intel_dp) &&
4055 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4056}
4057
4058static void
4059intel_dp_configure_mst(struct intel_dp *intel_dp)
4060{
4061 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4062 struct intel_encoder *encoder =
4063 &dp_to_dig_port(intel_dp)->base;
4064 bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4065
4066 drm_dbg_kms(&i915->drm,
4067 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
4068 encoder->base.base.id, encoder->base.name,
4069 str_yes_no(intel_dp_mst_source_support(intel_dp)),
4070 str_yes_no(sink_can_mst),
4071 str_yes_no(i915->display.params.enable_dp_mst));
4072
4073 if (!intel_dp_mst_source_support(intel_dp))
4074 return;
4075
4076 intel_dp->is_mst = sink_can_mst &&
4077 i915->display.params.enable_dp_mst;
4078
4079 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4080 intel_dp->is_mst);
4081}
4082
4083static bool
4084intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
4085{
4086 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
4087}
4088
4089static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
4090{
4091 int retry;
4092
4093 for (retry = 0; retry < 3; retry++) {
4094 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
4095 &esi[1], 3) == 3)
4096 return true;
4097 }
4098
4099 return false;
4100}
4101
4102bool
4103intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4104 const struct drm_connector_state *conn_state)
4105{
4106 /*
4107 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4108 * of Color Encoding Format and Content Color Gamut], in order to
4109 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4110 */
4111 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4112 return true;
4113
4114 switch (conn_state->colorspace) {
4115 case DRM_MODE_COLORIMETRY_SYCC_601:
4116 case DRM_MODE_COLORIMETRY_OPYCC_601:
4117 case DRM_MODE_COLORIMETRY_BT2020_YCC:
4118 case DRM_MODE_COLORIMETRY_BT2020_RGB:
4119 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4120 return true;
4121 default:
4122 break;
4123 }
4124
4125 return false;
4126}
4127
4128static ssize_t
4129intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
4130 const struct hdmi_drm_infoframe *drm_infoframe,
4131 struct dp_sdp *sdp,
4132 size_t size)
4133{
4134 size_t length = sizeof(struct dp_sdp);
4135 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
4136 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
4137 ssize_t len;
4138
4139 if (size < length)
4140 return -ENOSPC;
4141
4142 memset(sdp, 0, size);
4143
4144 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
4145 if (len < 0) {
4146 drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
4147 return -ENOSPC;
4148 }
4149
4150 if (len != infoframe_size) {
4151 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
4152 return -ENOSPC;
4153 }
4154
4155 /*
4156 * Set up the infoframe sdp packet for HDR static metadata.
4157 * Prepare VSC Header for SU as per DP 1.4a spec,
4158 * Table 2-100 and Table 2-101
4159 */
4160
4161 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
4162 sdp->sdp_header.HB0 = 0;
4163 /*
4164 * Packet Type 80h + Non-audio INFOFRAME Type value
4165 * HDMI_INFOFRAME_TYPE_DRM: 0x87
4166 * - 80h + Non-audio INFOFRAME Type value
4167 * - InfoFrame Type: 0x07
4168 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
4169 */
4170 sdp->sdp_header.HB1 = drm_infoframe->type;
4171 /*
4172 * Least Significant Eight Bits of (Data Byte Count – 1)
4173 * infoframe_size - 1
4174 */
4175 sdp->sdp_header.HB2 = 0x1D;
4176 /* INFOFRAME SDP Version Number */
4177 sdp->sdp_header.HB3 = (0x13 << 2);
4178 /* CTA Header Byte 2 (INFOFRAME Version Number) */
4179 sdp->db[0] = drm_infoframe->version;
4180 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4181 sdp->db[1] = drm_infoframe->length;
4182 /*
4183 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
4184 * HDMI_INFOFRAME_HEADER_SIZE
4185 */
4186 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
4187 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
4188 HDMI_DRM_INFOFRAME_SIZE);
4189
4190 /*
4191 * Size of DP infoframe sdp packet for HDR static metadata consists of
4192 * - DP SDP Header(struct dp_sdp_header): 4 bytes
4193 * - Two Data Blocks: 2 bytes
4194 * CTA Header Byte2 (INFOFRAME Version Number)
4195 * CTA Header Byte3 (Length of INFOFRAME)
4196 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
4197 *
4198 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
4199 * infoframe size. But GEN11+ has larger than that size, write_infoframe
4200 * will pad rest of the size.
4201 */
4202 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
4203}
4204
4205static void intel_write_dp_sdp(struct intel_encoder *encoder,
4206 const struct intel_crtc_state *crtc_state,
4207 unsigned int type)
4208{
4209 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4210 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4211 struct dp_sdp sdp = {};
4212 ssize_t len;
4213
4214 if ((crtc_state->infoframes.enable &
4215 intel_hdmi_infoframe_enable(type)) == 0)
4216 return;
4217
4218 switch (type) {
4219 case DP_SDP_VSC:
4220 len = drm_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp);
4221 break;
4222 case HDMI_PACKET_TYPE_GAMUT_METADATA:
4223 len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
4224 &crtc_state->infoframes.drm.drm,
4225 &sdp, sizeof(sdp));
4226 break;
4227 default:
4228 MISSING_CASE(type);
4229 return;
4230 }
4231
4232 if (drm_WARN_ON(&dev_priv->drm, len < 0))
4233 return;
4234
4235 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
4236}
4237
4238void intel_dp_set_infoframes(struct intel_encoder *encoder,
4239 bool enable,
4240 const struct intel_crtc_state *crtc_state,
4241 const struct drm_connector_state *conn_state)
4242{
4243 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4244 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
4245 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
4246 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
4247 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
4248 u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
4249
4250 /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
4251 if (!enable && HAS_DSC(dev_priv))
4252 val &= ~VDIP_ENABLE_PPS;
4253
4254 /* When PSR is enabled, this routine doesn't disable VSC DIP */
4255 if (!crtc_state->has_psr)
4256 val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
4257
4258 intel_de_write(dev_priv, reg, val);
4259 intel_de_posting_read(dev_priv, reg);
4260
4261 if (!enable)
4262 return;
4263
4264 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
4265
4266 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
4267}
4268
4269static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
4270 const void *buffer, size_t size)
4271{
4272 const struct dp_sdp *sdp = buffer;
4273
4274 if (size < sizeof(struct dp_sdp))
4275 return -EINVAL;
4276
4277 memset(vsc, 0, sizeof(*vsc));
4278
4279 if (sdp->sdp_header.HB0 != 0)
4280 return -EINVAL;
4281
4282 if (sdp->sdp_header.HB1 != DP_SDP_VSC)
4283 return -EINVAL;
4284
4285 vsc->sdp_type = sdp->sdp_header.HB1;
4286 vsc->revision = sdp->sdp_header.HB2;
4287 vsc->length = sdp->sdp_header.HB3;
4288
4289 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
4290 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
4291 /*
4292 * - HB2 = 0x2, HB3 = 0x8
4293 * VSC SDP supporting 3D stereo + PSR
4294 * - HB2 = 0x4, HB3 = 0xe
4295 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
4296 * first scan line of the SU region (applies to eDP v1.4b
4297 * and higher).
4298 */
4299 return 0;
4300 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
4301 /*
4302 * - HB2 = 0x5, HB3 = 0x13
4303 * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
4304 * Format.
4305 */
4306 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
4307 vsc->colorimetry = sdp->db[16] & 0xf;
4308 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
4309
4310 switch (sdp->db[17] & 0x7) {
4311 case 0x0:
4312 vsc->bpc = 6;
4313 break;
4314 case 0x1:
4315 vsc->bpc = 8;
4316 break;
4317 case 0x2:
4318 vsc->bpc = 10;
4319 break;
4320 case 0x3:
4321 vsc->bpc = 12;
4322 break;
4323 case 0x4:
4324 vsc->bpc = 16;
4325 break;
4326 default:
4327 MISSING_CASE(sdp->db[17] & 0x7);
4328 return -EINVAL;
4329 }
4330
4331 vsc->content_type = sdp->db[18] & 0x7;
4332 } else {
4333 return -EINVAL;
4334 }
4335
4336 return 0;
4337}
4338
4339static int
4340intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
4341 const void *buffer, size_t size)
4342{
4343 int ret;
4344
4345 const struct dp_sdp *sdp = buffer;
4346
4347 if (size < sizeof(struct dp_sdp))
4348 return -EINVAL;
4349
4350 if (sdp->sdp_header.HB0 != 0)
4351 return -EINVAL;
4352
4353 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
4354 return -EINVAL;
4355
4356 /*
4357 * Least Significant Eight Bits of (Data Byte Count – 1)
4358 * 1Dh (i.e., Data Byte Count = 30 bytes).
4359 */
4360 if (sdp->sdp_header.HB2 != 0x1D)
4361 return -EINVAL;
4362
4363 /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
4364 if ((sdp->sdp_header.HB3 & 0x3) != 0)
4365 return -EINVAL;
4366
4367 /* INFOFRAME SDP Version Number */
4368 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
4369 return -EINVAL;
4370
4371 /* CTA Header Byte 2 (INFOFRAME Version Number) */
4372 if (sdp->db[0] != 1)
4373 return -EINVAL;
4374
4375 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4376 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
4377 return -EINVAL;
4378
4379 ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
4380 HDMI_DRM_INFOFRAME_SIZE);
4381
4382 return ret;
4383}
4384
4385static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
4386 struct intel_crtc_state *crtc_state,
4387 struct drm_dp_vsc_sdp *vsc)
4388{
4389 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4390 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4391 unsigned int type = DP_SDP_VSC;
4392 struct dp_sdp sdp = {};
4393 int ret;
4394
4395 if ((crtc_state->infoframes.enable &
4396 intel_hdmi_infoframe_enable(type)) == 0)
4397 return;
4398
4399 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
4400
4401 ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
4402
4403 if (ret)
4404 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
4405}
4406
4407static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
4408 struct intel_crtc_state *crtc_state,
4409 struct hdmi_drm_infoframe *drm_infoframe)
4410{
4411 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4412 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4413 unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
4414 struct dp_sdp sdp = {};
4415 int ret;
4416
4417 if ((crtc_state->infoframes.enable &
4418 intel_hdmi_infoframe_enable(type)) == 0)
4419 return;
4420
4421 dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
4422 sizeof(sdp));
4423
4424 ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
4425 sizeof(sdp));
4426
4427 if (ret)
4428 drm_dbg_kms(&dev_priv->drm,
4429 "Failed to unpack DP HDR Metadata Infoframe SDP\n");
4430}
4431
4432void intel_read_dp_sdp(struct intel_encoder *encoder,
4433 struct intel_crtc_state *crtc_state,
4434 unsigned int type)
4435{
4436 switch (type) {
4437 case DP_SDP_VSC:
4438 intel_read_dp_vsc_sdp(encoder, crtc_state,
4439 &crtc_state->infoframes.vsc);
4440 break;
4441 case HDMI_PACKET_TYPE_GAMUT_METADATA:
4442 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
4443 &crtc_state->infoframes.drm.drm);
4444 break;
4445 default:
4446 MISSING_CASE(type);
4447 break;
4448 }
4449}
4450
4451static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4452{
4453 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4454 int status = 0;
4455 int test_link_rate;
4456 u8 test_lane_count, test_link_bw;
4457 /* (DP CTS 1.2)
4458 * 4.3.1.11
4459 */
4460 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4461 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4462 &test_lane_count);
4463
4464 if (status <= 0) {
4465 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
4466 return DP_TEST_NAK;
4467 }
4468 test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4469
4470 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4471 &test_link_bw);
4472 if (status <= 0) {
4473 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
4474 return DP_TEST_NAK;
4475 }
4476 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4477
4478 /* Validate the requested link rate and lane count */
4479 if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4480 test_lane_count))
4481 return DP_TEST_NAK;
4482
4483 intel_dp->compliance.test_lane_count = test_lane_count;
4484 intel_dp->compliance.test_link_rate = test_link_rate;
4485
4486 return DP_TEST_ACK;
4487}
4488
4489static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4490{
4491 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4492 u8 test_pattern;
4493 u8 test_misc;
4494 __be16 h_width, v_height;
4495 int status = 0;
4496
4497 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4498 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4499 &test_pattern);
4500 if (status <= 0) {
4501 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
4502 return DP_TEST_NAK;
4503 }
4504 if (test_pattern != DP_COLOR_RAMP)
4505 return DP_TEST_NAK;
4506
4507 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4508 &h_width, 2);
4509 if (status <= 0) {
4510 drm_dbg_kms(&i915->drm, "H Width read failed\n");
4511 return DP_TEST_NAK;
4512 }
4513
4514 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4515 &v_height, 2);
4516 if (status <= 0) {
4517 drm_dbg_kms(&i915->drm, "V Height read failed\n");
4518 return DP_TEST_NAK;
4519 }
4520
4521 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4522 &test_misc);
4523 if (status <= 0) {
4524 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
4525 return DP_TEST_NAK;
4526 }
4527 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4528 return DP_TEST_NAK;
4529 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4530 return DP_TEST_NAK;
4531 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4532 case DP_TEST_BIT_DEPTH_6:
4533 intel_dp->compliance.test_data.bpc = 6;
4534 break;
4535 case DP_TEST_BIT_DEPTH_8:
4536 intel_dp->compliance.test_data.bpc = 8;
4537 break;
4538 default:
4539 return DP_TEST_NAK;
4540 }
4541
4542 intel_dp->compliance.test_data.video_pattern = test_pattern;
4543 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4544 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4545 /* Set test active flag here so userspace doesn't interrupt things */
4546 intel_dp->compliance.test_active = true;
4547
4548 return DP_TEST_ACK;
4549}
4550
4551static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
4552{
4553 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4554 u8 test_result = DP_TEST_ACK;
4555 struct intel_connector *intel_connector = intel_dp->attached_connector;
4556 struct drm_connector *connector = &intel_connector->base;
4557
4558 if (intel_connector->detect_edid == NULL ||
4559 connector->edid_corrupt ||
4560 intel_dp->aux.i2c_defer_count > 6) {
4561 /* Check EDID read for NACKs, DEFERs and corruption
4562 * (DP CTS 1.2 Core r1.1)
4563 * 4.2.2.4 : Failed EDID read, I2C_NAK
4564 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4565 * 4.2.2.6 : EDID corruption detected
4566 * Use failsafe mode for all cases
4567 */
4568 if (intel_dp->aux.i2c_nack_count > 0 ||
4569 intel_dp->aux.i2c_defer_count > 0)
4570 drm_dbg_kms(&i915->drm,
4571 "EDID read had %d NACKs, %d DEFERs\n",
4572 intel_dp->aux.i2c_nack_count,
4573 intel_dp->aux.i2c_defer_count);
4574 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4575 } else {
4576 /* FIXME: Get rid of drm_edid_raw() */
4577 const struct edid *block = drm_edid_raw(intel_connector->detect_edid);
4578
4579 /* We have to write the checksum of the last block read */
4580 block += block->extensions;
4581
4582 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4583 block->checksum) <= 0)
4584 drm_dbg_kms(&i915->drm,
4585 "Failed to write EDID checksum\n");
4586
4587 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4588 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4589 }
4590
4591 /* Set test active flag here so userspace doesn't interrupt things */
4592 intel_dp->compliance.test_active = true;
4593
4594 return test_result;
4595}
4596
4597static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
4598 const struct intel_crtc_state *crtc_state)
4599{
4600 struct drm_i915_private *dev_priv =
4601 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4602 struct drm_dp_phy_test_params *data =
4603 &intel_dp->compliance.test_data.phytest;
4604 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4605 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4606 enum pipe pipe = crtc->pipe;
4607 u32 pattern_val;
4608
4609 switch (data->phy_pattern) {
4610 case DP_LINK_QUAL_PATTERN_DISABLE:
4611 drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");
4612 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
4613 if (DISPLAY_VER(dev_priv) >= 10)
4614 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
4615 DP_TP_CTL_TRAIN_PAT4_SEL_MASK | DP_TP_CTL_LINK_TRAIN_MASK,
4616 DP_TP_CTL_LINK_TRAIN_NORMAL);
4617 break;
4618 case DP_LINK_QUAL_PATTERN_D10_2:
4619 drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");
4620 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4621 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
4622 break;
4623 case DP_LINK_QUAL_PATTERN_ERROR_RATE:
4624 drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");
4625 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4626 DDI_DP_COMP_CTL_ENABLE |
4627 DDI_DP_COMP_CTL_SCRAMBLED_0);
4628 break;
4629 case DP_LINK_QUAL_PATTERN_PRBS7:
4630 drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");
4631 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4632 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
4633 break;
4634 case DP_LINK_QUAL_PATTERN_80BIT_CUSTOM:
4635 /*
4636 * FIXME: Ideally pattern should come from DPCD 0x250. As
4637 * current firmware of DPR-100 could not set it, so hardcoding
4638 * now for complaince test.
4639 */
4640 drm_dbg_kms(&dev_priv->drm,
4641 "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
4642 pattern_val = 0x3e0f83e0;
4643 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
4644 pattern_val = 0x0f83e0f8;
4645 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
4646 pattern_val = 0x0000f83e;
4647 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
4648 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4649 DDI_DP_COMP_CTL_ENABLE |
4650 DDI_DP_COMP_CTL_CUSTOM80);
4651 break;
4652 case DP_LINK_QUAL_PATTERN_CP2520_PAT_1:
4653 /*
4654 * FIXME: Ideally pattern should come from DPCD 0x24A. As
4655 * current firmware of DPR-100 could not set it, so hardcoding
4656 * now for complaince test.
4657 */
4658 drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n");
4659 pattern_val = 0xFB;
4660 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4661 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
4662 pattern_val);
4663 break;
4664 case DP_LINK_QUAL_PATTERN_CP2520_PAT_3:
4665 if (DISPLAY_VER(dev_priv) < 10) {
4666 drm_warn(&dev_priv->drm, "Platform does not support TPS4\n");
4667 break;
4668 }
4669 drm_dbg_kms(&dev_priv->drm, "Set TPS4 compliance Phy Test Pattern\n");
4670 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
4671 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
4672 DP_TP_CTL_TRAIN_PAT4_SEL_MASK | DP_TP_CTL_LINK_TRAIN_MASK,
4673 DP_TP_CTL_TRAIN_PAT4_SEL_TP4A | DP_TP_CTL_LINK_TRAIN_PAT4);
4674 break;
4675 default:
4676 drm_warn(&dev_priv->drm, "Invalid Phy Test Pattern\n");
4677 }
4678}
4679
4680static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
4681 const struct intel_crtc_state *crtc_state)
4682{
4683 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4684 struct drm_dp_phy_test_params *data =
4685 &intel_dp->compliance.test_data.phytest;
4686 u8 link_status[DP_LINK_STATUS_SIZE];
4687
4688 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
4689 link_status) < 0) {
4690 drm_dbg_kms(&i915->drm, "failed to get link status\n");
4691 return;
4692 }
4693
4694 /* retrieve vswing & pre-emphasis setting */
4695 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
4696 link_status);
4697
4698 intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
4699
4700 intel_dp_phy_pattern_update(intel_dp, crtc_state);
4701
4702 drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
4703 intel_dp->train_set, crtc_state->lane_count);
4704
4705 drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
4706 intel_dp->dpcd[DP_DPCD_REV]);
4707}
4708
4709static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4710{
4711 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4712 struct drm_dp_phy_test_params *data =
4713 &intel_dp->compliance.test_data.phytest;
4714
4715 if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
4716 drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n");
4717 return DP_TEST_NAK;
4718 }
4719
4720 /* Set test active flag here so userspace doesn't interrupt things */
4721 intel_dp->compliance.test_active = true;
4722
4723 return DP_TEST_ACK;
4724}
4725
4726static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4727{
4728 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4729 u8 response = DP_TEST_NAK;
4730 u8 request = 0;
4731 int status;
4732
4733 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4734 if (status <= 0) {
4735 drm_dbg_kms(&i915->drm,
4736 "Could not read test request from sink\n");
4737 goto update_status;
4738 }
4739
4740 switch (request) {
4741 case DP_TEST_LINK_TRAINING:
4742 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
4743 response = intel_dp_autotest_link_training(intel_dp);
4744 break;
4745 case DP_TEST_LINK_VIDEO_PATTERN:
4746 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
4747 response = intel_dp_autotest_video_pattern(intel_dp);
4748 break;
4749 case DP_TEST_LINK_EDID_READ:
4750 drm_dbg_kms(&i915->drm, "EDID test requested\n");
4751 response = intel_dp_autotest_edid(intel_dp);
4752 break;
4753 case DP_TEST_LINK_PHY_TEST_PATTERN:
4754 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
4755 response = intel_dp_autotest_phy_pattern(intel_dp);
4756 break;
4757 default:
4758 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
4759 request);
4760 break;
4761 }
4762
4763 if (response & DP_TEST_ACK)
4764 intel_dp->compliance.test_type = request;
4765
4766update_status:
4767 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4768 if (status <= 0)
4769 drm_dbg_kms(&i915->drm,
4770 "Could not write test response to sink\n");
4771}
4772
4773static bool intel_dp_link_ok(struct intel_dp *intel_dp,
4774 u8 link_status[DP_LINK_STATUS_SIZE])
4775{
4776 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4777 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4778 bool uhbr = intel_dp->link_rate >= 1000000;
4779 bool ok;
4780
4781 if (uhbr)
4782 ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
4783 intel_dp->lane_count);
4784 else
4785 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4786
4787 if (ok)
4788 return true;
4789
4790 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
4791 drm_dbg_kms(&i915->drm,
4792 "[ENCODER:%d:%s] %s link not ok, retraining\n",
4793 encoder->base.base.id, encoder->base.name,
4794 uhbr ? "128b/132b" : "8b/10b");
4795
4796 return false;
4797}
4798
4799static void
4800intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
4801{
4802 bool handled = false;
4803
4804 drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled);
4805
4806 if (esi[1] & DP_CP_IRQ) {
4807 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4808 ack[1] |= DP_CP_IRQ;
4809 }
4810}
4811
4812static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
4813{
4814 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4815 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4816 u8 link_status[DP_LINK_STATUS_SIZE] = {};
4817 const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
4818
4819 if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
4820 esi_link_status_size) != esi_link_status_size) {
4821 drm_err(&i915->drm,
4822 "[ENCODER:%d:%s] Failed to read link status\n",
4823 encoder->base.base.id, encoder->base.name);
4824 return false;
4825 }
4826
4827 return intel_dp_link_ok(intel_dp, link_status);
4828}
4829
4830/**
4831 * intel_dp_check_mst_status - service any pending MST interrupts, check link status
4832 * @intel_dp: Intel DP struct
4833 *
4834 * Read any pending MST interrupts, call MST core to handle these and ack the
4835 * interrupts. Check if the main and AUX link state is ok.
4836 *
4837 * Returns:
4838 * - %true if pending interrupts were serviced (or no interrupts were
4839 * pending) w/o detecting an error condition.
4840 * - %false if an error condition - like AUX failure or a loss of link - is
4841 * detected, or another condition - like a DP tunnel BW state change - needs
4842 * servicing from the hotplug work.
4843 */
4844static bool
4845intel_dp_check_mst_status(struct intel_dp *intel_dp)
4846{
4847 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4848 bool link_ok = true;
4849 bool reprobe_needed = false;
4850
4851 drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
4852
4853 for (;;) {
4854 u8 esi[4] = {};
4855 u8 ack[4] = {};
4856
4857 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
4858 drm_dbg_kms(&i915->drm,
4859 "failed to get ESI - device may have failed\n");
4860 link_ok = false;
4861
4862 break;
4863 }
4864
4865 drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
4866
4867 if (intel_dp->active_mst_links > 0 && link_ok &&
4868 esi[3] & LINK_STATUS_CHANGED) {
4869 if (!intel_dp_mst_link_status(intel_dp))
4870 link_ok = false;
4871 ack[3] |= LINK_STATUS_CHANGED;
4872 }
4873
4874 intel_dp_mst_hpd_irq(intel_dp, esi, ack);
4875
4876 if (esi[3] & DP_TUNNELING_IRQ) {
4877 if (drm_dp_tunnel_handle_irq(i915->display.dp_tunnel_mgr,
4878 &intel_dp->aux))
4879 reprobe_needed = true;
4880 ack[3] |= DP_TUNNELING_IRQ;
4881 }
4882
4883 if (!memchr_inv(ack, 0, sizeof(ack)))
4884 break;
4885
4886 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
4887 drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
4888
4889 if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY))
4890 drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr);
4891 }
4892
4893 return link_ok && !reprobe_needed;
4894}
4895
4896static void
4897intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
4898{
4899 bool is_active;
4900 u8 buf = 0;
4901
4902 is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
4903 if (intel_dp->frl.is_trained && !is_active) {
4904 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
4905 return;
4906
4907 buf &= ~DP_PCON_ENABLE_HDMI_LINK;
4908 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
4909 return;
4910
4911 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
4912
4913 intel_dp->frl.is_trained = false;
4914
4915 /* Restart FRL training or fall back to TMDS mode */
4916 intel_dp_check_frl_training(intel_dp);
4917 }
4918}
4919
4920static bool
4921intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4922{
4923 u8 link_status[DP_LINK_STATUS_SIZE];
4924
4925 if (!intel_dp->link_trained)
4926 return false;
4927
4928 /*
4929 * While PSR source HW is enabled, it will control main-link sending
4930 * frames, enabling and disabling it so trying to do a retrain will fail
4931 * as the link would or not be on or it could mix training patterns
4932 * and frame data at the same time causing retrain to fail.
4933 * Also when exiting PSR, HW will retrain the link anyways fixing
4934 * any link status error.
4935 */
4936 if (intel_psr_enabled(intel_dp))
4937 return false;
4938
4939 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
4940 link_status) < 0)
4941 return false;
4942
4943 /*
4944 * Validate the cached values of intel_dp->link_rate and
4945 * intel_dp->lane_count before attempting to retrain.
4946 *
4947 * FIXME would be nice to user the crtc state here, but since
4948 * we need to call this from the short HPD handler that seems
4949 * a bit hard.
4950 */
4951 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4952 intel_dp->lane_count))
4953 return false;
4954
4955 /* Retrain if link not ok */
4956 return !intel_dp_link_ok(intel_dp, link_status);
4957}
4958
4959static bool intel_dp_has_connector(struct intel_dp *intel_dp,
4960 const struct drm_connector_state *conn_state)
4961{
4962 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4963 struct intel_encoder *encoder;
4964 enum pipe pipe;
4965
4966 if (!conn_state->best_encoder)
4967 return false;
4968
4969 /* SST */
4970 encoder = &dp_to_dig_port(intel_dp)->base;
4971 if (conn_state->best_encoder == &encoder->base)
4972 return true;
4973
4974 /* MST */
4975 for_each_pipe(i915, pipe) {
4976 encoder = &intel_dp->mst_encoders[pipe]->base;
4977 if (conn_state->best_encoder == &encoder->base)
4978 return true;
4979 }
4980
4981 return false;
4982}
4983
4984int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
4985 struct drm_modeset_acquire_ctx *ctx,
4986 u8 *pipe_mask)
4987{
4988 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4989 struct drm_connector_list_iter conn_iter;
4990 struct intel_connector *connector;
4991 int ret = 0;
4992
4993 *pipe_mask = 0;
4994
4995 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4996 for_each_intel_connector_iter(connector, &conn_iter) {
4997 struct drm_connector_state *conn_state =
4998 connector->base.state;
4999 struct intel_crtc_state *crtc_state;
5000 struct intel_crtc *crtc;
5001
5002 if (!intel_dp_has_connector(intel_dp, conn_state))
5003 continue;
5004
5005 crtc = to_intel_crtc(conn_state->crtc);
5006 if (!crtc)
5007 continue;
5008
5009 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5010 if (ret)
5011 break;
5012
5013 crtc_state = to_intel_crtc_state(crtc->base.state);
5014
5015 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
5016
5017 if (!crtc_state->hw.active)
5018 continue;
5019
5020 if (conn_state->commit)
5021 drm_WARN_ON(&i915->drm,
5022 !wait_for_completion_timeout(&conn_state->commit->hw_done,
5023 msecs_to_jiffies(5000)));
5024
5025 *pipe_mask |= BIT(crtc->pipe);
5026 }
5027 drm_connector_list_iter_end(&conn_iter);
5028
5029 return ret;
5030}
5031
5032static bool intel_dp_is_connected(struct intel_dp *intel_dp)
5033{
5034 struct intel_connector *connector = intel_dp->attached_connector;
5035
5036 return connector->base.status == connector_status_connected ||
5037 intel_dp->is_mst;
5038}
5039
5040int intel_dp_retrain_link(struct intel_encoder *encoder,
5041 struct drm_modeset_acquire_ctx *ctx)
5042{
5043 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5044 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5045 struct intel_crtc *crtc;
5046 u8 pipe_mask;
5047 int ret;
5048
5049 if (!intel_dp_is_connected(intel_dp))
5050 return 0;
5051
5052 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5053 ctx);
5054 if (ret)
5055 return ret;
5056
5057 if (!intel_dp_needs_link_retrain(intel_dp))
5058 return 0;
5059
5060 ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);
5061 if (ret)
5062 return ret;
5063
5064 if (pipe_mask == 0)
5065 return 0;
5066
5067 if (!intel_dp_needs_link_retrain(intel_dp))
5068 return 0;
5069
5070 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
5071 encoder->base.base.id, encoder->base.name);
5072
5073 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5074 const struct intel_crtc_state *crtc_state =
5075 to_intel_crtc_state(crtc->base.state);
5076
5077 /* Suppress underruns caused by re-training */
5078 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5079 if (crtc_state->has_pch_encoder)
5080 intel_set_pch_fifo_underrun_reporting(dev_priv,
5081 intel_crtc_pch_transcoder(crtc), false);
5082 }
5083
5084 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5085 const struct intel_crtc_state *crtc_state =
5086 to_intel_crtc_state(crtc->base.state);
5087
5088 /* retrain on the MST master transcoder */
5089 if (DISPLAY_VER(dev_priv) >= 12 &&
5090 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
5091 !intel_dp_mst_is_master_trans(crtc_state))
5092 continue;
5093
5094 intel_dp_check_frl_training(intel_dp);
5095 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
5096 intel_dp_start_link_train(intel_dp, crtc_state);
5097 intel_dp_stop_link_train(intel_dp, crtc_state);
5098 break;
5099 }
5100
5101 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5102 const struct intel_crtc_state *crtc_state =
5103 to_intel_crtc_state(crtc->base.state);
5104
5105 /* Keep underrun reporting disabled until things are stable */
5106 intel_crtc_wait_for_next_vblank(crtc);
5107
5108 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
5109 if (crtc_state->has_pch_encoder)
5110 intel_set_pch_fifo_underrun_reporting(dev_priv,
5111 intel_crtc_pch_transcoder(crtc), true);
5112 }
5113
5114 return 0;
5115}
5116
5117static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
5118 struct drm_modeset_acquire_ctx *ctx,
5119 u8 *pipe_mask)
5120{
5121 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5122 struct drm_connector_list_iter conn_iter;
5123 struct intel_connector *connector;
5124 int ret = 0;
5125
5126 *pipe_mask = 0;
5127
5128 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
5129 for_each_intel_connector_iter(connector, &conn_iter) {
5130 struct drm_connector_state *conn_state =
5131 connector->base.state;
5132 struct intel_crtc_state *crtc_state;
5133 struct intel_crtc *crtc;
5134
5135 if (!intel_dp_has_connector(intel_dp, conn_state))
5136 continue;
5137
5138 crtc = to_intel_crtc(conn_state->crtc);
5139 if (!crtc)
5140 continue;
5141
5142 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5143 if (ret)
5144 break;
5145
5146 crtc_state = to_intel_crtc_state(crtc->base.state);
5147
5148 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
5149
5150 if (!crtc_state->hw.active)
5151 continue;
5152
5153 if (conn_state->commit &&
5154 !try_wait_for_completion(&conn_state->commit->hw_done))
5155 continue;
5156
5157 *pipe_mask |= BIT(crtc->pipe);
5158 }
5159 drm_connector_list_iter_end(&conn_iter);
5160
5161 return ret;
5162}
5163
5164static int intel_dp_do_phy_test(struct intel_encoder *encoder,
5165 struct drm_modeset_acquire_ctx *ctx)
5166{
5167 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5168 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5169 struct intel_crtc *crtc;
5170 u8 pipe_mask;
5171 int ret;
5172
5173 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5174 ctx);
5175 if (ret)
5176 return ret;
5177
5178 ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask);
5179 if (ret)
5180 return ret;
5181
5182 if (pipe_mask == 0)
5183 return 0;
5184
5185 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
5186 encoder->base.base.id, encoder->base.name);
5187
5188 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5189 const struct intel_crtc_state *crtc_state =
5190 to_intel_crtc_state(crtc->base.state);
5191
5192 /* test on the MST master transcoder */
5193 if (DISPLAY_VER(dev_priv) >= 12 &&
5194 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
5195 !intel_dp_mst_is_master_trans(crtc_state))
5196 continue;
5197
5198 intel_dp_process_phy_request(intel_dp, crtc_state);
5199 break;
5200 }
5201
5202 return 0;
5203}
5204
5205void intel_dp_phy_test(struct intel_encoder *encoder)
5206{
5207 struct drm_modeset_acquire_ctx ctx;
5208 int ret;
5209
5210 drm_modeset_acquire_init(&ctx, 0);
5211
5212 for (;;) {
5213 ret = intel_dp_do_phy_test(encoder, &ctx);
5214
5215 if (ret == -EDEADLK) {
5216 drm_modeset_backoff(&ctx);
5217 continue;
5218 }
5219
5220 break;
5221 }
5222
5223 drm_modeset_drop_locks(&ctx);
5224 drm_modeset_acquire_fini(&ctx);
5225 drm_WARN(encoder->base.dev, ret,
5226 "Acquiring modeset locks failed with %i\n", ret);
5227}
5228
5229static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
5230{
5231 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5232 u8 val;
5233
5234 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5235 return;
5236
5237 if (drm_dp_dpcd_readb(&intel_dp->aux,
5238 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
5239 return;
5240
5241 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
5242
5243 if (val & DP_AUTOMATED_TEST_REQUEST)
5244 intel_dp_handle_test_request(intel_dp);
5245
5246 if (val & DP_CP_IRQ)
5247 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5248
5249 if (val & DP_SINK_SPECIFIC_IRQ)
5250 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
5251}
5252
5253static bool intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
5254{
5255 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5256 bool reprobe_needed = false;
5257 u8 val;
5258
5259 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5260 return false;
5261
5262 if (drm_dp_dpcd_readb(&intel_dp->aux,
5263 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
5264 return false;
5265
5266 if ((val & DP_TUNNELING_IRQ) &&
5267 drm_dp_tunnel_handle_irq(i915->display.dp_tunnel_mgr,
5268 &intel_dp->aux))
5269 reprobe_needed = true;
5270
5271 if (drm_dp_dpcd_writeb(&intel_dp->aux,
5272 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
5273 return reprobe_needed;
5274
5275 if (val & HDMI_LINK_STATUS_CHANGED)
5276 intel_dp_handle_hdmi_link_status_change(intel_dp);
5277
5278 return reprobe_needed;
5279}
5280
5281/*
5282 * According to DP spec
5283 * 5.1.2:
5284 * 1. Read DPCD
5285 * 2. Configure link according to Receiver Capabilities
5286 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
5287 * 4. Check link status on receipt of hot-plug interrupt
5288 *
5289 * intel_dp_short_pulse - handles short pulse interrupts
5290 * when full detection is not required.
5291 * Returns %true if short pulse is handled and full detection
5292 * is NOT required and %false otherwise.
5293 */
5294static bool
5295intel_dp_short_pulse(struct intel_dp *intel_dp)
5296{
5297 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5298 u8 old_sink_count = intel_dp->sink_count;
5299 bool reprobe_needed = false;
5300 bool ret;
5301
5302 /*
5303 * Clearing compliance test variables to allow capturing
5304 * of values for next automated test request.
5305 */
5306 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5307
5308 /*
5309 * Now read the DPCD to see if it's actually running
5310 * If the current value of sink count doesn't match with
5311 * the value that was stored earlier or dpcd read failed
5312 * we need to do full detection
5313 */
5314 ret = intel_dp_get_dpcd(intel_dp);
5315
5316 if ((old_sink_count != intel_dp->sink_count) || !ret) {
5317 /* No need to proceed if we are going to do full detect */
5318 return false;
5319 }
5320
5321 intel_dp_check_device_service_irq(intel_dp);
5322 reprobe_needed = intel_dp_check_link_service_irq(intel_dp);
5323
5324 /* Handle CEC interrupts, if any */
5325 drm_dp_cec_irq(&intel_dp->aux);
5326
5327 /* defer to the hotplug work for link retraining if needed */
5328 if (intel_dp_needs_link_retrain(intel_dp))
5329 return false;
5330
5331 intel_psr_short_pulse(intel_dp);
5332
5333 switch (intel_dp->compliance.test_type) {
5334 case DP_TEST_LINK_TRAINING:
5335 drm_dbg_kms(&dev_priv->drm,
5336 "Link Training Compliance Test requested\n");
5337 /* Send a Hotplug Uevent to userspace to start modeset */
5338 drm_kms_helper_hotplug_event(&dev_priv->drm);
5339 break;
5340 case DP_TEST_LINK_PHY_TEST_PATTERN:
5341 drm_dbg_kms(&dev_priv->drm,
5342 "PHY test pattern Compliance Test requested\n");
5343 /*
5344 * Schedule long hpd to do the test
5345 *
5346 * FIXME get rid of the ad-hoc phy test modeset code
5347 * and properly incorporate it into the normal modeset.
5348 */
5349 reprobe_needed = true;
5350 }
5351
5352 return !reprobe_needed;
5353}
5354
5355/* XXX this is probably wrong for multiple downstream ports */
5356static enum drm_connector_status
5357intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5358{
5359 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5360 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5361 u8 *dpcd = intel_dp->dpcd;
5362 u8 type;
5363
5364 if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
5365 return connector_status_connected;
5366
5367 lspcon_resume(dig_port);
5368
5369 if (!intel_dp_get_dpcd(intel_dp))
5370 return connector_status_disconnected;
5371
5372 /* if there's no downstream port, we're done */
5373 if (!drm_dp_is_branch(dpcd))
5374 return connector_status_connected;
5375
5376 /* If we're HPD-aware, SINK_COUNT changes dynamically */
5377 if (intel_dp_has_sink_count(intel_dp) &&
5378 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5379 return intel_dp->sink_count ?
5380 connector_status_connected : connector_status_disconnected;
5381 }
5382
5383 if (intel_dp_can_mst(intel_dp))
5384 return connector_status_connected;
5385
5386 /* If no HPD, poke DDC gently */
5387 if (drm_probe_ddc(&intel_dp->aux.ddc))
5388 return connector_status_connected;
5389
5390 /* Well we tried, say unknown for unreliable port types */
5391 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5392 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5393 if (type == DP_DS_PORT_TYPE_VGA ||
5394 type == DP_DS_PORT_TYPE_NON_EDID)
5395 return connector_status_unknown;
5396 } else {
5397 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5398 DP_DWN_STRM_PORT_TYPE_MASK;
5399 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5400 type == DP_DWN_STRM_PORT_TYPE_OTHER)
5401 return connector_status_unknown;
5402 }
5403
5404 /* Anything else is out of spec, warn and ignore */
5405 drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
5406 return connector_status_disconnected;
5407}
5408
5409static enum drm_connector_status
5410edp_detect(struct intel_dp *intel_dp)
5411{
5412 return connector_status_connected;
5413}
5414
5415void intel_digital_port_lock(struct intel_encoder *encoder)
5416{
5417 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5418
5419 if (dig_port->lock)
5420 dig_port->lock(dig_port);
5421}
5422
5423void intel_digital_port_unlock(struct intel_encoder *encoder)
5424{
5425 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5426
5427 if (dig_port->unlock)
5428 dig_port->unlock(dig_port);
5429}
5430
5431/*
5432 * intel_digital_port_connected_locked - is the specified port connected?
5433 * @encoder: intel_encoder
5434 *
5435 * In cases where there's a connector physically connected but it can't be used
5436 * by our hardware we also return false, since the rest of the driver should
5437 * pretty much treat the port as disconnected. This is relevant for type-C
5438 * (starting on ICL) where there's ownership involved.
5439 *
5440 * The caller must hold the lock acquired by calling intel_digital_port_lock()
5441 * when calling this function.
5442 *
5443 * Return %true if port is connected, %false otherwise.
5444 */
5445bool intel_digital_port_connected_locked(struct intel_encoder *encoder)
5446{
5447 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5448 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5449 bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port);
5450 bool is_connected = false;
5451 intel_wakeref_t wakeref;
5452
5453 with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref) {
5454 unsigned long wait_expires = jiffies + msecs_to_jiffies_timeout(4);
5455
5456 do {
5457 is_connected = dig_port->connected(encoder);
5458 if (is_connected || is_glitch_free)
5459 break;
5460 usleep_range(10, 30);
5461 } while (time_before(jiffies, wait_expires));
5462 }
5463
5464 return is_connected;
5465}
5466
5467bool intel_digital_port_connected(struct intel_encoder *encoder)
5468{
5469 bool ret;
5470
5471 intel_digital_port_lock(encoder);
5472 ret = intel_digital_port_connected_locked(encoder);
5473 intel_digital_port_unlock(encoder);
5474
5475 return ret;
5476}
5477
5478static const struct drm_edid *
5479intel_dp_get_edid(struct intel_dp *intel_dp)
5480{
5481 struct intel_connector *connector = intel_dp->attached_connector;
5482 const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
5483
5484 /* Use panel fixed edid if we have one */
5485 if (fixed_edid) {
5486 /* invalid edid */
5487 if (IS_ERR(fixed_edid))
5488 return NULL;
5489
5490 return drm_edid_dup(fixed_edid);
5491 }
5492
5493 return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc);
5494}
5495
5496static void
5497intel_dp_update_dfp(struct intel_dp *intel_dp,
5498 const struct drm_edid *drm_edid)
5499{
5500 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5501 struct intel_connector *connector = intel_dp->attached_connector;
5502
5503 intel_dp->dfp.max_bpc =
5504 drm_dp_downstream_max_bpc(intel_dp->dpcd,
5505 intel_dp->downstream_ports, drm_edid);
5506
5507 intel_dp->dfp.max_dotclock =
5508 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
5509 intel_dp->downstream_ports);
5510
5511 intel_dp->dfp.min_tmds_clock =
5512 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
5513 intel_dp->downstream_ports,
5514 drm_edid);
5515 intel_dp->dfp.max_tmds_clock =
5516 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
5517 intel_dp->downstream_ports,
5518 drm_edid);
5519
5520 intel_dp->dfp.pcon_max_frl_bw =
5521 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
5522 intel_dp->downstream_ports);
5523
5524 drm_dbg_kms(&i915->drm,
5525 "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
5526 connector->base.base.id, connector->base.name,
5527 intel_dp->dfp.max_bpc,
5528 intel_dp->dfp.max_dotclock,
5529 intel_dp->dfp.min_tmds_clock,
5530 intel_dp->dfp.max_tmds_clock,
5531 intel_dp->dfp.pcon_max_frl_bw);
5532
5533 intel_dp_get_pcon_dsc_cap(intel_dp);
5534}
5535
5536static bool
5537intel_dp_can_ycbcr420(struct intel_dp *intel_dp)
5538{
5539 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) &&
5540 (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))
5541 return true;
5542
5543 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&
5544 dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
5545 return true;
5546
5547 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) &&
5548 dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
5549 return true;
5550
5551 return false;
5552}
5553
5554static void
5555intel_dp_update_420(struct intel_dp *intel_dp)
5556{
5557 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5558 struct intel_connector *connector = intel_dp->attached_connector;
5559
5560 intel_dp->dfp.ycbcr420_passthrough =
5561 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
5562 intel_dp->downstream_ports);
5563 /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
5564 intel_dp->dfp.ycbcr_444_to_420 =
5565 dp_to_dig_port(intel_dp)->lspcon.active ||
5566 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
5567 intel_dp->downstream_ports);
5568 intel_dp->dfp.rgb_to_ycbcr =
5569 drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
5570 intel_dp->downstream_ports,
5571 DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
5572
5573 connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);
5574
5575 drm_dbg_kms(&i915->drm,
5576 "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
5577 connector->base.base.id, connector->base.name,
5578 str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
5579 str_yes_no(connector->base.ycbcr_420_allowed),
5580 str_yes_no(intel_dp->dfp.ycbcr_444_to_420));
5581}
5582
5583static void
5584intel_dp_set_edid(struct intel_dp *intel_dp)
5585{
5586 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5587 struct intel_connector *connector = intel_dp->attached_connector;
5588 const struct drm_edid *drm_edid;
5589 bool vrr_capable;
5590
5591 intel_dp_unset_edid(intel_dp);
5592 drm_edid = intel_dp_get_edid(intel_dp);
5593 connector->detect_edid = drm_edid;
5594
5595 /* Below we depend on display info having been updated */
5596 drm_edid_connector_update(&connector->base, drm_edid);
5597
5598 vrr_capable = intel_vrr_is_capable(connector);
5599 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
5600 connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
5601 drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
5602
5603 intel_dp_update_dfp(intel_dp, drm_edid);
5604 intel_dp_update_420(intel_dp);
5605
5606 drm_dp_cec_attach(&intel_dp->aux,
5607 connector->base.display_info.source_physical_address);
5608}
5609
5610static void
5611intel_dp_unset_edid(struct intel_dp *intel_dp)
5612{
5613 struct intel_connector *connector = intel_dp->attached_connector;
5614
5615 drm_dp_cec_unset_edid(&intel_dp->aux);
5616 drm_edid_free(connector->detect_edid);
5617 connector->detect_edid = NULL;
5618
5619 intel_dp->dfp.max_bpc = 0;
5620 intel_dp->dfp.max_dotclock = 0;
5621 intel_dp->dfp.min_tmds_clock = 0;
5622 intel_dp->dfp.max_tmds_clock = 0;
5623
5624 intel_dp->dfp.pcon_max_frl_bw = 0;
5625
5626 intel_dp->dfp.ycbcr_444_to_420 = false;
5627 connector->base.ycbcr_420_allowed = false;
5628
5629 drm_connector_set_vrr_capable_property(&connector->base,
5630 false);
5631}
5632
5633static void
5634intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector)
5635{
5636 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5637
5638 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5639 if (!HAS_DSC(i915))
5640 return;
5641
5642 if (intel_dp_is_edp(intel_dp))
5643 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],
5644 connector);
5645 else
5646 intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],
5647 connector);
5648}
5649
5650static int
5651intel_dp_detect(struct drm_connector *connector,
5652 struct drm_modeset_acquire_ctx *ctx,
5653 bool force)
5654{
5655 struct drm_i915_private *dev_priv = to_i915(connector->dev);
5656 struct intel_connector *intel_connector =
5657 to_intel_connector(connector);
5658 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5659 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5660 struct intel_encoder *encoder = &dig_port->base;
5661 enum drm_connector_status status;
5662 int ret;
5663
5664 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5665 connector->base.id, connector->name);
5666 drm_WARN_ON(&dev_priv->drm,
5667 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5668
5669 if (!intel_display_device_enabled(dev_priv))
5670 return connector_status_disconnected;
5671
5672 if (!intel_display_driver_check_access(dev_priv))
5673 return connector->status;
5674
5675 /* Can't disconnect eDP */
5676 if (intel_dp_is_edp(intel_dp))
5677 status = edp_detect(intel_dp);
5678 else if (intel_digital_port_connected(encoder))
5679 status = intel_dp_detect_dpcd(intel_dp);
5680 else
5681 status = connector_status_disconnected;
5682
5683 if (status == connector_status_disconnected) {
5684 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5685 memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd));
5686 intel_dp->psr.sink_panel_replay_support = false;
5687
5688 if (intel_dp->is_mst) {
5689 drm_dbg_kms(&dev_priv->drm,
5690 "MST device may have disappeared %d vs %d\n",
5691 intel_dp->is_mst,
5692 intel_dp->mst_mgr.mst_state);
5693 intel_dp->is_mst = false;
5694 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5695 intel_dp->is_mst);
5696 }
5697
5698 intel_dp_tunnel_disconnect(intel_dp);
5699
5700 goto out;
5701 }
5702
5703 ret = intel_dp_tunnel_detect(intel_dp, ctx);
5704 if (ret == -EDEADLK)
5705 return ret;
5706
5707 if (ret == 1)
5708 intel_connector->base.epoch_counter++;
5709
5710 if (!intel_dp_is_edp(intel_dp))
5711 intel_psr_init_dpcd(intel_dp);
5712
5713 intel_dp_detect_dsc_caps(intel_dp, intel_connector);
5714
5715 intel_dp_configure_mst(intel_dp);
5716
5717 /*
5718 * TODO: Reset link params when switching to MST mode, until MST
5719 * supports link training fallback params.
5720 */
5721 if (intel_dp->reset_link_params || intel_dp->is_mst) {
5722 intel_dp_reset_max_link_params(intel_dp);
5723 intel_dp->reset_link_params = false;
5724 }
5725
5726 intel_dp_print_rates(intel_dp);
5727
5728 if (intel_dp->is_mst) {
5729 /*
5730 * If we are in MST mode then this connector
5731 * won't appear connected or have anything
5732 * with EDID on it
5733 */
5734 status = connector_status_disconnected;
5735 goto out;
5736 }
5737
5738 /*
5739 * Some external monitors do not signal loss of link synchronization
5740 * with an IRQ_HPD, so force a link status check.
5741 */
5742 if (!intel_dp_is_edp(intel_dp)) {
5743 ret = intel_dp_retrain_link(encoder, ctx);
5744 if (ret)
5745 return ret;
5746 }
5747
5748 /*
5749 * Clearing NACK and defer counts to get their exact values
5750 * while reading EDID which are required by Compliance tests
5751 * 4.2.2.4 and 4.2.2.5
5752 */
5753 intel_dp->aux.i2c_nack_count = 0;
5754 intel_dp->aux.i2c_defer_count = 0;
5755
5756 intel_dp_set_edid(intel_dp);
5757 if (intel_dp_is_edp(intel_dp) ||
5758 to_intel_connector(connector)->detect_edid)
5759 status = connector_status_connected;
5760
5761 intel_dp_check_device_service_irq(intel_dp);
5762
5763out:
5764 if (status != connector_status_connected && !intel_dp->is_mst)
5765 intel_dp_unset_edid(intel_dp);
5766
5767 if (!intel_dp_is_edp(intel_dp))
5768 drm_dp_set_subconnector_property(connector,
5769 status,
5770 intel_dp->dpcd,
5771 intel_dp->downstream_ports);
5772 return status;
5773}
5774
5775static void
5776intel_dp_force(struct drm_connector *connector)
5777{
5778 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5779 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5780 struct intel_encoder *intel_encoder = &dig_port->base;
5781 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5782
5783 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5784 connector->base.id, connector->name);
5785
5786 if (!intel_display_driver_check_access(dev_priv))
5787 return;
5788
5789 intel_dp_unset_edid(intel_dp);
5790
5791 if (connector->status != connector_status_connected)
5792 return;
5793
5794 intel_dp_set_edid(intel_dp);
5795}
5796
5797static int intel_dp_get_modes(struct drm_connector *connector)
5798{
5799 struct intel_connector *intel_connector = to_intel_connector(connector);
5800 int num_modes;
5801
5802 /* drm_edid_connector_update() done in ->detect() or ->force() */
5803 num_modes = drm_edid_connector_add_modes(connector);
5804
5805 /* Also add fixed mode, which may or may not be present in EDID */
5806 if (intel_dp_is_edp(intel_attached_dp(intel_connector)))
5807 num_modes += intel_panel_get_modes(intel_connector);
5808
5809 if (num_modes)
5810 return num_modes;
5811
5812 if (!intel_connector->detect_edid) {
5813 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5814 struct drm_display_mode *mode;
5815
5816 mode = drm_dp_downstream_mode(connector->dev,
5817 intel_dp->dpcd,
5818 intel_dp->downstream_ports);
5819 if (mode) {
5820 drm_mode_probed_add(connector, mode);
5821 num_modes++;
5822 }
5823 }
5824
5825 return num_modes;
5826}
5827
5828static int
5829intel_dp_connector_register(struct drm_connector *connector)
5830{
5831 struct drm_i915_private *i915 = to_i915(connector->dev);
5832 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5833 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5834 struct intel_lspcon *lspcon = &dig_port->lspcon;
5835 int ret;
5836
5837 ret = intel_connector_register(connector);
5838 if (ret)
5839 return ret;
5840
5841 drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
5842 intel_dp->aux.name, connector->kdev->kobj.name);
5843
5844 intel_dp->aux.dev = connector->kdev;
5845 ret = drm_dp_aux_register(&intel_dp->aux);
5846 if (!ret)
5847 drm_dp_cec_register_connector(&intel_dp->aux, connector);
5848
5849 if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata))
5850 return ret;
5851
5852 /*
5853 * ToDo: Clean this up to handle lspcon init and resume more
5854 * efficiently and streamlined.
5855 */
5856 if (lspcon_init(dig_port)) {
5857 lspcon_detect_hdr_capability(lspcon);
5858 if (lspcon->hdr_supported)
5859 drm_connector_attach_hdr_output_metadata_property(connector);
5860 }
5861
5862 return ret;
5863}
5864
5865static void
5866intel_dp_connector_unregister(struct drm_connector *connector)
5867{
5868 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5869
5870 drm_dp_cec_unregister_connector(&intel_dp->aux);
5871 drm_dp_aux_unregister(&intel_dp->aux);
5872 intel_connector_unregister(connector);
5873}
5874
5875void intel_dp_connector_sync_state(struct intel_connector *connector,
5876 const struct intel_crtc_state *crtc_state)
5877{
5878 struct drm_i915_private *i915 = to_i915(connector->base.dev);
5879
5880 if (crtc_state && crtc_state->dsc.compression_enable) {
5881 drm_WARN_ON(&i915->drm, !connector->dp.dsc_decompression_aux);
5882 connector->dp.dsc_decompression_enabled = true;
5883 } else {
5884 connector->dp.dsc_decompression_enabled = false;
5885 }
5886}
5887
5888void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5889{
5890 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
5891 struct intel_dp *intel_dp = &dig_port->dp;
5892
5893 intel_dp_mst_encoder_cleanup(dig_port);
5894
5895 intel_dp_tunnel_destroy(intel_dp);
5896
5897 intel_pps_vdd_off_sync(intel_dp);
5898
5899 /*
5900 * Ensure power off delay is respected on module remove, so that we can
5901 * reduce delays at driver probe. See pps_init_timestamps().
5902 */
5903 intel_pps_wait_power_cycle(intel_dp);
5904
5905 intel_dp_aux_fini(intel_dp);
5906}
5907
5908void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5909{
5910 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5911
5912 intel_pps_vdd_off_sync(intel_dp);
5913
5914 intel_dp_tunnel_suspend(intel_dp);
5915}
5916
5917void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
5918{
5919 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5920
5921 intel_pps_wait_power_cycle(intel_dp);
5922}
5923
5924static int intel_modeset_tile_group(struct intel_atomic_state *state,
5925 int tile_group_id)
5926{
5927 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5928 struct drm_connector_list_iter conn_iter;
5929 struct drm_connector *connector;
5930 int ret = 0;
5931
5932 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
5933 drm_for_each_connector_iter(connector, &conn_iter) {
5934 struct drm_connector_state *conn_state;
5935 struct intel_crtc_state *crtc_state;
5936 struct intel_crtc *crtc;
5937
5938 if (!connector->has_tile ||
5939 connector->tile_group->id != tile_group_id)
5940 continue;
5941
5942 conn_state = drm_atomic_get_connector_state(&state->base,
5943 connector);
5944 if (IS_ERR(conn_state)) {
5945 ret = PTR_ERR(conn_state);
5946 break;
5947 }
5948
5949 crtc = to_intel_crtc(conn_state->crtc);
5950
5951 if (!crtc)
5952 continue;
5953
5954 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
5955 crtc_state->uapi.mode_changed = true;
5956
5957 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5958 if (ret)
5959 break;
5960 }
5961 drm_connector_list_iter_end(&conn_iter);
5962
5963 return ret;
5964}
5965
5966static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
5967{
5968 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5969 struct intel_crtc *crtc;
5970
5971 if (transcoders == 0)
5972 return 0;
5973
5974 for_each_intel_crtc(&dev_priv->drm, crtc) {
5975 struct intel_crtc_state *crtc_state;
5976 int ret;
5977
5978 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5979 if (IS_ERR(crtc_state))
5980 return PTR_ERR(crtc_state);
5981
5982 if (!crtc_state->hw.enable)
5983 continue;
5984
5985 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
5986 continue;
5987
5988 crtc_state->uapi.mode_changed = true;
5989
5990 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
5991 if (ret)
5992 return ret;
5993
5994 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5995 if (ret)
5996 return ret;
5997
5998 transcoders &= ~BIT(crtc_state->cpu_transcoder);
5999 }
6000
6001 drm_WARN_ON(&dev_priv->drm, transcoders != 0);
6002
6003 return 0;
6004}
6005
6006static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
6007 struct drm_connector *connector)
6008{
6009 const struct drm_connector_state *old_conn_state =
6010 drm_atomic_get_old_connector_state(&state->base, connector);
6011 const struct intel_crtc_state *old_crtc_state;
6012 struct intel_crtc *crtc;
6013 u8 transcoders;
6014
6015 crtc = to_intel_crtc(old_conn_state->crtc);
6016 if (!crtc)
6017 return 0;
6018
6019 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
6020
6021 if (!old_crtc_state->hw.active)
6022 return 0;
6023
6024 transcoders = old_crtc_state->sync_mode_slaves_mask;
6025 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
6026 transcoders |= BIT(old_crtc_state->master_transcoder);
6027
6028 return intel_modeset_affected_transcoders(state,
6029 transcoders);
6030}
6031
6032static int intel_dp_connector_atomic_check(struct drm_connector *conn,
6033 struct drm_atomic_state *_state)
6034{
6035 struct drm_i915_private *dev_priv = to_i915(conn->dev);
6036 struct intel_atomic_state *state = to_intel_atomic_state(_state);
6037 struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn);
6038 struct intel_connector *intel_conn = to_intel_connector(conn);
6039 struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder);
6040 int ret;
6041
6042 ret = intel_digital_connector_atomic_check(conn, &state->base);
6043 if (ret)
6044 return ret;
6045
6046 if (intel_dp_mst_source_support(intel_dp)) {
6047 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr);
6048 if (ret)
6049 return ret;
6050 }
6051
6052 if (!intel_connector_needs_modeset(state, conn))
6053 return 0;
6054
6055 ret = intel_dp_tunnel_atomic_check_state(state,
6056 intel_dp,
6057 intel_conn);
6058 if (ret)
6059 return ret;
6060
6061 /*
6062 * We don't enable port sync on BDW due to missing w/as and
6063 * due to not having adjusted the modeset sequence appropriately.
6064 */
6065 if (DISPLAY_VER(dev_priv) < 9)
6066 return 0;
6067
6068 if (conn->has_tile) {
6069 ret = intel_modeset_tile_group(state, conn->tile_group->id);
6070 if (ret)
6071 return ret;
6072 }
6073
6074 return intel_modeset_synced_crtcs(state, conn);
6075}
6076
6077static void intel_dp_oob_hotplug_event(struct drm_connector *connector,
6078 enum drm_connector_status hpd_state)
6079{
6080 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
6081 struct drm_i915_private *i915 = to_i915(connector->dev);
6082 bool hpd_high = hpd_state == connector_status_connected;
6083 unsigned int hpd_pin = encoder->hpd_pin;
6084 bool need_work = false;
6085
6086 spin_lock_irq(&i915->irq_lock);
6087 if (hpd_high != test_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state)) {
6088 i915->display.hotplug.event_bits |= BIT(hpd_pin);
6089
6090 __assign_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state, hpd_high);
6091 need_work = true;
6092 }
6093 spin_unlock_irq(&i915->irq_lock);
6094
6095 if (need_work)
6096 intel_hpd_schedule_detection(i915);
6097}
6098
6099static const struct drm_connector_funcs intel_dp_connector_funcs = {
6100 .force = intel_dp_force,
6101 .fill_modes = drm_helper_probe_single_connector_modes,
6102 .atomic_get_property = intel_digital_connector_atomic_get_property,
6103 .atomic_set_property = intel_digital_connector_atomic_set_property,
6104 .late_register = intel_dp_connector_register,
6105 .early_unregister = intel_dp_connector_unregister,
6106 .destroy = intel_connector_destroy,
6107 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6108 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
6109 .oob_hotplug_event = intel_dp_oob_hotplug_event,
6110};
6111
6112static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6113 .detect_ctx = intel_dp_detect,
6114 .get_modes = intel_dp_get_modes,
6115 .mode_valid = intel_dp_mode_valid,
6116 .atomic_check = intel_dp_connector_atomic_check,
6117};
6118
6119enum irqreturn
6120intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
6121{
6122 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
6123 struct intel_dp *intel_dp = &dig_port->dp;
6124 u8 dpcd[DP_RECEIVER_CAP_SIZE];
6125
6126 if (dig_port->base.type == INTEL_OUTPUT_EDP &&
6127 (long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) {
6128 /*
6129 * vdd off can generate a long/short pulse on eDP which
6130 * would require vdd on to handle it, and thus we
6131 * would end up in an endless cycle of
6132 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
6133 */
6134 drm_dbg_kms(&i915->drm,
6135 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
6136 long_hpd ? "long" : "short",
6137 dig_port->base.base.base.id,
6138 dig_port->base.base.name);
6139 return IRQ_HANDLED;
6140 }
6141
6142 drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
6143 dig_port->base.base.base.id,
6144 dig_port->base.base.name,
6145 long_hpd ? "long" : "short");
6146
6147 /*
6148 * TBT DP tunnels require the GFX driver to read out the DPRX caps in
6149 * response to long HPD pulses. The DP hotplug handler does that,
6150 * however the hotplug handler may be blocked by another
6151 * connector's/encoder's hotplug handler. Since the TBT CM may not
6152 * complete the DP tunnel BW request for the latter connector/encoder
6153 * waiting for this encoder's DPRX read, perform a dummy read here.
6154 */
6155 if (long_hpd)
6156 intel_dp_read_dprx_caps(intel_dp, dpcd);
6157
6158 if (long_hpd) {
6159 intel_dp->reset_link_params = true;
6160 return IRQ_NONE;
6161 }
6162
6163 if (intel_dp->is_mst) {
6164 if (!intel_dp_check_mst_status(intel_dp))
6165 return IRQ_NONE;
6166 } else if (!intel_dp_short_pulse(intel_dp)) {
6167 return IRQ_NONE;
6168 }
6169
6170 return IRQ_HANDLED;
6171}
6172
6173static bool _intel_dp_is_port_edp(struct drm_i915_private *dev_priv,
6174 const struct intel_bios_encoder_data *devdata,
6175 enum port port)
6176{
6177 /*
6178 * eDP not supported on g4x. so bail out early just
6179 * for a bit extra safety in case the VBT is bonkers.
6180 */
6181 if (DISPLAY_VER(dev_priv) < 5)
6182 return false;
6183
6184 if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
6185 return true;
6186
6187 return devdata && intel_bios_encoder_supports_edp(devdata);
6188}
6189
6190bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port)
6191{
6192 const struct intel_bios_encoder_data *devdata =
6193 intel_bios_encoder_data_lookup(i915, port);
6194
6195 return _intel_dp_is_port_edp(i915, devdata, port);
6196}
6197
6198static bool
6199has_gamut_metadata_dip(struct intel_encoder *encoder)
6200{
6201 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
6202 enum port port = encoder->port;
6203
6204 if (intel_bios_encoder_is_lspcon(encoder->devdata))
6205 return false;
6206
6207 if (DISPLAY_VER(i915) >= 11)
6208 return true;
6209
6210 if (port == PORT_A)
6211 return false;
6212
6213 if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
6214 DISPLAY_VER(i915) >= 9)
6215 return true;
6216
6217 return false;
6218}
6219
6220static void
6221intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6222{
6223 struct drm_i915_private *dev_priv = to_i915(connector->dev);
6224 enum port port = dp_to_dig_port(intel_dp)->base.port;
6225
6226 if (!intel_dp_is_edp(intel_dp))
6227 drm_connector_attach_dp_subconnector_property(connector);
6228
6229 if (!IS_G4X(dev_priv) && port != PORT_A)
6230 intel_attach_force_audio_property(connector);
6231
6232 intel_attach_broadcast_rgb_property(connector);
6233 if (HAS_GMCH(dev_priv))
6234 drm_connector_attach_max_bpc_property(connector, 6, 10);
6235 else if (DISPLAY_VER(dev_priv) >= 5)
6236 drm_connector_attach_max_bpc_property(connector, 6, 12);
6237
6238 /* Register HDMI colorspace for case of lspcon */
6239 if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) {
6240 drm_connector_attach_content_type_property(connector);
6241 intel_attach_hdmi_colorspace_property(connector);
6242 } else {
6243 intel_attach_dp_colorspace_property(connector);
6244 }
6245
6246 if (has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
6247 drm_connector_attach_hdr_output_metadata_property(connector);
6248
6249 if (HAS_VRR(dev_priv))
6250 drm_connector_attach_vrr_capable_property(connector);
6251}
6252
6253static void
6254intel_edp_add_properties(struct intel_dp *intel_dp)
6255{
6256 struct intel_connector *connector = intel_dp->attached_connector;
6257 struct drm_i915_private *i915 = to_i915(connector->base.dev);
6258 const struct drm_display_mode *fixed_mode =
6259 intel_panel_preferred_fixed_mode(connector);
6260
6261 intel_attach_scaling_mode_property(&connector->base);
6262
6263 drm_connector_set_panel_orientation_with_quirk(&connector->base,
6264 i915->display.vbt.orientation,
6265 fixed_mode->hdisplay,
6266 fixed_mode->vdisplay);
6267}
6268
6269static void intel_edp_backlight_setup(struct intel_dp *intel_dp,
6270 struct intel_connector *connector)
6271{
6272 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6273 enum pipe pipe = INVALID_PIPE;
6274
6275 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
6276 /*
6277 * Figure out the current pipe for the initial backlight setup.
6278 * If the current pipe isn't valid, try the PPS pipe, and if that
6279 * fails just assume pipe A.
6280 */
6281 pipe = vlv_active_pipe(intel_dp);
6282
6283 if (pipe != PIPE_A && pipe != PIPE_B)
6284 pipe = intel_dp->pps.pps_pipe;
6285
6286 if (pipe != PIPE_A && pipe != PIPE_B)
6287 pipe = PIPE_A;
6288 }
6289
6290 intel_backlight_setup(connector, pipe);
6291}
6292
6293static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6294 struct intel_connector *intel_connector)
6295{
6296 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6297 struct drm_connector *connector = &intel_connector->base;
6298 struct drm_display_mode *fixed_mode;
6299 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6300 bool has_dpcd;
6301 const struct drm_edid *drm_edid;
6302
6303 if (!intel_dp_is_edp(intel_dp))
6304 return true;
6305
6306 /*
6307 * On IBX/CPT we may get here with LVDS already registered. Since the
6308 * driver uses the only internal power sequencer available for both
6309 * eDP and LVDS bail out early in this case to prevent interfering
6310 * with an already powered-on LVDS power sequencer.
6311 */
6312 if (intel_get_lvds_encoder(dev_priv)) {
6313 drm_WARN_ON(&dev_priv->drm,
6314 !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6315 drm_info(&dev_priv->drm,
6316 "LVDS was detected, not registering eDP\n");
6317
6318 return false;
6319 }
6320
6321 intel_bios_init_panel_early(dev_priv, &intel_connector->panel,
6322 encoder->devdata);
6323
6324 if (!intel_pps_init(intel_dp)) {
6325 drm_info(&dev_priv->drm,
6326 "[ENCODER:%d:%s] unusable PPS, disabling eDP\n",
6327 encoder->base.base.id, encoder->base.name);
6328 /*
6329 * The BIOS may have still enabled VDD on the PPS even
6330 * though it's unusable. Make sure we turn it back off
6331 * and to release the power domain references/etc.
6332 */
6333 goto out_vdd_off;
6334 }
6335
6336 /*
6337 * Enable HPD sense for live status check.
6338 * intel_hpd_irq_setup() will turn it off again
6339 * if it's no longer needed later.
6340 *
6341 * The DPCD probe below will make sure VDD is on.
6342 */
6343 intel_hpd_enable_detection(encoder);
6344
6345 /* Cache DPCD and EDID for edp. */
6346 has_dpcd = intel_edp_init_dpcd(intel_dp, intel_connector);
6347
6348 if (!has_dpcd) {
6349 /* if this fails, presume the device is a ghost */
6350 drm_info(&dev_priv->drm,
6351 "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n",
6352 encoder->base.base.id, encoder->base.name);
6353 goto out_vdd_off;
6354 }
6355
6356 /*
6357 * VBT and straps are liars. Also check HPD as that seems
6358 * to be the most reliable piece of information available.
6359 *
6360 * ... expect on devices that forgot to hook HPD up for eDP
6361 * (eg. Acer Chromebook C710), so we'll check it only if multiple
6362 * ports are attempting to use the same AUX CH, according to VBT.
6363 */
6364 if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) {
6365 /*
6366 * If this fails, presume the DPCD answer came
6367 * from some other port using the same AUX CH.
6368 *
6369 * FIXME maybe cleaner to check this before the
6370 * DPCD read? Would need sort out the VDD handling...
6371 */
6372 if (!intel_digital_port_connected(encoder)) {
6373 drm_info(&dev_priv->drm,
6374 "[ENCODER:%d:%s] HPD is down, disabling eDP\n",
6375 encoder->base.base.id, encoder->base.name);
6376 goto out_vdd_off;
6377 }
6378
6379 /*
6380 * Unfortunately even the HPD based detection fails on
6381 * eg. Asus B360M-A (CFL+CNP), so as a last resort fall
6382 * back to checking for a VGA branch device. Only do this
6383 * on known affected platforms to minimize false positives.
6384 */
6385 if (DISPLAY_VER(dev_priv) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&
6386 (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==
6387 DP_DWN_STRM_PORT_TYPE_ANALOG) {
6388 drm_info(&dev_priv->drm,
6389 "[ENCODER:%d:%s] VGA converter detected, disabling eDP\n",
6390 encoder->base.base.id, encoder->base.name);
6391 goto out_vdd_off;
6392 }
6393 }
6394
6395 mutex_lock(&dev_priv->drm.mode_config.mutex);
6396 drm_edid = drm_edid_read_ddc(connector, connector->ddc);
6397 if (!drm_edid) {
6398 /* Fallback to EDID from ACPI OpRegion, if any */
6399 drm_edid = intel_opregion_get_edid(intel_connector);
6400 if (drm_edid)
6401 drm_dbg_kms(&dev_priv->drm,
6402 "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
6403 connector->base.id, connector->name);
6404 }
6405 if (drm_edid) {
6406 if (drm_edid_connector_update(connector, drm_edid) ||
6407 !drm_edid_connector_add_modes(connector)) {
6408 drm_edid_connector_update(connector, NULL);
6409 drm_edid_free(drm_edid);
6410 drm_edid = ERR_PTR(-EINVAL);
6411 }
6412 } else {
6413 drm_edid = ERR_PTR(-ENOENT);
6414 }
6415
6416 intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata,
6417 IS_ERR(drm_edid) ? NULL : drm_edid);
6418
6419 intel_panel_add_edid_fixed_modes(intel_connector, true);
6420
6421 /* MSO requires information from the EDID */
6422 intel_edp_mso_init(intel_dp);
6423
6424 /* multiply the mode clock and horizontal timings for MSO */
6425 list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head)
6426 intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
6427
6428 /* fallback to VBT if available for eDP */
6429 if (!intel_panel_preferred_fixed_mode(intel_connector))
6430 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
6431
6432 mutex_unlock(&dev_priv->drm.mode_config.mutex);
6433
6434 if (!intel_panel_preferred_fixed_mode(intel_connector)) {
6435 drm_info(&dev_priv->drm,
6436 "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n",
6437 encoder->base.base.id, encoder->base.name);
6438 goto out_vdd_off;
6439 }
6440
6441 intel_panel_init(intel_connector, drm_edid);
6442
6443 intel_edp_backlight_setup(intel_dp, intel_connector);
6444
6445 intel_edp_add_properties(intel_dp);
6446
6447 intel_pps_init_late(intel_dp);
6448
6449 return true;
6450
6451out_vdd_off:
6452 intel_pps_vdd_off_sync(intel_dp);
6453
6454 return false;
6455}
6456
6457static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6458{
6459 struct intel_connector *intel_connector;
6460 struct drm_connector *connector;
6461
6462 intel_connector = container_of(work, typeof(*intel_connector),
6463 modeset_retry_work);
6464 connector = &intel_connector->base;
6465 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
6466 connector->name);
6467
6468 /* Grab the locks before changing connector property*/
6469 mutex_lock(&connector->dev->mode_config.mutex);
6470 /* Set connector link status to BAD and send a Uevent to notify
6471 * userspace to do a modeset.
6472 */
6473 drm_connector_set_link_status_property(connector,
6474 DRM_MODE_LINK_STATUS_BAD);
6475 mutex_unlock(&connector->dev->mode_config.mutex);
6476 /* Send Hotplug uevent so userspace can reprobe */
6477 drm_kms_helper_connector_hotplug_event(connector);
6478
6479 drm_connector_put(connector);
6480}
6481
6482void intel_dp_init_modeset_retry_work(struct intel_connector *connector)
6483{
6484 INIT_WORK(&connector->modeset_retry_work,
6485 intel_dp_modeset_retry_work_fn);
6486}
6487
6488bool
6489intel_dp_init_connector(struct intel_digital_port *dig_port,
6490 struct intel_connector *intel_connector)
6491{
6492 struct drm_connector *connector = &intel_connector->base;
6493 struct intel_dp *intel_dp = &dig_port->dp;
6494 struct intel_encoder *intel_encoder = &dig_port->base;
6495 struct drm_device *dev = intel_encoder->base.dev;
6496 struct drm_i915_private *dev_priv = to_i915(dev);
6497 enum port port = intel_encoder->port;
6498 enum phy phy = intel_port_to_phy(dev_priv, port);
6499 int type;
6500
6501 /* Initialize the work for modeset in case of link train failure */
6502 intel_dp_init_modeset_retry_work(intel_connector);
6503
6504 if (drm_WARN(dev, dig_port->max_lanes < 1,
6505 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
6506 dig_port->max_lanes, intel_encoder->base.base.id,
6507 intel_encoder->base.name))
6508 return false;
6509
6510 intel_dp->reset_link_params = true;
6511 intel_dp->pps.pps_pipe = INVALID_PIPE;
6512 intel_dp->pps.active_pipe = INVALID_PIPE;
6513
6514 /* Preserve the current hw state. */
6515 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
6516 intel_dp->attached_connector = intel_connector;
6517
6518 if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
6519 /*
6520 * Currently we don't support eDP on TypeC ports, although in
6521 * theory it could work on TypeC legacy ports.
6522 */
6523 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
6524 type = DRM_MODE_CONNECTOR_eDP;
6525 intel_encoder->type = INTEL_OUTPUT_EDP;
6526
6527 /* eDP only on port B and/or C on vlv/chv */
6528 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
6529 IS_CHERRYVIEW(dev_priv)) &&
6530 port != PORT_B && port != PORT_C))
6531 return false;
6532 } else {
6533 type = DRM_MODE_CONNECTOR_DisplayPort;
6534 }
6535
6536 intel_dp_set_default_sink_rates(intel_dp);
6537 intel_dp_set_default_max_sink_lane_count(intel_dp);
6538
6539 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6540 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
6541
6542 intel_dp_aux_init(intel_dp);
6543 intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
6544
6545 drm_dbg_kms(&dev_priv->drm,
6546 "Adding %s connector on [ENCODER:%d:%s]\n",
6547 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6548 intel_encoder->base.base.id, intel_encoder->base.name);
6549
6550 drm_connector_init_with_ddc(dev, connector, &intel_dp_connector_funcs,
6551 type, &intel_dp->aux.ddc);
6552 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6553
6554 if (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) < 12)
6555 connector->interlace_allowed = true;
6556
6557 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
6558 intel_connector->base.polled = intel_connector->polled;
6559
6560 intel_connector_attach_encoder(intel_connector, intel_encoder);
6561
6562 if (HAS_DDI(dev_priv))
6563 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6564 else
6565 intel_connector->get_hw_state = intel_connector_get_hw_state;
6566 intel_connector->sync_state = intel_dp_connector_sync_state;
6567
6568 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6569 intel_dp_aux_fini(intel_dp);
6570 goto fail;
6571 }
6572
6573 intel_dp_set_source_rates(intel_dp);
6574 intel_dp_set_common_rates(intel_dp);
6575 intel_dp_reset_max_link_params(intel_dp);
6576
6577 /* init MST on ports that can support it */
6578 intel_dp_mst_encoder_init(dig_port,
6579 intel_connector->base.base.id);
6580
6581 intel_dp_add_properties(intel_dp, connector);
6582
6583 if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6584 int ret = intel_dp_hdcp_init(dig_port, intel_connector);
6585 if (ret)
6586 drm_dbg_kms(&dev_priv->drm,
6587 "HDCP init failed, skipping.\n");
6588 }
6589
6590 intel_dp->colorimetry_support =
6591 intel_dp_get_colorimetry_status(intel_dp);
6592
6593 intel_dp->frl.is_trained = false;
6594 intel_dp->frl.trained_rate_gbps = 0;
6595
6596 intel_psr_init(intel_dp);
6597
6598 return true;
6599
6600fail:
6601 intel_display_power_flush_work(dev_priv);
6602 drm_connector_cleanup(connector);
6603
6604 return false;
6605}
6606
6607void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
6608{
6609 struct intel_encoder *encoder;
6610
6611 if (!HAS_DISPLAY(dev_priv))
6612 return;
6613
6614 for_each_intel_encoder(&dev_priv->drm, encoder) {
6615 struct intel_dp *intel_dp;
6616
6617 if (encoder->type != INTEL_OUTPUT_DDI)
6618 continue;
6619
6620 intel_dp = enc_to_intel_dp(encoder);
6621
6622 if (!intel_dp_mst_source_support(intel_dp))
6623 continue;
6624
6625 if (intel_dp->is_mst)
6626 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
6627 }
6628}
6629
6630void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
6631{
6632 struct intel_encoder *encoder;
6633
6634 if (!HAS_DISPLAY(dev_priv))
6635 return;
6636
6637 for_each_intel_encoder(&dev_priv->drm, encoder) {
6638 struct intel_dp *intel_dp;
6639 int ret;
6640
6641 if (encoder->type != INTEL_OUTPUT_DDI)
6642 continue;
6643
6644 intel_dp = enc_to_intel_dp(encoder);
6645
6646 if (!intel_dp_mst_source_support(intel_dp))
6647 continue;
6648
6649 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
6650 true);
6651 if (ret) {
6652 intel_dp->is_mst = false;
6653 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6654 false);
6655 }
6656 }
6657}