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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * linux/arch/arm/lib/delay.S
4 *
5 * Copyright (C) 1995, 1996 Russell King
6 */
7#include <linux/linkage.h>
8#include <linux/cfi_types.h>
9#include <asm/assembler.h>
10#include <asm/delay.h>
11
12#ifdef CONFIG_ARCH_RPC
13 .arch armv4
14#endif
15
16 .text
17
18.LC0: .word loops_per_jiffy
19.LC1: .word UDELAY_MULT
20
21/*
22 * loops = r0 * HZ * loops_per_jiffy / 1000000
23 *
24 * r0 <= 2000
25 * HZ <= 1000
26 */
27
28SYM_TYPED_FUNC_START(__loop_udelay)
29 ldr r2, .LC1
30 mul r0, r2, r0 @ r0 = delay_us * UDELAY_MULT
31 b __loop_const_udelay
32SYM_FUNC_END(__loop_udelay)
33
34SYM_TYPED_FUNC_START(__loop_const_udelay) @ 0 <= r0 <= 0xfffffaf0
35 ldr r2, .LC0
36 ldr r2, [r2]
37 umull r1, r0, r2, r0 @ r0-r1 = r0 * loops_per_jiffy
38 adds r1, r1, #0xffffffff @ rounding up ...
39 adcs r0, r0, r0 @ and right shift by 31
40 reteq lr
41 b __loop_delay
42SYM_FUNC_END(__loop_const_udelay)
43
44 .align 3
45
46@ Delay routine
47SYM_TYPED_FUNC_START(__loop_delay)
48 subs r0, r0, #1
49#if 0
50 retls lr
51 subs r0, r0, #1
52 retls lr
53 subs r0, r0, #1
54 retls lr
55 subs r0, r0, #1
56 retls lr
57 subs r0, r0, #1
58 retls lr
59 subs r0, r0, #1
60 retls lr
61 subs r0, r0, #1
62 retls lr
63 subs r0, r0, #1
64#endif
65 bhi __loop_delay
66 ret lr
67SYM_FUNC_END(__loop_delay)
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * linux/arch/arm/lib/delay.S
4 *
5 * Copyright (C) 1995, 1996 Russell King
6 */
7#include <linux/linkage.h>
8#include <asm/assembler.h>
9#include <asm/delay.h>
10
11#ifdef CONFIG_ARCH_RPC
12 .arch armv4
13#endif
14
15 .text
16
17.LC0: .word loops_per_jiffy
18.LC1: .word UDELAY_MULT
19
20/*
21 * loops = r0 * HZ * loops_per_jiffy / 1000000
22 *
23 * r0 <= 2000
24 * HZ <= 1000
25 */
26
27ENTRY(__loop_udelay)
28 ldr r2, .LC1
29 mul r0, r2, r0 @ r0 = delay_us * UDELAY_MULT
30ENTRY(__loop_const_udelay) @ 0 <= r0 <= 0xfffffaf0
31 ldr r2, .LC0
32 ldr r2, [r2]
33 umull r1, r0, r2, r0 @ r0-r1 = r0 * loops_per_jiffy
34 adds r1, r1, #0xffffffff @ rounding up ...
35 adcs r0, r0, r0 @ and right shift by 31
36 reteq lr
37
38 .align 3
39
40@ Delay routine
41ENTRY(__loop_delay)
42 subs r0, r0, #1
43#if 0
44 retls lr
45 subs r0, r0, #1
46 retls lr
47 subs r0, r0, #1
48 retls lr
49 subs r0, r0, #1
50 retls lr
51 subs r0, r0, #1
52 retls lr
53 subs r0, r0, #1
54 retls lr
55 subs r0, r0, #1
56 retls lr
57 subs r0, r0, #1
58#endif
59 bhi __loop_delay
60 ret lr
61ENDPROC(__loop_udelay)
62ENDPROC(__loop_const_udelay)
63ENDPROC(__loop_delay)