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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright(c) 2021-2022 Intel Corporation
4 *
5 * Authors: Cezary Rojewski <cezary.rojewski@intel.com>
6 * Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
7 */
8
9#ifndef __SOUND_SOC_INTEL_AVS_REGS_H
10#define __SOUND_SOC_INTEL_AVS_REGS_H
11
12#include <linux/io-64-nonatomic-lo-hi.h>
13#include <linux/iopoll.h>
14#include <linux/sizes.h>
15
16#define AZX_PCIREG_PGCTL 0x44
17#define AZX_PCIREG_CGCTL 0x48
18#define AZX_PGCTL_LSRMD_MASK BIT(4)
19#define AZX_CGCTL_MISCBDCGE_MASK BIT(6)
20#define AZX_VS_EM2_L1SEN BIT(13)
21#define AZX_VS_EM2_DUM BIT(23)
22
23/* Intel HD Audio General DSP Registers */
24#define AVS_ADSP_GEN_BASE 0x0
25#define AVS_ADSP_REG_ADSPCS (AVS_ADSP_GEN_BASE + 0x04)
26#define AVS_ADSP_REG_ADSPIC (AVS_ADSP_GEN_BASE + 0x08)
27#define AVS_ADSP_REG_ADSPIS (AVS_ADSP_GEN_BASE + 0x0C)
28
29#define AVS_ADSP_ADSPIC_IPC BIT(0)
30#define AVS_ADSP_ADSPIC_CLDMA BIT(1)
31#define AVS_ADSP_ADSPIS_IPC BIT(0)
32#define AVS_ADSP_ADSPIS_CLDMA BIT(1)
33
34#define AVS_ADSPCS_CRST_MASK(cm) (cm)
35#define AVS_ADSPCS_CSTALL_MASK(cm) ((cm) << 8)
36#define AVS_ADSPCS_SPA_MASK(cm) ((cm) << 16)
37#define AVS_ADSPCS_CPA_MASK(cm) ((cm) << 24)
38#define AVS_MAIN_CORE_MASK BIT(0)
39
40#define AVS_ADSP_HIPCCTL_BUSY BIT(0)
41#define AVS_ADSP_HIPCCTL_DONE BIT(1)
42
43/* SKL Intel HD Audio Inter-Processor Communication Registers */
44#define SKL_ADSP_IPC_BASE 0x40
45#define SKL_ADSP_REG_HIPCT (SKL_ADSP_IPC_BASE + 0x00)
46#define SKL_ADSP_REG_HIPCTE (SKL_ADSP_IPC_BASE + 0x04)
47#define SKL_ADSP_REG_HIPCI (SKL_ADSP_IPC_BASE + 0x08)
48#define SKL_ADSP_REG_HIPCIE (SKL_ADSP_IPC_BASE + 0x0C)
49#define SKL_ADSP_REG_HIPCCTL (SKL_ADSP_IPC_BASE + 0x10)
50
51#define SKL_ADSP_HIPCI_BUSY BIT(31)
52#define SKL_ADSP_HIPCIE_DONE BIT(30)
53#define SKL_ADSP_HIPCT_BUSY BIT(31)
54
55/* CNL Intel HD Audio Inter-Processor Communication Registers */
56#define CNL_ADSP_IPC_BASE 0xC0
57#define CNL_ADSP_REG_HIPCTDR (CNL_ADSP_IPC_BASE + 0x00)
58#define CNL_ADSP_REG_HIPCTDA (CNL_ADSP_IPC_BASE + 0x04)
59#define CNL_ADSP_REG_HIPCTDD (CNL_ADSP_IPC_BASE + 0x08)
60#define CNL_ADSP_REG_HIPCIDR (CNL_ADSP_IPC_BASE + 0x10)
61#define CNL_ADSP_REG_HIPCIDA (CNL_ADSP_IPC_BASE + 0x14)
62#define CNL_ADSP_REG_HIPCIDD (CNL_ADSP_IPC_BASE + 0x18)
63#define CNL_ADSP_REG_HIPCCTL (CNL_ADSP_IPC_BASE + 0x28)
64
65#define CNL_ADSP_HIPCTDR_BUSY BIT(31)
66#define CNL_ADSP_HIPCTDA_DONE BIT(31)
67#define CNL_ADSP_HIPCIDR_BUSY BIT(31)
68#define CNL_ADSP_HIPCIDA_DONE BIT(31)
69
70/* Intel HD Audio SRAM windows base addresses */
71#define SKL_ADSP_SRAM_BASE_OFFSET 0x8000
72#define SKL_ADSP_SRAM_WINDOW_SIZE 0x2000
73#define APL_ADSP_SRAM_BASE_OFFSET 0x80000
74#define APL_ADSP_SRAM_WINDOW_SIZE 0x20000
75
76/* Constants used when accessing SRAM, space shared with firmware */
77#define AVS_FW_REG_BASE(adev) ((adev)->spec->sram->base_offset)
78#define AVS_FW_REG_STATUS(adev) (AVS_FW_REG_BASE(adev) + 0x0)
79#define AVS_FW_REG_ERROR_CODE(adev) (AVS_FW_REG_BASE(adev) + 0x4)
80
81#define AVS_WINDOW_CHUNK_SIZE SZ_4K
82#define AVS_FW_REGS_SIZE AVS_WINDOW_CHUNK_SIZE
83#define AVS_FW_REGS_WINDOW 0
84/* DSP -> HOST communication window */
85#define AVS_UPLINK_WINDOW AVS_FW_REGS_WINDOW
86/* HOST -> DSP communication window */
87#define AVS_DOWNLINK_WINDOW 1
88#define AVS_DEBUG_WINDOW 2
89
90/* registry I/O helpers */
91#define avs_sram_offset(adev, window_idx) \
92 ((adev)->spec->sram->base_offset + \
93 (adev)->spec->sram->window_size * (window_idx))
94
95#define avs_sram_addr(adev, window_idx) \
96 ((adev)->dsp_ba + avs_sram_offset(adev, window_idx))
97
98#define avs_uplink_addr(adev) \
99 (avs_sram_addr(adev, AVS_UPLINK_WINDOW) + AVS_FW_REGS_SIZE)
100#define avs_downlink_addr(adev) \
101 avs_sram_addr(adev, AVS_DOWNLINK_WINDOW)
102
103#define snd_hdac_adsp_writeb(adev, reg, value) \
104 snd_hdac_reg_writeb(&(adev)->base.core, (adev)->dsp_ba + (reg), value)
105#define snd_hdac_adsp_readb(adev, reg) \
106 snd_hdac_reg_readb(&(adev)->base.core, (adev)->dsp_ba + (reg))
107#define snd_hdac_adsp_writew(adev, reg, value) \
108 snd_hdac_reg_writew(&(adev)->base.core, (adev)->dsp_ba + (reg), value)
109#define snd_hdac_adsp_readw(adev, reg) \
110 snd_hdac_reg_readw(&(adev)->base.core, (adev)->dsp_ba + (reg))
111#define snd_hdac_adsp_writel(adev, reg, value) \
112 snd_hdac_reg_writel(&(adev)->base.core, (adev)->dsp_ba + (reg), value)
113#define snd_hdac_adsp_readl(adev, reg) \
114 snd_hdac_reg_readl(&(adev)->base.core, (adev)->dsp_ba + (reg))
115#define snd_hdac_adsp_writeq(adev, reg, value) \
116 snd_hdac_reg_writeq(&(adev)->base.core, (adev)->dsp_ba + (reg), value)
117#define snd_hdac_adsp_readq(adev, reg) \
118 snd_hdac_reg_readq(&(adev)->base.core, (adev)->dsp_ba + (reg))
119
120#define snd_hdac_adsp_updateb(adev, reg, mask, val) \
121 snd_hdac_adsp_writeb(adev, reg, \
122 (snd_hdac_adsp_readb(adev, reg) & ~(mask)) | (val))
123#define snd_hdac_adsp_updatew(adev, reg, mask, val) \
124 snd_hdac_adsp_writew(adev, reg, \
125 (snd_hdac_adsp_readw(adev, reg) & ~(mask)) | (val))
126#define snd_hdac_adsp_updatel(adev, reg, mask, val) \
127 snd_hdac_adsp_writel(adev, reg, \
128 (snd_hdac_adsp_readl(adev, reg) & ~(mask)) | (val))
129#define snd_hdac_adsp_updateq(adev, reg, mask, val) \
130 snd_hdac_adsp_writeq(adev, reg, \
131 (snd_hdac_adsp_readq(adev, reg) & ~(mask)) | (val))
132
133#define snd_hdac_adsp_readb_poll(adev, reg, val, cond, delay_us, timeout_us) \
134 readb_poll_timeout((adev)->dsp_ba + (reg), val, cond, \
135 delay_us, timeout_us)
136#define snd_hdac_adsp_readw_poll(adev, reg, val, cond, delay_us, timeout_us) \
137 readw_poll_timeout((adev)->dsp_ba + (reg), val, cond, \
138 delay_us, timeout_us)
139#define snd_hdac_adsp_readl_poll(adev, reg, val, cond, delay_us, timeout_us) \
140 readl_poll_timeout((adev)->dsp_ba + (reg), val, cond, \
141 delay_us, timeout_us)
142#define snd_hdac_adsp_readq_poll(adev, reg, val, cond, delay_us, timeout_us) \
143 readq_poll_timeout((adev)->dsp_ba + (reg), val, cond, \
144 delay_us, timeout_us)
145
146#endif /* __SOUND_SOC_INTEL_AVS_REGS_H */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
4 *
5 * Authors: Cezary Rojewski <cezary.rojewski@intel.com>
6 * Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
7 */
8
9#ifndef __SOUND_SOC_INTEL_AVS_REGS_H
10#define __SOUND_SOC_INTEL_AVS_REGS_H
11
12#include <linux/sizes.h>
13
14#define AZX_PCIREG_PGCTL 0x44
15#define AZX_PCIREG_CGCTL 0x48
16#define AZX_PGCTL_LSRMD_MASK BIT(4)
17#define AZX_CGCTL_MISCBDCGE_MASK BIT(6)
18#define AZX_VS_EM2_L1SEN BIT(13)
19#define AZX_VS_EM2_DUM BIT(23)
20
21/* Intel HD Audio General DSP Registers */
22#define AVS_ADSP_GEN_BASE 0x0
23#define AVS_ADSP_REG_ADSPCS (AVS_ADSP_GEN_BASE + 0x04)
24#define AVS_ADSP_REG_ADSPIC (AVS_ADSP_GEN_BASE + 0x08)
25#define AVS_ADSP_REG_ADSPIS (AVS_ADSP_GEN_BASE + 0x0C)
26
27#define AVS_ADSP_ADSPIC_IPC BIT(0)
28#define AVS_ADSP_ADSPIC_CLDMA BIT(1)
29#define AVS_ADSP_ADSPIS_IPC BIT(0)
30#define AVS_ADSP_ADSPIS_CLDMA BIT(1)
31
32#define AVS_ADSPCS_CRST_MASK(cm) (cm)
33#define AVS_ADSPCS_CSTALL_MASK(cm) ((cm) << 8)
34#define AVS_ADSPCS_SPA_MASK(cm) ((cm) << 16)
35#define AVS_ADSPCS_CPA_MASK(cm) ((cm) << 24)
36#define AVS_MAIN_CORE_MASK BIT(0)
37
38#define AVS_ADSP_HIPCCTL_BUSY BIT(0)
39#define AVS_ADSP_HIPCCTL_DONE BIT(1)
40
41/* SKL Intel HD Audio Inter-Processor Communication Registers */
42#define SKL_ADSP_IPC_BASE 0x40
43#define SKL_ADSP_REG_HIPCT (SKL_ADSP_IPC_BASE + 0x00)
44#define SKL_ADSP_REG_HIPCTE (SKL_ADSP_IPC_BASE + 0x04)
45#define SKL_ADSP_REG_HIPCI (SKL_ADSP_IPC_BASE + 0x08)
46#define SKL_ADSP_REG_HIPCIE (SKL_ADSP_IPC_BASE + 0x0C)
47#define SKL_ADSP_REG_HIPCCTL (SKL_ADSP_IPC_BASE + 0x10)
48
49#define SKL_ADSP_HIPCI_BUSY BIT(31)
50#define SKL_ADSP_HIPCIE_DONE BIT(30)
51#define SKL_ADSP_HIPCT_BUSY BIT(31)
52
53/* Intel HD Audio SRAM windows base addresses */
54#define SKL_ADSP_SRAM_BASE_OFFSET 0x8000
55#define SKL_ADSP_SRAM_WINDOW_SIZE 0x2000
56#define APL_ADSP_SRAM_BASE_OFFSET 0x80000
57#define APL_ADSP_SRAM_WINDOW_SIZE 0x20000
58
59/* Constants used when accessing SRAM, space shared with firmware */
60#define AVS_FW_REG_BASE(adev) ((adev)->spec->sram_base_offset)
61#define AVS_FW_REG_STATUS(adev) (AVS_FW_REG_BASE(adev) + 0x0)
62#define AVS_FW_REG_ERROR_CODE(adev) (AVS_FW_REG_BASE(adev) + 0x4)
63
64#define AVS_WINDOW_CHUNK_SIZE SZ_4K
65#define AVS_FW_REGS_SIZE AVS_WINDOW_CHUNK_SIZE
66#define AVS_FW_REGS_WINDOW 0
67/* DSP -> HOST communication window */
68#define AVS_UPLINK_WINDOW AVS_FW_REGS_WINDOW
69/* HOST -> DSP communication window */
70#define AVS_DOWNLINK_WINDOW 1
71#define AVS_DEBUG_WINDOW 2
72
73/* registry I/O helpers */
74#define avs_sram_offset(adev, window_idx) \
75 ((adev)->spec->sram_base_offset + \
76 (adev)->spec->sram_window_size * (window_idx))
77
78#define avs_sram_addr(adev, window_idx) \
79 ((adev)->dsp_ba + avs_sram_offset(adev, window_idx))
80
81#define avs_uplink_addr(adev) \
82 (avs_sram_addr(adev, AVS_UPLINK_WINDOW) + AVS_FW_REGS_SIZE)
83#define avs_downlink_addr(adev) \
84 avs_sram_addr(adev, AVS_DOWNLINK_WINDOW)
85
86#endif /* __SOUND_SOC_INTEL_AVS_REGS_H */