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1// SPDX-License-Identifier: GPL-2.0-only
2//
3// Components shared between ASoC and HDA CS35L56 drivers
4//
5// Copyright (C) 2023 Cirrus Logic, Inc. and
6// Cirrus Logic International Semiconductor Ltd.
7
8#include <linux/array_size.h>
9#include <linux/firmware/cirrus/wmfw.h>
10#include <linux/gpio/consumer.h>
11#include <linux/regmap.h>
12#include <linux/regulator/consumer.h>
13#include <linux/spi/spi.h>
14#include <linux/types.h>
15#include <sound/cs-amp-lib.h>
16
17#include "cs35l56.h"
18
19static const struct reg_sequence cs35l56_patch[] = {
20 /*
21 * Firmware can change these to non-defaults to satisfy SDCA.
22 * Ensure that they are at known defaults.
23 */
24 { CS35L56_ASP1_ENABLES1, 0x00000000 },
25 { CS35L56_ASP1_CONTROL1, 0x00000028 },
26 { CS35L56_ASP1_CONTROL2, 0x18180200 },
27 { CS35L56_ASP1_CONTROL3, 0x00000002 },
28 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 },
29 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 },
30 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 },
31 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 },
32 { CS35L56_ASP1TX1_INPUT, 0x00000000 },
33 { CS35L56_ASP1TX2_INPUT, 0x00000000 },
34 { CS35L56_ASP1TX3_INPUT, 0x00000000 },
35 { CS35L56_ASP1TX4_INPUT, 0x00000000 },
36 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 },
37 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 },
38 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 },
39 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 },
40 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff },
41
42 /* These are not reset by a soft-reset, so patch to defaults. */
43 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 },
44 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 },
45 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 },
46};
47
48int cs35l56_set_patch(struct cs35l56_base *cs35l56_base)
49{
50 return regmap_register_patch(cs35l56_base->regmap, cs35l56_patch,
51 ARRAY_SIZE(cs35l56_patch));
52}
53EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, "SND_SOC_CS35L56_SHARED");
54
55static const struct reg_default cs35l56_reg_defaults[] = {
56 /* no defaults for OTP_MEM - first read populates cache */
57
58 { CS35L56_ASP1_ENABLES1, 0x00000000 },
59 { CS35L56_ASP1_CONTROL1, 0x00000028 },
60 { CS35L56_ASP1_CONTROL2, 0x18180200 },
61 { CS35L56_ASP1_CONTROL3, 0x00000002 },
62 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 },
63 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 },
64 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 },
65 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 },
66 { CS35L56_ASP1TX1_INPUT, 0x00000000 },
67 { CS35L56_ASP1TX2_INPUT, 0x00000000 },
68 { CS35L56_ASP1TX3_INPUT, 0x00000000 },
69 { CS35L56_ASP1TX4_INPUT, 0x00000000 },
70 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 },
71 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 },
72 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 },
73 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 },
74 { CS35L56_IRQ1_MASK_1, 0x83ffffff },
75 { CS35L56_IRQ1_MASK_2, 0xffff7fff },
76 { CS35L56_IRQ1_MASK_4, 0xe0ffffff },
77 { CS35L56_IRQ1_MASK_8, 0xfc000fff },
78 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff },
79 { CS35L56_IRQ1_MASK_20, 0x15c00000 },
80 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 },
81 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 },
82 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 },
83};
84
85static bool cs35l56_is_dsp_memory(unsigned int reg)
86{
87 switch (reg) {
88 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143:
89 case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095:
90 case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191:
91 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604:
92 case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070:
93 case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141:
94 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114:
95 return true;
96 default:
97 return false;
98 }
99}
100
101static bool cs35l56_readable_reg(struct device *dev, unsigned int reg)
102{
103 switch (reg) {
104 case CS35L56_DEVID:
105 case CS35L56_REVID:
106 case CS35L56_RELID:
107 case CS35L56_OTPID:
108 case CS35L56_SFT_RESET:
109 case CS35L56_GLOBAL_ENABLES:
110 case CS35L56_BLOCK_ENABLES:
111 case CS35L56_BLOCK_ENABLES2:
112 case CS35L56_REFCLK_INPUT:
113 case CS35L56_GLOBAL_SAMPLE_RATE:
114 case CS35L56_OTP_MEM_53:
115 case CS35L56_OTP_MEM_54:
116 case CS35L56_OTP_MEM_55:
117 case CS35L56_ASP1_ENABLES1:
118 case CS35L56_ASP1_CONTROL1:
119 case CS35L56_ASP1_CONTROL2:
120 case CS35L56_ASP1_CONTROL3:
121 case CS35L56_ASP1_FRAME_CONTROL1:
122 case CS35L56_ASP1_FRAME_CONTROL5:
123 case CS35L56_ASP1_DATA_CONTROL1:
124 case CS35L56_ASP1_DATA_CONTROL5:
125 case CS35L56_DACPCM1_INPUT:
126 case CS35L56_DACPCM2_INPUT:
127 case CS35L56_ASP1TX1_INPUT:
128 case CS35L56_ASP1TX2_INPUT:
129 case CS35L56_ASP1TX3_INPUT:
130 case CS35L56_ASP1TX4_INPUT:
131 case CS35L56_DSP1RX1_INPUT:
132 case CS35L56_DSP1RX2_INPUT:
133 case CS35L56_SWIRE_DP3_CH1_INPUT:
134 case CS35L56_SWIRE_DP3_CH2_INPUT:
135 case CS35L56_SWIRE_DP3_CH3_INPUT:
136 case CS35L56_SWIRE_DP3_CH4_INPUT:
137 case CS35L56_IRQ1_CFG:
138 case CS35L56_IRQ1_STATUS:
139 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8:
140 case CS35L56_IRQ1_EINT_18:
141 case CS35L56_IRQ1_EINT_20:
142 case CS35L56_IRQ1_MASK_1:
143 case CS35L56_IRQ1_MASK_2:
144 case CS35L56_IRQ1_MASK_4:
145 case CS35L56_IRQ1_MASK_8:
146 case CS35L56_IRQ1_MASK_18:
147 case CS35L56_IRQ1_MASK_20:
148 case CS35L56_DSP_VIRTUAL1_MBOX_1:
149 case CS35L56_DSP_VIRTUAL1_MBOX_2:
150 case CS35L56_DSP_VIRTUAL1_MBOX_3:
151 case CS35L56_DSP_VIRTUAL1_MBOX_4:
152 case CS35L56_DSP_VIRTUAL1_MBOX_5:
153 case CS35L56_DSP_VIRTUAL1_MBOX_6:
154 case CS35L56_DSP_VIRTUAL1_MBOX_7:
155 case CS35L56_DSP_VIRTUAL1_MBOX_8:
156 case CS35L56_DSP_RESTRICT_STS1:
157 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END:
158 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0:
159 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1:
160 case CS35L56_DSP1_SCRATCH1:
161 case CS35L56_DSP1_SCRATCH2:
162 case CS35L56_DSP1_SCRATCH3:
163 case CS35L56_DSP1_SCRATCH4:
164 return true;
165 default:
166 return cs35l56_is_dsp_memory(reg);
167 }
168}
169
170static bool cs35l56_precious_reg(struct device *dev, unsigned int reg)
171{
172 switch (reg) {
173 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143:
174 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604:
175 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114:
176 return true;
177 default:
178 return false;
179 }
180}
181
182static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg)
183{
184 switch (reg) {
185 case CS35L56_DEVID:
186 case CS35L56_REVID:
187 case CS35L56_RELID:
188 case CS35L56_OTPID:
189 case CS35L56_SFT_RESET:
190 case CS35L56_GLOBAL_ENABLES: /* owned by firmware */
191 case CS35L56_BLOCK_ENABLES: /* owned by firmware */
192 case CS35L56_BLOCK_ENABLES2: /* owned by firmware */
193 case CS35L56_REFCLK_INPUT: /* owned by firmware */
194 case CS35L56_GLOBAL_SAMPLE_RATE: /* owned by firmware */
195 case CS35L56_DACPCM1_INPUT: /* owned by firmware */
196 case CS35L56_DACPCM2_INPUT: /* owned by firmware */
197 case CS35L56_DSP1RX1_INPUT: /* owned by firmware */
198 case CS35L56_DSP1RX2_INPUT: /* owned by firmware */
199 case CS35L56_IRQ1_STATUS:
200 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8:
201 case CS35L56_IRQ1_EINT_18:
202 case CS35L56_IRQ1_EINT_20:
203 case CS35L56_DSP_VIRTUAL1_MBOX_1:
204 case CS35L56_DSP_VIRTUAL1_MBOX_2:
205 case CS35L56_DSP_VIRTUAL1_MBOX_3:
206 case CS35L56_DSP_VIRTUAL1_MBOX_4:
207 case CS35L56_DSP_VIRTUAL1_MBOX_5:
208 case CS35L56_DSP_VIRTUAL1_MBOX_6:
209 case CS35L56_DSP_VIRTUAL1_MBOX_7:
210 case CS35L56_DSP_VIRTUAL1_MBOX_8:
211 case CS35L56_DSP_RESTRICT_STS1:
212 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END:
213 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0:
214 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1:
215 case CS35L56_DSP1_SCRATCH1:
216 case CS35L56_DSP1_SCRATCH2:
217 case CS35L56_DSP1_SCRATCH3:
218 case CS35L56_DSP1_SCRATCH4:
219 return true;
220 case CS35L56_MAIN_RENDER_USER_MUTE:
221 case CS35L56_MAIN_RENDER_USER_VOLUME:
222 case CS35L56_MAIN_POSTURE_NUMBER:
223 return false;
224 default:
225 return cs35l56_is_dsp_memory(reg);
226 }
227}
228
229int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command)
230{
231 unsigned int val;
232 int ret;
233
234 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command);
235 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1,
236 val, (val == 0),
237 CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US);
238 if (ret) {
239 dev_warn(cs35l56_base->dev, "MBOX command %#x failed: %d\n", command, ret);
240 return ret;
241 }
242
243 return 0;
244}
245EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, "SND_SOC_CS35L56_SHARED");
246
247int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base)
248{
249 int ret;
250 unsigned int val;
251
252 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN);
253 if (ret)
254 return ret;
255
256 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP1_PM_CUR_STATE,
257 val, (val == CS35L56_HALO_STATE_SHUTDOWN),
258 CS35L56_HALO_STATE_POLL_US,
259 CS35L56_HALO_STATE_TIMEOUT_US);
260 if (ret < 0)
261 dev_err(cs35l56_base->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n",
262 val, ret);
263 return ret;
264}
265EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, "SND_SOC_CS35L56_SHARED");
266
267int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base)
268{
269 unsigned int val = 0;
270 int read_ret, poll_ret;
271
272 /*
273 * The regmap must remain in cache-only until the chip has
274 * booted, so use a bypassed read of the status register.
275 */
276 poll_ret = read_poll_timeout(regmap_read_bypassed, read_ret,
277 (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE),
278 CS35L56_HALO_STATE_POLL_US,
279 CS35L56_HALO_STATE_TIMEOUT_US,
280 false,
281 cs35l56_base->regmap, CS35L56_DSP1_HALO_STATE, &val);
282
283 if (poll_ret) {
284 dev_err(cs35l56_base->dev, "Firmware boot timed out(%d): HALO_STATE=%#x\n",
285 read_ret, val);
286 return -EIO;
287 }
288
289 return 0;
290}
291EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, "SND_SOC_CS35L56_SHARED");
292
293void cs35l56_wait_control_port_ready(void)
294{
295 /* Wait for control port to be ready (datasheet tIRS). */
296 usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US);
297}
298EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, "SND_SOC_CS35L56_SHARED");
299
300void cs35l56_wait_min_reset_pulse(void)
301{
302 /* Satisfy minimum reset pulse width spec */
303 usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US);
304}
305EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pulse, "SND_SOC_CS35L56_SHARED");
306
307static const struct {
308 u32 addr;
309 u32 value;
310} cs35l56_spi_system_reset_stages[] = {
311 { .addr = CS35L56_DSP_VIRTUAL1_MBOX_1, .value = CS35L56_MBOX_CMD_SYSTEM_RESET },
312 /* The next write is necessary to delimit the soft reset */
313 { .addr = CS35L56_DSP_MBOX_1_RAW, .value = CS35L56_MBOX_CMD_PING },
314};
315
316static void cs35l56_spi_issue_bus_locked_reset(struct cs35l56_base *cs35l56_base,
317 struct spi_device *spi)
318{
319 struct cs35l56_spi_payload *buf = cs35l56_base->spi_payload_buf;
320 struct spi_transfer t = {
321 .tx_buf = buf,
322 .len = sizeof(*buf),
323 };
324 struct spi_message m;
325 int i, ret;
326
327 for (i = 0; i < ARRAY_SIZE(cs35l56_spi_system_reset_stages); i++) {
328 buf->addr = cpu_to_be32(cs35l56_spi_system_reset_stages[i].addr);
329 buf->value = cpu_to_be32(cs35l56_spi_system_reset_stages[i].value);
330 spi_message_init_with_transfers(&m, &t, 1);
331 ret = spi_sync_locked(spi, &m);
332 if (ret)
333 dev_warn(cs35l56_base->dev, "spi_sync failed: %d\n", ret);
334
335 usleep_range(CS35L56_SPI_RESET_TO_PORT_READY_US,
336 2 * CS35L56_SPI_RESET_TO_PORT_READY_US);
337 }
338}
339
340static void cs35l56_spi_system_reset(struct cs35l56_base *cs35l56_base)
341{
342 struct spi_device *spi = to_spi_device(cs35l56_base->dev);
343 unsigned int val;
344 int read_ret, ret;
345
346 /*
347 * There must not be any other SPI bus activity while the amp is
348 * soft-resetting.
349 */
350 ret = spi_bus_lock(spi->controller);
351 if (ret) {
352 dev_warn(cs35l56_base->dev, "spi_bus_lock failed: %d\n", ret);
353 return;
354 }
355
356 cs35l56_spi_issue_bus_locked_reset(cs35l56_base, spi);
357 spi_bus_unlock(spi->controller);
358
359 /*
360 * Check firmware boot by testing for a response in MBOX_2.
361 * HALO_STATE cannot be trusted yet because the reset sequence
362 * can leave it with stale state. But MBOX is reset.
363 * The regmap must remain in cache-only until the chip has
364 * booted, so use a bypassed read.
365 */
366 ret = read_poll_timeout(regmap_read_bypassed, read_ret,
367 (val > 0) && (val < 0xffffffff),
368 CS35L56_HALO_STATE_POLL_US,
369 CS35L56_HALO_STATE_TIMEOUT_US,
370 false,
371 cs35l56_base->regmap,
372 CS35L56_DSP_VIRTUAL1_MBOX_2,
373 &val);
374 if (ret) {
375 dev_err(cs35l56_base->dev, "SPI reboot timed out(%d): MBOX2=%#x\n",
376 read_ret, val);
377 }
378}
379
380static const struct reg_sequence cs35l56_system_reset_seq[] = {
381 REG_SEQ0(CS35L56_DSP1_HALO_STATE, 0),
382 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET),
383};
384
385void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire)
386{
387 /*
388 * Must enter cache-only first so there can't be any more register
389 * accesses other than the controlled system reset sequence below.
390 */
391 regcache_cache_only(cs35l56_base->regmap, true);
392
393 if (cs35l56_is_spi(cs35l56_base)) {
394 cs35l56_spi_system_reset(cs35l56_base);
395 return;
396 }
397
398 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
399 cs35l56_system_reset_seq,
400 ARRAY_SIZE(cs35l56_system_reset_seq));
401
402 /* On SoundWire the registers won't be accessible until it re-enumerates. */
403 if (is_soundwire)
404 return;
405
406 cs35l56_wait_control_port_ready();
407
408 /* Leave in cache-only. This will be revoked when the chip has rebooted. */
409}
410EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, "SND_SOC_CS35L56_SHARED");
411
412int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq)
413{
414 int ret;
415
416 if (irq < 1)
417 return 0;
418
419 ret = devm_request_threaded_irq(cs35l56_base->dev, irq, NULL, cs35l56_irq,
420 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW,
421 "cs35l56", cs35l56_base);
422 if (!ret)
423 cs35l56_base->irq = irq;
424 else
425 dev_err(cs35l56_base->dev, "Failed to get IRQ: %d\n", ret);
426
427 return ret;
428}
429EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, "SND_SOC_CS35L56_SHARED");
430
431irqreturn_t cs35l56_irq(int irq, void *data)
432{
433 struct cs35l56_base *cs35l56_base = data;
434 unsigned int status1 = 0, status8 = 0, status20 = 0;
435 unsigned int mask1, mask8, mask20;
436 unsigned int val;
437 int rv;
438
439 irqreturn_t ret = IRQ_NONE;
440
441 if (!cs35l56_base->init_done)
442 return IRQ_NONE;
443
444 mutex_lock(&cs35l56_base->irq_lock);
445
446 rv = pm_runtime_resume_and_get(cs35l56_base->dev);
447 if (rv < 0) {
448 dev_err(cs35l56_base->dev, "irq: failed to get pm_runtime: %d\n", rv);
449 goto err_unlock;
450 }
451
452 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val);
453 if ((val & CS35L56_IRQ1_STS_MASK) == 0) {
454 dev_dbg(cs35l56_base->dev, "Spurious IRQ: no pending interrupt\n");
455 goto err;
456 }
457
458 /* Ack interrupts */
459 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, &status1);
460 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, &mask1);
461 status1 &= ~mask1;
462 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, status1);
463
464 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, &status8);
465 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, &mask8);
466 status8 &= ~mask8;
467 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, status8);
468
469 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_20, &status20);
470 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, &mask20);
471 status20 &= ~mask20;
472 /* We don't want EINT20 but they default to unmasked: force mask */
473 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff);
474
475 dev_dbg(cs35l56_base->dev, "%s: %#x %#x\n", __func__, status1, status8);
476
477 /* Check to see if unmasked bits are active */
478 if (!status1 && !status8 && !status20)
479 goto err;
480
481 if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK)
482 dev_crit(cs35l56_base->dev, "Amp short error\n");
483
484 if (status8 & CS35L56_TEMP_ERR_EINT1_MASK)
485 dev_crit(cs35l56_base->dev, "Overtemp error\n");
486
487 ret = IRQ_HANDLED;
488
489err:
490 pm_runtime_put(cs35l56_base->dev);
491err_unlock:
492 mutex_unlock(&cs35l56_base->irq_lock);
493
494 return ret;
495}
496EXPORT_SYMBOL_NS_GPL(cs35l56_irq, "SND_SOC_CS35L56_SHARED");
497
498int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base)
499{
500 unsigned int val;
501 int ret;
502
503 /*
504 * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so
505 * can't be used here to test for memory retention.
506 * Assume that tuning must be re-loaded.
507 */
508 if (cs35l56_base->secured)
509 return true;
510
511 ret = pm_runtime_resume_and_get(cs35l56_base->dev);
512 if (ret) {
513 dev_err(cs35l56_base->dev, "Failed to runtime_get: %d\n", ret);
514 return ret;
515 }
516
517 ret = regmap_read(cs35l56_base->regmap, CS35L56_PROTECTION_STATUS, &val);
518 if (ret)
519 dev_err(cs35l56_base->dev, "Failed to read PROTECTION_STATUS: %d\n", ret);
520 else
521 ret = !!(val & CS35L56_FIRMWARE_MISSING);
522
523 pm_runtime_put_autosuspend(cs35l56_base->dev);
524
525 return ret;
526}
527EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, "SND_SOC_CS35L56_SHARED");
528
529static const struct reg_sequence cs35l56_hibernate_seq[] = {
530 /* This must be the last register access */
531 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE),
532};
533
534static void cs35l56_issue_wake_event(struct cs35l56_base *cs35l56_base)
535{
536 unsigned int val;
537
538 /*
539 * Dummy transactions to trigger I2C/SPI auto-wake. Issue two
540 * transactions to meet the minimum required time from the rising edge
541 * to the last falling edge of wake.
542 *
543 * It uses bypassed read because we must wake the chip before
544 * disabling regmap cache-only.
545 */
546 regmap_read_bypassed(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val);
547
548 usleep_range(CS35L56_WAKE_HOLD_TIME_US, 2 * CS35L56_WAKE_HOLD_TIME_US);
549
550 regmap_read_bypassed(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val);
551
552 cs35l56_wait_control_port_ready();
553}
554
555int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base)
556{
557 unsigned int val;
558 int ret;
559
560 if (!cs35l56_base->init_done)
561 return 0;
562
563 /* Firmware must have entered a power-save state */
564 ret = regmap_read_poll_timeout(cs35l56_base->regmap,
565 CS35L56_TRANSDUCER_ACTUAL_PS,
566 val, (val >= CS35L56_PS3),
567 CS35L56_PS3_POLL_US,
568 CS35L56_PS3_TIMEOUT_US);
569 if (ret)
570 dev_warn(cs35l56_base->dev, "PS3 wait failed: %d\n", ret);
571
572 /* Clear BOOT_DONE so it can be used to detect a reboot */
573 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK);
574
575 if (!cs35l56_base->can_hibernate) {
576 regcache_cache_only(cs35l56_base->regmap, true);
577 dev_dbg(cs35l56_base->dev, "Suspended: no hibernate");
578
579 return 0;
580 }
581
582 /*
583 * Must enter cache-only first so there can't be any more register
584 * accesses other than the controlled hibernate sequence below.
585 */
586 regcache_cache_only(cs35l56_base->regmap, true);
587
588 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
589 cs35l56_hibernate_seq,
590 ARRAY_SIZE(cs35l56_hibernate_seq));
591
592 dev_dbg(cs35l56_base->dev, "Suspended: hibernate");
593
594 return 0;
595}
596EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_common, "SND_SOC_CS35L56_SHARED");
597
598int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire)
599{
600 unsigned int val;
601 int ret;
602
603 if (!cs35l56_base->init_done)
604 return 0;
605
606 if (!cs35l56_base->can_hibernate)
607 goto out_sync;
608
609 /* Must be done before releasing cache-only */
610 if (!is_soundwire)
611 cs35l56_issue_wake_event(cs35l56_base);
612
613out_sync:
614 ret = cs35l56_wait_for_firmware_boot(cs35l56_base);
615 if (ret) {
616 dev_err(cs35l56_base->dev, "Hibernate wake failed: %d\n", ret);
617 goto err;
618 }
619
620 regcache_cache_only(cs35l56_base->regmap, false);
621
622 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE);
623 if (ret)
624 goto err;
625
626 /* BOOT_DONE will be 1 if the amp reset */
627 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, &val);
628 if (val & CS35L56_OTP_BOOT_DONE_MASK) {
629 dev_dbg(cs35l56_base->dev, "Registers reset in suspend\n");
630 regcache_mark_dirty(cs35l56_base->regmap);
631 }
632
633 regcache_sync(cs35l56_base->regmap);
634
635 dev_dbg(cs35l56_base->dev, "Resumed");
636
637 return 0;
638
639err:
640 regcache_cache_only(cs35l56_base->regmap, true);
641
642 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
643 cs35l56_hibernate_seq,
644 ARRAY_SIZE(cs35l56_hibernate_seq));
645
646 return ret;
647}
648EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, "SND_SOC_CS35L56_SHARED");
649
650static const struct cs_dsp_region cs35l56_dsp1_regions[] = {
651 { .type = WMFW_HALO_PM_PACKED, .base = CS35L56_DSP1_PMEM_0 },
652 { .type = WMFW_HALO_XM_PACKED, .base = CS35L56_DSP1_XMEM_PACKED_0 },
653 { .type = WMFW_HALO_YM_PACKED, .base = CS35L56_DSP1_YMEM_PACKED_0 },
654 { .type = WMFW_ADSP2_XM, .base = CS35L56_DSP1_XMEM_UNPACKED24_0 },
655 { .type = WMFW_ADSP2_YM, .base = CS35L56_DSP1_YMEM_UNPACKED24_0 },
656};
657
658void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp)
659{
660 cs_dsp->num = 1;
661 cs_dsp->type = WMFW_HALO;
662 cs_dsp->rev = 0;
663 cs_dsp->dev = cs35l56_base->dev;
664 cs_dsp->regmap = cs35l56_base->regmap;
665 cs_dsp->base = CS35L56_DSP1_CORE_BASE;
666 cs_dsp->base_sysinfo = CS35L56_DSP1_SYS_INFO_ID;
667 cs_dsp->mem = cs35l56_dsp1_regions;
668 cs_dsp->num_mems = ARRAY_SIZE(cs35l56_dsp1_regions);
669 cs_dsp->no_core_startstop = true;
670}
671EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, "SND_SOC_CS35L56_SHARED");
672
673struct cs35l56_pte {
674 u8 x;
675 u8 wafer_id;
676 u8 pte[2];
677 u8 lot[3];
678 u8 y;
679 u8 unused[3];
680 u8 dvs;
681} __packed;
682static_assert((sizeof(struct cs35l56_pte) % sizeof(u32)) == 0);
683
684static int cs35l56_read_silicon_uid(struct cs35l56_base *cs35l56_base, u64 *uid)
685{
686 struct cs35l56_pte pte;
687 u64 unique_id;
688 int ret;
689
690 ret = regmap_raw_read(cs35l56_base->regmap, CS35L56_OTP_MEM_53, &pte, sizeof(pte));
691 if (ret) {
692 dev_err(cs35l56_base->dev, "Failed to read OTP: %d\n", ret);
693 return ret;
694 }
695
696 unique_id = (u32)pte.lot[2] | ((u32)pte.lot[1] << 8) | ((u32)pte.lot[0] << 16);
697 unique_id <<= 32;
698 unique_id |= (u32)pte.x | ((u32)pte.y << 8) | ((u32)pte.wafer_id << 16) |
699 ((u32)pte.dvs << 24);
700
701 dev_dbg(cs35l56_base->dev, "UniqueID = %#llx\n", unique_id);
702
703 *uid = unique_id;
704
705 return 0;
706}
707
708/* Firmware calibration controls */
709const struct cirrus_amp_cal_controls cs35l56_calibration_controls = {
710 .alg_id = 0x9f210,
711 .mem_region = WMFW_ADSP2_YM,
712 .ambient = "CAL_AMBIENT",
713 .calr = "CAL_R",
714 .status = "CAL_STATUS",
715 .checksum = "CAL_CHECKSUM",
716};
717EXPORT_SYMBOL_NS_GPL(cs35l56_calibration_controls, "SND_SOC_CS35L56_SHARED");
718
719int cs35l56_get_calibration(struct cs35l56_base *cs35l56_base)
720{
721 u64 silicon_uid = 0;
722 int ret;
723
724 /* Driver can't apply calibration to a secured part, so skip */
725 if (cs35l56_base->secured)
726 return 0;
727
728 ret = cs35l56_read_silicon_uid(cs35l56_base, &silicon_uid);
729 if (ret < 0)
730 return ret;
731
732 ret = cs_amp_get_efi_calibration_data(cs35l56_base->dev, silicon_uid,
733 cs35l56_base->cal_index,
734 &cs35l56_base->cal_data);
735
736 /* Only return an error status if probe should be aborted */
737 if ((ret == -ENOENT) || (ret == -EOVERFLOW))
738 return 0;
739
740 if (ret < 0)
741 return ret;
742
743 cs35l56_base->cal_data_valid = true;
744
745 return 0;
746}
747EXPORT_SYMBOL_NS_GPL(cs35l56_get_calibration, "SND_SOC_CS35L56_SHARED");
748
749int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base,
750 bool *fw_missing, unsigned int *fw_version)
751{
752 unsigned int prot_status;
753 int ret;
754
755 ret = regmap_read(cs35l56_base->regmap, CS35L56_PROTECTION_STATUS, &prot_status);
756 if (ret) {
757 dev_err(cs35l56_base->dev, "Get PROTECTION_STATUS failed: %d\n", ret);
758 return ret;
759 }
760
761 *fw_missing = !!(prot_status & CS35L56_FIRMWARE_MISSING);
762
763 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP1_FW_VER, fw_version);
764 if (ret) {
765 dev_err(cs35l56_base->dev, "Get FW VER failed: %d\n", ret);
766 return ret;
767 }
768
769 return 0;
770}
771EXPORT_SYMBOL_NS_GPL(cs35l56_read_prot_status, "SND_SOC_CS35L56_SHARED");
772
773int cs35l56_hw_init(struct cs35l56_base *cs35l56_base)
774{
775 int ret;
776 unsigned int devid, revid, otpid, secured, fw_ver;
777 bool fw_missing;
778
779 /*
780 * When the system is not using a reset_gpio ensure the device is
781 * awake, otherwise the device has just been released from reset and
782 * the driver must wait for the control port to become usable.
783 */
784 if (!cs35l56_base->reset_gpio)
785 cs35l56_issue_wake_event(cs35l56_base);
786 else
787 cs35l56_wait_control_port_ready();
788
789 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_REVID, &revid);
790 if (ret < 0) {
791 dev_err(cs35l56_base->dev, "Get Revision ID failed\n");
792 return ret;
793 }
794 cs35l56_base->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK);
795
796 ret = cs35l56_wait_for_firmware_boot(cs35l56_base);
797 if (ret)
798 return ret;
799
800 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_DEVID, &devid);
801 if (ret < 0) {
802 dev_err(cs35l56_base->dev, "Get Device ID failed\n");
803 return ret;
804 }
805 devid &= CS35L56_DEVID_MASK;
806
807 switch (devid) {
808 case 0x35A54:
809 case 0x35A56:
810 case 0x35A57:
811 break;
812 default:
813 dev_err(cs35l56_base->dev, "Unknown device %x\n", devid);
814 return ret;
815 }
816
817 cs35l56_base->type = devid & 0xFF;
818
819 /* Silicon is now identified and booted so exit cache-only */
820 regcache_cache_only(cs35l56_base->regmap, false);
821
822 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP_RESTRICT_STS1, &secured);
823 if (ret) {
824 dev_err(cs35l56_base->dev, "Get Secure status failed\n");
825 return ret;
826 }
827
828 /* When any bus is restricted treat the device as secured */
829 if (secured & CS35L56_RESTRICTED_MASK)
830 cs35l56_base->secured = true;
831
832 ret = regmap_read(cs35l56_base->regmap, CS35L56_OTPID, &otpid);
833 if (ret < 0) {
834 dev_err(cs35l56_base->dev, "Get OTP ID failed\n");
835 return ret;
836 }
837
838 ret = cs35l56_read_prot_status(cs35l56_base, &fw_missing, &fw_ver);
839 if (ret)
840 return ret;
841
842 dev_info(cs35l56_base->dev, "Cirrus Logic CS35L%02X%s Rev %02X OTP%d fw:%d.%d.%d (patched=%u)\n",
843 cs35l56_base->type, cs35l56_base->secured ? "s" : "", cs35l56_base->rev, otpid,
844 fw_ver >> 16, (fw_ver >> 8) & 0xff, fw_ver & 0xff, !fw_missing);
845
846 /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */
847 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff);
848 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1,
849 CS35L56_AMP_SHORT_ERR_EINT1_MASK,
850 0);
851 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8,
852 CS35L56_TEMP_ERR_EINT1_MASK,
853 0);
854
855 return 0;
856}
857EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, "SND_SOC_CS35L56_SHARED");
858
859int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base)
860{
861 struct gpio_descs *descs;
862 u32 speaker_id;
863 int i, ret;
864
865 /* Attempt to read the speaker type from a device property first */
866 ret = device_property_read_u32(cs35l56_base->dev, "cirrus,speaker-id", &speaker_id);
867 if (!ret) {
868 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id);
869 return speaker_id;
870 }
871
872 /* Read the speaker type qualifier from the motherboard GPIOs */
873 descs = gpiod_get_array_optional(cs35l56_base->dev, "spk-id", GPIOD_IN);
874 if (!descs) {
875 return -ENOENT;
876 } else if (IS_ERR(descs)) {
877 ret = PTR_ERR(descs);
878 return dev_err_probe(cs35l56_base->dev, ret, "Failed to get spk-id-gpios\n");
879 }
880
881 speaker_id = 0;
882 for (i = 0; i < descs->ndescs; i++) {
883 ret = gpiod_get_value_cansleep(descs->desc[i]);
884 if (ret < 0) {
885 dev_err_probe(cs35l56_base->dev, ret, "Failed to read spk-id[%d]\n", i);
886 goto err;
887 }
888
889 speaker_id |= (ret << i);
890 }
891
892 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id);
893 ret = speaker_id;
894err:
895 gpiod_put_array(descs);
896
897 return ret;
898}
899EXPORT_SYMBOL_NS_GPL(cs35l56_get_speaker_id, "SND_SOC_CS35L56_SHARED");
900
901static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = {
902 [0x0C] = 128000,
903 [0x0F] = 256000,
904 [0x11] = 384000,
905 [0x12] = 512000,
906 [0x15] = 768000,
907 [0x17] = 1024000,
908 [0x1A] = 1500000,
909 [0x1B] = 1536000,
910 [0x1C] = 2000000,
911 [0x1D] = 2048000,
912 [0x1E] = 2400000,
913 [0x20] = 3000000,
914 [0x21] = 3072000,
915 [0x23] = 4000000,
916 [0x24] = 4096000,
917 [0x25] = 4800000,
918 [0x27] = 6000000,
919 [0x28] = 6144000,
920 [0x29] = 6250000,
921 [0x2A] = 6400000,
922 [0x2E] = 8000000,
923 [0x2F] = 8192000,
924 [0x30] = 9600000,
925 [0x32] = 12000000,
926 [0x33] = 12288000,
927 [0x37] = 13500000,
928 [0x38] = 19200000,
929 [0x39] = 22579200,
930 [0x3B] = 24576000,
931};
932
933int cs35l56_get_bclk_freq_id(unsigned int freq)
934{
935 int i;
936
937 if (freq == 0)
938 return -EINVAL;
939
940 /* The BCLK frequency must be a valid PLL REFCLK */
941 for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) {
942 if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq)
943 return i;
944 }
945
946 return -EINVAL;
947}
948EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, "SND_SOC_CS35L56_SHARED");
949
950static const char * const cs35l56_supplies[/* auto-sized */] = {
951 "VDD_P",
952 "VDD_IO",
953 "VDD_A",
954};
955
956void cs35l56_fill_supply_names(struct regulator_bulk_data *data)
957{
958 int i;
959
960 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES);
961 for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++)
962 data[i].supply = cs35l56_supplies[i];
963}
964EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, "SND_SOC_CS35L56_SHARED");
965
966const char * const cs35l56_tx_input_texts[] = {
967 "None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH",
968 "VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4",
969 "DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON",
970 "INTERPOLATOR", "SDW1RX1", "SDW1RX2",
971};
972EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, "SND_SOC_CS35L56_SHARED");
973
974const unsigned int cs35l56_tx_input_values[] = {
975 CS35L56_INPUT_SRC_NONE,
976 CS35L56_INPUT_SRC_ASP1RX1,
977 CS35L56_INPUT_SRC_ASP1RX2,
978 CS35L56_INPUT_SRC_VMON,
979 CS35L56_INPUT_SRC_IMON,
980 CS35L56_INPUT_SRC_ERR_VOL,
981 CS35L56_INPUT_SRC_CLASSH,
982 CS35L56_INPUT_SRC_VDDBMON,
983 CS35L56_INPUT_SRC_VBSTMON,
984 CS35L56_INPUT_SRC_DSP1TX1,
985 CS35L56_INPUT_SRC_DSP1TX2,
986 CS35L56_INPUT_SRC_DSP1TX3,
987 CS35L56_INPUT_SRC_DSP1TX4,
988 CS35L56_INPUT_SRC_DSP1TX5,
989 CS35L56_INPUT_SRC_DSP1TX6,
990 CS35L56_INPUT_SRC_DSP1TX7,
991 CS35L56_INPUT_SRC_DSP1TX8,
992 CS35L56_INPUT_SRC_TEMPMON,
993 CS35L56_INPUT_SRC_INTERPOLATOR,
994 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1,
995 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2,
996};
997EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, "SND_SOC_CS35L56_SHARED");
998
999const struct regmap_config cs35l56_regmap_i2c = {
1000 .reg_bits = 32,
1001 .val_bits = 32,
1002 .reg_stride = 4,
1003 .reg_format_endian = REGMAP_ENDIAN_BIG,
1004 .val_format_endian = REGMAP_ENDIAN_BIG,
1005 .max_register = CS35L56_DSP1_PMEM_5114,
1006 .reg_defaults = cs35l56_reg_defaults,
1007 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
1008 .volatile_reg = cs35l56_volatile_reg,
1009 .readable_reg = cs35l56_readable_reg,
1010 .precious_reg = cs35l56_precious_reg,
1011 .cache_type = REGCACHE_MAPLE,
1012};
1013EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, "SND_SOC_CS35L56_SHARED");
1014
1015const struct regmap_config cs35l56_regmap_spi = {
1016 .reg_bits = 32,
1017 .val_bits = 32,
1018 .pad_bits = 16,
1019 .reg_stride = 4,
1020 .reg_format_endian = REGMAP_ENDIAN_BIG,
1021 .val_format_endian = REGMAP_ENDIAN_BIG,
1022 .max_register = CS35L56_DSP1_PMEM_5114,
1023 .reg_defaults = cs35l56_reg_defaults,
1024 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
1025 .volatile_reg = cs35l56_volatile_reg,
1026 .readable_reg = cs35l56_readable_reg,
1027 .precious_reg = cs35l56_precious_reg,
1028 .cache_type = REGCACHE_MAPLE,
1029};
1030EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, "SND_SOC_CS35L56_SHARED");
1031
1032const struct regmap_config cs35l56_regmap_sdw = {
1033 .reg_bits = 32,
1034 .val_bits = 32,
1035 .reg_stride = 4,
1036 .reg_format_endian = REGMAP_ENDIAN_LITTLE,
1037 .val_format_endian = REGMAP_ENDIAN_BIG,
1038 .max_register = CS35L56_DSP1_PMEM_5114,
1039 .reg_defaults = cs35l56_reg_defaults,
1040 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
1041 .volatile_reg = cs35l56_volatile_reg,
1042 .readable_reg = cs35l56_readable_reg,
1043 .precious_reg = cs35l56_precious_reg,
1044 .cache_type = REGCACHE_MAPLE,
1045};
1046EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, "SND_SOC_CS35L56_SHARED");
1047
1048MODULE_DESCRIPTION("ASoC CS35L56 Shared");
1049MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
1050MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>");
1051MODULE_LICENSE("GPL");
1052MODULE_IMPORT_NS("SND_SOC_CS_AMP_LIB");
1// SPDX-License-Identifier: GPL-2.0-only
2//
3// Components shared between ASoC and HDA CS35L56 drivers
4//
5// Copyright (C) 2023 Cirrus Logic, Inc. and
6// Cirrus Logic International Semiconductor Ltd.
7
8#include <linux/gpio/consumer.h>
9#include <linux/regmap.h>
10#include <linux/regulator/consumer.h>
11#include <linux/types.h>
12
13#include "cs35l56.h"
14
15static const struct reg_sequence cs35l56_patch[] = {
16 /*
17 * Firmware can change these to non-defaults to satisfy SDCA.
18 * Ensure that they are at known defaults.
19 */
20 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 },
21 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 },
22 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 },
23 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 },
24
25 /* These are not reset by a soft-reset, so patch to defaults. */
26 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 },
27 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 },
28 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 },
29};
30
31int cs35l56_set_patch(struct cs35l56_base *cs35l56_base)
32{
33 return regmap_register_patch(cs35l56_base->regmap, cs35l56_patch,
34 ARRAY_SIZE(cs35l56_patch));
35}
36EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, SND_SOC_CS35L56_SHARED);
37
38static const struct reg_default cs35l56_reg_defaults[] = {
39 { CS35L56_ASP1_ENABLES1, 0x00000000 },
40 { CS35L56_ASP1_CONTROL1, 0x00000028 },
41 { CS35L56_ASP1_CONTROL2, 0x18180200 },
42 { CS35L56_ASP1_CONTROL3, 0x00000002 },
43 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 },
44 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 },
45 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 },
46 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 },
47
48 /* no defaults for ASP1TX mixer */
49
50 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 },
51 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 },
52 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 },
53 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 },
54 { CS35L56_IRQ1_MASK_1, 0x83ffffff },
55 { CS35L56_IRQ1_MASK_2, 0xffff7fff },
56 { CS35L56_IRQ1_MASK_4, 0xe0ffffff },
57 { CS35L56_IRQ1_MASK_8, 0xfc000fff },
58 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff },
59 { CS35L56_IRQ1_MASK_20, 0x15c00000 },
60 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 },
61 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 },
62 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 },
63};
64
65static bool cs35l56_is_dsp_memory(unsigned int reg)
66{
67 switch (reg) {
68 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143:
69 case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095:
70 case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191:
71 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604:
72 case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070:
73 case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141:
74 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114:
75 return true;
76 default:
77 return false;
78 }
79}
80
81static bool cs35l56_readable_reg(struct device *dev, unsigned int reg)
82{
83 switch (reg) {
84 case CS35L56_DEVID:
85 case CS35L56_REVID:
86 case CS35L56_RELID:
87 case CS35L56_OTPID:
88 case CS35L56_SFT_RESET:
89 case CS35L56_GLOBAL_ENABLES:
90 case CS35L56_BLOCK_ENABLES:
91 case CS35L56_BLOCK_ENABLES2:
92 case CS35L56_REFCLK_INPUT:
93 case CS35L56_GLOBAL_SAMPLE_RATE:
94 case CS35L56_ASP1_ENABLES1:
95 case CS35L56_ASP1_CONTROL1:
96 case CS35L56_ASP1_CONTROL2:
97 case CS35L56_ASP1_CONTROL3:
98 case CS35L56_ASP1_FRAME_CONTROL1:
99 case CS35L56_ASP1_FRAME_CONTROL5:
100 case CS35L56_ASP1_DATA_CONTROL1:
101 case CS35L56_ASP1_DATA_CONTROL5:
102 case CS35L56_DACPCM1_INPUT:
103 case CS35L56_DACPCM2_INPUT:
104 case CS35L56_ASP1TX1_INPUT:
105 case CS35L56_ASP1TX2_INPUT:
106 case CS35L56_ASP1TX3_INPUT:
107 case CS35L56_ASP1TX4_INPUT:
108 case CS35L56_DSP1RX1_INPUT:
109 case CS35L56_DSP1RX2_INPUT:
110 case CS35L56_SWIRE_DP3_CH1_INPUT:
111 case CS35L56_SWIRE_DP3_CH2_INPUT:
112 case CS35L56_SWIRE_DP3_CH3_INPUT:
113 case CS35L56_SWIRE_DP3_CH4_INPUT:
114 case CS35L56_IRQ1_CFG:
115 case CS35L56_IRQ1_STATUS:
116 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8:
117 case CS35L56_IRQ1_EINT_18:
118 case CS35L56_IRQ1_EINT_20:
119 case CS35L56_IRQ1_MASK_1:
120 case CS35L56_IRQ1_MASK_2:
121 case CS35L56_IRQ1_MASK_4:
122 case CS35L56_IRQ1_MASK_8:
123 case CS35L56_IRQ1_MASK_18:
124 case CS35L56_IRQ1_MASK_20:
125 case CS35L56_DSP_VIRTUAL1_MBOX_1:
126 case CS35L56_DSP_VIRTUAL1_MBOX_2:
127 case CS35L56_DSP_VIRTUAL1_MBOX_3:
128 case CS35L56_DSP_VIRTUAL1_MBOX_4:
129 case CS35L56_DSP_VIRTUAL1_MBOX_5:
130 case CS35L56_DSP_VIRTUAL1_MBOX_6:
131 case CS35L56_DSP_VIRTUAL1_MBOX_7:
132 case CS35L56_DSP_VIRTUAL1_MBOX_8:
133 case CS35L56_DSP_RESTRICT_STS1:
134 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END:
135 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0:
136 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1:
137 case CS35L56_DSP1_SCRATCH1:
138 case CS35L56_DSP1_SCRATCH2:
139 case CS35L56_DSP1_SCRATCH3:
140 case CS35L56_DSP1_SCRATCH4:
141 return true;
142 default:
143 return cs35l56_is_dsp_memory(reg);
144 }
145}
146
147static bool cs35l56_precious_reg(struct device *dev, unsigned int reg)
148{
149 switch (reg) {
150 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143:
151 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604:
152 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114:
153 return true;
154 default:
155 return false;
156 }
157}
158
159static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg)
160{
161 switch (reg) {
162 case CS35L56_DEVID:
163 case CS35L56_REVID:
164 case CS35L56_RELID:
165 case CS35L56_OTPID:
166 case CS35L56_SFT_RESET:
167 case CS35L56_GLOBAL_ENABLES: /* owned by firmware */
168 case CS35L56_BLOCK_ENABLES: /* owned by firmware */
169 case CS35L56_BLOCK_ENABLES2: /* owned by firmware */
170 case CS35L56_REFCLK_INPUT: /* owned by firmware */
171 case CS35L56_GLOBAL_SAMPLE_RATE: /* owned by firmware */
172 case CS35L56_DACPCM1_INPUT: /* owned by firmware */
173 case CS35L56_DACPCM2_INPUT: /* owned by firmware */
174 case CS35L56_DSP1RX1_INPUT: /* owned by firmware */
175 case CS35L56_DSP1RX2_INPUT: /* owned by firmware */
176 case CS35L56_IRQ1_STATUS:
177 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8:
178 case CS35L56_IRQ1_EINT_18:
179 case CS35L56_IRQ1_EINT_20:
180 case CS35L56_DSP_VIRTUAL1_MBOX_1:
181 case CS35L56_DSP_VIRTUAL1_MBOX_2:
182 case CS35L56_DSP_VIRTUAL1_MBOX_3:
183 case CS35L56_DSP_VIRTUAL1_MBOX_4:
184 case CS35L56_DSP_VIRTUAL1_MBOX_5:
185 case CS35L56_DSP_VIRTUAL1_MBOX_6:
186 case CS35L56_DSP_VIRTUAL1_MBOX_7:
187 case CS35L56_DSP_VIRTUAL1_MBOX_8:
188 case CS35L56_DSP_RESTRICT_STS1:
189 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END:
190 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0:
191 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1:
192 case CS35L56_DSP1_SCRATCH1:
193 case CS35L56_DSP1_SCRATCH2:
194 case CS35L56_DSP1_SCRATCH3:
195 case CS35L56_DSP1_SCRATCH4:
196 return true;
197 case CS35L56_MAIN_RENDER_USER_MUTE:
198 case CS35L56_MAIN_RENDER_USER_VOLUME:
199 case CS35L56_MAIN_POSTURE_NUMBER:
200 return false;
201 default:
202 return cs35l56_is_dsp_memory(reg);
203 }
204}
205
206/*
207 * The firmware boot sequence can overwrite the ASP1 config registers so that
208 * they don't match regmap's view of their values. Rewrite the values from the
209 * regmap cache into the hardware registers.
210 */
211int cs35l56_force_sync_asp1_registers_from_cache(struct cs35l56_base *cs35l56_base)
212{
213 struct reg_sequence asp1_regs[] = {
214 { .reg = CS35L56_ASP1_ENABLES1 },
215 { .reg = CS35L56_ASP1_CONTROL1 },
216 { .reg = CS35L56_ASP1_CONTROL2 },
217 { .reg = CS35L56_ASP1_CONTROL3 },
218 { .reg = CS35L56_ASP1_FRAME_CONTROL1 },
219 { .reg = CS35L56_ASP1_FRAME_CONTROL5 },
220 { .reg = CS35L56_ASP1_DATA_CONTROL1 },
221 { .reg = CS35L56_ASP1_DATA_CONTROL5 },
222 };
223 int i, ret;
224
225 /* Read values from regmap cache into a write sequence */
226 for (i = 0; i < ARRAY_SIZE(asp1_regs); ++i) {
227 ret = regmap_read(cs35l56_base->regmap, asp1_regs[i].reg, &asp1_regs[i].def);
228 if (ret)
229 goto err;
230 }
231
232 /* Write the values cache-bypassed so that they will be written to silicon */
233 ret = regmap_multi_reg_write_bypassed(cs35l56_base->regmap, asp1_regs,
234 ARRAY_SIZE(asp1_regs));
235 if (ret)
236 goto err;
237
238 return 0;
239
240err:
241 dev_err(cs35l56_base->dev, "Failed to sync ASP1 registers: %d\n", ret);
242
243 return ret;
244}
245EXPORT_SYMBOL_NS_GPL(cs35l56_force_sync_asp1_registers_from_cache, SND_SOC_CS35L56_SHARED);
246
247int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command)
248{
249 unsigned int val;
250 int ret;
251
252 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command);
253 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1,
254 val, (val == 0),
255 CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US);
256 if (ret) {
257 dev_warn(cs35l56_base->dev, "MBOX command %#x failed: %d\n", command, ret);
258 return ret;
259 }
260
261 return 0;
262}
263EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, SND_SOC_CS35L56_SHARED);
264
265int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base)
266{
267 int ret;
268 unsigned int reg;
269 unsigned int val;
270
271 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN);
272 if (ret)
273 return ret;
274
275 if (cs35l56_base->rev < CS35L56_REVID_B0)
276 reg = CS35L56_DSP1_PM_CUR_STATE_A1;
277 else
278 reg = CS35L56_DSP1_PM_CUR_STATE;
279
280 ret = regmap_read_poll_timeout(cs35l56_base->regmap, reg,
281 val, (val == CS35L56_HALO_STATE_SHUTDOWN),
282 CS35L56_HALO_STATE_POLL_US,
283 CS35L56_HALO_STATE_TIMEOUT_US);
284 if (ret < 0)
285 dev_err(cs35l56_base->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n",
286 val, ret);
287 return ret;
288}
289EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, SND_SOC_CS35L56_SHARED);
290
291int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base)
292{
293 unsigned int reg;
294 unsigned int val = 0;
295 int read_ret, poll_ret;
296
297 if (cs35l56_base->rev < CS35L56_REVID_B0)
298 reg = CS35L56_DSP1_HALO_STATE_A1;
299 else
300 reg = CS35L56_DSP1_HALO_STATE;
301
302 /*
303 * This can't be a regmap_read_poll_timeout() because cs35l56 will NAK
304 * I2C until it has booted which would terminate the poll
305 */
306 poll_ret = read_poll_timeout(regmap_read, read_ret,
307 (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE),
308 CS35L56_HALO_STATE_POLL_US,
309 CS35L56_HALO_STATE_TIMEOUT_US,
310 false,
311 cs35l56_base->regmap, reg, &val);
312
313 if (poll_ret) {
314 dev_err(cs35l56_base->dev, "Firmware boot timed out(%d): HALO_STATE=%#x\n",
315 read_ret, val);
316 return -EIO;
317 }
318
319 return 0;
320}
321EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, SND_SOC_CS35L56_SHARED);
322
323void cs35l56_wait_control_port_ready(void)
324{
325 /* Wait for control port to be ready (datasheet tIRS). */
326 usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US);
327}
328EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, SND_SOC_CS35L56_SHARED);
329
330void cs35l56_wait_min_reset_pulse(void)
331{
332 /* Satisfy minimum reset pulse width spec */
333 usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US);
334}
335EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pulse, SND_SOC_CS35L56_SHARED);
336
337static const struct reg_sequence cs35l56_system_reset_seq[] = {
338 REG_SEQ0(CS35L56_DSP1_HALO_STATE, 0),
339 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET),
340};
341
342void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire)
343{
344 /*
345 * Must enter cache-only first so there can't be any more register
346 * accesses other than the controlled system reset sequence below.
347 */
348 regcache_cache_only(cs35l56_base->regmap, true);
349 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
350 cs35l56_system_reset_seq,
351 ARRAY_SIZE(cs35l56_system_reset_seq));
352
353 /* On SoundWire the registers won't be accessible until it re-enumerates. */
354 if (is_soundwire)
355 return;
356
357 cs35l56_wait_control_port_ready();
358 regcache_cache_only(cs35l56_base->regmap, false);
359}
360EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, SND_SOC_CS35L56_SHARED);
361
362int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq)
363{
364 int ret;
365
366 if (!irq)
367 return 0;
368
369 ret = devm_request_threaded_irq(cs35l56_base->dev, irq, NULL, cs35l56_irq,
370 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW,
371 "cs35l56", cs35l56_base);
372 if (!ret)
373 cs35l56_base->irq = irq;
374 else
375 dev_err(cs35l56_base->dev, "Failed to get IRQ: %d\n", ret);
376
377 return ret;
378}
379EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, SND_SOC_CS35L56_SHARED);
380
381irqreturn_t cs35l56_irq(int irq, void *data)
382{
383 struct cs35l56_base *cs35l56_base = data;
384 unsigned int status1 = 0, status8 = 0, status20 = 0;
385 unsigned int mask1, mask8, mask20;
386 unsigned int val;
387 int rv;
388
389 irqreturn_t ret = IRQ_NONE;
390
391 if (!cs35l56_base->init_done)
392 return IRQ_NONE;
393
394 mutex_lock(&cs35l56_base->irq_lock);
395
396 rv = pm_runtime_resume_and_get(cs35l56_base->dev);
397 if (rv < 0) {
398 dev_err(cs35l56_base->dev, "irq: failed to get pm_runtime: %d\n", rv);
399 goto err_unlock;
400 }
401
402 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val);
403 if ((val & CS35L56_IRQ1_STS_MASK) == 0) {
404 dev_dbg(cs35l56_base->dev, "Spurious IRQ: no pending interrupt\n");
405 goto err;
406 }
407
408 /* Ack interrupts */
409 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, &status1);
410 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, &mask1);
411 status1 &= ~mask1;
412 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, status1);
413
414 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, &status8);
415 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, &mask8);
416 status8 &= ~mask8;
417 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, status8);
418
419 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_20, &status20);
420 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, &mask20);
421 status20 &= ~mask20;
422 /* We don't want EINT20 but they default to unmasked: force mask */
423 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff);
424
425 dev_dbg(cs35l56_base->dev, "%s: %#x %#x\n", __func__, status1, status8);
426
427 /* Check to see if unmasked bits are active */
428 if (!status1 && !status8 && !status20)
429 goto err;
430
431 if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK)
432 dev_crit(cs35l56_base->dev, "Amp short error\n");
433
434 if (status8 & CS35L56_TEMP_ERR_EINT1_MASK)
435 dev_crit(cs35l56_base->dev, "Overtemp error\n");
436
437 ret = IRQ_HANDLED;
438
439err:
440 pm_runtime_put(cs35l56_base->dev);
441err_unlock:
442 mutex_unlock(&cs35l56_base->irq_lock);
443
444 return ret;
445}
446EXPORT_SYMBOL_NS_GPL(cs35l56_irq, SND_SOC_CS35L56_SHARED);
447
448int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base)
449{
450 unsigned int val;
451 int ret;
452
453 /*
454 * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so
455 * can't be used here to test for memory retention.
456 * Assume that tuning must be re-loaded.
457 */
458 if (cs35l56_base->secured)
459 return true;
460
461 ret = pm_runtime_resume_and_get(cs35l56_base->dev);
462 if (ret) {
463 dev_err(cs35l56_base->dev, "Failed to runtime_get: %d\n", ret);
464 return ret;
465 }
466
467 ret = regmap_read(cs35l56_base->regmap, CS35L56_PROTECTION_STATUS, &val);
468 if (ret)
469 dev_err(cs35l56_base->dev, "Failed to read PROTECTION_STATUS: %d\n", ret);
470 else
471 ret = !!(val & CS35L56_FIRMWARE_MISSING);
472
473 pm_runtime_put_autosuspend(cs35l56_base->dev);
474
475 return ret;
476}
477EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, SND_SOC_CS35L56_SHARED);
478
479static const struct reg_sequence cs35l56_hibernate_seq[] = {
480 /* This must be the last register access */
481 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE),
482};
483
484static const struct reg_sequence cs35l56_hibernate_wake_seq[] = {
485 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_WAKEUP),
486};
487
488static void cs35l56_issue_wake_event(struct cs35l56_base *cs35l56_base)
489{
490 /*
491 * Dummy transactions to trigger I2C/SPI auto-wake. Issue two
492 * transactions to meet the minimum required time from the rising edge
493 * to the last falling edge of wake.
494 *
495 * It uses bypassed write because we must wake the chip before
496 * disabling regmap cache-only.
497 *
498 * This can NAK on I2C which will terminate the write sequence so the
499 * single-write sequence is issued twice.
500 */
501 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
502 cs35l56_hibernate_wake_seq,
503 ARRAY_SIZE(cs35l56_hibernate_wake_seq));
504
505 usleep_range(CS35L56_WAKE_HOLD_TIME_US, 2 * CS35L56_WAKE_HOLD_TIME_US);
506
507 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
508 cs35l56_hibernate_wake_seq,
509 ARRAY_SIZE(cs35l56_hibernate_wake_seq));
510
511 cs35l56_wait_control_port_ready();
512}
513
514int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base)
515{
516 unsigned int val;
517 int ret;
518
519 if (!cs35l56_base->init_done)
520 return 0;
521
522 /* Firmware must have entered a power-save state */
523 ret = regmap_read_poll_timeout(cs35l56_base->regmap,
524 CS35L56_TRANSDUCER_ACTUAL_PS,
525 val, (val >= CS35L56_PS3),
526 CS35L56_PS3_POLL_US,
527 CS35L56_PS3_TIMEOUT_US);
528 if (ret)
529 dev_warn(cs35l56_base->dev, "PS3 wait failed: %d\n", ret);
530
531 /* Clear BOOT_DONE so it can be used to detect a reboot */
532 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK);
533
534 if (!cs35l56_base->can_hibernate) {
535 regcache_cache_only(cs35l56_base->regmap, true);
536 dev_dbg(cs35l56_base->dev, "Suspended: no hibernate");
537
538 return 0;
539 }
540
541 /*
542 * Must enter cache-only first so there can't be any more register
543 * accesses other than the controlled hibernate sequence below.
544 */
545 regcache_cache_only(cs35l56_base->regmap, true);
546
547 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
548 cs35l56_hibernate_seq,
549 ARRAY_SIZE(cs35l56_hibernate_seq));
550
551 dev_dbg(cs35l56_base->dev, "Suspended: hibernate");
552
553 return 0;
554}
555EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_common, SND_SOC_CS35L56_SHARED);
556
557int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire)
558{
559 unsigned int val;
560 int ret;
561
562 if (!cs35l56_base->init_done)
563 return 0;
564
565 if (!cs35l56_base->can_hibernate)
566 goto out_sync;
567
568 /* Must be done before releasing cache-only */
569 if (!is_soundwire)
570 cs35l56_issue_wake_event(cs35l56_base);
571
572out_sync:
573 regcache_cache_only(cs35l56_base->regmap, false);
574
575 ret = cs35l56_wait_for_firmware_boot(cs35l56_base);
576 if (ret) {
577 dev_err(cs35l56_base->dev, "Hibernate wake failed: %d\n", ret);
578 goto err;
579 }
580
581 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE);
582 if (ret)
583 goto err;
584
585 /* BOOT_DONE will be 1 if the amp reset */
586 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, &val);
587 if (val & CS35L56_OTP_BOOT_DONE_MASK) {
588 dev_dbg(cs35l56_base->dev, "Registers reset in suspend\n");
589 regcache_mark_dirty(cs35l56_base->regmap);
590 }
591
592 regcache_sync(cs35l56_base->regmap);
593
594 dev_dbg(cs35l56_base->dev, "Resumed");
595
596 return 0;
597
598err:
599 regcache_cache_only(cs35l56_base->regmap, true);
600
601 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
602 cs35l56_hibernate_seq,
603 ARRAY_SIZE(cs35l56_hibernate_seq));
604
605 return ret;
606}
607EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, SND_SOC_CS35L56_SHARED);
608
609static const struct cs_dsp_region cs35l56_dsp1_regions[] = {
610 { .type = WMFW_HALO_PM_PACKED, .base = CS35L56_DSP1_PMEM_0 },
611 { .type = WMFW_HALO_XM_PACKED, .base = CS35L56_DSP1_XMEM_PACKED_0 },
612 { .type = WMFW_HALO_YM_PACKED, .base = CS35L56_DSP1_YMEM_PACKED_0 },
613 { .type = WMFW_ADSP2_XM, .base = CS35L56_DSP1_XMEM_UNPACKED24_0 },
614 { .type = WMFW_ADSP2_YM, .base = CS35L56_DSP1_YMEM_UNPACKED24_0 },
615};
616
617void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp)
618{
619 cs_dsp->num = 1;
620 cs_dsp->type = WMFW_HALO;
621 cs_dsp->rev = 0;
622 cs_dsp->dev = cs35l56_base->dev;
623 cs_dsp->regmap = cs35l56_base->regmap;
624 cs_dsp->base = CS35L56_DSP1_CORE_BASE;
625 cs_dsp->base_sysinfo = CS35L56_DSP1_SYS_INFO_ID;
626 cs_dsp->mem = cs35l56_dsp1_regions;
627 cs_dsp->num_mems = ARRAY_SIZE(cs35l56_dsp1_regions);
628 cs_dsp->no_core_startstop = true;
629}
630EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, SND_SOC_CS35L56_SHARED);
631
632int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base,
633 bool *fw_missing, unsigned int *fw_version)
634{
635 unsigned int prot_status;
636 int ret;
637
638 ret = regmap_read(cs35l56_base->regmap, CS35L56_PROTECTION_STATUS, &prot_status);
639 if (ret) {
640 dev_err(cs35l56_base->dev, "Get PROTECTION_STATUS failed: %d\n", ret);
641 return ret;
642 }
643
644 *fw_missing = !!(prot_status & CS35L56_FIRMWARE_MISSING);
645
646 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP1_FW_VER, fw_version);
647 if (ret) {
648 dev_err(cs35l56_base->dev, "Get FW VER failed: %d\n", ret);
649 return ret;
650 }
651
652 return 0;
653}
654EXPORT_SYMBOL_NS_GPL(cs35l56_read_prot_status, SND_SOC_CS35L56_SHARED);
655
656int cs35l56_hw_init(struct cs35l56_base *cs35l56_base)
657{
658 int ret;
659 unsigned int devid, revid, otpid, secured, fw_ver;
660 bool fw_missing;
661
662 /*
663 * When the system is not using a reset_gpio ensure the device is
664 * awake, otherwise the device has just been released from reset and
665 * the driver must wait for the control port to become usable.
666 */
667 if (!cs35l56_base->reset_gpio)
668 cs35l56_issue_wake_event(cs35l56_base);
669 else
670 cs35l56_wait_control_port_ready();
671
672 /*
673 * The HALO_STATE register is in different locations on Ax and B0
674 * devices so the REVID needs to be determined before waiting for the
675 * firmware to boot.
676 */
677 ret = regmap_read(cs35l56_base->regmap, CS35L56_REVID, &revid);
678 if (ret < 0) {
679 dev_err(cs35l56_base->dev, "Get Revision ID failed\n");
680 return ret;
681 }
682 cs35l56_base->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK);
683
684 ret = cs35l56_wait_for_firmware_boot(cs35l56_base);
685 if (ret)
686 return ret;
687
688 ret = regmap_read(cs35l56_base->regmap, CS35L56_DEVID, &devid);
689 if (ret < 0) {
690 dev_err(cs35l56_base->dev, "Get Device ID failed\n");
691 return ret;
692 }
693 devid &= CS35L56_DEVID_MASK;
694
695 switch (devid) {
696 case 0x35A56:
697 break;
698 default:
699 dev_err(cs35l56_base->dev, "Unknown device %x\n", devid);
700 return ret;
701 }
702
703 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP_RESTRICT_STS1, &secured);
704 if (ret) {
705 dev_err(cs35l56_base->dev, "Get Secure status failed\n");
706 return ret;
707 }
708
709 /* When any bus is restricted treat the device as secured */
710 if (secured & CS35L56_RESTRICTED_MASK)
711 cs35l56_base->secured = true;
712
713 ret = regmap_read(cs35l56_base->regmap, CS35L56_OTPID, &otpid);
714 if (ret < 0) {
715 dev_err(cs35l56_base->dev, "Get OTP ID failed\n");
716 return ret;
717 }
718
719 ret = cs35l56_read_prot_status(cs35l56_base, &fw_missing, &fw_ver);
720 if (ret)
721 return ret;
722
723 dev_info(cs35l56_base->dev, "Cirrus Logic CS35L56%s Rev %02X OTP%d fw:%d.%d.%d (patched=%u)\n",
724 cs35l56_base->secured ? "s" : "", cs35l56_base->rev, otpid,
725 fw_ver >> 16, (fw_ver >> 8) & 0xff, fw_ver & 0xff, !fw_missing);
726
727 /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */
728 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff);
729 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1,
730 CS35L56_AMP_SHORT_ERR_EINT1_MASK,
731 0);
732 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8,
733 CS35L56_TEMP_ERR_EINT1_MASK,
734 0);
735
736 return 0;
737}
738EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, SND_SOC_CS35L56_SHARED);
739
740int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base)
741{
742 struct gpio_descs *descs;
743 int speaker_id;
744 int i, ret;
745
746 /* Read the speaker type qualifier from the motherboard GPIOs */
747 descs = gpiod_get_array_optional(cs35l56_base->dev, "spk-id", GPIOD_IN);
748 if (!descs) {
749 return -ENOENT;
750 } else if (IS_ERR(descs)) {
751 ret = PTR_ERR(descs);
752 return dev_err_probe(cs35l56_base->dev, ret, "Failed to get spk-id-gpios\n");
753 }
754
755 speaker_id = 0;
756 for (i = 0; i < descs->ndescs; i++) {
757 ret = gpiod_get_value_cansleep(descs->desc[i]);
758 if (ret < 0) {
759 dev_err_probe(cs35l56_base->dev, ret, "Failed to read spk-id[%d]\n", i);
760 goto err;
761 }
762
763 speaker_id |= (ret << i);
764 }
765
766 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id);
767 ret = speaker_id;
768err:
769 gpiod_put_array(descs);
770
771 return ret;
772}
773EXPORT_SYMBOL_NS_GPL(cs35l56_get_speaker_id, SND_SOC_CS35L56_SHARED);
774
775static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = {
776 [0x0C] = 128000,
777 [0x0F] = 256000,
778 [0x11] = 384000,
779 [0x12] = 512000,
780 [0x15] = 768000,
781 [0x17] = 1024000,
782 [0x1A] = 1500000,
783 [0x1B] = 1536000,
784 [0x1C] = 2000000,
785 [0x1D] = 2048000,
786 [0x1E] = 2400000,
787 [0x20] = 3000000,
788 [0x21] = 3072000,
789 [0x23] = 4000000,
790 [0x24] = 4096000,
791 [0x25] = 4800000,
792 [0x27] = 6000000,
793 [0x28] = 6144000,
794 [0x29] = 6250000,
795 [0x2A] = 6400000,
796 [0x2E] = 8000000,
797 [0x2F] = 8192000,
798 [0x30] = 9600000,
799 [0x32] = 12000000,
800 [0x33] = 12288000,
801 [0x37] = 13500000,
802 [0x38] = 19200000,
803 [0x39] = 22579200,
804 [0x3B] = 24576000,
805};
806
807int cs35l56_get_bclk_freq_id(unsigned int freq)
808{
809 int i;
810
811 if (freq == 0)
812 return -EINVAL;
813
814 /* The BCLK frequency must be a valid PLL REFCLK */
815 for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) {
816 if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq)
817 return i;
818 }
819
820 return -EINVAL;
821}
822EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, SND_SOC_CS35L56_SHARED);
823
824static const char * const cs35l56_supplies[/* auto-sized */] = {
825 "VDD_P",
826 "VDD_IO",
827 "VDD_A",
828};
829
830void cs35l56_fill_supply_names(struct regulator_bulk_data *data)
831{
832 int i;
833
834 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES);
835 for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++)
836 data[i].supply = cs35l56_supplies[i];
837}
838EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, SND_SOC_CS35L56_SHARED);
839
840const char * const cs35l56_tx_input_texts[] = {
841 "None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH",
842 "VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4",
843 "DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON",
844 "INTERPOLATOR", "SDW1RX1", "SDW1RX2",
845};
846EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, SND_SOC_CS35L56_SHARED);
847
848const unsigned int cs35l56_tx_input_values[] = {
849 CS35L56_INPUT_SRC_NONE,
850 CS35L56_INPUT_SRC_ASP1RX1,
851 CS35L56_INPUT_SRC_ASP1RX2,
852 CS35L56_INPUT_SRC_VMON,
853 CS35L56_INPUT_SRC_IMON,
854 CS35L56_INPUT_SRC_ERR_VOL,
855 CS35L56_INPUT_SRC_CLASSH,
856 CS35L56_INPUT_SRC_VDDBMON,
857 CS35L56_INPUT_SRC_VBSTMON,
858 CS35L56_INPUT_SRC_DSP1TX1,
859 CS35L56_INPUT_SRC_DSP1TX2,
860 CS35L56_INPUT_SRC_DSP1TX3,
861 CS35L56_INPUT_SRC_DSP1TX4,
862 CS35L56_INPUT_SRC_DSP1TX5,
863 CS35L56_INPUT_SRC_DSP1TX6,
864 CS35L56_INPUT_SRC_DSP1TX7,
865 CS35L56_INPUT_SRC_DSP1TX8,
866 CS35L56_INPUT_SRC_TEMPMON,
867 CS35L56_INPUT_SRC_INTERPOLATOR,
868 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1,
869 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2,
870};
871EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, SND_SOC_CS35L56_SHARED);
872
873struct regmap_config cs35l56_regmap_i2c = {
874 .reg_bits = 32,
875 .val_bits = 32,
876 .reg_stride = 4,
877 .reg_format_endian = REGMAP_ENDIAN_BIG,
878 .val_format_endian = REGMAP_ENDIAN_BIG,
879 .max_register = CS35L56_DSP1_PMEM_5114,
880 .reg_defaults = cs35l56_reg_defaults,
881 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
882 .volatile_reg = cs35l56_volatile_reg,
883 .readable_reg = cs35l56_readable_reg,
884 .precious_reg = cs35l56_precious_reg,
885 .cache_type = REGCACHE_MAPLE,
886};
887EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, SND_SOC_CS35L56_SHARED);
888
889struct regmap_config cs35l56_regmap_spi = {
890 .reg_bits = 32,
891 .val_bits = 32,
892 .pad_bits = 16,
893 .reg_stride = 4,
894 .reg_format_endian = REGMAP_ENDIAN_BIG,
895 .val_format_endian = REGMAP_ENDIAN_BIG,
896 .max_register = CS35L56_DSP1_PMEM_5114,
897 .reg_defaults = cs35l56_reg_defaults,
898 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
899 .volatile_reg = cs35l56_volatile_reg,
900 .readable_reg = cs35l56_readable_reg,
901 .precious_reg = cs35l56_precious_reg,
902 .cache_type = REGCACHE_MAPLE,
903};
904EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, SND_SOC_CS35L56_SHARED);
905
906struct regmap_config cs35l56_regmap_sdw = {
907 .reg_bits = 32,
908 .val_bits = 32,
909 .reg_stride = 4,
910 .reg_format_endian = REGMAP_ENDIAN_LITTLE,
911 .val_format_endian = REGMAP_ENDIAN_BIG,
912 .max_register = CS35L56_DSP1_PMEM_5114,
913 .reg_defaults = cs35l56_reg_defaults,
914 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
915 .volatile_reg = cs35l56_volatile_reg,
916 .readable_reg = cs35l56_readable_reg,
917 .precious_reg = cs35l56_precious_reg,
918 .cache_type = REGCACHE_MAPLE,
919};
920EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, SND_SOC_CS35L56_SHARED);
921
922MODULE_DESCRIPTION("ASoC CS35L56 Shared");
923MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
924MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>");
925MODULE_LICENSE("GPL");