1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * Copyright (c) 2019 MediaTek Inc.
 4 * Author: Yong Liang <yong.liang@mediatek.com>
 5 */
 6
 7#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2712
 8#define _DT_BINDINGS_RESET_CONTROLLER_MT2712
 9
10#define MT2712_TOPRGU_INFRA_SW_RST				0
11#define MT2712_TOPRGU_MM_SW_RST					1
12#define MT2712_TOPRGU_MFG_SW_RST				2
13#define MT2712_TOPRGU_VENC_SW_RST				3
14#define MT2712_TOPRGU_VDEC_SW_RST				4
15#define MT2712_TOPRGU_IMG_SW_RST				5
16#define MT2712_TOPRGU_INFRA_AO_SW_RST				8
17#define MT2712_TOPRGU_USB_SW_RST				9
18#define MT2712_TOPRGU_APMIXED_SW_RST				10
19
20#define MT2712_TOPRGU_SW_RST_NUM				11
21
22#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT2712 */

 1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * Copyright (c) 2019 MediaTek Inc.
 4 * Author: Yong Liang <yong.liang@mediatek.com>
 5 */
 6
 7#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2712
 8#define _DT_BINDINGS_RESET_CONTROLLER_MT2712
 9
10#define MT2712_TOPRGU_INFRA_SW_RST				0
11#define MT2712_TOPRGU_MM_SW_RST					1
12#define MT2712_TOPRGU_MFG_SW_RST				2
13#define MT2712_TOPRGU_VENC_SW_RST				3
14#define MT2712_TOPRGU_VDEC_SW_RST				4
15#define MT2712_TOPRGU_IMG_SW_RST				5
16#define MT2712_TOPRGU_INFRA_AO_SW_RST				8
17#define MT2712_TOPRGU_USB_SW_RST				9
18#define MT2712_TOPRGU_APMIXED_SW_RST				10
19
20#define MT2712_TOPRGU_SW_RST_NUM				11
21
22#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT2712 */